26255 lines
1.0 MiB
Executable File
26255 lines
1.0 MiB
Executable File
<?xml version="1.0" encoding="UTF-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<vendor>Freescale Semiconductor, Inc.</vendor>
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<vendorID>Freescale</vendorID>
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<series>Kinetis_EA</series>
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<name>SKEAZ1284</name>
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<version>1.6</version>
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<description>SKEAZ1284 Freescale Microcontroller</description>
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<licenseText>Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</licenseText>
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<cpu>
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<name>CM0PLUS</name>
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<revision>r0p0</revision>
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<endian>little</endian>
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<mpuPresent>false</mpuPresent>
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<fpuPresent>false</fpuPresent>
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<mpuPresent>false</mpuPresent>
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<vtorPresent>true</vtorPresent>
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<nvicPrioBits>2</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<peripherals>
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<peripheral>
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<name>FTMRE_FlashConfig</name>
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<description>Flash configuration field</description>
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<prependToName>NV_</prependToName>
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<baseAddress>0x400</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0x10</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>BACKKEY0</name>
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<description>Backdoor Comparison Key 0</description>
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<addressOffset>0</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY1</name>
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<description>Backdoor Comparison Key 1</description>
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<addressOffset>0x1</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY2</name>
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<description>Backdoor Comparison Key 2</description>
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<addressOffset>0x2</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY3</name>
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<description>Backdoor Comparison Key 3</description>
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<addressOffset>0x3</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY4</name>
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<description>Backdoor Comparison Key 4</description>
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<addressOffset>0x4</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY5</name>
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<description>Backdoor Comparison Key 5</description>
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<addressOffset>0x5</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
|
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY6</name>
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<description>Backdoor Comparison Key 6</description>
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<addressOffset>0x6</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY7</name>
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<description>Backdoor Comparison Key 7</description>
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<addressOffset>0x7</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT</name>
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<description>Non-volatile P-Flash Protection Register</description>
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<addressOffset>0xD</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>FPLS</name>
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<description>no description available</description>
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<bitOffset>0</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>00</name>
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<description>Address range: 0x00_0000-0x00_07FF; protected size: 2 KB</description>
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<value>#00</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>01</name>
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<description>Address range: 0x00_0000-0x00_0FFF; protected size: 4 KB</description>
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<value>#01</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>10</name>
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<description>Address range: 0x00_0000-0x00_1FFF; protected size: 8 KB</description>
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<value>#10</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>11</name>
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<description>Address range: 0x00_0000-0x00_3FFF; protected size: 16 KB</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>FPLDIS</name>
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<description>no description available</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>00</name>
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<description>Protection/Unprotection enabled</description>
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<value>#00</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>01</name>
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<description>Protection/Unprotection disabled</description>
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<value>#01</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>FPHS</name>
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<description>no description available</description>
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<bitOffset>3</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>00</name>
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<description>Address range: 0x00_7C00-0x00_7FFF; protected size: 1 KB</description>
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<value>#00</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>01</name>
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<description>Address range: 0x00_7800-0x00_7FFF; protected size: 2 KB</description>
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<value>#01</value>
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</enumeratedValue>
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<enumeratedValue>
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|
<name>10</name>
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<description>Address range: 0x00_7000-0x00_7FFF; protected size: 4 KB</description>
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<value>#10</value>
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</enumeratedValue>
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<enumeratedValue>
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|
<name>11</name>
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<description>Address range: 0x00_6000-0x00_7FFF; protected size: 8 KB</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>FPHDIS</name>
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<description>no description available</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>00</name>
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|
<description>Protection/Unprotection enabled</description>
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<value>#00</value>
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</enumeratedValue>
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<enumeratedValue>
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|
<name>01</name>
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<description>Protection/Unprotection disabled</description>
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<value>#01</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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|
<name>FPOPEN</name>
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<description>no description available</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>00</name>
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<description>FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits FPROT1.1</description>
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<value>#00</value>
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</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>01</name>
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<description>FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits</description>
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<value>#01</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>FSEC</name>
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<description>Non-volatile Flash Security Register</description>
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<addressOffset>0xE</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>SEC</name>
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<description>Flash Security</description>
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<bitOffset>0</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>10</name>
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<description>MCU security status is unsecure</description>
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<value>#10</value>
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</enumeratedValue>
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|
<enumeratedValue>
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|
<name>11</name>
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|
<description>MCU security status is secure</description>
|
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>KEYEN</name>
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<description>Backdoor Key Security Enable</description>
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<bitOffset>6</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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|
<name>10</name>
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<description>Backdoor key access enabled</description>
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<value>#10</value>
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</enumeratedValue>
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|
<enumeratedValue>
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|
<name>11</name>
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<description>Backdoor key access disabled</description>
|
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
|
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</register>
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<register>
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|
<name>FOPT</name>
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<description>Non-volatile Flash Option Register</description>
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<addressOffset>0xF</addressOffset>
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<size>8</size>
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<access>read-only</access>
|
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<resetValue>0xFF</resetValue>
|
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<resetMask>0xFF</resetMask>
|
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>FTMRE</name>
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<description>Flash Memory</description>
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<prependToName>FTMRE_</prependToName>
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<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
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<offset>0x1</offset>
|
|
<size>0xF</size>
|
|
<usage>registers</usage>
|
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</addressBlock>
|
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<interrupt>
|
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<name>FTMRE</name>
|
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<value>5</value>
|
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</interrupt>
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<registers>
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<register>
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|
<name>FCCOBIX</name>
|
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<description>Flash CCOB Index Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCOBIX</name>
|
|
<description>Common Command Register Index</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSEC</name>
|
|
<description>Flash Security Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Flash Security Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Secured</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Secured</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Unsecured</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Secured</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEYEN</name>
|
|
<description>Backdoor Key Security Enable Bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Disabled</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Enabled</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Disabled</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCLKDIV</name>
|
|
<description>Flash Clock Divider Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FDIV</name>
|
|
<description>Clock Divider Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FDIVLCK</name>
|
|
<description>Clock Divider Locked</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FDIV field is open for writing.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FDIV value is locked and cannot be changed. After the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in user mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FDIVLD</name>
|
|
<description>Clock Divider Loaded</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FCLKDIV register has not been written since the last reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FCLKDIV register has been written since the last reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSTAT</name>
|
|
<description>Flash Status Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MGSTAT</name>
|
|
<description>Memory Controller Command Completion Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MGBUSY</name>
|
|
<description>Memory Controller Busy Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Memory controller is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Memory controller is busy executing a flash command (CCIF = 0).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FPVIOL</name>
|
|
<description>Flash Protection Violation Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No protection violation is detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Protection violation is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACCERR</name>
|
|
<description>Flash Access Error Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No access error is detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Access error is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIF</name>
|
|
<description>Command Complete Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Flash command is in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Flash command has completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCNFG</name>
|
|
<description>Flash Configuration Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERSAREQ</name>
|
|
<description>Debugger Mass Erase Request</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No request or request complete</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request to run the Erase All Blocks command verify the erased state program the security byte in the Flash Configuration Field to the unsecure state release MCU security by setting FSEC[SEC] to the unsecure state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIE</name>
|
|
<description>Command Complete Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Command complete interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An interrupt will be requested whenever the CCIF flag in the FSTAT register is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCCOBLO</name>
|
|
<description>Flash Common Command Object Register: Low</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCOB</name>
|
|
<description>Common Command Object Bit 7:0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCCOBHI</name>
|
|
<description>Flash Common Command Object Register:High</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCOB</name>
|
|
<description>Common Command Object Bit 15:8</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPROT</name>
|
|
<description>Flash Protection Register</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FPLS</name>
|
|
<description>Flash Protection Lower Address Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPLDIS</name>
|
|
<description>Flash Protection Lower Address Range Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Protection/Unprotection enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Protection/Unprotection disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FPHS</name>
|
|
<description>Flash Protection Higher Address Size</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPHDIS</name>
|
|
<description>Flash Protection Higher Address Range Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Protection/Unprotection enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Protection/Unprotection disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RNV6</name>
|
|
<description>Reserved Nonvolatile Bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FPOPEN</name>
|
|
<description>Flash Protection Operation Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>When FPOPEN is clear, the FPHDIS and FPLDIS fields define unprotected address ranges as specified by the corresponding FPHS and FPLS fields.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When FPOPEN is set, the FPHDIS and FPLDIS fields enable protection for the address range specified by the corresponding FPHS and FPLS fields.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FOPT</name>
|
|
<description>Flash Option Register</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NV</name>
|
|
<description>Nonvolatile Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MSCAN</name>
|
|
<description>Freescale's Scalable Controller Area Network</description>
|
|
<prependToName>MSCAN_</prependToName>
|
|
<baseAddress>0x40024000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x40</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>MSCAN_RX</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>MSCAN_TX</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CANCTL0</name>
|
|
<description>MSCAN Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INITRQ</name>
|
|
<description>Initialization Mode Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSCAN in initialization mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLPRQ</name>
|
|
<description>Sleep Mode Request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Running - The MSCAN functions normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sleep mode request - The MSCAN enters sleep mode when CAN bus idle.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPE</name>
|
|
<description>WakeUp Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Wakeup disabled - The MSCAN ignores traffic on CAN.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Wakeup enabled - The MSCAN is able to restart.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIME</name>
|
|
<description>Timer Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable internal MSCAN timer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable internal MSCAN timer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Synchronized Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MSCAN is not synchronized to the CAN bus.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSCAN is synchronized to the CAN bus.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSWAI</name>
|
|
<description>CAN Stops in Wait Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The module is not affected during wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The module ceases to be clocked during wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXACT</name>
|
|
<description>Receiver Active Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MSCAN is transmitting or idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSCAN is receiving a message, including when arbitration is lost.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFRM</name>
|
|
<description>Received Frame Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No valid message was received since last clearing this flag.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A valid message was received since last clearing of this flag.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANCTL1</name>
|
|
<description>MSCAN Control Register 1</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x11</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INITAK</name>
|
|
<description>Initialization Mode Acknowledge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Running - The MSCAN operates normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Initialization mode active - The MSCAN has entered initialization mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLPAK</name>
|
|
<description>Sleep Mode Acknowledge</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Running - The MSCAN operates normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sleep mode active - The MSCAN has entered sleep mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPM</name>
|
|
<description>WakeUp Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MSCAN wakes on any dominant level on the CAN bus.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSCAN wakes only in case of a dominant pulse on the CAN bus that has a length of Twup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BORM</name>
|
|
<description>Bus-Off Recovery Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specification).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus-off recovery upon user request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LISTEN</name>
|
|
<description>Listen Only Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Listen only mode activated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPB</name>
|
|
<description>Loopback Self Test Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loopback self test disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loopback self test enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSRC</name>
|
|
<description>MSCAN Clock Source</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MSCAN clock source is the oscillator clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSCAN clock source is the bus clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CANE</name>
|
|
<description>MSCAN Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MSCAN module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSCAN module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANBTR0</name>
|
|
<description>MSCAN Bus Timing Register 0</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRP</name>
|
|
<description>Baud Rate Prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000000</name>
|
|
<description>1</description>
|
|
<value>#000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>000001</name>
|
|
<description>2</description>
|
|
<value>#000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>000010</name>
|
|
<description>......</description>
|
|
<value>#000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>000011</name>
|
|
<description>......</description>
|
|
<value>#000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111110</name>
|
|
<description>63</description>
|
|
<value>#111110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111111</name>
|
|
<description>64</description>
|
|
<value>#111111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SJW</name>
|
|
<description>Synchronization Jump Width</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1 Tq clock cycle.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>2 Tq clock cycles.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>3 Tq clock cycle.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>4 Tq clock cycles.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANBTR1</name>
|
|
<description>MSCAN Bus Timing Register 1</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSEG1</name>
|
|
<description>Time Segment 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>1 Tq clock cycle (not valid)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>2 Tq clock cycles (not valid)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>3 Tq clock cycles (not valid)</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>4 Tq clock cycles</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>15 Tq clock cycles</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>16 Tq clock cycles</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSEG2</name>
|
|
<description>Time Segment 2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1 Tq clock cycle (not valid)</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 Tq clock cycles</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3 Tq clock cycles</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4 Tq clock cycles</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>5 Tq clock cycles</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>6 Tq clock cycles</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>7 Tq clock cycles</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>8 Tq clock cycles</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAMP</name>
|
|
<description>Sampling</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One sample per bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Three samples per bit. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANRFLG</name>
|
|
<description>MSCAN Receiver Flag Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXF</name>
|
|
<description>Receive Buffer Full Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No new message available within the RxFG.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The receiver FIFO is not empty. A new message is available in the RxFG.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVRIF</name>
|
|
<description>Overrun Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No data overrun condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A data overrun detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTAT</name>
|
|
<description>Transmitter Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>TxOK: 0<=transmit error counter<96</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>TxWRN: 96<=transmit error counter<128</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>TxERR: 128<=transmit error counter<256</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Bus-off: 256<=transmit error counter</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTAT</name>
|
|
<description>Receiver Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>RxOK: 0<=receive error counter<96</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>RxWRN: 96<=receive error counter<128</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>RxERR: 128<=receive error counter</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Bus-off: 256<=transmit error counter (Redundant Information for the most critical CAN bus status which is "bus-off". This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT[1:0] coding in this register. )</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCIF</name>
|
|
<description>CAN Status Change Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No change in CAN bus status occurred since last interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSCAN changed current CAN bus status.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPIF</name>
|
|
<description>Wake-Up Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No wakeup activity observed while in sleep mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSCAN detected activity on the CAN bus and requested wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANRIER</name>
|
|
<description>MSCAN Receiver Interrupt Enable Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIE</name>
|
|
<description>Receiver Full Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt request is generated from this event.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A receive buffer full (successful message reception) event causes a receiver interrupt request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVRIE</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt request is generated from this event.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An overrun event causes an error interrupt request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTATE</name>
|
|
<description>Transmitter Status Change Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Do not generate any CSCIF interrupt caused by transmitter state changes.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Generate CSCIF interrupt only if the transmitter enters or leaves "bus-off" state. Discard other transmitter state changes for generating CSCIF interrupt.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Generate CSCIF interrupt only if the transmitter enters or leaves "TxErr" or "bus-off" state. Discard other transmitter state changes for generating CSCIF interrupt.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Generate CSCIF interrupt on all state changes.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTATE</name>
|
|
<description>Receiver Status Change Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Do not generate any CSCIF interrupt caused by receiver state changes.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Generate CSCIF interrupt only if the receiver enters or leaves "bus-off" state. Discard other receiver state changes for generating CSCIF interrupt.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Generate CSCIF interrupt only if the receiver enters or leaves "RxErr" or "bus-off"Bus-off state is only defined for transmitters by the CAN standard (see Bosch CAN 2.0A/B protocol specification). Because the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver state. Discard other receiver state changes for generating CSCIF interrupt.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Generate CSCIF interrupt on all state changes.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCIE</name>
|
|
<description>CAN Status Change Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt request is generated from this event.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A CAN Status Change event causes an error interrupt request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WUPIE</name>
|
|
<description>WakeUp Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt request is generated from this event.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A wake-up event causes a Wake-Up interrupt request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANTFLG</name>
|
|
<description>MSCAN Transmitter Flag Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Transmitter Buffer Empty</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The associated message buffer is full (loaded with a message due for transmission).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The associated message buffer is empty (not scheduled).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANTIER</name>
|
|
<description>MSCAN Transmitter Interrupt Enable Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXEIE</name>
|
|
<description>Transmitter Empty Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt request is generated from this event.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANTARQ</name>
|
|
<description>MSCAN Transmitter Message Abort Request Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ABTRQ</name>
|
|
<description>Abort Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No abort request.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Abort request pending.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANTAAK</name>
|
|
<description>MSCAN Transmitter Message Abort Acknowledge Register</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ABTAK</name>
|
|
<description>Abort Acknowledge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The message was not aborted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The message was aborted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANTBSEL</name>
|
|
<description>MSCAN Transmit Buffer Selection Register</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>Transmit Buffer Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The associated message buffer is deselected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The associated message buffer is selected, if lowest numbered bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDAC</name>
|
|
<description>MSCAN Identifier Acceptance Control Register</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IDHIT</name>
|
|
<description>Identifier Acceptance Hit Indicator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Filter 0 hit.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Filter 1 hit.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Filter 2 hit.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Filter 3 hit.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Filter 4 hit.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Filter 5 hit.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Filter 6 hit.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Filter 7 hit.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDAM</name>
|
|
<description>Identifier Acceptance Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Two 32-bit acceptance filters.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Four 16-bit acceptance filters.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Eight 8-bit acceptance filters.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Filter closed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANMISC</name>
|
|
<description>MSCAN Miscellaneous Register</description>
|
|
<addressOffset>0xD</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BOHOLD</name>
|
|
<description>Bus-off State Hold Until User Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module is not bus-off or recovery has been requested by user in bus-off state.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module is bus-off and holds this state until user request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANRXERR</name>
|
|
<description>MSCAN Receive Error Counter</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXERR</name>
|
|
<description>Receive Error Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANTXERR</name>
|
|
<description>MSCAN Transmit Error Counter</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXERR</name>
|
|
<description>Transmit Error Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDAR0</name>
|
|
<description>MSCAN Identifier Acceptance Register n of First Bank</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AC</name>
|
|
<description>Acceptance Code Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDAR1</name>
|
|
<description>MSCAN Identifier Acceptance Register n of First Bank</description>
|
|
<addressOffset>0x11</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AC</name>
|
|
<description>Acceptance Code Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDAR2</name>
|
|
<description>MSCAN Identifier Acceptance Register n of First Bank</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AC</name>
|
|
<description>Acceptance Code Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDAR3</name>
|
|
<description>MSCAN Identifier Acceptance Register n of First Bank</description>
|
|
<addressOffset>0x13</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AC</name>
|
|
<description>Acceptance Code Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDMR0</name>
|
|
<description>MSCAN Identifier Mask Register n of First Bank</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AM</name>
|
|
<description>Acceptance Mask Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Match corresponding acceptance code register and identifier bits.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Ignore corresponding acceptance code register bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDMR1</name>
|
|
<description>MSCAN Identifier Mask Register n of First Bank</description>
|
|
<addressOffset>0x15</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AM</name>
|
|
<description>Acceptance Mask Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Match corresponding acceptance code register and identifier bits.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Ignore corresponding acceptance code register bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDMR2</name>
|
|
<description>MSCAN Identifier Mask Register n of First Bank</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AM</name>
|
|
<description>Acceptance Mask Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Match corresponding acceptance code register and identifier bits.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Ignore corresponding acceptance code register bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDMR3</name>
|
|
<description>MSCAN Identifier Mask Register n of First Bank</description>
|
|
<addressOffset>0x17</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AM</name>
|
|
<description>Acceptance Mask Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Match corresponding acceptance code register and identifier bits.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Ignore corresponding acceptance code register bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDAR4</name>
|
|
<description>MSCAN Identifier Acceptance Register n of Second Bank</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AC</name>
|
|
<description>Acceptance Code Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDAR5</name>
|
|
<description>MSCAN Identifier Acceptance Register n of Second Bank</description>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AC</name>
|
|
<description>Acceptance Code Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDAR6</name>
|
|
<description>MSCAN Identifier Acceptance Register n of Second Bank</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AC</name>
|
|
<description>Acceptance Code Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDAR7</name>
|
|
<description>MSCAN Identifier Acceptance Register n of Second Bank</description>
|
|
<addressOffset>0x1B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AC</name>
|
|
<description>Acceptance Code Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDMR4</name>
|
|
<description>MSCAN Identifier Mask Register n of Second Bank</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AM</name>
|
|
<description>Acceptance Mask Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Match corresponding acceptance code register and identifier bits.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Ignore corresponding acceptance code register bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDMR5</name>
|
|
<description>MSCAN Identifier Mask Register n of Second Bank</description>
|
|
<addressOffset>0x1D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AM</name>
|
|
<description>Acceptance Mask Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Match corresponding acceptance code register and identifier bits.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Ignore corresponding acceptance code register bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDMR6</name>
|
|
<description>MSCAN Identifier Mask Register n of Second Bank</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AM</name>
|
|
<description>Acceptance Mask Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Match corresponding acceptance code register and identifier bits.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Ignore corresponding acceptance code register bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CANIDMR7</name>
|
|
<description>MSCAN Identifier Mask Register n of Second Bank</description>
|
|
<addressOffset>0x1F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AM</name>
|
|
<description>Acceptance Mask Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Match corresponding acceptance code register and identifier bits.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Ignore corresponding acceptance code register bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REIDR0</name>
|
|
<description>Receive Extended Identifier Register 0</description>
|
|
<alternateGroup>MSCAN</alternateGroup>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REID28_REID21</name>
|
|
<description>Extended Format Identifier</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSIDR0</name>
|
|
<description>Receive Standard Identifier Register 0</description>
|
|
<alternateGroup>MSCAN</alternateGroup>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSID10_RSID3</name>
|
|
<description>Standard Format Identifier</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REIDR1</name>
|
|
<description>Receive Extended Identifier Register 1</description>
|
|
<alternateGroup>MSCAN</alternateGroup>
|
|
<addressOffset>0x21</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REID17_REID15</name>
|
|
<description>Extended Format Identifier 17-15</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REIDE</name>
|
|
<description>ID Extended</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard format (11 bit).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Extended format (29 bit).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRR</name>
|
|
<description>Substitute Remote Request</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REID20_REID18</name>
|
|
<description>Extended Format Identifier 20-18</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSIDR1</name>
|
|
<description>Standard Identifier Register 1</description>
|
|
<alternateGroup>MSCAN</alternateGroup>
|
|
<addressOffset>0x21</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSIDE</name>
|
|
<description>ID Extended</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard format (11 bit).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Extended format (29 bit).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRTR</name>
|
|
<description>Remote Transmission Request</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data frame.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Remote frame.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSID2_RSID0</name>
|
|
<description>Standard Format Identifier 2-0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REIDR2</name>
|
|
<description>Receive Extended Identifier Register 2</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REID14_REID7</name>
|
|
<description>Extended Format Identifier 14-7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REIDR3</name>
|
|
<description>Receive Extended Identifier Register 3</description>
|
|
<addressOffset>0x23</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RERTR</name>
|
|
<description>Remote Transmission Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data frame.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Remote frame.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REID6_REID0</name>
|
|
<description>Extended Format Identifier 6-0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>REDSR%s</name>
|
|
<description>Receive Extended Data Segment Register N</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDB</name>
|
|
<description>Data Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDLR</name>
|
|
<description>Receive Data Length Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDLC</name>
|
|
<description>Data Length Code Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>0</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>2</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>3</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>4</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>5</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>6</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>7</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>8</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTSRH</name>
|
|
<description>Receive Time Stamp Register High</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTS</name>
|
|
<description>Time Stamp</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTSRL</name>
|
|
<description>Receive Time Stamp Register Low</description>
|
|
<addressOffset>0x2F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTS</name>
|
|
<description>Time Stamp</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEIDR0</name>
|
|
<description>Transmit Extended Identifier Register 0</description>
|
|
<alternateGroup>MSCAN</alternateGroup>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEID28_TEID21</name>
|
|
<description>Extended Format Identifier</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSIDR0</name>
|
|
<description>Transmit Standard Identifier Register 0</description>
|
|
<alternateGroup>MSCAN</alternateGroup>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSID10_TSID3</name>
|
|
<description>Standard Format Identifier</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEIDR1</name>
|
|
<description>Transmit Extended Identifier Register 1</description>
|
|
<alternateGroup>MSCAN</alternateGroup>
|
|
<addressOffset>0x31</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEID17_TEID15</name>
|
|
<description>Extended Format Identifier 17-15</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIDE</name>
|
|
<description>ID Extended</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard format (11 bit).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Extended format (29 bit).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSRR</name>
|
|
<description>Substitute Remote Request</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEID20_TEID18</name>
|
|
<description>Extended Format Identifier 20-18</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSIDR1</name>
|
|
<description>Transmit Standard Identifier Register 1</description>
|
|
<alternateGroup>MSCAN</alternateGroup>
|
|
<addressOffset>0x31</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSIDE</name>
|
|
<description>ID Extended</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard format (11 bit).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Extended format (29 bit).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSRTR</name>
|
|
<description>Remote Transmission Request</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data frame.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Remote frame.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSID2_TSID0</name>
|
|
<description>Standard Format Identifier 2-0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEIDR2</name>
|
|
<description>Transmit Extended Identifier Register 2</description>
|
|
<addressOffset>0x32</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEID14_TEID7</name>
|
|
<description>Extended Format Identifier 14-7</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEIDR3</name>
|
|
<description>Transmit Extended Identifier Register 3</description>
|
|
<addressOffset>0x33</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TERTR</name>
|
|
<description>Remote Transmission Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data frame.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Remote frame.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEID6_TEID0</name>
|
|
<description>Extended Format Identifier 6-0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TEDSR%s</name>
|
|
<description>Transmit Extended Data Segment Register N</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDB</name>
|
|
<description>Data Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDLR</name>
|
|
<description>This register keeps the data length field of the CAN frame.</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDLC</name>
|
|
<description>Data Length Code Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>0</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>1</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>2</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>3</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>4</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>5</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>6</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>7</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>8</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBPR</name>
|
|
<description>Transmit Buffer Priority Register</description>
|
|
<addressOffset>0x3D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRIO</name>
|
|
<description>Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TTSRH</name>
|
|
<description>Transmit Time Stamp Register High</description>
|
|
<addressOffset>0x3E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TTS</name>
|
|
<description>Time Stamp</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TTSRL</name>
|
|
<description>Transmit Time Stamp Register Low</description>
|
|
<addressOffset>0x3F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TTS</name>
|
|
<description>Time Stamp</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IRQ</name>
|
|
<description>Interrupt</description>
|
|
<prependToName>IRQ_</prependToName>
|
|
<baseAddress>0x40031000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>IRQ</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Interrupt Pin Request Status and Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQMOD</name>
|
|
<description>IRQ Detection Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IRQ event is detected only on falling/rising edges.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IRQ event is detected on falling/rising edges and low/high levels.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQIE</name>
|
|
<description>IRQ Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt request when IRQF set is disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt requested whenever IRQF = 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQACK</name>
|
|
<description>IRQ Acknowledge</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IRQF</name>
|
|
<description>IRQ Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No IRQ request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IRQ event is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQPE</name>
|
|
<description>IRQ Pin Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IRQ pin function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IRQ pin function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQEDG</name>
|
|
<description>Interrupt Request (IRQ) Edge Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IRQ is falling-edge or falling-edge/low-level sensitive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IRQ is rising-edge or rising-edge/high-level sensitive.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQPDD</name>
|
|
<description>Interrupt Request (IRQ) Pull Device Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IRQ pull device enabled if IRQPE = 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IRQ pull device disabled if IRQPE = 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>Cyclic Redundancy Check</description>
|
|
<prependToName>CRC_</prependToName>
|
|
<baseAddress>0x40032000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>CRC Data register</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LL</name>
|
|
<description>CRC Low Lower Byte</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LU</name>
|
|
<description>CRC Low Upper Byte</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HL</name>
|
|
<description>CRC High Lower Byte</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HU</name>
|
|
<description>CRC High Upper Byte</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATAL</name>
|
|
<description>CRC_DATAL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAL</name>
|
|
<description>DATAL stores the lower 16 bits of the 16/32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATALL</name>
|
|
<description>CRC_DATALL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATALL</name>
|
|
<description>CRCLL stores the first 8 bits of the 32 bit DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATALU</name>
|
|
<description>CRC_DATALU register.</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATALU</name>
|
|
<description>DATALL stores the second 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATAH</name>
|
|
<description>CRC_DATAH register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAH</name>
|
|
<description>DATAH stores the high 16 bits of the 16/32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATAHL</name>
|
|
<description>CRC_DATAHL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHL</name>
|
|
<description>DATAHL stores the third 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATAHU</name>
|
|
<description>CRC_DATAHU register.</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHU</name>
|
|
<description>DATAHU stores the fourth 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLY</name>
|
|
<description>CRC Polynomial register</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1021</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOW</name>
|
|
<description>Low Polynominal Half-word</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HIGH</name>
|
|
<description>High Polynominal Half-word</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYL</name>
|
|
<description>CRC_GPOLYL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYL</name>
|
|
<description>POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYLL</name>
|
|
<description>CRC_GPOLYLL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYLL</name>
|
|
<description>POLYLL stores the first 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYLU</name>
|
|
<description>CRC_GPOLYLU register.</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYLU</name>
|
|
<description>POLYLL stores the second 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYH</name>
|
|
<description>CRC_GPOLYH register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYH</name>
|
|
<description>POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYHL</name>
|
|
<description>CRC_GPOLYHL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYHL</name>
|
|
<description>POLYHL stores the third 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYHU</name>
|
|
<description>CRC_GPOLYHU register.</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYHU</name>
|
|
<description>POLYHU stores the fourth 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>CRC Control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCRC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>16-bit CRC protocol.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>32-bit CRC protocol.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAS</name>
|
|
<description>Write CRC Data Register As Seed</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the CRC data register are data values.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the CRC data register are seed values.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FXOR</name>
|
|
<description>Complement Read Of CRC Data Register</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No XOR on reading.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Invert or complement the read value of the CRC Data register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOTR</name>
|
|
<description>Type Of Transpose For Read</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed; bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOT</name>
|
|
<description>Type Of Transpose For Writes</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed; bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLHU</name>
|
|
<description>CRC_CTRLHU register.</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCRC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>16-bit CRC protocol.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>32-bit CRC protocol.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to CRC data register are data values.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to CRC data reguster are seed values.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FXOR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No XOR on reading.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Invert or complement the read value of CRC data register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOTR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No Transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed, bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No Transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed, bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PWT</name>
|
|
<description>Pulse Width Timer</description>
|
|
<prependToName>PWT_</prependToName>
|
|
<baseAddress>0x40033000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PWT</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>R1</name>
|
|
<description>Pulse Width Timer Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWTOV</name>
|
|
<description>PWT Counter Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PWT counter no overflow.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PWT counter runs from 0xFFFF to 0x0000.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTRDY</name>
|
|
<description>PWT Pulse Width Valid</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PWT pulse width register(s) is not up-to-date.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PWT pulse width register(s) has been updated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTSR</name>
|
|
<description>PWT Soft Reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No action taken.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing 1 to this field will perform soft reset to PWT.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POVIE</name>
|
|
<description>PWT Counter Overflow Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable PWT to generate interrupt when PWTOV is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable PWT to generate interrupt when PWTOV is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRDYIE</name>
|
|
<description>PWT Pulse Width Data Ready Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable PWT to generate interrupt when PWTRDY is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable PWT to generate interrupt when PWTRDY is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTIE</name>
|
|
<description>PWT Module Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the PWT to generate interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the PWT to generate interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTEN</name>
|
|
<description>PWT Module Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWT is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWT is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRE</name>
|
|
<description>PWT Clock Prescaler (CLKPRE) Setting</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock divided by 1.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Clock divided by 2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Clock divided by 4.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Clock divided by 8.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Clock divided by 16.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Clock divided by 32.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Clock divided by 64.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Clock divided by 128.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>PWT Input Edge Sensitivity</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The first falling-edge starts the pulse width measurement, and on all the subsequent falling edges, the pulse width is captured.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The first rising edge starts the pulse width measurement, and on all the subsequent rising and falling edges, the pulse width is captured.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The first falling edge starts the pulse width measurement, and on all the subsequent rising and falling edges, the pulse width is captured.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The first-rising edge starts the pulse width measurement, and on all the subsequent rising edges, the pulse width is captured.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINSEL</name>
|
|
<description>PWT Pulse Inputs Selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PWTIN[0] is enabled.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PWTIN[1] is enabled.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PWTIN[2] enabled.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PWTIN[3] enabled.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCLKS</name>
|
|
<description>PWT Clock Source Selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock is selected as the clock source of PWT counter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Alternative clock is selected as the clock source of PWT counter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PPW</name>
|
|
<description>Positive Pulse Width</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>R2</name>
|
|
<description>Pulse Width Timer Register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NPW</name>
|
|
<description>Negative Pulse Width. It is suggested to use half-word (16-bit) or word (32-bit) to read out this value.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWTC</name>
|
|
<description>PWT Counter. It is suggested to use half-word (16-bit) or word (32-bit) to read out this value.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PIT</name>
|
|
<description>Periodic Interrupt Timer</description>
|
|
<prependToName>PIT_</prependToName>
|
|
<baseAddress>0x40037000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x120</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PIT_CH0</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIT_CH1</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>PIT Module Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x6</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRZ</name>
|
|
<description>Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timers continue to run in Debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timers are stopped in Debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDIS</name>
|
|
<description>Module Disable - (PIT section)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock for standard PIT timers is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock for standard PIT timers is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>LDVAL%s</name>
|
|
<description>Timer Load Value Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSV</name>
|
|
<description>Timer Start Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CVAL%s</name>
|
|
<description>Current Timer Value Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TVL</name>
|
|
<description>Current Timer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>TCTRL%s</name>
|
|
<description>Timer Control Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Timer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer n is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer n is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Timer Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt requests from Timer n are disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt will be requested whenever TIF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHN</name>
|
|
<description>Chain Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer is not chained.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>TFLG%s</name>
|
|
<description>Timer Flag Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>Timer Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timeout has not yet occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTM0</name>
|
|
<description>FlexTimer Module</description>
|
|
<groupName>FTM</groupName>
|
|
<prependToName>FTM0_</prependToName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x70</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTM0</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status And Control</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Prescale Factor Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No clock selected. This in effect disables the FTM counter.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>System clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fixed frequency clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPWMS</name>
|
|
<description>Center-Aligned PWM Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter operates in Up Counting mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter operates in Up-Down Counting mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Timer Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TOF interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sSC</name>
|
|
<description>Channel (n) Status And Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ELSA</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELSB</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSA</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSB</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable channel interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable channel interrupts.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHF</name>
|
|
<description>Channel Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sV</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTTRIG</name>
|
|
<description>FTM External Trigger</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH2TRIG</name>
|
|
<description>Channel 2 Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3TRIG</name>
|
|
<description>Channel 3 Trigger Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4TRIG</name>
|
|
<description>Channel 4 Trigger Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5TRIG</name>
|
|
<description>Channel 5 Trigger Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0TRIG</name>
|
|
<description>Channel 0 Trigger Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1TRIG</name>
|
|
<description>Channel 1 Trigger Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INITTRIGEN</name>
|
|
<description>Initialization Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of initialization trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of initialization trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGF</name>
|
|
<description>Channel Trigger Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel trigger was generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel trigger was generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTM1</name>
|
|
<description>FlexTimer Module</description>
|
|
<groupName>FTM</groupName>
|
|
<prependToName>FTM1_</prependToName>
|
|
<baseAddress>0x40039000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTM1</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status And Control</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Prescale Factor Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No clock selected. This in effect disables the FTM counter.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>System clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fixed frequency clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPWMS</name>
|
|
<description>Center-Aligned PWM Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter operates in Up Counting mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter operates in Up-Down Counting mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Timer Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TOF interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sSC</name>
|
|
<description>Channel (n) Status And Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ELSA</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELSB</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSA</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSB</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable channel interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable channel interrupts.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHF</name>
|
|
<description>Channel Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>C%sV</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTM2</name>
|
|
<description>FlexTimer Module</description>
|
|
<groupName>FTM</groupName>
|
|
<prependToName>FTM2_</prependToName>
|
|
<baseAddress>0x4003A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x9C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTM2</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status And Control</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Prescale Factor Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No clock selected. This in effect disables the FTM counter.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>System clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fixed frequency clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPWMS</name>
|
|
<description>Center-Aligned PWM Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter operates in Up Counting mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter operates in Up-Down Counting mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Timer Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TOF interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5</dimIndex>
|
|
<name>C%sSC</name>
|
|
<description>Channel (n) Status And Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ELSA</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELSB</name>
|
|
<description>Edge or Level Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSA</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSB</name>
|
|
<description>Channel Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable channel interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable channel interrupts.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHF</name>
|
|
<description>Channel Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5</dimIndex>
|
|
<name>C%sV</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTIN</name>
|
|
<description>Counter Initial Value</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Capture And Compare Status</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0F</name>
|
|
<description>Channel 0 Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1F</name>
|
|
<description>Channel 1 Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2F</name>
|
|
<description>Channel 2 Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3F</name>
|
|
<description>Channel 3 Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4F</name>
|
|
<description>Channel 4 Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5F</name>
|
|
<description>Channel 5 Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6F</name>
|
|
<description>Channel 6 Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7F</name>
|
|
<description>Channel 7 Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Features Mode Selection</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTMEN</name>
|
|
<description>FTM Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initialize The Channels Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPDIS</name>
|
|
<description>Write Protection Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSYNC</name>
|
|
<description>PWM Synchronization Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEST</name>
|
|
<description>Capture Test Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Capture test mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Capture test mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTM</name>
|
|
<description>Fault Control Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Fault control is disabled for all channels.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the manual fault clearing.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIE</name>
|
|
<description>Fault Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault control interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault control interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>Synchronization</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTMIN</name>
|
|
<description>Minimum Loading Point Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minimum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minimum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTMAX</name>
|
|
<description>Maximum Loading Point Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The maximum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The maximum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REINIT</name>
|
|
<description>FTM Counter Reinitialization By Synchronization (FTM counter synchronization)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter continues to count normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter is updated with its initial value when the selected trigger is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCHOM</name>
|
|
<description>Output Mask Synchronization</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OUTMASK register is updated with the value of its buffer only by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG0</name>
|
|
<description>PWM Synchronization Hardware Trigger 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1</name>
|
|
<description>PWM Synchronization Hardware Trigger 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2</name>
|
|
<description>PWM Synchronization Hardware Trigger 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSYNC</name>
|
|
<description>PWM Synchronization Software Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTINIT</name>
|
|
<description>Initial State For Channels Output</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OI</name>
|
|
<description>Channel 0 Output Initialization Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OI</name>
|
|
<description>Channel 1 Output Initialization Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OI</name>
|
|
<description>Channel 2 Output Initialization Value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OI</name>
|
|
<description>Channel 3 Output Initialization Value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OI</name>
|
|
<description>Channel 4 Output Initialization Value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OI</name>
|
|
<description>Channel 5 Output Initialization Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OI</name>
|
|
<description>Channel 6 Output Initialization Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OI</name>
|
|
<description>Channel 7 Output Initialization Value</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTMASK</name>
|
|
<description>Output Mask</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OM</name>
|
|
<description>Channel 0 Output Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OM</name>
|
|
<description>Channel 1 Output Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OM</name>
|
|
<description>Channel 2 Output Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OM</name>
|
|
<description>Channel 3 Output Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OM</name>
|
|
<description>Channel 4 Output Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OM</name>
|
|
<description>Channel 5 Output Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OM</name>
|
|
<description>Channel 6 Output Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OM</name>
|
|
<description>Channel 7 Output Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMBINE</name>
|
|
<description>Function For Linked Channels</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMBINE0</name>
|
|
<description>Combine Channels For n = 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Complement Of Channel (n) For n = 0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN0</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP0</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN0</name>
|
|
<description>Deadtime Enable For n = 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN0</name>
|
|
<description>Synchronization Enable For n = 0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN0</name>
|
|
<description>Fault Control Enable For n = 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE1</name>
|
|
<description>Combine Channels For n = 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Complement Of Channel (n) For n = 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN1</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP1</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN1</name>
|
|
<description>Deadtime Enable For n = 2</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN1</name>
|
|
<description>Synchronization Enable For n = 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN1</name>
|
|
<description>Fault Control Enable For n = 2</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE2</name>
|
|
<description>Combine Channels For n = 4</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP2</name>
|
|
<description>Complement Of Channel (n) For n = 4</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN2</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 4</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP2</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 4</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN2</name>
|
|
<description>Deadtime Enable For n = 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN2</name>
|
|
<description>Synchronization Enable For n = 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN2</name>
|
|
<description>Fault Control Enable For n = 4</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE3</name>
|
|
<description>Combine Channels For n = 6</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channels (n) and (n+1) are independent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channels (n) and (n+1) are combined.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP3</name>
|
|
<description>Complement Of Channel (n) for n = 6</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN3</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAP3</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 6</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN3</name>
|
|
<description>Deadtime Enable For n = 6</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN3</name>
|
|
<description>Synchronization Enable For n = 6</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN3</name>
|
|
<description>Fault Control Enable For n = 6</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEADTIME</name>
|
|
<description>Deadtime Insertion Control</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTVAL</name>
|
|
<description>Deadtime Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPS</name>
|
|
<description>Deadtime Prescaler Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x</name>
|
|
<description>Divide the system clock by 1.</description>
|
|
<value>#0x</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Divide the system clock by 4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Divide the system clock by 16.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTTRIG</name>
|
|
<description>FTM External Trigger</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH2TRIG</name>
|
|
<description>Channel 2 Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3TRIG</name>
|
|
<description>Channel 3 Trigger Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4TRIG</name>
|
|
<description>Channel 4 Trigger Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5TRIG</name>
|
|
<description>Channel 5 Trigger Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0TRIG</name>
|
|
<description>Channel 0 Trigger Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1TRIG</name>
|
|
<description>Channel 1 Trigger Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INITTRIGEN</name>
|
|
<description>Initialization Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of initialization trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of initialization trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGF</name>
|
|
<description>Channel Trigger Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel trigger was generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel trigger was generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POL</name>
|
|
<description>Channels Polarity</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POL0</name>
|
|
<description>Channel 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Channel 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Channel 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL3</name>
|
|
<description>Channel 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL4</name>
|
|
<description>Channel 4 Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL5</name>
|
|
<description>Channel 5 Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL6</name>
|
|
<description>Channel 6 Polarity</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL7</name>
|
|
<description>Channel 7 Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMS</name>
|
|
<description>Fault Mode Status</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULTF0</name>
|
|
<description>Fault Detection Flag 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF1</name>
|
|
<description>Fault Detection Flag 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF2</name>
|
|
<description>Fault Detection Flag 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF3</name>
|
|
<description>Fault Detection Flag 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIN</name>
|
|
<description>Fault Inputs</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The logic OR of the enabled fault inputs is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The logic OR of the enabled fault inputs is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is disabled. Write protected bits can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is enabled. Write protected bits cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF</name>
|
|
<description>Fault Detection Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTER</name>
|
|
<description>Input Capture Filter Control</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0FVAL</name>
|
|
<description>Channel 0 Input Filter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1FVAL</name>
|
|
<description>Channel 1 Input Filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2FVAL</name>
|
|
<description>Channel 2 Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3FVAL</name>
|
|
<description>Channel 3 Input Filter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTCTRL</name>
|
|
<description>Fault Control</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULT0EN</name>
|
|
<description>Fault Input 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1EN</name>
|
|
<description>Fault Input 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2EN</name>
|
|
<description>Fault Input 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT3EN</name>
|
|
<description>Fault Input 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR0EN</name>
|
|
<description>Fault Input 0 Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR1EN</name>
|
|
<description>Fault Input 1 Filter Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR2EN</name>
|
|
<description>Fault Input 2 Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR3EN</name>
|
|
<description>Fault Input 3 Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFVAL</name>
|
|
<description>Fault Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUMTOF</name>
|
|
<description>TOF Frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BDMMODE</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GTBEEN</name>
|
|
<description>Global Time Base Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Use of an external global time base is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use of an external global time base is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTBEOUT</name>
|
|
<description>Global Time Base Output</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A global time base signal generation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A global time base signal generation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTPOL</name>
|
|
<description>FTM Fault Input Polarity</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT0POL</name>
|
|
<description>Fault Input 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT1POL</name>
|
|
<description>Fault Input 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT2POL</name>
|
|
<description>Fault Input 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT3POL</name>
|
|
<description>Fault Input 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCONF</name>
|
|
<description>Synchronization Configuration</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWTRIGMODE</name>
|
|
<description>Hardware Trigger Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTINC</name>
|
|
<description>CNTIN Register Synchronization</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CNTIN register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CNTIN register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVC</name>
|
|
<description>INVCTRL Register Synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>INVCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>INVCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOC</name>
|
|
<description>SWOCTRL Register Synchronization</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SWOCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SWOCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCMODE</name>
|
|
<description>Synchronization Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Legacy PWM synchronization is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enhanced PWM synchronization is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRSTCNT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWWRBUF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOM</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWINVC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSOC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWRSTCNT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWWRBUF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates MOD, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWOM</name>
|
|
<description>no description available</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWINVC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWSOC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INVCTRL</name>
|
|
<description>FTM Inverting Control</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV0EN</name>
|
|
<description>Pair Channels 0 Inverting Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV1EN</name>
|
|
<description>Pair Channels 1 Inverting Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV2EN</name>
|
|
<description>Pair Channels 2 Inverting Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV3EN</name>
|
|
<description>Pair Channels 3 Inverting Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWOCTRL</name>
|
|
<description>FTM Software Output Control</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OC</name>
|
|
<description>Channel 0 Software Output Control Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OC</name>
|
|
<description>Channel 1 Software Output Control Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OC</name>
|
|
<description>Channel 2 Software Output Control Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OC</name>
|
|
<description>Channel 3 Software Output Control Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OC</name>
|
|
<description>Channel 4 Software Output Control Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OC</name>
|
|
<description>Channel 5 Software Output Control Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OC</name>
|
|
<description>Channel 6 Software Output Control Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OC</name>
|
|
<description>Channel 7 Software Output Control Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0OCV</name>
|
|
<description>Channel 0 Software Output Control Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OCV</name>
|
|
<description>Channel 1 Software Output Control Value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OCV</name>
|
|
<description>Channel 2 Software Output Control Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OCV</name>
|
|
<description>Channel 3 Software Output Control Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OCV</name>
|
|
<description>Channel 4 Software Output Control Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OCV</name>
|
|
<description>Channel 5 Software Output Control Value</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OCV</name>
|
|
<description>Channel 6 Software Output Control Value</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OCV</name>
|
|
<description>Channel 7 Software Output Control Value</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMLOAD</name>
|
|
<description>FTM PWM Load</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0SEL</name>
|
|
<description>Channel 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1SEL</name>
|
|
<description>Channel 1 Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2SEL</name>
|
|
<description>Channel 2 Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3SEL</name>
|
|
<description>Channel 3 Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4SEL</name>
|
|
<description>Channel 4 Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5SEL</name>
|
|
<description>Channel 5 Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6SEL</name>
|
|
<description>Channel 6 Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7SEL</name>
|
|
<description>Channel 7 Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not include the channel in the matching process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Include the channel in the matching process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDOK</name>
|
|
<description>Load Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loading updated values is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loading updated values is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC</name>
|
|
<description>Analog-to-digital converter</description>
|
|
<prependToName>ADC_</prependToName>
|
|
<baseAddress>0x4003B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC0</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC1</name>
|
|
<description>Status and Control Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCH</name>
|
|
<description>Input Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>Temperature Sensor</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>Bandgap</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>VREFH</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>VREFL</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>Module disabled Reset FIFO in FIFO mode.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCO</name>
|
|
<description>Continuous Conversion Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One conversion following a write to the ADC_SC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversion are triggered when ADC_SC2[ADTRG]=0 or both ADC_SC2[ADTRG]=1 and ADC_SC4[HTRGME]=1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous conversions are initiated following a write to ADC_SC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are loop triggered.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AIEN</name>
|
|
<description>Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion complete interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion complete interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COCO</name>
|
|
<description>Conversion Complete Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC2</name>
|
|
<description>Status and Control Register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Voltage Reference Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Default voltage reference pin pair (VREFH/VREFL).</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Analog supply pin pair (VDDA/VSSA).</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Reserved - Selects default voltage reference (VREFH/VREFL) pin pair.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFULL</name>
|
|
<description>Result FIFO full</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Indicates that ADC result FIFO is not full and next conversion data still can be stored into FIFO.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates that ADC result FIFO is full and next conversion will override old data in case of no read action.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEMPTY</name>
|
|
<description>Result FIFO empty</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Indicates that ADC result FIFO have at least one valid new data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates that ADC result FIFO have no valid new data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFGT</name>
|
|
<description>Compare Function Greater Than Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compare triggers when input is less than compare level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compare triggers when input is greater than or equal to compare level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFE</name>
|
|
<description>Compare Function Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compare function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compare function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTRG</name>
|
|
<description>Conversion Trigger Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware trigger selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADACT</name>
|
|
<description>Conversion Active</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion not in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion in progress.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC3</name>
|
|
<description>Status and Control Register 3</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADICLK</name>
|
|
<description>Input Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Bus clock</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bus clock divided by 2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Alternate clock (ALTCLK)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Asynchronous clock (ADACK)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Conversion Mode Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>8-bit conversion (N = 8)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>10-bit conversion (N = 10)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>12-bit conversion (N = 12)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADLSMP</name>
|
|
<description>Long Sample Time Configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Short sample time.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Long sample time.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADIV</name>
|
|
<description>Clock Divide Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Divide ration = 1, and clock rate = Input clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Divide ration = 2, and clock rate = Input clock * 2.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Divide ration = 3, and clock rate = Input clock * 4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Divide ration = 4, and clock rate = Input clock * 8.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADLPC</name>
|
|
<description>Low-Power Configuration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>High speed configuration.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low power configuration:The power is reduced at the expense of maximum clock speed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC4</name>
|
|
<description>Status and Control Register 4</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AFDEP</name>
|
|
<description>FIFO Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>FIFO is disabled.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2-level FIFO is enabled.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3-level FIFO is enabled..</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4-level FIFO is enabled.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>5-level FIFO is enabled.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>6-level FIFO is enabled.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>7-level FIFO is enabled.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>8-level FIFO is enabled.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFSEL</name>
|
|
<description>Compare Function Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR all of compare trigger.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>AND all of compare trigger.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASCANE</name>
|
|
<description>FIFO Scan Mode Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO scan mode disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO scan mode enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HTRGME</name>
|
|
<description>Hardware Trigger Multiple Conversion Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One hardware trigger pulse triggers one conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>One hardware trigger pulse triggers multiple conversions in fifo mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>R</name>
|
|
<description>Conversion Result Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>Conversion Result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CV</name>
|
|
<description>Compare Value Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Conversion Result[11:0]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APCTL1</name>
|
|
<description>Pin Control 1 Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADPC</name>
|
|
<description>ADC Pin Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ADx pin I/O control enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ADx pin I/O control disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC5</name>
|
|
<description>Status and Control Register 5</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HTRGMASKSEL</name>
|
|
<description>Hardware Trigger Mask Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware trigger mask with HTRGMASKE.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware trigger mask automatically when data fifo is not empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HTRGMASKE</name>
|
|
<description>Hardware Trigger Mask Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware trigger mask disable.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware trigger mask enable and hardware trigger cannot trigger ADC conversion..</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>Real-time counter</description>
|
|
<prependToName>RTC_</prependToName>
|
|
<baseAddress>0x4003D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>RTC Status and Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTCO</name>
|
|
<description>Real-Time Counter Output</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Real-time counter output disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Real-time counter output enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTIE</name>
|
|
<description>Real-Time Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Real-time interrupt requests are disabled. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Real-time interrupt requests are enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTIF</name>
|
|
<description>Real-Time Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RTC counter has not reached the value in the RTC modulo register.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTC counter has reached the value in the RTC modulo register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCPS</name>
|
|
<description>Real-Time Clock Prescaler Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Off</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>If RTCLKS = x0, it is 1; if RTCLKS = x1, it is 128.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>If RTCLKS = x0, it is 2; if RTCLKS = x1, it is 256.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>If RTCLKS = x0, it is 4; if RTCLKS = x1, it is 512.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>If RTCLKS = x0, it is 8; if RTCLKS = x1, it is 1024.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>If RTCLKS = x0, it is 16; if RTCLKS = x1, it is 2048.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>If RTCLKS = x0, it is 32; if RTCLKS = x1, it is 100.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>If RTCLKS = x0, it is 64; if RTCLKS = x1, it is 1000.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCLKS</name>
|
|
<description>Real-Time Clock Source Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External clock source.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Real-time clock source is 1 kHz (LPOCLK).</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Internal reference clock (ICSIRCLK).</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Bus clock.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>RTC Modulo Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>RTC Modulo</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>RTC Counter Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>RTC Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SIM</name>
|
|
<description>System Integration Module</description>
|
|
<prependToName>SIM_</prependToName>
|
|
<baseAddress>0x40048000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SRSID</name>
|
|
<description>System Reset Status and ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x6000002</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVD</name>
|
|
<description>Low Voltage Detect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset is not caused by LVD trip or POR.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset is caused by LVD trip or POR.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOC</name>
|
|
<description>Internal Clock Source Module Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset is not caused by the ICS module.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset is caused by the ICS module.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDOG</name>
|
|
<description>Watchdog (WDOG)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset is not caused by WDOG timeout.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset is caused by WDOG timeout.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIN</name>
|
|
<description>External Reset Pin</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset is not caused by external reset pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset came from external reset pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>Power-On Reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by POR.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>POR caused reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCKUP</name>
|
|
<description>Core Lockup</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset is not caused by core LOCKUP event.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset is caused by core LOCKUP event.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>Software</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset is not caused by software setting of SYSRESETREQ bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by software setting of SYSRESETREQ bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDMAP</name>
|
|
<description>MDM-AP System Reset Request</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset is not caused by host debugger system setting of the System Reset Request bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset is caused by host debugger system setting of the System Reset Request bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SACKERR</name>
|
|
<description>Stop Mode Acknowledge Error Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset is not caused by peripheral failure to acknowledge attempt to enter Stop mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset is caused by peripheral failure to acknowledge attempt to enter Stop mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINID</name>
|
|
<description>Device Pin ID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>8-pin</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>16-pin</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>20-pin</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>24-pin</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>32-pin</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>44-pin</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>48-pin</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>64-pin</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>80-pin</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>100-pin</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RevID</name>
|
|
<description>Device Revision Number</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SUBFAMID</name>
|
|
<description>Kinetis sub-family ID</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>KEx4 sub-family</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>KEx6 sub-family</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAMID</name>
|
|
<description>Kinetis family ID</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>KE0x family.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOPT0</name>
|
|
<description>System Options Register 0</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xE</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NMIE</name>
|
|
<description>NMI Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PTB4/KBI0_P12/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as PTB4, KBI0_P12, FTM2_CH4, SPI0_MISO or ACMP1_IN2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PTB4/KBI0_P12/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as NMI.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTPE</name>
|
|
<description>RESET Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PTA5/KBI0_P5/IRQ/TCLK0/RESET pin functions as PTA5/KBI0_P5/IRQ/TCLK0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PTA5/KBI0_P5/IRQ/TCLK0/RESET pin functions as RESET.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWDE</name>
|
|
<description>Single Wire Debug Port Pin Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PTA4/KBI0_P4/ACMP0_OUT/SWD_DIO as PTA4 or ACMP0_OUT function, PTC4/KBI0_P20/RTC_CLKOUT/FTM1_CH0/ACMP0_IN2/SWD_CLK as PTC4, KBI0_P20, RTC_CLKOUT, FTM1_CH0, OR ACMP0_IN2 function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PTA4/KBI0_P4/ACMP0_OUT/SWD_DIO as SWD_DIO function, PTC4/KBI0_P20/RTC_CLKOUT/FTM1_CH0/ACMP0_IN2/SWD_CLK as SWD_CLK function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTRG</name>
|
|
<description>ACMP Trigger FTM2 selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ACMP0 out</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ACMP1 out</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDFE</name>
|
|
<description>UART0 RxD Filter Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>RXD0 input signal is connected to UART0 module directly.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>RXD0 input signal is filtered by ACMP0, then injected to UART0.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>RXD0 input signal is filtered by ACMP1, then injected to UART0.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCC</name>
|
|
<description>Real-Time Counter Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RTC overflow is not connected to FTM1 input channel 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTC overflow is connected to FTM1 input channel 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACIC</name>
|
|
<description>Analog Comparator to Input Capture Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ACMP0 output is not connected to FTM1 input channel 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ACMP0 output is connected to FTM1 input channel 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDCE</name>
|
|
<description>UART0_RX Capture Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART0_RX input signal is connected to the UART0 module only.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART0_RX input signal is connected to the UART0 module and FTM0 channel 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTMSYNC</name>
|
|
<description>FTM2 Synchronization Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No synchronization triggered.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generates a PWM synchronization trigger to the FTM2 modules.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDME</name>
|
|
<description>UART0_TX Modulation Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART0_TX output is connected to pinout directly.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART0_TX output is modulated by FTM0 channel 0 before mapped to pinout.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSREF</name>
|
|
<description>BUS Clock Output select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Bus</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Bus divided by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Bus divided by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Bus divided by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Bus divided by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Bus divided by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Bus divided by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Bus divided by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKOE</name>
|
|
<description>Bus Clock Output Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock output is disabled on PTH2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock output is enabled on PTH2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADHWT</name>
|
|
<description>ADC Hardware Trigger Source</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>RTC overflow as the ADC hardware trigger</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>FTM0 as the ADC hardware trigger</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>FTM2 init trigger with 8-bit programmable counter delay</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>FTM2 match trigger with 8-bit programmable counter delay</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>PIT channel0 overflow as the ADC hardware trigger</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>PIT channel1 overflow as the ADC hardware trigger</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>ACMP0 out as the ADC hardware trigger.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>ACMP1 out as the ADC hardware trigger</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLYACT</name>
|
|
<description>FTM2 Trigger Delay Active</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The delay is inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The delay is active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DELAY</name>
|
|
<description>FTM2 Trigger Delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOPT1</name>
|
|
<description>System Options Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2C04WEN</name>
|
|
<description>I2C0 4-Wire Interface Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C0 4-wire interface configuration is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C0 4-wire interface configuration is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C0OINV</name>
|
|
<description>I2C0 Output Invert</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Under I2C0 4-wire interface configuration, SDA_OUT and SCL_OUT are not inverted before output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Under I2C0 4-wire interface configuration, SDA_OUT and SCL_OUT are inverted before output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACPWTS</name>
|
|
<description>PWT ACMP_OUT select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ACMP0_OUT is connectted to PWTIN2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ACMP1_OUT is connectted to PWTIN2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UARTPWTS</name>
|
|
<description>PWT UART RX select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>UART0 RX is connectted to PWTIN3.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>UART1 RX is connectted to PWTIN3.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>UART2 RX is connectted to PWTIN3.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINSEL0</name>
|
|
<description>Pin Selection Register 0</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQPS</name>
|
|
<description>IRQ Port Pin Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IRQ is mapped on PTA5.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IRQ is mapped on PTI0.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IRQ is mapped on PTI1.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IRQ is mapped on PTI2.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IRQ is mapped on PTI3.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IRQ is mapped on PTI4.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IRQ is mapped on PTI5.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IRQ is mapped on PTI6.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCPS</name>
|
|
<description>RTCO Pin Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RTCO is mapped on PTC4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTCO is mapped on PTC5.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C0PS</name>
|
|
<description>I2C0 Port Pin Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI0PS</name>
|
|
<description>SPI0 Pin Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS are mapped on PTB2, PTB3, PTB4, and PTB5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS are mapped on PTE0, PTE1, PTE2, and PTE3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0PS</name>
|
|
<description>UART0 Pin Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART0_RX and UART0_TX are mapped on PTB0 and PTB1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART0_RX and UART0_TX are mapped on PTA2 and PTA3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM0PS0</name>
|
|
<description>FTM0_CH0 Port Pin Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM0_CH0 channels are mapped on PTA0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM0_CH0 channels are mapped on PTB2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM0PS1</name>
|
|
<description>FTM0_CH1 Port Pin Select</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM0_CH1 channels are mapped on PTA1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM0_CH1 channels are mapped on PTB3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM1PS0</name>
|
|
<description>FTM1_CH0 Port Pin Select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM1_CH0 channels are mapped on PTC4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM1_CH0 channels are mapped on PTH2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM1PS1</name>
|
|
<description>FTM1_CH1 Port Pin Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM1_CH1 channels are mapped on PTC5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM1_CH1 channels are mapped on PTE7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM0CLKPS</name>
|
|
<description>FTM0 TCLK Pin Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Selects TCLK0 for FTM0 module..</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Selects TCLK1 for FTM0 module.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Selects TCLK2 for FTM0 module.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM1CLKPS</name>
|
|
<description>FTM1 TCLK Pin Select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Selects TCLK0 for FTM1 module..</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Selects TCLK1 for FTM1 module.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Selects TCLK2 for FTM1 module.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2CLKPS</name>
|
|
<description>FTM2 TCLK Pin Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Selects TCLK0 for FTM2 module..</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Selects TCLK1 for FTM2 module.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Selects TCLK2 for FTM2 module.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTCLKPS</name>
|
|
<description>PWT TCLK Pin Select</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Selects TCLK0 for PWT module.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Selects TCLK1 for PWT module.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Selects TCLK2 for PWT module.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINSEL1</name>
|
|
<description>Pin Selection Register 1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTM2PS0</name>
|
|
<description>FTM2 Channel 0 Pin Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>FTM2 CH0 mapped on PTC0.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FTM2 CH0 mapped on PTH0.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FTM2 CH0 mapped on PTF0.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2PS1</name>
|
|
<description>FTM2 Channel 1 Pin Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>FTM2 CH1 mapped on PTC1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FTM2 CH1 mapped on PTH1.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FTM2 CH1 mapped on PTF1.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2PS2</name>
|
|
<description>FTM2 Channel 2 Pin Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>FTM2 CH2 mapped on PTC2.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FTM2 CH2 mapped on PTD0.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FTM2 CH2 mapped on PTG4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2PS3</name>
|
|
<description>FTM2 Channel 3 Pin Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>FTM2 CH3 mapped on PTC3.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FTM2 CH3 mapped on PTD1.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FTM2 CH3 mapped on PTG5.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2PS4</name>
|
|
<description>FTM2 Channel4 Pin Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM2 CH4 mapped on PTB4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM2 CH4 mapped on PTG6.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2PS5</name>
|
|
<description>FTM2 Channel 5 Pin Select</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM2 CH5 mapped on PTB5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM2 CH5 mapped on PTG7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C1PS</name>
|
|
<description>I2C1 Pin Select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C1_SCL on PTE1, I2C1_SDA on PTE0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C1_SCL on PTH4, I2C1_SDA on PTH3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI1PS</name>
|
|
<description>SPI1 Pin Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI1_SCK, SPI1_MOSI, SPI1_MISO, and SPI1_PCS are mapped on PTD0, PTD1, PTD2, and PTD3.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI1_SCK, SPI1_MOSI, SPI1_MISO, and SPI1_PCS are mapped on PTG4, PTG5, PTG6, and PTG7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART1PS</name>
|
|
<description>UART1 Pin Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART1_TX on PTC7, UART1_RX on PTC6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART1_TX on PTF3, UART1_RX on PTF2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART2PS</name>
|
|
<description>UART2 Pin Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART2_TX on PTD7, UART2_RX on PTD6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART2_TX on PTI1, UART2_RX on PTI0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTIN0PS</name>
|
|
<description>PWTIN0 Pin Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PWTIN0 on PTD5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PWTIN0 on PTE2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTIN1PS</name>
|
|
<description>PWTIN1 Pin Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PWTIN1 on PTB0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PWTIN1 on PTH7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSCANPS</name>
|
|
<description>MSCAN Pin Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CAN_TX on PTC7, CAN_RX on PTC6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CAN_TX on PTE7, CAN_RX on PTH2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC</name>
|
|
<description>System Clock Gating Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTC</name>
|
|
<description>RTC Clock Gate Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the RTC module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the RTC module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIT</name>
|
|
<description>PIT Clock Gate Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the PIT module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the PIT module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWT</name>
|
|
<description>PWT Clock Gate Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer clock to the PWT module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer clock to the PWT module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM0</name>
|
|
<description>FTM0 Clock Gate Control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the FTM0 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the FTM0 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM1</name>
|
|
<description>FTM1 Clock Gate Control</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the FTM1 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the FTM1 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2</name>
|
|
<description>FTM2 Clock Gate Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the FTM2 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the FTM2 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRC</name>
|
|
<description>CRC Clock Gate Control</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the CRC module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the CRC module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH</name>
|
|
<description>Flash Clock Gate Control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the flash module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the flash module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWD</name>
|
|
<description>SWD (single wire debugger) Clock Gate Control</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the SWD module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the SWD module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSCAN</name>
|
|
<description>MSCAN Clock Gate Control</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the MSCAN module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the MSCAN module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C0</name>
|
|
<description>I2C0 Clock Gate Control</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the I2C0 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the I2C0 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C1</name>
|
|
<description>I2C1 Clock Gate Control</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the I2C1 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the I2C1 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI0</name>
|
|
<description>SPI0 Clock Gate Control</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the SPI0 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the SPI0 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI1</name>
|
|
<description>SPI1 Clock Gate Control</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the SPI1 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the SPI1 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0</name>
|
|
<description>UART0 Clock Gate Control</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the UART0 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the UART0 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART1</name>
|
|
<description>UART1 Clock Gate Control</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the UART1 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the UART1 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART2</name>
|
|
<description>UART2 Clock Gate Control</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the UART2 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the UART2 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBI0</name>
|
|
<description>KBI0 Clock Gate Control</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the KBI0 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the KBI0 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBI1</name>
|
|
<description>KBI1 Clock Gate Control</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the KBI1 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the KBI1 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ</name>
|
|
<description>IRQ Clock Gate Control</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the IRQ module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the IRQ module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC</name>
|
|
<description>ADC Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the ADC module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the ADC module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP0</name>
|
|
<description>ACMP0 Clock Gate Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the ACMP0 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the ACMP0 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP1</name>
|
|
<description>ACMP1 Clock Gate Control</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus clock to the ACMP1 module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus clock to the ACMP1 module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UUIDL</name>
|
|
<description>Universally Unique Identifier Low Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Universally Unique Identifier</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UUIDML</name>
|
|
<description>Universally Unique Identifier Middle Low Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Universally Unique Identifier</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UUIDMH</name>
|
|
<description>Universally Unique Identifier Middle High Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Universally Unique Identifier</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Divider Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUTDIV3</name>
|
|
<description>Clock 3 output divider value</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Same as ICSOUTCLK.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ICSOUTCLK divides by 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTDIV2</name>
|
|
<description>Clock 2 output divider value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not divided from divider1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Divide by 2 from divider1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTDIV1</name>
|
|
<description>Clock 1 output divider value</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Same as ICSOUTCLK.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>ICSOUTCLK divides by 2.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>ICSOUTCLK divides by 3.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>ICSOUTCLK divides by 4.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORT</name>
|
|
<description>Port control and interrupts</description>
|
|
<prependToName>PORT_</prependToName>
|
|
<baseAddress>0x40049000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>IOFLT0</name>
|
|
<description>Port Filter Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC00000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLTA</name>
|
|
<description>Filter Selection for Input from PTA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>BUSCLK</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTB</name>
|
|
<description>Filter Selection for Input from PTB</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>BUSCLK</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTC</name>
|
|
<description>Filter Selection for Input from PTC</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>BUSCLK</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTD</name>
|
|
<description>Filter Selection for Input from PTD</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>BUSCLK</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTE</name>
|
|
<description>Filter Selection for Input from PTD</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>BUSCLK</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTF</name>
|
|
<description>Filter Selection for Input from PTF</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>BUSCLK</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTG</name>
|
|
<description>Filter Selection for Input from PTG</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>BUSCLK</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTH</name>
|
|
<description>Filter Selection for Input from PTH</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>BUSCLK</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTRST</name>
|
|
<description>Filter Selection for Input from RESET/IRQ</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No filter.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTKBI0</name>
|
|
<description>Filter selection for Input from KBI0</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No filter.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTKBI1</name>
|
|
<description>Filter Selection for Input from KBI1</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No filter</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTNMI</name>
|
|
<description>Filter Selection for Input from NMI</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No filter.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTDIV1</name>
|
|
<description>Filter Division Set 1</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>BUSCLK/2</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>BUSCLK/4</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>BUSCLK/8</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>BUSCLK/16</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTDIV2</name>
|
|
<description>Filter Division Set 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>BUSCLK/32</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>BUSCLK/64</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>BUSCLK/128</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>BUSCLK/256</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>BUSCLK/512</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>BUSCLK/1024</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>BUSCLK/2048</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>BUSCLK/4096</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTDIV3</name>
|
|
<description>Filter Division Set 3</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>LPOCLK</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>LPOCLK/2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>LPOCLK/4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>LPOCLK/8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>LPOCLK/16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>LPOCLK/32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>LPOCLK/64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>LPOCLK/128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOFLT1</name>
|
|
<description>Port Filter Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLTI</name>
|
|
<description>Filter Selection for Input from PTI</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>BUSCLK</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTIRQ</name>
|
|
<description>Filter Selection for Input from IRQ</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No filter</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTFTM0</name>
|
|
<description>Filter Selection For Input from FTM0CH0/FTM0CH1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No filter</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Select FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Select FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Select FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTFTM1</name>
|
|
<description>Filter Selection For Input from FTM1CH0/FTM1CH1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No filter</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Select FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Select FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Select FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTPWT</name>
|
|
<description>Filter Selection For Input from PWT_IN1/PWT_IN0</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No filter</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Select FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Select FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Select FLTDIV3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTI2C0</name>
|
|
<description>Filter Selection For Input from SCL0/SDA0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No filter</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Select FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Select FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Select BUSCLK</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLTI2C1</name>
|
|
<description>Filter Selection For Input from SCL1/SDA1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No filter</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Select FLTDIV1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Select FLTDIV2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Select BUSCLK</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUE0</name>
|
|
<description>Port Pullup Enable Register 0</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTAPE0</name>
|
|
<description>Pull Enable for Port A Bit 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port A bit 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port A bit 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTAPE1</name>
|
|
<description>Pull Enable for Port A Bit 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port A bit 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port A bit 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTAPE2</name>
|
|
<description>Pull Enable for Port A Bit 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port A bit 2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port A bit 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTAPE3</name>
|
|
<description>Pull Enable for Port A Bit 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port A bit 3.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port A bit 3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTAPE4</name>
|
|
<description>Pull Enable for Port A Bit 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port A bit 4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port A bit 4.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTAPE5</name>
|
|
<description>Pull Enable for Port A Bit 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port A bit 5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port A bit 5.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTAPE6</name>
|
|
<description>Pull Enable for Port A Bit 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port A bit 6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port A bit 6.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTAPE7</name>
|
|
<description>Pull Enable for Port A Bit 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port A bit 7.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port A bit 7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTBPE0</name>
|
|
<description>Pull Enable for Port B Bit 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port B bit 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port B bit 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTBPE1</name>
|
|
<description>Pull Enable for Port B Bit 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port B bit 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port B bit 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTBPE2</name>
|
|
<description>Pull Enable for Port B Bit 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port B bit 2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port B bit 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTBPE3</name>
|
|
<description>Pull Enable for Port B Bit 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port B bit 3.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port B bit 3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTBPE4</name>
|
|
<description>Pull Enable for Port B Bit 4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port B bit 4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port B bit 4.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTBPE5</name>
|
|
<description>Pull Enable for Port B Bit 5</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port B bit 5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port B bit 5.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTBPE6</name>
|
|
<description>Pull Enable for Port B Bit 6</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port B bit 6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port B bit 6.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTBPE7</name>
|
|
<description>Pull Enable for Port B Bit 7</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port B bit 7.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port B bit 7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTCPE0</name>
|
|
<description>Pull Enable for Port C Bit 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port C bit 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port C bit 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTCPE1</name>
|
|
<description>Pull Enable for Port C Bit 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port C bit 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port C bit 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTCPE2</name>
|
|
<description>Pull Enable for Port C Bit 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port C bit 2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port C bit 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTCPE3</name>
|
|
<description>Pull Enable for Port C Bit 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port C bit 3.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port C bit 3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTCPE4</name>
|
|
<description>Pull Enable for Port C Bit 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port C bit 4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port C bit 4.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTCPE5</name>
|
|
<description>Pull Enable for Port C Bit 5</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port C bit 5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port C bit 5.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTCPE6</name>
|
|
<description>Pull Enable for Port C Bit 6</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port C bit 6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port C bit 6.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTCPE7</name>
|
|
<description>Pull Enable for Port C Bit 7</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port C bit 7.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port C bit 7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTDPE0</name>
|
|
<description>Pull Enable for Port D Bit 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port D bit 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port D bit 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTDPE1</name>
|
|
<description>Pull Enable for Port D Bit 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port D bit 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port D bit 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTDPE2</name>
|
|
<description>Pull Enable for Port D Bit 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port D bit 2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port D bit 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTDPE3</name>
|
|
<description>Pull Enable for Port D Bit 3</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port D bit 3.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port D bit 3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTDPE4</name>
|
|
<description>Pull Enable for Port D Bit 4</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port D bit 4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port D bit 4.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTDPE5</name>
|
|
<description>Pull Enable for Port D Bit 5</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port D bit 5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port D bit 5.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTDPE6</name>
|
|
<description>Pull Enable for Port D Bit 6</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port D bit 6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port D bit 6.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTDPE7</name>
|
|
<description>Pull Enable for Port D Bit 7</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port D bit 7.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port D bit 7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUE1</name>
|
|
<description>Port Pullup Enable Register 1</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTEPE0</name>
|
|
<description>Pull Enable for Port E Bit 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port E bit 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port E bit 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTEPE1</name>
|
|
<description>Pull Enable for Port E Bit 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port E bit 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port E bit 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTEPE2</name>
|
|
<description>Pull Enable for Port E Bit 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port E bit 2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port E bit 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTEPE3</name>
|
|
<description>Pull Enable for Port E Bit 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port E bit 3.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port E bit 3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTEPE4</name>
|
|
<description>Pull Enable for Port E Bit 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port E bit 4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port E bit 4.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTEPE5</name>
|
|
<description>Pull Enable for Port E Bit 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port E bit 5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port E bit 5.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTEPE6</name>
|
|
<description>Pull Enable for Port E Bit 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port E bit 6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port E bit 6.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTEPE7</name>
|
|
<description>Pull Enable for Port E Bit 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port E bit 7.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port E bit 7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTFPE0</name>
|
|
<description>Pull Enable for Port F Bit 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port F bit 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port F bit 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTFPE1</name>
|
|
<description>Pull Enable for Port F Bit 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port F bit 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port F bit 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTFPE2</name>
|
|
<description>Pull Enable for Port F Bit 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port F bit 2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port F bit 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTFPE3</name>
|
|
<description>Pull Enable for Port F Bit 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port F bit 3.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port F bit 3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTFPE4</name>
|
|
<description>Pull Enable for Port F Bit 4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port F bit 4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port F bit 4.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTFPE5</name>
|
|
<description>Pull Enable for Port F Bit 5</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port F bit 5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port F bit 5.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTFPE6</name>
|
|
<description>Pull Enable for Port F Bit 6</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port F bit 6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port F bit 6.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTFPE7</name>
|
|
<description>Pull Enable for Port F Bit 7</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port F bit 7.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port F bit 7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTGPE0</name>
|
|
<description>Pull Enable for Port G Bit 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port G bit 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port G bit 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTGPE1</name>
|
|
<description>Pull Enable for Port G Bit 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port G bit 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port G bit 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTGPE2</name>
|
|
<description>Pull Enable for Port G Bit 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port G bit 2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port G bit 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTGPE3</name>
|
|
<description>Pull Enable for Port G Bit 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port G bit 3.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port G bit 3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTGPE4</name>
|
|
<description>Pull Enable for Port G Bit 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port G bit 4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port G bit 4.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTGPE5</name>
|
|
<description>Pull Enable for Port G Bit 5</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port G bit 5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port G bit 5.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTGPE6</name>
|
|
<description>Pull Enable for Port G Bit 6</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port G bit 6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port G bit 6.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTGPE7</name>
|
|
<description>Pull Enable for Port G Bit 7</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port G bit 7.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port G bit 7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTHPE0</name>
|
|
<description>Pull Enable for Port H Bit 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port H bit 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port H bit 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTHPE1</name>
|
|
<description>Pull Enable for Port H Bit 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port H bit 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port H bit 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTHPE2</name>
|
|
<description>Pull Enable for Port H Bit 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port H bit 2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port H bit 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTHPE3</name>
|
|
<description>Pull Enable for Port H Bit 3</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port H bit 3.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port H bit 3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTHPE4</name>
|
|
<description>Pull Enable for Port H Bit 4</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port H bit 4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port H bit 4.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTHPE5</name>
|
|
<description>Pull Enable for Port H Bit 5</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port H bit 5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port H bit 5.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTHPE6</name>
|
|
<description>Pull Enable for Port H Bit 6</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port H bit 6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port H bit 6.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTHPE7</name>
|
|
<description>Pull Enable for Port H Bit 7</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port H bit 7.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port H bit 7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUE2</name>
|
|
<description>Port Pullup Enable Register 2</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTIPE0</name>
|
|
<description>Pull Enable for Port I Bit 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port I bit 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port I bit 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTIPE1</name>
|
|
<description>Pull Enable for Port I Bit 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port I bit 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port I bit 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTIPE2</name>
|
|
<description>Pull Enable for Port I Bit 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port I bit 2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port I bit 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTIPE3</name>
|
|
<description>Pull Enable for Port I Bit 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port I bit 3.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port I bit 3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTIPE4</name>
|
|
<description>Pull Enable for Port I Bit 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port I bit 4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port I bit 4.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTIPE5</name>
|
|
<description>Pull Enable for Port I Bit 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port I bit 5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port I bit 5.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTIPE6</name>
|
|
<description>Pull Enable for Port I Bit 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pullup is disabled for port I bit 6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pullup is enabled for port I bit 6.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HDRVE</name>
|
|
<description>Port High Drive Enable Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTB4</name>
|
|
<description>High Current Drive Capability of PTB4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PTB4 is disabled to offer high current drive capability.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PTB4 is enabled to offer high current drive capability.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTB5</name>
|
|
<description>High Current Drive Capability of PTB5</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PTB5 is disabled to offer high current drive capability.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PTB5 is enabled to offer high current drive capability.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTD0</name>
|
|
<description>High Current Drive Capability of PTD0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PTD0 is disabled to offer high current drive capability.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PTD0 is enabled to offer high current drive capability.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTD1</name>
|
|
<description>High Current Drive Capability of PTD1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PTD1 is disabled to offer high current drive capability.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PTD1 is enable to offer high current drive capability.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTE0</name>
|
|
<description>High Current Drive Capability of PTE0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PTE0 is disabled to offer high current drive capability.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PTE0 is enable to offer high current drive capability.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTE1</name>
|
|
<description>High Current Drive Capability of PTE1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PTE1 is disabled to offer high current drive capability.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PTE1 is enabled to offer high current drive capability.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTH0</name>
|
|
<description>High Current Drive Capability of PTH0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PTH0 is disabled to offer high current drive capability.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PTH0 is enabled to offer high current drive capability.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTH1</name>
|
|
<description>High Current Drive Capability of PTH1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PTH1 is disabled to offer high current drive capability.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PTH1 is enabled to offer high current drive capability.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WDOG</name>
|
|
<description>Watchdog timer</description>
|
|
<prependToName>WDOG_</prependToName>
|
|
<baseAddress>0x40052000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WDOG_EWM</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CS1</name>
|
|
<description>Watchdog Control and Status Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Watchdog disabled in chip stop mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Watchdog enabled in chip stop mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAIT</name>
|
|
<description>Wait Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Watchdog disabled in chip wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Watchdog enabled in chip wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBG</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Watchdog disabled in chip debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Watchdog enabled in chip debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TST</name>
|
|
<description>Watchdog Test</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Watchdog test mode disabled.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Watchdog test mode enabled, only the low byte is used. WDOG_CNTL is compared with WDOG_TOVALL.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Watchdog test mode enabled, only the high byte is used. WDOG_CNTH is compared with WDOG_TOVALH.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>Allow updates</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT</name>
|
|
<description>Watchdog Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Watchdog interrupts are disabled. Watchdog resets are not delayed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Watchdog Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Watchdog disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Watchdog enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CS2</name>
|
|
<description>Watchdog Control and Status Register 2</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLK</name>
|
|
<description>Watchdog Clock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Bus clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>1 kHz internal low-power oscillator (LPOCLK).</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>32 kHz internal oscillator (ICSIRCLK).</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External clock source.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRES</name>
|
|
<description>Watchdog Prescalar</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>256 prescalar disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>256 prescalar enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLG</name>
|
|
<description>Watchdog Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An interrupt occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WIN</name>
|
|
<description>Watchdog Window</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Window mode disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Window mode enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Watchdog Counter Register.</description>
|
|
<alternateGroup>WDOG</alternateGroup>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Watchdog Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTH</name>
|
|
<description>Watchdog Counter Register: High</description>
|
|
<alternateGroup>WDOG</alternateGroup>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTHIGH</name>
|
|
<description>High byte of the Watchdog Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTL</name>
|
|
<description>Watchdog Counter Register: Low</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTLOW</name>
|
|
<description>Low byte of the Watchdog Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOVAL</name>
|
|
<description>Watchdog Timeout Value Register.</description>
|
|
<alternateGroup>WDOG</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOVAL</name>
|
|
<description>Watchdog Timeout Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOVALH</name>
|
|
<description>Watchdog Timeout Value Register: High</description>
|
|
<alternateGroup>WDOG</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOVALHIGH</name>
|
|
<description>High byte of the timeout value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOVALL</name>
|
|
<description>Watchdog Timeout Value Register: Low</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOVALLOW</name>
|
|
<description>Low byte of the timeout value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WIN</name>
|
|
<description>Watchdog Window Register.</description>
|
|
<alternateGroup>WDOG</alternateGroup>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WIN</name>
|
|
<description>Watchdog Window Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINH</name>
|
|
<description>Watchdog Window Register: High</description>
|
|
<alternateGroup>WDOG</alternateGroup>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINHIGH</name>
|
|
<description>High byte of Watchdog Window</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINL</name>
|
|
<description>Watchdog Window Register: Low</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINLOW</name>
|
|
<description>Low byte of Watchdog Window</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ICS</name>
|
|
<description>Clock management</description>
|
|
<prependToName>ICS_</prependToName>
|
|
<baseAddress>0x40064000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ICS</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>ICS Control Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IREFSTEN</name>
|
|
<description>Internal Reference Stop Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal reference clock is disabled in Stop mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal reference clock stays enabled in Stop mode if IRCLKEN is set, or if ICS is in FEI, FBI, or FBILP mode before entering Stop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRCLKEN</name>
|
|
<description>Internal Reference Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ICSIRCLK is inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ICSIRCLK is active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREFS</name>
|
|
<description>Internal Reference Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External reference clock is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal reference clock is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDIV</name>
|
|
<description>Reference Divider</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Output of FLL is selected.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Internal reference clock is selected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External reference clock is selected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Reserved, defaults to 00.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>ICS Control Register 2</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LP</name>
|
|
<description>Low Power Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FLL is not disabled in bypass mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FLL is disabled in bypass modes unless debug is active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BDIV</name>
|
|
<description>Bus Frequency Divider</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Encoding 0-Divides the selected clock by 1.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Encoding 1-Divides the selected clock by 2 (reset default).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Encoding 2-Divides the selected clock by 4.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Encoding 3-Divides the selected clock by 8.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Encoding 4-Divides the selected clock by 16.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Encoding 5-Divides the selected clock by 32.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Encoding 6-Divides the selected clock by 64.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Encoding 7-Divides the selected clock by 128.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>ICS Control Register 3</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCTRIM</name>
|
|
<description>Slow Internal Reference Clock Trim Setting</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4</name>
|
|
<description>ICS Control Register 4</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCFTRIM</name>
|
|
<description>Slow Internal Reference Clock Fine Trim</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CME</name>
|
|
<description>Clock Monitor Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock monitor is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generates a reset request on loss of external clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOLIE</name>
|
|
<description>Loss of Lock Interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No request on loss of lock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Generates an interrupt request on loss of lock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S</name>
|
|
<description>ICS Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKST</name>
|
|
<description>Clock Mode Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Output of FLL is selected.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FLL Bypassed, internal reference clock is selected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FLL Bypassed, external reference clock is selected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREFST</name>
|
|
<description>Internal Reference Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Source of reference clock is external clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Source of reference clock is internal clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FLL is currently unlocked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FLL is currently locked.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOLS</name>
|
|
<description>Loss of Lock Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FLL has not lost lock since LOLS was last cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FLL has lost lock since LOLS was last cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OSC</name>
|
|
<description>Oscillator</description>
|
|
<prependToName>OSC_</prependToName>
|
|
<baseAddress>0x40065000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>OSC Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OSCINIT</name>
|
|
<description>OSC Initialization</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Oscillator initialization is not complete.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Oscillator initialization is completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HGO</name>
|
|
<description>High Gain Oscillator Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low-power mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High-gain mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RANGE</name>
|
|
<description>Frequency Range Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low frequency range of 32 kHz.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High frequency range of 4-24 MHz.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCOS</name>
|
|
<description>OSC Output Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External clock source from EXTAL pin is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Oscillator clock source is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCSTEN</name>
|
|
<description>OSC Enable in Stop mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OSC clock is disabled in Stop mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSC clock stays enabled in Stop mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCEN</name>
|
|
<description>OSC Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OSC module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSC module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C0</name>
|
|
<description>Inter-Integrated Circuit</description>
|
|
<groupName>I2C</groupName>
|
|
<prependToName>I2C0_</prependToName>
|
|
<baseAddress>0x40066000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C0</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>A1</name>
|
|
<description>I2C Address Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F</name>
|
|
<description>I2C Frequency Divider register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICR</name>
|
|
<description>ClockRate</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MULT</name>
|
|
<description>Multiplier Factor</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>mul = 1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>mul = 2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>mul = 4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>I2C Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUEN</name>
|
|
<description>Wakeup Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the wakeup function in low power mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTA</name>
|
|
<description>Repeat START</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXAK</name>
|
|
<description>Transmit Acknowledge Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>Transmit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MST</name>
|
|
<description>Master Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIE</name>
|
|
<description>I2C Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICEN</name>
|
|
<description>I2C Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>I2C Status register 1</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXAK</name>
|
|
<description>Receive Acknowledge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIF</name>
|
|
<description>Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRW</name>
|
|
<description>Slave Read/Write</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave receive, master writing to slave</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave transmit, master reading from slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAM</name>
|
|
<description>Range Address Match</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBL</name>
|
|
<description>Arbitration Lost</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard bus operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loss of arbitration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Bus Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus is idle</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus is busy</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IAAS</name>
|
|
<description>Addressed As A Slave</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer Complete Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer complete</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>I2C Data I/O register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>I2C Control Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Slave Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMEN</name>
|
|
<description>Range Address Matching Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBRC</name>
|
|
<description>Slave Baud Rate Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave baud rate is independent of the master baud rate</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADEXT</name>
|
|
<description>Address Extension</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>7-bit address scheme</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>10-bit address scheme</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCAEN</name>
|
|
<description>General Call Address Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLT</name>
|
|
<description>I2C Programmable Input Glitch Filter register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT</name>
|
|
<description>I2C Programmable Filter Factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No filter/bypass</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>I2C Bus Start Detect Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No start happens on I2C bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Start detected on I2C bus</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSIE</name>
|
|
<description>I2C Bus Stop or Start Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop or start detection interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop or start detection interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPF</name>
|
|
<description>I2C Bus Stop Detect Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No stop happens on I2C bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop detected on I2C bus</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHEN</name>
|
|
<description>Stop Hold Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop holdoff is disabled. The MCU's entry to stop mode is not gated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop holdoff is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RA</name>
|
|
<description>I2C Range Address register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAD</name>
|
|
<description>Range Slave Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMB</name>
|
|
<description>I2C SMBus Control and Status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHTF2IE</name>
|
|
<description>SHTF2 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SHTF2 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SHTF2 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHTF2</name>
|
|
<description>SCL High Timeout Flag 2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No SCL high and SDA low timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SCL high and SDA low timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHTF1</name>
|
|
<description>SCL High Timeout Flag 1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No SCL high and SDA high timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SCL high and SDA high timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLTF</name>
|
|
<description>SCL Low Timeout Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No low timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCKSEL</name>
|
|
<description>Timeout Counter Clock Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timeout counter counts at the frequency of the I2C module clock / 64</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout counter counts at the frequency of the I2C module clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIICAEN</name>
|
|
<description>Second I2C Address Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C address register 2 matching is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C address register 2 matching is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERTEN</name>
|
|
<description>SMBus Alert Response Address Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SMBus alert response address matching is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SMBus alert response address matching is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FACK</name>
|
|
<description>Fast NACK/ACK Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An ACK or NACK is sent on the following receiving data byte</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>A2</name>
|
|
<description>I2C Address Register 2</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC2</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SAD</name>
|
|
<description>SMBus Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLTH</name>
|
|
<description>I2C SCL Low Timeout Register High</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSLT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLTL</name>
|
|
<description>I2C SCL Low Timeout Register Low</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSLT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C1</name>
|
|
<description>Inter-Integrated Circuit</description>
|
|
<groupName>I2C</groupName>
|
|
<prependToName>I2C1_</prependToName>
|
|
<baseAddress>0x40067000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C1</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>A1</name>
|
|
<description>I2C Address Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F</name>
|
|
<description>I2C Frequency Divider register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICR</name>
|
|
<description>ClockRate</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MULT</name>
|
|
<description>Multiplier Factor</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>mul = 1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>mul = 2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>mul = 4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>I2C Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUEN</name>
|
|
<description>Wakeup Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the wakeup function in low power mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTA</name>
|
|
<description>Repeat START</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXAK</name>
|
|
<description>Transmit Acknowledge Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>Transmit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MST</name>
|
|
<description>Master Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIE</name>
|
|
<description>I2C Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICEN</name>
|
|
<description>I2C Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>I2C Status register 1</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXAK</name>
|
|
<description>Receive Acknowledge</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No acknowledge signal detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IICIF</name>
|
|
<description>Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRW</name>
|
|
<description>Slave Read/Write</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave receive, master writing to slave</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave transmit, master reading from slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAM</name>
|
|
<description>Range Address Match</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBL</name>
|
|
<description>Arbitration Lost</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard bus operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loss of arbitration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Bus Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bus is idle</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bus is busy</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IAAS</name>
|
|
<description>Addressed As A Slave</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Not addressed</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Addressed as a slave</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer Complete Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer complete</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>I2C Data I/O register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>I2C Control Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD</name>
|
|
<description>Slave Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMEN</name>
|
|
<description>Range Address Matching Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBRC</name>
|
|
<description>Slave Baud Rate Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave baud rate is independent of the master baud rate</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADEXT</name>
|
|
<description>Address Extension</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>7-bit address scheme</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>10-bit address scheme</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCAEN</name>
|
|
<description>General Call Address Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLT</name>
|
|
<description>I2C Programmable Input Glitch Filter register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT</name>
|
|
<description>I2C Programmable Filter Factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No filter/bypass</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>I2C Bus Start Detect Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No start happens on I2C bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Start detected on I2C bus</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSIE</name>
|
|
<description>I2C Bus Stop or Start Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop or start detection interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop or start detection interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPF</name>
|
|
<description>I2C Bus Stop Detect Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No stop happens on I2C bus</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop detected on I2C bus</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHEN</name>
|
|
<description>Stop Hold Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Stop holdoff is disabled. The MCU's entry to stop mode is not gated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stop holdoff is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RA</name>
|
|
<description>I2C Range Address register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAD</name>
|
|
<description>Range Slave Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMB</name>
|
|
<description>I2C SMBus Control and Status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHTF2IE</name>
|
|
<description>SHTF2 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SHTF2 interrupt is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SHTF2 interrupt is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHTF2</name>
|
|
<description>SCL High Timeout Flag 2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No SCL high and SDA low timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SCL high and SDA low timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHTF1</name>
|
|
<description>SCL High Timeout Flag 1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No SCL high and SDA high timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SCL high and SDA high timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLTF</name>
|
|
<description>SCL Low Timeout Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No low timeout occurs</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low timeout occurs</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCKSEL</name>
|
|
<description>Timeout Counter Clock Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timeout counter counts at the frequency of the I2C module clock / 64</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout counter counts at the frequency of the I2C module clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIICAEN</name>
|
|
<description>Second I2C Address Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C address register 2 matching is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C address register 2 matching is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERTEN</name>
|
|
<description>SMBus Alert Response Address Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SMBus alert response address matching is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SMBus alert response address matching is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FACK</name>
|
|
<description>Fast NACK/ACK Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An ACK or NACK is sent on the following receiving data byte</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>A2</name>
|
|
<description>I2C Address Register 2</description>
|
|
<addressOffset>0x9</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC2</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SAD</name>
|
|
<description>SMBus Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLTH</name>
|
|
<description>I2C SCL Low Timeout Register High</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSLT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLTL</name>
|
|
<description>I2C SCL Low Timeout Register Low</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSLT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART0</name>
|
|
<description>Universal Asynchronous Receiver/Transmitter (UART)</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART0_</prependToName>
|
|
<baseAddress>0x4006A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART0</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BDH</name>
|
|
<description>UART Baud Rate Register: High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SBNS</name>
|
|
<description>Stop Bit Number Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One stop bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Two stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RxD Input Active Edge Interrupt Enable (for RXEDGIF)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable (for LBKDIF)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDL</name>
|
|
<description>UART Baud Rate Register: Low</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>UART Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No hardware parity generation or checking.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle-line wake-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address-mark wake-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-Bit or 8-Bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal - start + 8 data bits (lsb first) + stop.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UARTSWAI</name>
|
|
<description>UART Stops in Wait Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART clocks continue to run in Wait mode so the UART can be the source of an interrupt that wakes up the CPU.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART clocks freeze while CPU is in Wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation - RxD and TxD use separate pins.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>UART Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal UART receiver operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver in standby waiting for wake-up condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable for IDLE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from S1[IDLE] disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when S1[IDLE] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Interrupt Enable for RDRF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from S1[RDRF] disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when S1[RDRF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable for TC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TC disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TC flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable for TDRE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TDRE disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TDRE flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>UART Status Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected. This does not guarantee the framing is correct.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Noise detected in the received character in UART_D.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive overrun (new UART data lost).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No idle line detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle line was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data register empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data register full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmission Complete Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data register (buffer) full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data register (buffer) empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S2</name>
|
|
<description>UART Status Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART receiver idle waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver active (RxD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break detection is enabled (Break character is detected at length 11 bit times (if C1[M] = 0, BDH[SBNS] = 0) or 12 (if C1[M] = 1, BDH[SBNS] = 0 or C1[M] = 0, BDH[SBNS] = 1) or 13 (if C1[M] = 1, BDH[SBNS] = 1)).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Character Generation Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wake Up Idle Detect</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>During receive standby state (RWU = 1), S1[IDLE] does not get set upon detection of an idle character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>During receive standby state (RWU = 1), S1[IDLE] gets set upon detection of an idle character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RxD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>UART Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when PF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when FE is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when NF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when OR is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>TxD Pin Direction in Single-Wire Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TxD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TxD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T8</name>
|
|
<description>Ninth Data Bit for Transmitter</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8</name>
|
|
<description>Ninth Data Bit for Receiver</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>UART Data Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R0T0</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R1T1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R2T2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R3T3</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R4T4</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R5T5</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R6T6</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R7T7</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART1</name>
|
|
<description>Universal Asynchronous Receiver/Transmitter (UART)</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART1_</prependToName>
|
|
<baseAddress>0x4006B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART1</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BDH</name>
|
|
<description>UART Baud Rate Register: High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SBNS</name>
|
|
<description>Stop Bit Number Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One stop bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Two stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RxD Input Active Edge Interrupt Enable (for RXEDGIF)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable (for LBKDIF)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDL</name>
|
|
<description>UART Baud Rate Register: Low</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>UART Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No hardware parity generation or checking.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle-line wake-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address-mark wake-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-Bit or 8-Bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal - start + 8 data bits (lsb first) + stop.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UARTSWAI</name>
|
|
<description>UART Stops in Wait Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART clocks continue to run in Wait mode so the UART can be the source of an interrupt that wakes up the CPU.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART clocks freeze while CPU is in Wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation - RxD and TxD use separate pins.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>UART Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal UART receiver operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver in standby waiting for wake-up condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable for IDLE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from S1[IDLE] disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when S1[IDLE] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Interrupt Enable for RDRF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from S1[RDRF] disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when S1[RDRF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable for TC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TC disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TC flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable for TDRE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TDRE disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TDRE flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>UART Status Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected. This does not guarantee the framing is correct.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Noise detected in the received character in UART_D.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive overrun (new UART data lost).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No idle line detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle line was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data register empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data register full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmission Complete Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data register (buffer) full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data register (buffer) empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S2</name>
|
|
<description>UART Status Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART receiver idle waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver active (RxD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break detection is enabled (Break character is detected at length 11 bit times (if C1[M] = 0, BDH[SBNS] = 0) or 12 (if C1[M] = 1, BDH[SBNS] = 0 or C1[M] = 0, BDH[SBNS] = 1) or 13 (if C1[M] = 1, BDH[SBNS] = 1)).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Character Generation Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wake Up Idle Detect</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>During receive standby state (RWU = 1), S1[IDLE] does not get set upon detection of an idle character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>During receive standby state (RWU = 1), S1[IDLE] gets set upon detection of an idle character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RxD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>UART Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when PF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when FE is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when NF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when OR is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>TxD Pin Direction in Single-Wire Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TxD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TxD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T8</name>
|
|
<description>Ninth Data Bit for Transmitter</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8</name>
|
|
<description>Ninth Data Bit for Receiver</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>UART Data Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R0T0</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R1T1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R2T2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R3T3</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R4T4</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R5T5</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R6T6</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R7T7</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART2</name>
|
|
<description>Universal Asynchronous Receiver/Transmitter (UART)</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART2_</prependToName>
|
|
<baseAddress>0x4006C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART2</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BDH</name>
|
|
<description>UART Baud Rate Register: High</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SBNS</name>
|
|
<description>Stop Bit Number Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One stop bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Two stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RxD Input Active Edge Interrupt Enable (for RXEDGIF)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable (for LBKDIF)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDL</name>
|
|
<description>UART Baud Rate Register: Low</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>UART Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No hardware parity generation or checking.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle-line wake-up.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address-mark wake-up.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-Bit or 8-Bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal - start + 8 data bits (lsb first) + stop.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UARTSWAI</name>
|
|
<description>UART Stops in Wait Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART clocks continue to run in Wait mode so the UART can be the source of an interrupt that wakes up the CPU.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART clocks freeze while CPU is in Wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation - RxD and TxD use separate pins.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>UART Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal UART receiver operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver in standby waiting for wake-up condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable for IDLE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from S1[IDLE] disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when S1[IDLE] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Interrupt Enable for RDRF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from S1[RDRF] disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when S1[RDRF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable for TC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TC disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TC flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable for TDRE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TDRE disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TDRE flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S1</name>
|
|
<description>UART Status Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected. This does not guarantee the framing is correct.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Noise detected in the received character in UART_D.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive overrun (new UART data lost).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No idle line detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle line was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data register empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data register full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmission Complete Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data register (buffer) full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data register (buffer) empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S2</name>
|
|
<description>UART Status Register 2</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>UART receiver idle waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>UART receiver active (RxD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break detection is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break detection is enabled (Break character is detected at length 11 bit times (if C1[M] = 0, BDH[SBNS] = 0) or 12 (if C1[M] = 1, BDH[SBNS] = 0 or C1[M] = 0, BDH[SBNS] = 1) or 13 (if C1[M] = 1, BDH[SBNS] = 1)).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Character Generation Length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wake Up Idle Detect</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>During receive standby state (RWU = 1), S1[IDLE] does not get set upon detection of an idle character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>During receive standby state (RWU = 1), S1[IDLE] gets set upon detection of an idle character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RxD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3</name>
|
|
<description>UART Control Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when PF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when FE is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when NF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when OR is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>TxD Pin Direction in Single-Wire Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TxD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TxD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T8</name>
|
|
<description>Ninth Data Bit for Transmitter</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8</name>
|
|
<description>Ninth Data Bit for Receiver</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>UART Data Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R0T0</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R1T1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R2T2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R3T3</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R4T4</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R5T5</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R6T6</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R7T7</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ACMP0</name>
|
|
<description>Analog comparator</description>
|
|
<groupName>ACMP</groupName>
|
|
<prependToName>ACMP0_</prependToName>
|
|
<baseAddress>0x40073000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ACMP0</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CS</name>
|
|
<description>ACMP Control and Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMOD</name>
|
|
<description>ACMP MOD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>ACMP interrupt on output falling edge.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>ACMP interrupt on output rising edge.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>ACMP interrupt on output falling edge.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>ACMP interrupt on output falling or rising edge.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACOPE</name>
|
|
<description>ACMP Output Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ACMP output cannot be placed onto external pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ACMP output can be placed onto external pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACO</name>
|
|
<description>ACMP Output</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACIE</name>
|
|
<description>ACMP Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the ACMP Interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the ACMP Interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACF</name>
|
|
<description>ACMP Interrupt Flag Bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>Analog Comparator Hysterisis Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>20 mV.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>30 mV.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACE</name>
|
|
<description>Analog Comparator Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The ACMP is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The ACMP is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C0</name>
|
|
<description>ACMP Control Register 0</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACNSEL</name>
|
|
<description>ACMP Negative Input Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External reference 0</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External reference 1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External reference 2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>DAC output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACPSEL</name>
|
|
<description>ACMP Positive Input Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External reference 0</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External reference 1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External reference 2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>DAC output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>ACMP Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DACVAL</name>
|
|
<description>DAC Output Level Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACREF</name>
|
|
<description>DAC Reference Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC selects Bandgap as the reference.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC selects VDDA as the reference.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>ACMP Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACIPE</name>
|
|
<description>ACMP Input Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding external analog input is not allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding external analog input is allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ACMP1</name>
|
|
<description>Analog comparator</description>
|
|
<groupName>ACMP</groupName>
|
|
<prependToName>ACMP1_</prependToName>
|
|
<baseAddress>0x40074000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ACMP1</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CS</name>
|
|
<description>ACMP Control and Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMOD</name>
|
|
<description>ACMP MOD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>ACMP interrupt on output falling edge.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>ACMP interrupt on output rising edge.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>ACMP interrupt on output falling edge.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>ACMP interrupt on output falling or rising edge.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACOPE</name>
|
|
<description>ACMP Output Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>ACMP output cannot be placed onto external pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>ACMP output can be placed onto external pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACO</name>
|
|
<description>ACMP Output</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACIE</name>
|
|
<description>ACMP Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable the ACMP Interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable the ACMP Interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACF</name>
|
|
<description>ACMP Interrupt Flag Bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>Analog Comparator Hysterisis Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>20 mV.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>30 mV.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACE</name>
|
|
<description>Analog Comparator Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The ACMP is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The ACMP is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C0</name>
|
|
<description>ACMP Control Register 0</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACNSEL</name>
|
|
<description>ACMP Negative Input Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External reference 0</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External reference 1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External reference 2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>DAC output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACPSEL</name>
|
|
<description>ACMP Positive Input Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>External reference 0</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>External reference 1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>External reference 2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>DAC output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>ACMP Control Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DACVAL</name>
|
|
<description>DAC Output Level Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACREF</name>
|
|
<description>DAC Reference Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC selects Bandgap as the reference.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC selects VDDA as the reference.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DAC is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DAC is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>ACMP Control Register 2</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACIPE</name>
|
|
<description>ACMP Input Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The corresponding external analog input is not allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The corresponding external analog input is allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI0</name>
|
|
<description>Serial Peripheral Interface</description>
|
|
<groupName>SPI</groupName>
|
|
<prependToName>SPI0_</prependToName>
|
|
<baseAddress>0x40076000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI0</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>SPI Control Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LSBFE</name>
|
|
<description>LSB First (shifter direction)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI serial data transfers start with the most significant bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI serial data transfers start with the least significant bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSOE</name>
|
|
<description>Slave Select Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>First edge on SPSCK occurs at the middle of the first cycle of a data transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>First edge on SPSCK occurs at the start of the first cycle of a data transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Active-high SPI clock (idles low)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Active-low SPI clock (idles high)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>Master/Slave Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI module configured as a slave SPI device</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI module configured as a master SPI device</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPTIE</name>
|
|
<description>SPI Transmit Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts from SPTEF inhibited (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When SPTEF is 1, hardware interrupt requested</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPE</name>
|
|
<description>SPI System Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI system inactive</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI system enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIE</name>
|
|
<description>SPI Interrupt Enable: for SPRF and MODF</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts from SPRF and MODF are inhibited-use polling</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request a hardware interrupt when SPRF or MODF is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>SPI Control Register 2</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPC0</name>
|
|
<description>SPI Pin Control 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPISWAI</name>
|
|
<description>SPI Stop in Wait Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI clocks continue to operate in Wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI clocks stop when the MCU enters Wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIDIROE</name>
|
|
<description>Bidirectional Mode Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output driver disabled so SPI data I/O pin acts as an input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI I/O pin enabled as an output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODFEN</name>
|
|
<description>Master Mode-Fault Function Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPMIE</name>
|
|
<description>SPI Match Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts from SPMF inhibited (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When SPMF is 1, requests a hardware interrupt</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BR</name>
|
|
<description>SPI Baud Rate Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPR</name>
|
|
<description>SPI Baud Rate Divisor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Baud rate divisor is 2.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Baud rate divisor is 4.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Baud rate divisor is 8.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Baud rate divisor is 16.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Baud rate divisor is 32.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Baud rate divisor is 64.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Baud rate divisor is 128.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Baud rate divisor is 256.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Baud rate divisor is 512.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPPR</name>
|
|
<description>SPI Baud Rate Prescale Divisor</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Baud rate prescaler divisor is 1.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Baud rate prescaler divisor is 2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Baud rate prescaler divisor is 3.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Baud rate prescaler divisor is 4.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Baud rate prescaler divisor is 5.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Baud rate prescaler divisor is 6.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Baud rate prescaler divisor is 7.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Baud rate prescaler divisor is 8.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S</name>
|
|
<description>SPI Status Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Master Mode Fault Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No mode fault error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mode fault error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPTEF</name>
|
|
<description>SPI Transmit Buffer Empty Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI transmit buffer not empty</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI transmit buffer empty</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPMF</name>
|
|
<description>SPI Match Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Value in the receive data buffer does not match the value in the M register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Value in the receive data buffer matches the value in the M register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPRF</name>
|
|
<description>SPI Read Buffer Full Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No data available in the receive data buffer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data available in the receive data buffer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>SPI Data Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Bits</name>
|
|
<description>Data (low byte)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M</name>
|
|
<description>SPI Match Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Bits</name>
|
|
<description>Hardware compare value (low byte)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI1</name>
|
|
<description>Serial Peripheral Interface</description>
|
|
<groupName>SPI</groupName>
|
|
<prependToName>SPI1_</prependToName>
|
|
<baseAddress>0x40077000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI1</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>SPI Control Register 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LSBFE</name>
|
|
<description>LSB First (shifter direction)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI serial data transfers start with the most significant bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI serial data transfers start with the least significant bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSOE</name>
|
|
<description>Slave Select Output Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>First edge on SPSCK occurs at the middle of the first cycle of a data transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>First edge on SPSCK occurs at the start of the first cycle of a data transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Active-high SPI clock (idles low)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Active-low SPI clock (idles high)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>Master/Slave Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI module configured as a slave SPI device</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI module configured as a master SPI device</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPTIE</name>
|
|
<description>SPI Transmit Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts from SPTEF inhibited (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When SPTEF is 1, hardware interrupt requested</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPE</name>
|
|
<description>SPI System Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI system inactive</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI system enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIE</name>
|
|
<description>SPI Interrupt Enable: for SPRF and MODF</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts from SPRF and MODF are inhibited-use polling</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request a hardware interrupt when SPRF or MODF is 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>SPI Control Register 2</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPC0</name>
|
|
<description>SPI Pin Control 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPISWAI</name>
|
|
<description>SPI Stop in Wait Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI clocks continue to operate in Wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI clocks stop when the MCU enters Wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIDIROE</name>
|
|
<description>Bidirectional Mode Output Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output driver disabled so SPI data I/O pin acts as an input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI I/O pin enabled as an output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODFEN</name>
|
|
<description>Master Mode-Fault Function Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPMIE</name>
|
|
<description>SPI Match Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupts from SPMF inhibited (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When SPMF is 1, requests a hardware interrupt</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BR</name>
|
|
<description>SPI Baud Rate Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPR</name>
|
|
<description>SPI Baud Rate Divisor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Baud rate divisor is 2.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Baud rate divisor is 4.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Baud rate divisor is 8.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Baud rate divisor is 16.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Baud rate divisor is 32.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Baud rate divisor is 64.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Baud rate divisor is 128.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Baud rate divisor is 256.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Baud rate divisor is 512.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPPR</name>
|
|
<description>SPI Baud Rate Prescale Divisor</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Baud rate prescaler divisor is 1.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Baud rate prescaler divisor is 2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Baud rate prescaler divisor is 3.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Baud rate prescaler divisor is 4.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Baud rate prescaler divisor is 5.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Baud rate prescaler divisor is 6.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Baud rate prescaler divisor is 7.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Baud rate prescaler divisor is 8.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>S</name>
|
|
<description>SPI Status Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Master Mode Fault Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No mode fault error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Mode fault error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPTEF</name>
|
|
<description>SPI Transmit Buffer Empty Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SPI transmit buffer not empty</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SPI transmit buffer empty</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPMF</name>
|
|
<description>SPI Match Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Value in the receive data buffer does not match the value in the M register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Value in the receive data buffer matches the value in the M register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPRF</name>
|
|
<description>SPI Read Buffer Full Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No data available in the receive data buffer</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data available in the receive data buffer</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>D</name>
|
|
<description>SPI Data Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Bits</name>
|
|
<description>Data (low byte)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M</name>
|
|
<description>SPI Match Register</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Bits</name>
|
|
<description>Hardware compare value (low byte)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>KBI0</name>
|
|
<description>Keyboard interrupts</description>
|
|
<groupName>KBI</groupName>
|
|
<prependToName>KBI0_</prependToName>
|
|
<baseAddress>0x40079000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>KBI0</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PE</name>
|
|
<description>KBI Pin Enable Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KBIPE</name>
|
|
<description>KBI Pin Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is not enabled as KBI interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is enabled as KBI interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ES</name>
|
|
<description>KBI Edge Select Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KBEDG</name>
|
|
<description>KBI Edge Selects</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Falling edge/low level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rising edge/high level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>KBI Status and Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KBMOD</name>
|
|
<description>KBI Detection Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Keyboard detects edges only.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Keyboard detects both edges and levels.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBIE</name>
|
|
<description>KBI Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>KBI interrupt not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>KBI interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBACK</name>
|
|
<description>KBI Acknowledge</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>KBF</name>
|
|
<description>KBI Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>KBI interrupt request not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>KBI interrupt request detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBSPEN</name>
|
|
<description>Real KBI_SP register enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The real time value of Keyboard source pin to be read.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The latched value in KBxSP register while interrupt flag occur to be read.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTKBSP</name>
|
|
<description>Reset KBI_SP registe</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SP</name>
|
|
<description>KBI Source Pin Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SP</name>
|
|
<description>KBI Source Pin</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>KBI1</name>
|
|
<description>Keyboard interrupts</description>
|
|
<groupName>KBI</groupName>
|
|
<prependToName>KBI1_</prependToName>
|
|
<baseAddress>0x4007A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>KBI1</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PE</name>
|
|
<description>KBI Pin Enable Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KBIPE</name>
|
|
<description>KBI Pin Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is not enabled as KBI interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is enabled as KBI interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ES</name>
|
|
<description>KBI Edge Select Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KBEDG</name>
|
|
<description>KBI Edge Selects</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Falling edge/low level.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Rising edge/high level.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>KBI Status and Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KBMOD</name>
|
|
<description>KBI Detection Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Keyboard detects edges only.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Keyboard detects both edges and levels.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBIE</name>
|
|
<description>KBI Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>KBI interrupt not enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>KBI interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBACK</name>
|
|
<description>KBI Acknowledge</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>KBF</name>
|
|
<description>KBI Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>KBI interrupt request not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>KBI interrupt request detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBSPEN</name>
|
|
<description>Real KBI_SP register enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The real time value of Keyboard source pin to be read.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The latched value in KBxSP register while interrupt flag occur to be read.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTKBSP</name>
|
|
<description>Reset KBI_SP registe</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SP</name>
|
|
<description>KBI Source Pin Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SP</name>
|
|
<description>KBI Source Pin</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMC</name>
|
|
<description>Power management</description>
|
|
<prependToName>PMC_</prependToName>
|
|
<baseAddress>0x4007D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x2</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LVD_LLW</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SPMSC1</name>
|
|
<description>System Power Management Status and Control 1 Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1C</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BGBE</name>
|
|
<description>Bandgap Buffer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bandgap buffer is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Bandgap buffer is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDE</name>
|
|
<description>Low-Voltage Detect Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LVD logic is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LVD logic is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDSE</name>
|
|
<description>Low-Voltage Detect Stop Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low-voltage detect is disabled during Stop mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-voltage detect is enabled during Stop mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDRE</name>
|
|
<description>Low-Voltage Detect Reset Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LVD events do not generate hardware resets.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Forces an MCU reset when an enabled low-voltage detect event occurs.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVWIE</name>
|
|
<description>Low-Voltage Warning Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupt is disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Requests a hardware interrupt when LVWF = 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVWACK</name>
|
|
<description>Low-Voltage Warning Acknowledge</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LVWF</name>
|
|
<description>Low-Voltage Warning Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low-voltage warning is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-voltage warning is present or was present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPMSC2</name>
|
|
<description>System Power Management Status and Control 2 Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVWV</name>
|
|
<description>Low-Voltage Warning Voltage Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Low trip point is selected (VLVW = VLVW1).</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Middle 1 trip point is selected (VLVW = VLVW2).</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Middle 2 trip point is selected (VLVW = VLVW3).</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High trip point is selected (VLVW = VLVW4).</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDV</name>
|
|
<description>Low-Voltage Detect Voltage Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low trip point is selected (VLVD = VLVDL).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High trip point is selected (VLVD = VLVDH).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOA</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOA_</prependToName>
|
|
<baseAddress>0x400FF000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIDR</name>
|
|
<description>Port Input Disable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Port Input Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured for General Purpose Input, provided the pin is configured for any digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is not configured as General Purpose Input.Corresponding Port Data Input Register bit will read zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOB</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOB_</prependToName>
|
|
<baseAddress>0x400FF040</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIDR</name>
|
|
<description>Port Input Disable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Port Input Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured for General Purpose Input, provided the pin is configured for any digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is not configured as General Purpose Input.Corresponding Port Data Input Register bit will read zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOC</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOC_</prependToName>
|
|
<baseAddress>0x400FF080</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIDR</name>
|
|
<description>Port Input Disable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Port Input Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured for General Purpose Input, provided the pin is configured for any digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is not configured as General Purpose Input.Corresponding Port Data Input Register bit will read zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SystemControl</name>
|
|
<description>System Control Registers</description>
|
|
<prependToName>SCB_</prependToName>
|
|
<baseAddress>0xE000E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0xD2C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ACTLR</name>
|
|
<description>Auxiliary Control Register,</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>CPUID</name>
|
|
<description>CPUID Base Register</description>
|
|
<addressOffset>0xD00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x410CC601</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Indicates patch release: 0x0 = Patch 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARTNO</name>
|
|
<description>Indicates part number</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VARIANT</name>
|
|
<description>Indicates processor revision: 0x2 = Revision 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IMPLEMENTER</name>
|
|
<description>Implementer code</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR</name>
|
|
<description>Interrupt Control and State Register</description>
|
|
<addressOffset>0xD04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VECTPENDING</name>
|
|
<description>Exception number of the highest priority pending enabled exception</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTCLR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>removes the pending state from the SysTick exception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTSET</name>
|
|
<description>no description available</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: SysTick exception is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes SysTick exception state to pending; read: SysTick exception is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVCLR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>removes the pending state from the PendSV exception</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVSET</name>
|
|
<description>no description available</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: PendSV exception is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes PendSV exception state to pending; read: PendSV exception is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMIPENDSET</name>
|
|
<description>no description available</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: NMI exception is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes NMI exception state to pending; read: NMI exception is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VTOR</name>
|
|
<description>Vector Table Offset Register</description>
|
|
<addressOffset>0xD08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBLOFF</name>
|
|
<description>Vector table base offset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>25</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIRCR</name>
|
|
<description>Application Interrupt and Reset Control Register</description>
|
|
<addressOffset>0xD0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VECTCLRACTIVE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSRESETREQ</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>no system reset request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>asserts a signal to the outer system that requests a reset</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENDIANNESS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Little-endian</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Big-endian</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VECTKEY</name>
|
|
<description>Register key</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>System Control Register</description>
|
|
<addressOffset>0xD10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPONEXIT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>do not sleep when returning to Thread mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>enter sleep, or deep sleep, on return from an ISR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPDEEP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>sleep</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>deep sleep</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEVONPEND</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>enabled events and all interrupts, including disabled interrupts, can wakeup the processor</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Configuration and Control Register</description>
|
|
<addressOffset>0xD14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x208</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UNALIGN_TRP</name>
|
|
<description>Always reads as one, indicates that all unaligned accesses generate a HardFault</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STKALIGN</name>
|
|
<description>Indicates stack alignment on exception entry</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR2</name>
|
|
<description>System Handler Priority Register 2</description>
|
|
<addressOffset>0xD1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_11</name>
|
|
<description>Priority of system handler 11, SVCall</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR3</name>
|
|
<description>System Handler Priority Register 3</description>
|
|
<addressOffset>0xD20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_14</name>
|
|
<description>Priority of system handler 14, PendSV</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_15</name>
|
|
<description>Priority of system handler 15, SysTick exception</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHCSR</name>
|
|
<description>System Handler Control and State Register</description>
|
|
<addressOffset>0xD24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SVCALLPENDED</name>
|
|
<description>no description available</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>exception is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exception is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFSR</name>
|
|
<description>Debug Fault Status Register</description>
|
|
<addressOffset>0xD30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HALTED</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active halt request debug event</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Halt request debug event active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BKPT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No current breakpoint debug event</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one current breakpoint debug event</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DWTTRAP</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No current debug events generated by the DWT</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one current debug event generated by the DWT</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VCATCH</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Vector catch triggered</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Vector catch triggered</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTERNAL</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No EDBGRQ debug event</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EDBGRQ debug event</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SysTick</name>
|
|
<description>System timer</description>
|
|
<prependToName>SYST_</prependToName>
|
|
<baseAddress>0xE000E010</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CSR</name>
|
|
<description>SysTick Control and Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>counter disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>counter enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TICKINT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>counting down to 0 does not assert the SysTick exception request</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>counting down to 0 asserts the SysTick exception request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSOURCE</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>external clock</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>processor clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COUNTFLAG</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RVR</name>
|
|
<description>SysTick Reload Value Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>Value to load into the SysTick Current Value Register when the counter reaches 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CVR</name>
|
|
<description>SysTick Current Value Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CURRENT</name>
|
|
<description>Current value at the time the register is accessed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALIB</name>
|
|
<description>SysTick Calibration Value Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TENMS</name>
|
|
<description>Reload value to use for 10ms timing</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SKEW</name>
|
|
<description>no description available</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>10ms calibration value is exact</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>10ms calibration value is inexact, because of the clock frequency</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOREF</name>
|
|
<description>no description available</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The reference clock is provided</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The reference clock is not provided</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>NVIC</name>
|
|
<description>Nested Vectored Interrupt Controller</description>
|
|
<baseAddress>0xE000E100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x320</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>NVIC_ISER</name>
|
|
<description>Interrupt Set Enable Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA0</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 16 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Reserved iv 16 interrupt; read: Reserved iv 16 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 17 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Reserved iv 17 interrupt; read: Reserved iv 17 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 18 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Reserved iv 18 interrupt; read: Reserved iv 18 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA3</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 19 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Reserved iv 19 interrupt; read: Reserved iv 19 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA4</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 20 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA5</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Command complete and read collision interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Command complete and read collision interrupt; read: Command complete and read collision interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA6</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Low-voltage detect, low-voltage warning interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA7</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: External Interrupt interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable External Interrupt interrupt; read: External Interrupt interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA8</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA9</name>
|
|
<description>no description available</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Inter-Integrated Circuit 1 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA10</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Serial Peripheral Interface 0 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA11</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Serial Peripheral Interface 1 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA12</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART0 status and error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable UART0 status and error interrupt; read: UART0 status and error interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA13</name>
|
|
<description>no description available</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART1 status and error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable UART1 status and error interrupt; read: UART1 status and error interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA14</name>
|
|
<description>no description available</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART2 status and error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable UART2 status and error interrupt; read: UART2 status and error interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA15</name>
|
|
<description>no description available</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA16</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog comparator 0 interrupt interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Analog comparator 0 interrupt interrupt; read: Analog comparator 0 interrupt interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA17</name>
|
|
<description>no description available</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 0 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable FlexTimer Module 0 interrupt; read: FlexTimer Module 0 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA18</name>
|
|
<description>no description available</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 1 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable FlexTimer Module 1 interrupt; read: FlexTimer Module 1 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA19</name>
|
|
<description>no description available</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 2 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable FlexTimer Module 2 interrupt; read: FlexTimer Module 2 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA20</name>
|
|
<description>no description available</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Real-time counter interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Real-time counter interrupt; read: Real-time counter interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA21</name>
|
|
<description>no description available</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog comparator 1 interrupt interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Analog comparator 1 interrupt interrupt; read: Analog comparator 1 interrupt interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA22</name>
|
|
<description>no description available</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Periodic timer overflow channel 0 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Periodic timer overflow channel 0 interrupt; read: Periodic timer overflow channel 0 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA23</name>
|
|
<description>no description available</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Periodic timer overflow channel 1 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Periodic timer overflow channel 1 interrupt; read: Periodic timer overflow channel 1 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA24</name>
|
|
<description>no description available</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Keyboard interrupt interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Keyboard interrupt interrupt; read: Keyboard interrupt interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA25</name>
|
|
<description>no description available</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Keyboard interrupt interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Keyboard interrupt interrupt; read: Keyboard interrupt interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA26</name>
|
|
<description>no description available</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 42 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Reserved iv 42 interrupt; read: Reserved iv 42 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA27</name>
|
|
<description>no description available</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Clock loss of lock interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Clock loss of lock interrupt; read: Clock loss of lock interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA28</name>
|
|
<description>no description available</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: WDOG interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable WDOG interrupt; read: WDOG interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA29</name>
|
|
<description>no description available</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Pulse width timer interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Pulse width timer interrupt; read: Pulse width timer interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA30</name>
|
|
<description>no description available</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Freescale's Scalable Controller Area Network Rx interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Freescale's Scalable Controller Area Network Rx interrupt; read: Freescale's Scalable Controller Area Network Rx interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETENA31</name>
|
|
<description>no description available</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Freescale's Scalable Controller Area Network Tx and error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: enable Freescale's Scalable Controller Area Network Tx and error interrupt; read: Freescale's Scalable Controller Area Network Tx and error interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVIC_ICER</name>
|
|
<description>Interrupt Clear Enable Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA0</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 16 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Reserved iv 16 interrupt; read: Reserved iv 16 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 17 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Reserved iv 17 interrupt; read: Reserved iv 17 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 18 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Reserved iv 18 interrupt; read: Reserved iv 18 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA3</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 19 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Reserved iv 19 interrupt; read: Reserved iv 19 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA4</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 20 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA5</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Command complete and read collision interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Command complete and read collision interrupt; read: Command complete and read collision interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA6</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Low-voltage detect, low-voltage warning interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA7</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: External Interrupt interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable External Interrupt interrupt; read: External Interrupt interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA8</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA9</name>
|
|
<description>no description available</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Inter-Integrated Circuit 1 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA10</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Serial Peripheral Interface 0 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA11</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Serial Peripheral Interface 1 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA12</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART0 status and error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable UART0 status and error interrupt; read: UART0 status and error interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA13</name>
|
|
<description>no description available</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART1 status and error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable UART1 status and error interrupt; read: UART1 status and error interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA14</name>
|
|
<description>no description available</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART2 status and error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable UART2 status and error interrupt; read: UART2 status and error interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA15</name>
|
|
<description>no description available</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA16</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog comparator 0 interrupt interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Analog comparator 0 interrupt interrupt; read: Analog comparator 0 interrupt interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA17</name>
|
|
<description>no description available</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 0 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable FlexTimer Module 0 interrupt; read: FlexTimer Module 0 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA18</name>
|
|
<description>no description available</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 1 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable FlexTimer Module 1 interrupt; read: FlexTimer Module 1 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA19</name>
|
|
<description>no description available</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 2 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable FlexTimer Module 2 interrupt; read: FlexTimer Module 2 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA20</name>
|
|
<description>no description available</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Real-time counter interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Real-time counter interrupt; read: Real-time counter interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA21</name>
|
|
<description>no description available</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog comparator 1 interrupt interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Analog comparator 1 interrupt interrupt; read: Analog comparator 1 interrupt interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA22</name>
|
|
<description>no description available</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Periodic timer overflow channel 0 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Periodic timer overflow channel 0 interrupt; read: Periodic timer overflow channel 0 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA23</name>
|
|
<description>no description available</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Periodic timer overflow channel 1 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Periodic timer overflow channel 1 interrupt; read: Periodic timer overflow channel 1 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA24</name>
|
|
<description>no description available</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Keyboard interrupt interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Keyboard interrupt interrupt; read: Keyboard interrupt interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA25</name>
|
|
<description>no description available</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Keyboard interrupt interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Keyboard interrupt interrupt; read: Keyboard interrupt interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA26</name>
|
|
<description>no description available</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 42 interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Reserved iv 42 interrupt; read: Reserved iv 42 interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA27</name>
|
|
<description>no description available</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Clock loss of lock interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Clock loss of lock interrupt; read: Clock loss of lock interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA28</name>
|
|
<description>no description available</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: WDOG interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable WDOG interrupt; read: WDOG interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA29</name>
|
|
<description>no description available</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Pulse width timer interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Pulse width timer interrupt; read: Pulse width timer interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA30</name>
|
|
<description>no description available</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Freescale's Scalable Controller Area Network Rx interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Freescale's Scalable Controller Area Network Rx interrupt; read: Freescale's Scalable Controller Area Network Rx interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRENA31</name>
|
|
<description>no description available</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Freescale's Scalable Controller Area Network Tx and error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: disable Freescale's Scalable Controller Area Network Tx and error interrupt; read: Freescale's Scalable Controller Area Network Tx and error interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVIC_ISPR</name>
|
|
<description>Interrupt Set Pending Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND0</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 16 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Reserved iv 16 interrupt state to pending; read: Reserved iv 16 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 17 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Reserved iv 17 interrupt state to pending; read: Reserved iv 17 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 18 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Reserved iv 18 interrupt state to pending; read: Reserved iv 18 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND3</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 19 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Reserved iv 19 interrupt state to pending; read: Reserved iv 19 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND4</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 20 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Reserved iv 20 interrupt state to pending; read: Reserved iv 20 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND5</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Command complete and read collision interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Command complete and read collision interrupt state to pending; read: Command complete and read collision interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND6</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Low-voltage detect, low-voltage warning interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Low-voltage detect, low-voltage warning interrupt state to pending; read: Low-voltage detect, low-voltage warning interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND7</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: External Interrupt interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the External Interrupt interrupt state to pending; read: External Interrupt interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND8</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Inter-Integrated Circuit 0 interrupt state to pending; read: Inter-Integrated Circuit 0 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND9</name>
|
|
<description>no description available</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Inter-Integrated Circuit 1 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Inter-Integrated Circuit 1 interrupt state to pending; read: Inter-Integrated Circuit 1 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND10</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Serial Peripheral Interface 0 interrupt state to pending; read: Serial Peripheral Interface 0 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND11</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Serial Peripheral Interface 1 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Serial Peripheral Interface 1 interrupt state to pending; read: Serial Peripheral Interface 1 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND12</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART0 status and error interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the UART0 status and error interrupt state to pending; read: UART0 status and error interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND13</name>
|
|
<description>no description available</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART1 status and error interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the UART1 status and error interrupt state to pending; read: UART1 status and error interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND14</name>
|
|
<description>no description available</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART2 status and error interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the UART2 status and error interrupt state to pending; read: UART2 status and error interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND15</name>
|
|
<description>no description available</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Analog-to-Digital Converter 0 interrupt state to pending; read: Analog-to-Digital Converter 0 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND16</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog comparator 0 interrupt interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Analog comparator 0 interrupt interrupt state to pending; read: Analog comparator 0 interrupt interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND17</name>
|
|
<description>no description available</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 0 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the FlexTimer Module 0 interrupt state to pending; read: FlexTimer Module 0 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND18</name>
|
|
<description>no description available</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 1 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the FlexTimer Module 1 interrupt state to pending; read: FlexTimer Module 1 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND19</name>
|
|
<description>no description available</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 2 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the FlexTimer Module 2 interrupt state to pending; read: FlexTimer Module 2 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND20</name>
|
|
<description>no description available</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Real-time counter interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Real-time counter interrupt state to pending; read: Real-time counter interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND21</name>
|
|
<description>no description available</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog comparator 1 interrupt interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Analog comparator 1 interrupt interrupt state to pending; read: Analog comparator 1 interrupt interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND22</name>
|
|
<description>no description available</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Periodic timer overflow channel 0 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Periodic timer overflow channel 0 interrupt state to pending; read: Periodic timer overflow channel 0 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND23</name>
|
|
<description>no description available</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Periodic timer overflow channel 1 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Periodic timer overflow channel 1 interrupt state to pending; read: Periodic timer overflow channel 1 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND24</name>
|
|
<description>no description available</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Keyboard interrupt interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Keyboard interrupt interrupt state to pending; read: Keyboard interrupt interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND25</name>
|
|
<description>no description available</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Keyboard interrupt interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Keyboard interrupt interrupt state to pending; read: Keyboard interrupt interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND26</name>
|
|
<description>no description available</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 42 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Reserved iv 42 interrupt state to pending; read: Reserved iv 42 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND27</name>
|
|
<description>no description available</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Clock loss of lock interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Clock loss of lock interrupt state to pending; read: Clock loss of lock interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND28</name>
|
|
<description>no description available</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: WDOG interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the WDOG interrupt state to pending; read: WDOG interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND29</name>
|
|
<description>no description available</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Pulse width timer interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Pulse width timer interrupt state to pending; read: Pulse width timer interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND30</name>
|
|
<description>no description available</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Freescale's Scalable Controller Area Network Rx interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Freescale's Scalable Controller Area Network Rx interrupt state to pending; read: Freescale's Scalable Controller Area Network Rx interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETPEND31</name>
|
|
<description>no description available</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Freescale's Scalable Controller Area Network Tx and error interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: changes the Freescale's Scalable Controller Area Network Tx and error interrupt state to pending; read: Freescale's Scalable Controller Area Network Tx and error interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVIC_ICPR</name>
|
|
<description>Interrupt Clear Pending Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND0</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 16 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Reserved iv 16 interrupt; read: Reserved iv 16 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND1</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 17 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Reserved iv 17 interrupt; read: Reserved iv 17 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND2</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 18 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Reserved iv 18 interrupt; read: Reserved iv 18 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND3</name>
|
|
<description>no description available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 19 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Reserved iv 19 interrupt; read: Reserved iv 19 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND4</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 20 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Reserved iv 20 interrupt; read: Reserved iv 20 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND5</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Command complete and read collision interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Command complete and read collision interrupt; read: Command complete and read collision interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND6</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Low-voltage detect, low-voltage warning interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND7</name>
|
|
<description>no description available</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: External Interrupt interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the External Interrupt interrupt; read: External Interrupt interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND8</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND9</name>
|
|
<description>no description available</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Inter-Integrated Circuit 1 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND10</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND11</name>
|
|
<description>no description available</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Serial Peripheral Interface 1 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND12</name>
|
|
<description>no description available</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART0 status and error interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the UART0 status and error interrupt; read: UART0 status and error interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND13</name>
|
|
<description>no description available</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART1 status and error interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the UART1 status and error interrupt; read: UART1 status and error interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND14</name>
|
|
<description>no description available</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: UART2 status and error interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the UART2 status and error interrupt; read: UART2 status and error interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND15</name>
|
|
<description>no description available</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND16</name>
|
|
<description>no description available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog comparator 0 interrupt interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Analog comparator 0 interrupt interrupt; read: Analog comparator 0 interrupt interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND17</name>
|
|
<description>no description available</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 0 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the FlexTimer Module 0 interrupt; read: FlexTimer Module 0 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND18</name>
|
|
<description>no description available</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 1 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the FlexTimer Module 1 interrupt; read: FlexTimer Module 1 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND19</name>
|
|
<description>no description available</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: FlexTimer Module 2 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the FlexTimer Module 2 interrupt; read: FlexTimer Module 2 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND20</name>
|
|
<description>no description available</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Real-time counter interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Real-time counter interrupt; read: Real-time counter interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND21</name>
|
|
<description>no description available</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Analog comparator 1 interrupt interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Analog comparator 1 interrupt interrupt; read: Analog comparator 1 interrupt interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND22</name>
|
|
<description>no description available</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Periodic timer overflow channel 0 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Periodic timer overflow channel 0 interrupt; read: Periodic timer overflow channel 0 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND23</name>
|
|
<description>no description available</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Periodic timer overflow channel 1 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Periodic timer overflow channel 1 interrupt; read: Periodic timer overflow channel 1 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND24</name>
|
|
<description>no description available</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Keyboard interrupt interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Keyboard interrupt interrupt; read: Keyboard interrupt interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND25</name>
|
|
<description>no description available</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Keyboard interrupt interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Keyboard interrupt interrupt; read: Keyboard interrupt interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND26</name>
|
|
<description>no description available</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Reserved iv 42 interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Reserved iv 42 interrupt; read: Reserved iv 42 interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND27</name>
|
|
<description>no description available</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Clock loss of lock interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Clock loss of lock interrupt; read: Clock loss of lock interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND28</name>
|
|
<description>no description available</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: WDOG interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the WDOG interrupt; read: WDOG interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND29</name>
|
|
<description>no description available</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Pulse width timer interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Pulse width timer interrupt; read: Pulse width timer interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND30</name>
|
|
<description>no description available</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Freescale's Scalable Controller Area Network Rx interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Freescale's Scalable Controller Area Network Rx interrupt; read: Freescale's Scalable Controller Area Network Rx interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRPEND31</name>
|
|
<description>no description available</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>write: no effect; read: Freescale's Scalable Controller Area Network Tx and error interrupt is not pending</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>write: removes pending state from the Freescale's Scalable Controller Area Network Tx and error interrupt; read: Freescale's Scalable Controller Area Network Tx and error interrupt is pending</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVIC_IPR0</name>
|
|
<description>Interrupt Priority Register 0</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_0</name>
|
|
<description>Priority of the Reserved iv 16 interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_1</name>
|
|
<description>Priority of the Reserved iv 17 interrupt</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_2</name>
|
|
<description>Priority of the Reserved iv 18 interrupt</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_3</name>
|
|
<description>Priority of the Reserved iv 19 interrupt</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVIC_IPR1</name>
|
|
<description>Interrupt Priority Register 1</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_4</name>
|
|
<description>Priority of the Reserved iv 20 interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_5</name>
|
|
<description>Priority of the Command complete and read collision interrupt</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_6</name>
|
|
<description>Priority of the Low-voltage detect, low-voltage warning interrupt</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_7</name>
|
|
<description>Priority of the External Interrupt interrupt</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVIC_IPR2</name>
|
|
<description>Interrupt Priority Register 2</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_8</name>
|
|
<description>Priority of the Inter-Integrated Circuit 0 interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_9</name>
|
|
<description>Priority of the Inter-Integrated Circuit 1 interrupt</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_10</name>
|
|
<description>Priority of the Serial Peripheral Interface 0 interrupt</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_11</name>
|
|
<description>Priority of the Serial Peripheral Interface 1 interrupt</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVIC_IPR3</name>
|
|
<description>Interrupt Priority Register 3</description>
|
|
<addressOffset>0x30C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_12</name>
|
|
<description>Priority of the UART0 status and error interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_13</name>
|
|
<description>Priority of the UART1 status and error interrupt</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_14</name>
|
|
<description>Priority of the UART2 status and error interrupt</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_15</name>
|
|
<description>Priority of the Analog-to-Digital Converter 0 interrupt</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVIC_IPR4</name>
|
|
<description>Interrupt Priority Register 4</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_16</name>
|
|
<description>Priority of the Analog comparator 0 interrupt interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_17</name>
|
|
<description>Priority of the FlexTimer Module 0 interrupt</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_18</name>
|
|
<description>Priority of the FlexTimer Module 1 interrupt</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_19</name>
|
|
<description>Priority of the FlexTimer Module 2 interrupt</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVIC_IPR5</name>
|
|
<description>Interrupt Priority Register 5</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_20</name>
|
|
<description>Priority of the Real-time counter interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_21</name>
|
|
<description>Priority of the Analog comparator 1 interrupt interrupt</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_22</name>
|
|
<description>Priority of the Periodic timer overflow channel 0 interrupt</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_23</name>
|
|
<description>Priority of the Periodic timer overflow channel 1 interrupt</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVIC_IPR6</name>
|
|
<description>Interrupt Priority Register 6</description>
|
|
<addressOffset>0x318</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_24</name>
|
|
<description>Priority of the Keyboard interrupt interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_25</name>
|
|
<description>Priority of the Keyboard interrupt interrupt</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_26</name>
|
|
<description>Priority of the Reserved iv 42 interrupt</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_27</name>
|
|
<description>Priority of the Clock loss of lock interrupt</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVIC_IPR7</name>
|
|
<description>Interrupt Priority Register 7</description>
|
|
<addressOffset>0x31C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_28</name>
|
|
<description>Priority of the WDOG interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_29</name>
|
|
<description>Priority of the Pulse width timer interrupt</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_30</name>
|
|
<description>Priority of the Freescale's Scalable Controller Area Network Rx interrupt</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_31</name>
|
|
<description>Priority of the Freescale's Scalable Controller Area Network Tx and error interrupt</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ROM</name>
|
|
<description>System ROM</description>
|
|
<prependToName>ROM_</prependToName>
|
|
<baseAddress>0xF0002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ENTRY</name>
|
|
<description>Entry</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENTRY</name>
|
|
<description>ENTRY</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TABLEMARK</name>
|
|
<description>End of Table Marker Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MARK</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSACCESS</name>
|
|
<description>System Access Register</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYSACCESS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
|
|
<name>PERIPHID%s</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHID</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>COMPID%s</name>
|
|
<description>Component ID Register</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPID</name>
|
|
<description>Component ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MCM</name>
|
|
<description>Core Platform Miscellaneous Control Module</description>
|
|
<prependToName>MCM_</prependToName>
|
|
<baseAddress>0xF0003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PLASC</name>
|
|
<description>Crossbar Switch (AXBS) Slave Configuration</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASC</name>
|
|
<description>Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A bus slave connection to AXBS input port n is absent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A bus slave connection to AXBS input port n is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLAMC</name>
|
|
<description>Crossbar Switch (AXBS) Master Configuration</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMC</name>
|
|
<description>Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A bus master connection to AXBS input port n is absent</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A bus master connection to AXBS input port n is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLACR</name>
|
|
<description>Platform Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x800</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CFCC</name>
|
|
<description>Clear Flash Controller Cache</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DFCDA</name>
|
|
<description>Disable Flash Controller Data Caching</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller data caching</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller data caching.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFCIC</name>
|
|
<description>Disable Flash Controller Instruction Caching</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller instruction caching.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller instruction caching.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFCC</name>
|
|
<description>Disable Flash Controller Cache</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller cache.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller cache.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EFDS</name>
|
|
<description>Enable Flash Data Speculation</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable flash data speculation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable flash data speculation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFCS</name>
|
|
<description>Disable Flash Controller Speculation</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller speculation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller speculation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESFC</name>
|
|
<description>Enable Stalling Flash Controller</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable stalling flash controller when flash is busy.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable stalling flash controller when flash is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FGPIOA</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>FGPIO</groupName>
|
|
<prependToName>FGPIOA_</prependToName>
|
|
<baseAddress>0xF8000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIDR</name>
|
|
<description>Port Input Disable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Port Input Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured for General Purpose Input, provided the pin is configured for any digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is not configured as General Purpose Input. Corresponding Port Data Input Register bit will read zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FGPIOB</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>FGPIO</groupName>
|
|
<prependToName>FGPIOB_</prependToName>
|
|
<baseAddress>0xF8000040</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIDR</name>
|
|
<description>Port Input Disable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Port Input Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured for General Purpose Input, provided the pin is configured for any digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is not configured as General Purpose Input. Corresponding Port Data Input Register bit will read zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FGPIOC</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>FGPIO</groupName>
|
|
<prependToName>FGPIOC_</prependToName>
|
|
<baseAddress>0xF8000080</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIDR</name>
|
|
<description>Port Input Disable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Port Input Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured for General Purpose Input, provided the pin is configured for any digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is not configured as General Purpose Input. Corresponding Port Data Input Register bit will read zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|