RMUL2025/lib/cmsis_svd/data/Freescale/MKV31F12810.svd

42121 lines
1.6 MiB
Executable File

<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<vendor>Freescale Semiconductor, Inc.</vendor>
<vendorID>Freescale</vendorID>
<series>Kinetis_V</series>
<name>MKV31F12810</name>
<version>1.6</version>
<description>MKV31F12810 Freescale Microcontroller</description>
<licenseText>Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS &quot;AS IS&quot; AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</licenseText>
<cpu>
<name>CM4</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>true</fpuPresent>
<mpuPresent>false</mpuPresent>
<vtorPresent>true</vtorPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<peripherals>
<peripheral>
<name>FTFA_FlashConfig</name>
<description>Flash configuration field</description>
<prependToName>NV_</prependToName>
<baseAddress>0x400</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xE</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>BACKKEY3</name>
<description>Backdoor Comparison Key 3.</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY2</name>
<description>Backdoor Comparison Key 2.</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY1</name>
<description>Backdoor Comparison Key 1.</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY0</name>
<description>Backdoor Comparison Key 0.</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY7</name>
<description>Backdoor Comparison Key 7.</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY6</name>
<description>Backdoor Comparison Key 6.</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY5</name>
<description>Backdoor Comparison Key 5.</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BACKKEY4</name>
<description>Backdoor Comparison Key 4.</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Backdoor Comparison Key.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT3</name>
<description>Non-volatile P-Flash Protection 1 - Low Register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT2</name>
<description>Non-volatile P-Flash Protection 1 - High Register</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT1</name>
<description>Non-volatile P-Flash Protection 0 - Low Register</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FPROT0</name>
<description>Non-volatile P-Flash Protection 0 - High Register</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PROT</name>
<description>P-Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FSEC</name>
<description>Non-volatile Flash Security Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SEC</name>
<description>Flash Security</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>MCU security status is unsecure</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>MCU security status is secure</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSLACC</name>
<description>Freescale Failure Analysis Access Code</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>Freescale factory access denied</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Freescale factory access granted</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MEEN</name>
<description>no description available</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>Mass erase is disabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Mass erase is enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>KEYEN</name>
<description>Backdoor Key Security Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>10</name>
<description>Backdoor key access enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Backdoor key access disabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FOPT</name>
<description>Non-volatile Flash Option Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LPBOOT</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Low-power boot</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Normal boot</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EZPORT_DIS</name>
<description>no description available</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>EzPort operation is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>EzPort operation is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NMI_DIS</name>
<description>no description available</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>NMI interrupts are always blocked</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>NMI_b pin/interrupts reset default to enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAST_INIT</name>
<description>no description available</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Slower initialization</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Fast Initialization</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMA</name>
<description>Enhanced direct memory access controller</description>
<prependToName>DMA_</prependToName>
<baseAddress>0x40008000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1080</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA0</name>
<value>0</value>
</interrupt>
<interrupt>
<name>DMA1</name>
<value>1</value>
</interrupt>
<interrupt>
<name>DMA2</name>
<value>2</value>
</interrupt>
<interrupt>
<name>DMA3</name>
<value>3</value>
</interrupt>
<interrupt>
<name>DMA_Error</name>
<value>16</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EDBG</name>
<description>Enable Debug</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>When in debug mode, the DMA continues to operate.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERCA</name>
<description>Enable Round Robin Channel Arbitration</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fixed priority arbitration is used for channel selection .</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Round robin arbitration is used for channel selection .</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HOE</name>
<description>Halt On Error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HALT</name>
<description>Halt DMA Operations</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLM</name>
<description>Continuous Link Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A minor loop channel link made to itself goes through channel arbitration before being activated again.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EMLM</name>
<description>Enable Minor Loop Mapping</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ECX</name>
<description>Error Cancel Transfer</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CX</name>
<description>Cancel Transfer</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACTIVE</name>
<description>DMA Active Status</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>eDMA is idle.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>eDMA is executing a channel.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ES</name>
<description>Error Status Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DBE</name>
<description>Destination Bus Error</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No destination bus error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last recorded error was a bus error on a destination write</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SBE</name>
<description>Source Bus Error</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No source bus error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last recorded error was a bus error on a source read</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SGE</name>
<description>Scatter/Gather Configuration Error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No scatter/gather configuration error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NCE</name>
<description>NBYTES/CITER Configuration Error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No NBYTES/CITER configuration error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DOE</name>
<description>Destination Offset Error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No destination offset configuration error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAE</name>
<description>Destination Address Error</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No destination address configuration error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SOE</name>
<description>Source Offset Error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No source offset configuration error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAE</name>
<description>Source Address Error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No source address configuration error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERRCHN</name>
<description>Error Channel Number or Canceled Channel Number</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CPE</name>
<description>Channel Priority Error</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel priority error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ECX</name>
<description>Transfer Canceled</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No canceled transfers</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The last recorded entry was a canceled transfer by the error cancel transfer input</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VLD</name>
<description>Logical OR of all ERR status bits</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No ERR bits are set</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one ERR bit is set indicating a valid error exists that has not been cleared</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ERQ</name>
<description>Enable Request Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ERQ0</name>
<description>Enable DMA Request 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DMA request signal for the corresponding channel is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA request signal for the corresponding channel is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERQ1</name>
<description>Enable DMA Request 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DMA request signal for the corresponding channel is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA request signal for the corresponding channel is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERQ2</name>
<description>Enable DMA Request 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DMA request signal for the corresponding channel is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA request signal for the corresponding channel is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERQ3</name>
<description>Enable DMA Request 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DMA request signal for the corresponding channel is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DMA request signal for the corresponding channel is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EEI</name>
<description>Enable Error Interrupt Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EEI0</name>
<description>Enable Error Interrupt 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The error signal for corresponding channel does not generate an error interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EEI1</name>
<description>Enable Error Interrupt 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The error signal for corresponding channel does not generate an error interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EEI2</name>
<description>Enable Error Interrupt 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The error signal for corresponding channel does not generate an error interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EEI3</name>
<description>Enable Error Interrupt 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The error signal for corresponding channel does not generate an error interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CEEI</name>
<description>Clear Enable Error Interrupt Register</description>
<addressOffset>0x18</addressOffset>
<size>8</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CEEI</name>
<description>Clear Enable Error Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CAEE</name>
<description>Clear All Enable Error Interrupts</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clear only the EEI bit specified in the CEEI field</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear all bits in EEI</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOP</name>
<description>No Op enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No operation, ignore the other bits in this register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SEEI</name>
<description>Set Enable Error Interrupt Register</description>
<addressOffset>0x19</addressOffset>
<size>8</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SEEI</name>
<description>Set Enable Error Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SAEE</name>
<description>Sets All Enable Error Interrupts</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Set only the EEI bit specified in the SEEI field.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Sets all bits in EEI</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOP</name>
<description>No Op enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No operation, ignore the other bits in this register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CERQ</name>
<description>Clear Enable Request Register</description>
<addressOffset>0x1A</addressOffset>
<size>8</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CERQ</name>
<description>Clear Enable Request</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CAER</name>
<description>Clear All Enable Requests</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clear only the ERQ bit specified in the CERQ field</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear all bits in ERQ</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOP</name>
<description>No Op enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No operation, ignore the other bits in this register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SERQ</name>
<description>Set Enable Request Register</description>
<addressOffset>0x1B</addressOffset>
<size>8</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SERQ</name>
<description>Set enable request</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SAER</name>
<description>Set All Enable Requests</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Set only the ERQ bit specified in the SERQ field</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Set all bits in ERQ</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOP</name>
<description>No Op enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No operation, ignore the other bits in this register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CDNE</name>
<description>Clear DONE Status Bit Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CDNE</name>
<description>Clear DONE Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CADN</name>
<description>Clears All DONE Bits</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clears only the TCDn_CSR[DONE] bit specified in the CDNE field</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clears all bits in TCDn_CSR[DONE]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOP</name>
<description>No Op enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No operation, ignore the other bits in this register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SSRT</name>
<description>Set START Bit Register</description>
<addressOffset>0x1D</addressOffset>
<size>8</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSRT</name>
<description>Set START Bit</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SAST</name>
<description>Set All START Bits (activates all channels)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Set only the TCDn_CSR[START] bit specified in the SSRT field</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Set all bits in TCDn_CSR[START]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOP</name>
<description>No Op enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No operation, ignore the other bits in this register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CERR</name>
<description>Clear Error Register</description>
<addressOffset>0x1E</addressOffset>
<size>8</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CERR</name>
<description>Clear Error Indicator</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CAEI</name>
<description>Clear All Error Indicators</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clear only the ERR bit specified in the CERR field</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear all bits in ERR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOP</name>
<description>No Op enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No operation, ignore the other bits in this register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CINT</name>
<description>Clear Interrupt Request Register</description>
<addressOffset>0x1F</addressOffset>
<size>8</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CINT</name>
<description>Clear Interrupt Request</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CAIR</name>
<description>Clear All Interrupt Requests</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clear only the INT bit specified in the CINT field</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear all bits in INT</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOP</name>
<description>No Op enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No operation, ignore the other bits in this register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>INT</name>
<description>Interrupt Request Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INT0</name>
<description>Interrupt Request 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The interrupt request for corresponding channel is cleared</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The interrupt request for corresponding channel is active</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INT1</name>
<description>Interrupt Request 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The interrupt request for corresponding channel is cleared</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The interrupt request for corresponding channel is active</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INT2</name>
<description>Interrupt Request 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The interrupt request for corresponding channel is cleared</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The interrupt request for corresponding channel is active</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INT3</name>
<description>Interrupt Request 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The interrupt request for corresponding channel is cleared</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The interrupt request for corresponding channel is active</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ERR</name>
<description>Error Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ERR0</name>
<description>Error In Channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An error in the corresponding channel has not occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An error in the corresponding channel has occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERR1</name>
<description>Error In Channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An error in the corresponding channel has not occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An error in the corresponding channel has occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERR2</name>
<description>Error In Channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An error in the corresponding channel has not occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An error in the corresponding channel has occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERR3</name>
<description>Error In Channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An error in the corresponding channel has not occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An error in the corresponding channel has occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>HRS</name>
<description>Hardware Request Status Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HRS0</name>
<description>Hardware Request Status Channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware service request for channel 0 is not present</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware service request for channel 0 is present</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HRS1</name>
<description>Hardware Request Status Channel 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware service request for channel 1 is not present</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware service request for channel 1 is present</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HRS2</name>
<description>Hardware Request Status Channel 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware service request for channel 2 is not present</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware service request for channel 2 is present</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HRS3</name>
<description>Hardware Request Status Channel 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware service request for channel 3 is not present</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware service request for channel 3 is present</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EARS</name>
<description>Enable Asynchronous Request in Stop Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EDREQ_0</name>
<description>Enable asynchronous DMA request in stop for channel 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable asynchronous DMA request for channel 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable asynchronous DMA request for channel 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EDREQ_1</name>
<description>Enable asynchronous DMA request in stop for channel 1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable asynchronous DMA request for channel 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable asynchronous DMA request for channel 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EDREQ_2</name>
<description>Enable asynchronous DMA request in stop for channel 2.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable asynchronous DMA request for channel 2.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable asynchronous DMA request for channel 2.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EDREQ_3</name>
<description>Enable asynchronous DMA request in stop for channel 3.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable asynchronous DMA request for channel 3.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable asynchronous DMA request for channel 3.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>3,2,1,0</dimIndex>
<name>DCHPRI%s</name>
<description>Channel n Priority Register</description>
<addressOffset>0x100</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CHPRI</name>
<description>Channel n Arbitration Priority</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DPA</name>
<description>Disable Preempt Ability</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel n can suspend a lower priority channel</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel n cannot suspend any channel, regardless of channel priority</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ECP</name>
<description>Enable Channel Preemption</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel n cannot be suspended by a higher priority channel&apos;s service request</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel n can be temporarily suspended by the service request of a higher priority channel</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_SADDR</name>
<description>TCD Source Address</description>
<addressOffset>0x1000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SADDR</name>
<description>Source Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_SOFF</name>
<description>TCD Signed Source Address Offset</description>
<addressOffset>0x1004</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SOFF</name>
<description>Source address signed offset</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_ATTR</name>
<description>TCD Transfer Attributes</description>
<addressOffset>0x1006</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DSIZE</name>
<description>Destination Data Transfer Size</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMOD</name>
<description>Destination Address Modulo</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SSIZE</name>
<description>Source data transfer size</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>8-bit</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>16-bit</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>32-bit</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>16-byte</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>32-byte</description>
<value>#101</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMOD</name>
<description>Source Address Modulo.</description>
<bitOffset>11</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Source address modulo feature is disabled</description>
<value>#00000</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_NBYTES_MLNO</name>
<description>TCD Minor Byte Count (Minor Loop Disabled)</description>
<alternateGroup>DMA</alternateGroup>
<addressOffset>0x1008</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>NBYTES</name>
<description>Minor Byte Transfer Count</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_NBYTES_MLOFFNO</name>
<description>TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)</description>
<alternateGroup>DMA</alternateGroup>
<addressOffset>0x1008</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>NBYTES</name>
<description>Minor Byte Transfer Count</description>
<bitOffset>0</bitOffset>
<bitWidth>30</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMLOE</name>
<description>Destination Minor Loop Offset enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The minor loop offset is not applied to the DADDR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The minor loop offset is applied to the DADDR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMLOE</name>
<description>Source Minor Loop Offset Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The minor loop offset is not applied to the SADDR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The minor loop offset is applied to the SADDR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_NBYTES_MLOFFYES</name>
<description>TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)</description>
<alternateGroup>DMA</alternateGroup>
<addressOffset>0x1008</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>NBYTES</name>
<description>Minor Byte Transfer Count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MLOFF</name>
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
<bitOffset>10</bitOffset>
<bitWidth>20</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMLOE</name>
<description>Destination Minor Loop Offset enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The minor loop offset is not applied to the DADDR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The minor loop offset is applied to the DADDR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMLOE</name>
<description>Source Minor Loop Offset Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The minor loop offset is not applied to the SADDR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The minor loop offset is applied to the SADDR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_SLAST</name>
<description>TCD Last Source Address Adjustment</description>
<addressOffset>0x100C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SLAST</name>
<description>Last source Address Adjustment</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_DADDR</name>
<description>TCD Destination Address</description>
<addressOffset>0x1010</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DADDR</name>
<description>Destination Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_DOFF</name>
<description>TCD Signed Destination Address Offset</description>
<addressOffset>0x1014</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DOFF</name>
<description>Destination Address Signed offset</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_CITER_ELINKNO</name>
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
<alternateGroup>DMA</alternateGroup>
<addressOffset>0x1016</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>CITER</name>
<description>Current Major Iteration Count</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ELINK</name>
<description>Enable channel-to-channel linking on minor-loop complete</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel-to-channel linking is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel-to-channel linking is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_CITER_ELINKYES</name>
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
<alternateGroup>DMA</alternateGroup>
<addressOffset>0x1016</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>CITER</name>
<description>Current Major Iteration Count</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LINKCH</name>
<description>Link Channel Number</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ELINK</name>
<description>Enable channel-to-channel linking on minor-loop complete</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel-to-channel linking is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel-to-channel linking is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_DLASTSGA</name>
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
<addressOffset>0x1018</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>DLASTSGA</name>
<description>Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_CSR</name>
<description>TCD Control and Status</description>
<addressOffset>0x101C</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>START</name>
<description>Channel Start</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel is not explicitly started</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel is explicitly started via a software initiated service request</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTMAJOR</name>
<description>Enable an interrupt when major iteration count completes</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The end-of-major loop interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The end-of-major loop interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTHALF</name>
<description>Enable an interrupt when major counter is half complete.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The half-point interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The half-point interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DREQ</name>
<description>Disable Request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel&apos;s ERQ bit is not affected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel&apos;s ERQ bit is cleared when the major loop is complete</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ESG</name>
<description>Enable Scatter/Gather Processing</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The current channel&apos;s TCD is normal format.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The current channel&apos;s TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAJORELINK</name>
<description>Enable channel-to-channel linking on major loop complete</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel-to-channel linking is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel-to-channel linking is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACTIVE</name>
<description>Channel Active</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>Channel Done</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MAJORLINKCH</name>
<description>Link Channel Number</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BWC</name>
<description>Bandwidth Control</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No eDMA engine stalls</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>eDMA engine stalls for 4 cycles after each r/w</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>eDMA engine stalls for 8 cycles after each r/w</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_BITER_ELINKNO</name>
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
<alternateGroup>DMA</alternateGroup>
<addressOffset>0x101E</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>BITER</name>
<description>Starting Major Iteration Count</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ELINK</name>
<description>Enables channel-to-channel linking on minor loop complete</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel-to-channel linking is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel-to-channel linking is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x20</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCD%s_BITER_ELINKYES</name>
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
<alternateGroup>DMA</alternateGroup>
<addressOffset>0x101E</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>BITER</name>
<description>Starting Major Iteration Count</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LINKCH</name>
<description>Link Channel Number</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ELINK</name>
<description>Enables channel-to-channel linking on minor loop complete</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel-to-channel linking is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel-to-channel linking is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FMC</name>
<description>Flash Memory Controller</description>
<prependToName>FMC_</prependToName>
<baseAddress>0x4001F000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x300</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PFAPR</name>
<description>Flash Access Protection Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF8003F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>M0AP</name>
<description>Master 0 Access Protection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No access may be performed by this master</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Only read accesses may be performed by this master</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Only write accesses may be performed by this master</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both read and write accesses may be performed by this master</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M1AP</name>
<description>Master 1 Access Protection</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No access may be performed by this master</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Only read accesses may be performed by this master</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Only write accesses may be performed by this master</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both read and write accesses may be performed by this master</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M2AP</name>
<description>Master 2 Access Protection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No access may be performed by this master</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Only read accesses may be performed by this master</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Only write accesses may be performed by this master</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both read and write accesses may be performed by this master</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M3AP</name>
<description>Master 3 Access Protection</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No access may be performed by this master</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Only read accesses may be performed by this master</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Only write accesses may be performed by this master</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both read and write accesses may be performed by this master</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M4AP</name>
<description>Master 4 Access Protection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No access may be performed by this master</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Only read accesses may be performed by this master</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Only write accesses may be performed by this master</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both read and write accesses may be performed by this master</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M5AP</name>
<description>Master 5 Access Protection</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No access may be performed by this master</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Only read accesses may be performed by this master</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Only write accesses may be performed by this master</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both read and write accesses may be performed by this master</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M6AP</name>
<description>Master 6 Access Protection</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No access may be performed by this master</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Only read accesses may be performed by this master</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Only write accesses may be performed by this master</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both read and write accesses may be performed by this master</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M7AP</name>
<description>Master 7 Access Protection</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No access may be performed by this master.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Only read accesses may be performed by this master.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Only write accesses may be performed by this master.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Both read and write accesses may be performed by this master.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M0PFD</name>
<description>Master 0 Prefetch Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Prefetching for this master is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Prefetching for this master is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M1PFD</name>
<description>Master 1 Prefetch Disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Prefetching for this master is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Prefetching for this master is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M2PFD</name>
<description>Master 2 Prefetch Disable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Prefetching for this master is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Prefetching for this master is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M3PFD</name>
<description>Master 3 Prefetch Disable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Prefetching for this master is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Prefetching for this master is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M4PFD</name>
<description>Master 4 Prefetch Disable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Prefetching for this master is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Prefetching for this master is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M5PFD</name>
<description>Master 5 Prefetch Disable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Prefetching for this master is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Prefetching for this master is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M6PFD</name>
<description>Master 6 Prefetch Disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Prefetching for this master is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Prefetching for this master is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M7PFD</name>
<description>Master 7 Prefetch Disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Prefetching for this master is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Prefetching for this master is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PFB0CR</name>
<description>Flash Bank 0 Control Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3002001F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>B0SEBE</name>
<description>Bank 0 Single Entry Buffer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Single entry buffer is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single entry buffer is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B0IPE</name>
<description>Bank 0 Instruction Prefetch Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not prefetch in response to instruction fetches.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable prefetches in response to instruction fetches.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B0DPE</name>
<description>Bank 0 Data Prefetch Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not prefetch in response to data references.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable prefetches in response to data references.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B0ICE</name>
<description>Bank 0 Instruction Cache Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not cache instruction fetches.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Cache instruction fetches.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B0DCE</name>
<description>Bank 0 Data Cache Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not cache data references.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Cache data references.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRC</name>
<description>Cache Replacement Control</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>LRU replacement algorithm per set across all four ways</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Independent LRU with ways [0-1] for ifetches, [2-3] for data</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Independent LRU with ways [0-2] for ifetches, [3] for data</description>
<value>#011</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B0MW</name>
<description>Bank 0 Memory Width</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32 bits</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>64 bits</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>S_B_INV</name>
<description>Invalidate Prefetch Speculation Buffer</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Speculation buffer and single entry buffer are not affected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Invalidate (clear) speculation buffer and single entry buffer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CINV_WAY</name>
<description>Cache Invalidate Way x</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No cache way invalidation for the corresponding cache</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected</description>
<value>#0001</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLCK_WAY</name>
<description>Cache Lock Way x</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Cache way is unlocked and may be displaced</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Cache way is locked and its contents are not displaced</description>
<value>#0001</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B0RWSC</name>
<description>Bank 0 Read Wait State Control</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PFB1CR</name>
<description>Flash Bank 1 Control Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3002001F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>B1SEBE</name>
<description>Bank 1 Single Entry Buffer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Single entry buffer is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single entry buffer is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1IPE</name>
<description>Bank 1 Instruction Prefetch Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not prefetch in response to instruction fetches.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable prefetches in response to instruction fetches.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1DPE</name>
<description>Bank 1 Data Prefetch Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not prefetch in response to data references.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable prefetches in response to data references.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1ICE</name>
<description>Bank 1 Instruction Cache Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not cache instruction fetches.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Cache instruction fetches.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1DCE</name>
<description>Bank 1 Data Cache Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not cache data references.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Cache data references.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1MW</name>
<description>Bank 1 Memory Width</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>32 bits</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>64 bits</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1RWSC</name>
<description>Bank 1 Read Wait State Control</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>TAGVDW0S%s</name>
<description>Cache Tag Storage</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>valid</name>
<description>1-bit valid for cache entry</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>tag</name>
<description>14-bit tag for cache entry</description>
<bitOffset>5</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>TAGVDW1S%s</name>
<description>Cache Tag Storage</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>valid</name>
<description>1-bit valid for cache entry</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>tag</name>
<description>14-bit tag for cache entry</description>
<bitOffset>5</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>TAGVDW2S%s</name>
<description>Cache Tag Storage</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>valid</name>
<description>1-bit valid for cache entry</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>tag</name>
<description>14-bit tag for cache entry</description>
<bitOffset>5</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>TAGVDW3S%s</name>
<description>Cache Tag Storage</description>
<addressOffset>0x160</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>valid</name>
<description>1-bit valid for cache entry</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>tag</name>
<description>14-bit tag for cache entry</description>
<bitOffset>5</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>DATAW0S%sU</name>
<description>Cache Data Storage (upper word)</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>data</name>
<description>Bits [63:32] of data entry</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>DATAW0S%sL</name>
<description>Cache Data Storage (lower word)</description>
<addressOffset>0x204</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>data</name>
<description>Bits [31:0] of data entry</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>DATAW1S%sU</name>
<description>Cache Data Storage (upper word)</description>
<addressOffset>0x240</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>data</name>
<description>Bits [63:32] of data entry</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>DATAW1S%sL</name>
<description>Cache Data Storage (lower word)</description>
<addressOffset>0x244</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>data</name>
<description>Bits [31:0] of data entry</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>DATAW2S%sU</name>
<description>Cache Data Storage (upper word)</description>
<addressOffset>0x280</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>data</name>
<description>Bits [63:32] of data entry</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>DATAW2S%sL</name>
<description>Cache Data Storage (lower word)</description>
<addressOffset>0x284</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>data</name>
<description>Bits [31:0] of data entry</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>DATAW3S%sU</name>
<description>Cache Data Storage (upper word)</description>
<addressOffset>0x2C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>data</name>
<description>Bits [63:32] of data entry</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>DATAW3S%sL</name>
<description>Cache Data Storage (lower word)</description>
<addressOffset>0x2C4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>data</name>
<description>Bits [31:0] of data entry</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FTFA</name>
<description>Flash Memory Interface</description>
<prependToName>FTFA_</prependToName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x2C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FTF</name>
<value>18</value>
</interrupt>
<interrupt>
<name>Read_Collision</name>
<value>19</value>
</interrupt>
<registers>
<register>
<name>FSTAT</name>
<description>Flash Status Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MGSTAT0</name>
<description>Memory Controller Command Completion Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FPVIOL</name>
<description>Flash Protection Violation Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No protection violation detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Protection violation detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACCERR</name>
<description>Flash Access Error Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No access error detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Access error detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDCOLERR</name>
<description>Flash Read Collision Error Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No collision error detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Collision error detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIF</name>
<description>Command Complete Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Flash command in progress</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Flash command has completed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FCNFG</name>
<description>Flash Configuration Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ERSSUSP</name>
<description>Erase Suspend</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No suspend requested</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Suspend the current Erase Flash Sector command execution.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERSAREQ</name>
<description>Erase All Request</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No request or request complete</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDCOLLIE</name>
<description>Read Collision Error Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Read collision error interrupt disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIE</name>
<description>Command Complete Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Command complete interrupt disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FSEC</name>
<description>Flash Security Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SEC</name>
<description>Flash Security</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>MCU security status is secure.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>MCU security status is secure.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>MCU security status is secure.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FSLACC</name>
<description>Freescale Failure Analysis Access Code</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Freescale factory access granted</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Freescale factory access denied</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Freescale factory access denied</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Freescale factory access granted</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MEEN</name>
<description>Mass Erase Enable Bits</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Mass erase is enabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Mass erase is enabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Mass erase is disabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Mass erase is enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>KEYEN</name>
<description>Backdoor Key Security Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Backdoor key access disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Backdoor key access enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Backdoor key access disabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FOPT</name>
<description>Flash Option Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>OPT</name>
<description>Nonvolatile Option</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>12</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>3,2,1,0,7,6,5,4,B,A,9,8</dimIndex>
<name>FCCOB%s</name>
<description>Flash Common Command Object Registers</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CCOBn</name>
<description>The FCCOB register provides a command code and relevant parameters to the memory controller</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>3,2,1,0</dimIndex>
<name>FPROT%s</name>
<description>Program Flash Protection Registers</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>PROT</name>
<description>Program Flash Region Protect</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Program flash region is protected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Program flash region is not protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>H3,H2,H1,H0,L3,L2,L1,L0</dimIndex>
<name>XACC%s</name>
<description>Execute-only Access Registers</description>
<addressOffset>0x18</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>XA</name>
<description>Execute-only access control</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Associated segment is accessible in execute mode only (as an instruction fetch)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Associated segment is accessible as data or in execute mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>H3,H2,H1,H0,L3,L2,L1,L0</dimIndex>
<name>SACC%s</name>
<description>Supervisor-only Access Registers</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SA</name>
<description>Supervisor-only access control</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Associated segment is accessible in supervisor mode only</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Associated segment is accessible in user or supervisor mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FACSS</name>
<description>Flash Access Segment Size Register</description>
<addressOffset>0x28</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SGSIZE</name>
<description>Segment Size</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FACSN</name>
<description>Flash Access Segment Number Register</description>
<addressOffset>0x2B</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>NUMSG</name>
<description>Number of Segments Indicator</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>100000</name>
<description>Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes)</description>
<value>#100000</value>
</enumeratedValue>
<enumeratedValue>
<name>101000</name>
<description>Program flash memory is divided into 40 segments (160 Kbytes)</description>
<value>#101000</value>
</enumeratedValue>
<enumeratedValue>
<name>1000000</name>
<description>Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes)</description>
<value>#1000000</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMAMUX</name>
<description>DMA channel multiplexor</description>
<prependToName>DMAMUX_</prependToName>
<baseAddress>0x40021000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>4</dim>
<dimIncrement>0x1</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>CHCFG%s</name>
<description>Channel Configuration register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>DMA Channel Source (Slot)</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRIG</name>
<description>DMA Channel Trigger Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENBL</name>
<description>DMA Channel Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA channel is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC0</name>
<description>Analog-to-Digital Converter</description>
<groupName>ADC</groupName>
<prependToName>ADC0_</prependToName>
<baseAddress>0x4003B000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x70</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC0</name>
<value>39</value>
</interrupt>
<registers>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>A,B</dimIndex>
<name>SC1%s</name>
<description>ADC Status and Control Registers 1</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADCH</name>
<description>Input channel select</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00000</name>
<description>When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.</description>
<value>#00000</value>
</enumeratedValue>
<enumeratedValue>
<name>00001</name>
<description>When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.</description>
<value>#00001</value>
</enumeratedValue>
<enumeratedValue>
<name>00010</name>
<description>When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.</description>
<value>#00010</value>
</enumeratedValue>
<enumeratedValue>
<name>00011</name>
<description>When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.</description>
<value>#00011</value>
</enumeratedValue>
<enumeratedValue>
<name>00100</name>
<description>When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00100</value>
</enumeratedValue>
<enumeratedValue>
<name>00101</name>
<description>When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00101</value>
</enumeratedValue>
<enumeratedValue>
<name>00110</name>
<description>When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00110</value>
</enumeratedValue>
<enumeratedValue>
<name>00111</name>
<description>When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00111</value>
</enumeratedValue>
<enumeratedValue>
<name>01000</name>
<description>When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01000</value>
</enumeratedValue>
<enumeratedValue>
<name>01001</name>
<description>When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01001</value>
</enumeratedValue>
<enumeratedValue>
<name>01010</name>
<description>When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01010</value>
</enumeratedValue>
<enumeratedValue>
<name>01011</name>
<description>When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01011</value>
</enumeratedValue>
<enumeratedValue>
<name>01100</name>
<description>When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01100</value>
</enumeratedValue>
<enumeratedValue>
<name>01101</name>
<description>When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01101</value>
</enumeratedValue>
<enumeratedValue>
<name>01110</name>
<description>When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01110</value>
</enumeratedValue>
<enumeratedValue>
<name>01111</name>
<description>When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01111</value>
</enumeratedValue>
<enumeratedValue>
<name>10000</name>
<description>When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10000</value>
</enumeratedValue>
<enumeratedValue>
<name>10001</name>
<description>When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10001</value>
</enumeratedValue>
<enumeratedValue>
<name>10010</name>
<description>When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10010</value>
</enumeratedValue>
<enumeratedValue>
<name>10011</name>
<description>When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10011</value>
</enumeratedValue>
<enumeratedValue>
<name>10100</name>
<description>When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10100</value>
</enumeratedValue>
<enumeratedValue>
<name>10101</name>
<description>When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10101</value>
</enumeratedValue>
<enumeratedValue>
<name>10110</name>
<description>When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10110</value>
</enumeratedValue>
<enumeratedValue>
<name>10111</name>
<description>When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10111</value>
</enumeratedValue>
<enumeratedValue>
<name>11010</name>
<description>When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.</description>
<value>#11010</value>
</enumeratedValue>
<enumeratedValue>
<name>11011</name>
<description>When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.</description>
<value>#11011</value>
</enumeratedValue>
<enumeratedValue>
<name>11101</name>
<description>When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
<value>#11101</value>
</enumeratedValue>
<enumeratedValue>
<name>11110</name>
<description>When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].</description>
<value>#11110</value>
</enumeratedValue>
<enumeratedValue>
<name>11111</name>
<description>Module is disabled.</description>
<value>#11111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIFF</name>
<description>Differential Mode Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Single-ended conversions and input channels are selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Differential conversions and input channels are selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AIEN</name>
<description>Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion complete interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion complete interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COCO</name>
<description>Conversion Complete Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion is not completed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion is completed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFG1</name>
<description>ADC Configuration Register 1</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADICLK</name>
<description>Input Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bus clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Alternate clock 2 (ALTCLK2)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Alternate clock (ALTCLK)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Asynchronous clock (ADACK)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Conversion mode selection</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2&apos;s complement output.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2&apos;s complement output.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2&apos;s complement output</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2&apos;s complement output</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADLSMP</name>
<description>Sample Time Configuration</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Short sample time.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Long sample time.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADIV</name>
<description>Clock Divide Select</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>The divide ratio is 1 and the clock rate is input clock.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>The divide ratio is 2 and the clock rate is (input clock)/2.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>The divide ratio is 4 and the clock rate is (input clock)/4.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>The divide ratio is 8 and the clock rate is (input clock)/8.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADLPC</name>
<description>Low-Power Configuration</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal power configuration.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-power configuration. The power is reduced at the expense of maximum clock speed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFG2</name>
<description>ADC Configuration Register 2</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADLSTS</name>
<description>Long Sample Time Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>12 extra ADCK cycles; 16 ADCK cycles total sample time.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>6 extra ADCK cycles; 10 ADCK cycles total sample time.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>2 extra ADCK cycles; 6 ADCK cycles total sample time.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADHSC</name>
<description>High-Speed Configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal conversion sequence selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADACKEN</name>
<description>Asynchronous Clock Output Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Asynchronous clock and clock output is enabled regardless of the state of the ADC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUXSEL</name>
<description>ADC Mux Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ADxxa channels are selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ADxxb channels are selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>A,B</dimIndex>
<name>R%s</name>
<description>ADC Data Result Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>D</name>
<description>Data result</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>1,2</dimIndex>
<name>CV%s</name>
<description>Compare Value Registers</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CV</name>
<description>Compare Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SC2</name>
<description>Status and Control Register 2</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>REFSEL</name>
<description>Voltage Reference Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Default voltage reference pin pair, that is, external pins VREFH and VREFL</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACREN</name>
<description>Compare Function Range Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Range function disabled. Only CV1 is compared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Range function enabled. Both CV1 and CV2 are compared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACFGT</name>
<description>Compare Function Greater Than Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACFE</name>
<description>Compare Function Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Compare function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Compare function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADTRG</name>
<description>Conversion Trigger Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware trigger selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADACT</name>
<description>Conversion Active</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion not in progress.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion in progress.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SC3</name>
<description>Status and Control Register 3</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AVGS</name>
<description>Hardware Average Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>4 samples averaged.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8 samples averaged.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16 samples averaged.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>32 samples averaged.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AVGE</name>
<description>Hardware Average Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware average function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware average function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCO</name>
<description>Continuous Conversion Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CALF</name>
<description>Calibration Failed Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Calibration completed normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Calibration failed. ADC accuracy specifications are not guaranteed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAL</name>
<description>Calibration</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OFS</name>
<description>ADC Offset Correction Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OFS</name>
<description>Offset Error Correction Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PG</name>
<description>ADC Plus-Side Gain Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PG</name>
<description>Plus-Side Gain</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MG</name>
<description>ADC Minus-Side Gain Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MG</name>
<description>Minus-Side Gain</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLPD</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLPD</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLPS</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLPS</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP4</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP4</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP3</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP3</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP2</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP2</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP1</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP1</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP0</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP0</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLMD</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLMD</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLMS</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLMS</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM4</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM4</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM3</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM3</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM2</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM2</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM1</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM1</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM0</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM0</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC1</name>
<description>Analog-to-Digital Converter</description>
<groupName>ADC</groupName>
<prependToName>ADC1_</prependToName>
<baseAddress>0x40027000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x70</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC1</name>
<value>73</value>
</interrupt>
<registers>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>A,B</dimIndex>
<name>SC1%s</name>
<description>ADC Status and Control Registers 1</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADCH</name>
<description>Input channel select</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00000</name>
<description>When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.</description>
<value>#00000</value>
</enumeratedValue>
<enumeratedValue>
<name>00001</name>
<description>When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.</description>
<value>#00001</value>
</enumeratedValue>
<enumeratedValue>
<name>00010</name>
<description>When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.</description>
<value>#00010</value>
</enumeratedValue>
<enumeratedValue>
<name>00011</name>
<description>When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.</description>
<value>#00011</value>
</enumeratedValue>
<enumeratedValue>
<name>00100</name>
<description>When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00100</value>
</enumeratedValue>
<enumeratedValue>
<name>00101</name>
<description>When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00101</value>
</enumeratedValue>
<enumeratedValue>
<name>00110</name>
<description>When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00110</value>
</enumeratedValue>
<enumeratedValue>
<name>00111</name>
<description>When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.</description>
<value>#00111</value>
</enumeratedValue>
<enumeratedValue>
<name>01000</name>
<description>When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01000</value>
</enumeratedValue>
<enumeratedValue>
<name>01001</name>
<description>When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01001</value>
</enumeratedValue>
<enumeratedValue>
<name>01010</name>
<description>When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01010</value>
</enumeratedValue>
<enumeratedValue>
<name>01011</name>
<description>When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01011</value>
</enumeratedValue>
<enumeratedValue>
<name>01100</name>
<description>When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01100</value>
</enumeratedValue>
<enumeratedValue>
<name>01101</name>
<description>When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01101</value>
</enumeratedValue>
<enumeratedValue>
<name>01110</name>
<description>When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01110</value>
</enumeratedValue>
<enumeratedValue>
<name>01111</name>
<description>When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.</description>
<value>#01111</value>
</enumeratedValue>
<enumeratedValue>
<name>10000</name>
<description>When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10000</value>
</enumeratedValue>
<enumeratedValue>
<name>10001</name>
<description>When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10001</value>
</enumeratedValue>
<enumeratedValue>
<name>10010</name>
<description>When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10010</value>
</enumeratedValue>
<enumeratedValue>
<name>10011</name>
<description>When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10011</value>
</enumeratedValue>
<enumeratedValue>
<name>10100</name>
<description>When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10100</value>
</enumeratedValue>
<enumeratedValue>
<name>10101</name>
<description>When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10101</value>
</enumeratedValue>
<enumeratedValue>
<name>10110</name>
<description>When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10110</value>
</enumeratedValue>
<enumeratedValue>
<name>10111</name>
<description>When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.</description>
<value>#10111</value>
</enumeratedValue>
<enumeratedValue>
<name>11010</name>
<description>When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.</description>
<value>#11010</value>
</enumeratedValue>
<enumeratedValue>
<name>11011</name>
<description>When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.</description>
<value>#11011</value>
</enumeratedValue>
<enumeratedValue>
<name>11101</name>
<description>When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
<value>#11101</value>
</enumeratedValue>
<enumeratedValue>
<name>11110</name>
<description>When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].</description>
<value>#11110</value>
</enumeratedValue>
<enumeratedValue>
<name>11111</name>
<description>Module is disabled.</description>
<value>#11111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIFF</name>
<description>Differential Mode Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Single-ended conversions and input channels are selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Differential conversions and input channels are selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AIEN</name>
<description>Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion complete interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion complete interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COCO</name>
<description>Conversion Complete Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion is not completed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion is completed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFG1</name>
<description>ADC Configuration Register 1</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADICLK</name>
<description>Input Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bus clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Alternate clock 2 (ALTCLK2)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Alternate clock (ALTCLK)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Asynchronous clock (ADACK)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Conversion mode selection</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2&apos;s complement output.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2&apos;s complement output.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2&apos;s complement output</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2&apos;s complement output</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADLSMP</name>
<description>Sample Time Configuration</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Short sample time.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Long sample time.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADIV</name>
<description>Clock Divide Select</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>The divide ratio is 1 and the clock rate is input clock.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>The divide ratio is 2 and the clock rate is (input clock)/2.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>The divide ratio is 4 and the clock rate is (input clock)/4.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>The divide ratio is 8 and the clock rate is (input clock)/8.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADLPC</name>
<description>Low-Power Configuration</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal power configuration.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-power configuration. The power is reduced at the expense of maximum clock speed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFG2</name>
<description>ADC Configuration Register 2</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADLSTS</name>
<description>Long Sample Time Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>12 extra ADCK cycles; 16 ADCK cycles total sample time.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>6 extra ADCK cycles; 10 ADCK cycles total sample time.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>2 extra ADCK cycles; 6 ADCK cycles total sample time.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADHSC</name>
<description>High-Speed Configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal conversion sequence selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADACKEN</name>
<description>Asynchronous Clock Output Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Asynchronous clock and clock output is enabled regardless of the state of the ADC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUXSEL</name>
<description>ADC Mux Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ADxxa channels are selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ADxxb channels are selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>A,B</dimIndex>
<name>R%s</name>
<description>ADC Data Result Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>D</name>
<description>Data result</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>1,2</dimIndex>
<name>CV%s</name>
<description>Compare Value Registers</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CV</name>
<description>Compare Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SC2</name>
<description>Status and Control Register 2</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>REFSEL</name>
<description>Voltage Reference Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Default voltage reference pin pair, that is, external pins VREFH and VREFL</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACREN</name>
<description>Compare Function Range Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Range function disabled. Only CV1 is compared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Range function enabled. Both CV1 and CV2 are compared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACFGT</name>
<description>Compare Function Greater Than Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACFE</name>
<description>Compare Function Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Compare function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Compare function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADTRG</name>
<description>Conversion Trigger Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware trigger selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADACT</name>
<description>Conversion Active</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion not in progress.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion in progress.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SC3</name>
<description>Status and Control Register 3</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AVGS</name>
<description>Hardware Average Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>4 samples averaged.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>8 samples averaged.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>16 samples averaged.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>32 samples averaged.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AVGE</name>
<description>Hardware Average Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware average function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware average function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCO</name>
<description>Continuous Conversion Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CALF</name>
<description>Calibration Failed Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Calibration completed normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Calibration failed. ADC accuracy specifications are not guaranteed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAL</name>
<description>Calibration</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OFS</name>
<description>ADC Offset Correction Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OFS</name>
<description>Offset Error Correction Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PG</name>
<description>ADC Plus-Side Gain Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PG</name>
<description>Plus-Side Gain</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MG</name>
<description>ADC Minus-Side Gain Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MG</name>
<description>Minus-Side Gain</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLPD</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLPD</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLPS</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLPS</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP4</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP4</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP3</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP3</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP2</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP2</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP1</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP1</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLP0</name>
<description>ADC Plus-Side General Calibration Value Register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLP0</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLMD</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLMD</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLMS</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLMS</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM4</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM4</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM3</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM3</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM2</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM2</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM1</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM1</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLM0</name>
<description>ADC Minus-Side General Calibration Value Register</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLM0</name>
<description>Calibration Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LPUART0</name>
<description>Universal Asynchronous Receiver/Transmitter</description>
<prependToName>LPUART0_</prependToName>
<baseAddress>0x4002A000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LPUART0</name>
<value>30</value>
</interrupt>
<registers>
<register>
<name>BAUD</name>
<description>LPUART Baud Rate Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF000004</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>Baud Rate Modulo Divisor.</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SBNS</name>
<description>Stop Bit Number Select</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One stop bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Two stop bits.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIE</name>
<description>RX Input Active Edge Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIE</name>
<description>LIN Break Detect Interrupt Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESYNCDIS</name>
<description>Resynchronization Disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Resynchronization during received data word is supported</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Resynchronization during received data word is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BOTHEDGE</name>
<description>Both Edge Sampling</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver samples input data using the rising edge of the baud rate clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver samples input data using the rising and falling edge of the baud rate clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MATCFG</name>
<description>Match Configuration</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Address Match Wakeup</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Idle Match Wakeup</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Match On and Match Off</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Enables RWU on Data Match and Match On/Off for transmitter CTS input</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDMAE</name>
<description>Receiver Full DMA Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAE</name>
<description>Transmitter DMA Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA request disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSR</name>
<description>Over Sampling Ratio</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M10</name>
<description>10-bit Mode select</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver and transmitter use 8-bit or 9-bit data characters.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver and transmitter use 10-bit data characters.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN2</name>
<description>Match Address Mode Enable 2</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables automatic address matching or data matching mode for MATCH[MA2].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN1</name>
<description>Match Address Mode Enable 1</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables automatic address matching or data matching mode for MATCH[MA1].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>LPUART Status Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC00000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MA2F</name>
<description>Match 2 Flag</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Received data is not equal to MA2</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Received data is equal to MA2</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MA1F</name>
<description>Match 1 Flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Received data is not equal to MA1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Received data is equal to MA1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PF</name>
<description>Parity Error Flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error Flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No framing error detected. This does not guarantee the framing is correct.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Framing error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NF</name>
<description>Noise Flag</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No noise detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Noise detected in the received character in LPUART_DATA.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OR</name>
<description>Receiver Overrun Flag</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive overrun (new LPUART data lost).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLE</name>
<description>Idle Line Flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No idle line detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle line was detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Flag</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data buffer empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data buffer full.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC</name>
<description>Transmission Complete Flag</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter active (sending data, a preamble, or a break).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter idle (transmission activity complete).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Flag</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data buffer full.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data buffer empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAF</name>
<description>Receiver Active Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LPUART receiver idle waiting for a start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LPUART receiver active (LPUART_RX input not idle).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDE</name>
<description>LIN Break Detection Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRK13</name>
<description>Break Character Generation Length</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWUID</name>
<description>Receive Wake Up Idle Detect</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXINV</name>
<description>Receive Data Inversion</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSBF</name>
<description>MSB First</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIF</name>
<description>LPUART_RX Pin Active Edge Interrupt Flag</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No active edge on the receive pin has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An active edge on the receive pin has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIF</name>
<description>LIN Break Detect Interrupt Flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No LIN break character has been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LIN break character has been detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>LPUART Control Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PT</name>
<description>Parity Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Even parity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Odd parity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No hardware parity generation or checking.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILT</name>
<description>Idle Line Type Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle character bit count starts after start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle character bit count starts after stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Receiver Wakeup Method Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configures RWU for idle-line wakeup.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configures RWU with address-mark wakeup.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M</name>
<description>9-Bit or 8-Bit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver and transmitter use 8-bit data characters.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver and transmitter use 9-bit data characters.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRC</name>
<description>Receiver Source Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DOZEEN</name>
<description>Doze Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LPUART is enabled in Doze mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LPUART is disabled in Doze mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOPS</name>
<description>Loop Mode Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation - LPUART_RX and LPUART_TX use separate pins.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLECFG</name>
<description>Idle Configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>1 idle character</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>2 idle characters</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>4 idle characters</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>8 idle characters</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>16 idle characters</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>32 idle characters</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>64 idle characters</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>128 idle characters</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MA2IE</name>
<description>Match 2 Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MA2F interrupt disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MA2F interrupt enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MA1IE</name>
<description>Match 1 Interrupt Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MA1F interrupt disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MA1F interrupt enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SBK</name>
<description>Send Break</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal transmitter operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Queue break character(s) to be sent.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver Wakeup Control</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal receiver operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LPUART receiver in standby waiting for wakeup condition.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILIE</name>
<description>Idle Line Interrupt Enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from IDLE disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when IDLE flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIE</name>
<description>Receiver Interrupt Enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from RDRF disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when RDRF flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission Complete Interrupt Enable for</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from TC disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when TC flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Transmit Interrupt Enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from TDRE disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when TDRE flag is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PEIE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PF interrupts disabled; use polling).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when PF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FE interrupts disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when FE is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEIE</name>
<description>Noise Error Interrupt Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NF interrupts disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when NF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIE</name>
<description>Overrun Interrupt Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OR interrupts disabled; use polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Hardware interrupt requested when OR is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXINV</name>
<description>Transmit Data Inversion</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIR</name>
<description>LPUART_TX Pin Direction in Single-Wire Mode</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LPUART_TX pin is an input in single-wire mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LPUART_TX pin is an output in single-wire mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>R9T8</name>
<description>Receive Bit 9 / Transmit Bit 8</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8T9</name>
<description>Receive Bit 8 / Transmit Bit 9</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description>LPUART Data Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>R0T0</name>
<description>Read receive data buffer 0 or write transmit data buffer 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R1T1</name>
<description>Read receive data buffer 1 or write transmit data buffer 1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R2T2</name>
<description>Read receive data buffer 2 or write transmit data buffer 2.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R3T3</name>
<description>Read receive data buffer 3 or write transmit data buffer 3.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R4T4</name>
<description>Read receive data buffer 4 or write transmit data buffer 4.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R5T5</name>
<description>Read receive data buffer 5 or write transmit data buffer 5.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R6T6</name>
<description>Read receive data buffer 6 or write transmit data buffer 6.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R7T7</name>
<description>Read receive data buffer 7 or write transmit data buffer 7.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8T8</name>
<description>Read receive data buffer 8 or write transmit data buffer 8.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R9T9</name>
<description>Read receive data buffer 9 or write transmit data buffer 9.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IDLINE</name>
<description>Idle Line</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver was not idle before receiving this character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver was idle before receiving this character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEMPT</name>
<description>Receive Buffer Empty</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive buffer contains valid data.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive buffer is empty, data returned on read is not valid.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRETSC</name>
<description>Frame Error / Transmit Special Character</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without a frame error on read, transmit a normal character on write.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dataword was received with a frame error, transmit an idle or break character on transmit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PARITYE</name>
<description>The current received dataword contained in DATA[R9:R0] was received with a parity error.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dataword was received with a parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOISY</name>
<description>The current received dataword contained in DATA[R9:R0] was received with noise.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The data was received with noise.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MATCH</name>
<description>LPUART Match Address Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MA1</name>
<description>Match Address 1</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MA2</name>
<description>Match Address 2</description>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MODIR</name>
<description>LPUART Modem IrDA Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXCTSE</name>
<description>Transmitter clear-to-send enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS has no effect on the transmitter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSE</name>
<description>Transmitter request-to-send enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The transmitter has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSPOL</name>
<description>Transmitter request-to-send polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter RTS is active low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter RTS is active high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXRTSE</name>
<description>Receiver request-to-send enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The receiver has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXCTSC</name>
<description>Transmit CTS Configuration</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS input is sampled at the start of each character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CTS input is sampled when the transmitter is idle.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXCTSSRC</name>
<description>Transmit CTS Source</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS input is the LPUART_CTS pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CTS input is the inverted Receiver Match result.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TNP</name>
<description>Transmitter narrow pulse</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>1/OSR.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>2/OSR.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>3/OSR.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>4/OSR.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IREN</name>
<description>Infrared enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IR disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IR enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI0</name>
<description>Serial Peripheral Interface</description>
<groupName>SPI</groupName>
<prependToName>SPI0_</prependToName>
<baseAddress>0x4002C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x8C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI0</name>
<value>26</value>
</interrupt>
<registers>
<register>
<name>MCR</name>
<description>Module Configuration Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HALT</name>
<description>Halt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Start transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMPL_PT</name>
<description>Sample Point</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>0 protocol clock cycles between SCK edge and SIN sample</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>1 protocol clock cycle between SCK edge and SIN sample</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>2 protocol clock cycles between SCK edge and SIN sample</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLR_RXF</name>
<description>Flushes the RX FIFO</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not clear the RX FIFO counter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear the RX FIFO counter.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLR_TXF</name>
<description>Clear TX FIFO</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not clear the TX FIFO counter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear the TX FIFO counter.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIS_RXF</name>
<description>Disable Receive FIFO</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RX FIFO is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RX FIFO is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIS_TXF</name>
<description>Disable Transmit FIFO</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TX FIFO is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX FIFO is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDIS</name>
<description>Module Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enables the module clocks.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Allows external logic to disable the module clocks.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DOZE</name>
<description>Doze Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Doze mode has no effect on the module.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Doze mode disables the module.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCSIS</name>
<description>Peripheral Chip Select x Inactive State</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The inactive state of PCSx is low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The inactive state of PCSx is high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROOE</name>
<description>Receive FIFO Overflow Overwrite Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Incoming data is ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Incoming data is shifted into the shift register.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCSSE</name>
<description>Peripheral Chip Select Strobe Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PCS5/ PCSS is used as an active-low PCS Strobe signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MTFE</name>
<description>Modified Timing Format Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Modified SPI transfer format disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Modified SPI transfer format enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRZ</name>
<description>Freeze</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not halt serial transfers in Debug mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Halt serial transfers in Debug mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCONF</name>
<description>SPI Configuration.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>SPI</description>
<value>#00</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CONT_SCKE</name>
<description>Continuous SCK Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Continuous SCK disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Continuous SCK enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTR</name>
<description>Master/Slave Mode Select</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enables Slave mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables Master mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TCR</name>
<description>Transfer Count Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SPI_TCNT</name>
<description>SPI Transfer Counter</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>CTAR%s</name>
<description>Clock and Transfer Attributes Register (In Master Mode)</description>
<alternateGroup>SPI0</alternateGroup>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x78000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BR</name>
<description>Baud Rate Scaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DT</name>
<description>Delay After Transfer Scaler</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ASC</name>
<description>After SCK Delay Scaler</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CSSCK</name>
<description>PCS to SCK Delay Scaler</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PBR</name>
<description>Baud Rate Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Baud Rate Prescaler value is 2.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Baud Rate Prescaler value is 3.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Baud Rate Prescaler value is 5.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Baud Rate Prescaler value is 7.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PDT</name>
<description>Delay after Transfer Prescaler</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Delay after Transfer Prescaler value is 1.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Delay after Transfer Prescaler value is 3.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Delay after Transfer Prescaler value is 5.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Delay after Transfer Prescaler value is 7.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PASC</name>
<description>After SCK Delay Prescaler</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Delay after Transfer Prescaler value is 1.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Delay after Transfer Prescaler value is 3.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Delay after Transfer Prescaler value is 5.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Delay after Transfer Prescaler value is 7.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCSSCK</name>
<description>PCS to SCK Delay Prescaler</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>PCS to SCK Prescaler value is 1.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>PCS to SCK Prescaler value is 3.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>PCS to SCK Prescaler value is 5.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>PCS to SCK Prescaler value is 7.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSBFE</name>
<description>LSB First</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data is transferred MSB first.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data is transferred LSB first.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock Phase</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Polarity</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The inactive state value of SCK is low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The inactive state value of SCK is high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMSZ</name>
<description>Frame Size</description>
<bitOffset>27</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DBR</name>
<description>Double Baud Rate</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The baud rate is computed normally with a 50/50 duty cycle.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CTAR_SLAVE</name>
<description>Clock and Transfer Attributes Register (In Slave Mode)</description>
<alternateGroup>SPI0</alternateGroup>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x78000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CPHA</name>
<description>Clock Phase</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Polarity</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The inactive state value of SCK is low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The inactive state value of SCK is high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMSZ</name>
<description>Frame Size</description>
<bitOffset>27</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POPNXTPTR</name>
<description>Pop Next Pointer</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXCTR</name>
<description>RX FIFO Counter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXNXTPTR</name>
<description>Transmit Next Pointer</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXCTR</name>
<description>TX FIFO Counter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RFDF</name>
<description>Receive FIFO Drain Flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RX FIFO is empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RX FIFO is not empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFOF</name>
<description>Receive FIFO Overflow Flag</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Rx FIFO overflow.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Rx FIFO overflow has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFFF</name>
<description>Transmit FIFO Fill Flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TX FIFO is full.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX FIFO is not full.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFUF</name>
<description>Transmit FIFO Underflow Flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No TX FIFO underflow.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX FIFO underflow has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOQF</name>
<description>End of Queue Flag</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>EOQ is not set in the executing command.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>EOQ is set in the executing SPI command.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRXS</name>
<description>TX and RX Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit and receive operations are disabled (The module is in Stopped state).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit and receive operations are enabled (The module is in Running state).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF</name>
<description>Transfer Complete Flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer not complete.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transfer complete.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RSER</name>
<description>DMA/Interrupt Request Select and Enable Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFDF_DIRS</name>
<description>Receive FIFO Drain DMA or Interrupt Request Select</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt request.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFDF_RE</name>
<description>Receive FIFO Drain Request Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RFDF interrupt or DMA requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RFDF interrupt or DMA requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFOF_RE</name>
<description>Receive FIFO Overflow Request Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RFOF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RFOF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFFF_DIRS</name>
<description>Transmit FIFO Fill DMA or Interrupt Request Select</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TFFF flag generates interrupt requests.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TFFF flag generates DMA requests.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFFF_RE</name>
<description>Transmit FIFO Fill Request Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TFFF interrupts or DMA requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TFFF interrupts or DMA requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFUF_RE</name>
<description>Transmit FIFO Underflow Request Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TFUF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TFUF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOQF_RE</name>
<description>Finished Request Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>EOQF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>EOQF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF_RE</name>
<description>Transmission Complete Request Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TCF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TCF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PUSHR</name>
<description>PUSH TX FIFO Register In Master Mode</description>
<alternateGroup>SPI0</alternateGroup>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXDATA</name>
<description>Transmit Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PCS</name>
<description>Select which PCS signals are to be asserted for the transfer</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Negate the PCS[x] signal.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Assert the PCS[x] signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTCNT</name>
<description>Clear Transfer Counter</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not clear the TCR[TCNT] field.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear the TCR[TCNT] field.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOQ</name>
<description>End Of Queue</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The SPI data is not the last data to transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The SPI data is the last data to transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTAS</name>
<description>Clock and Transfer Attributes Select</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>CTAR0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>CTAR1</description>
<value>#001</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CONT</name>
<description>Continuous Peripheral Chip Select Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Return PCSn signals to their inactive state between transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Keep PCSn signals asserted between transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PUSHR_SLAVE</name>
<description>PUSH TX FIFO Register In Slave Mode</description>
<alternateGroup>SPI0</alternateGroup>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXDATA</name>
<description>Transmit Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>POPR</name>
<description>POP RX FIFO Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXDATA</name>
<description>Received Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TXFR%s</name>
<description>Transmit FIFO Registers</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXDATA</name>
<description>Transmit Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXCMD_TXDATA</name>
<description>Transmit Command or Transmit Data</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>RXFR%s</name>
<description>Receive FIFO Registers</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXDATA</name>
<description>Receive Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI1</name>
<description>Serial Peripheral Interface</description>
<groupName>SPI</groupName>
<prependToName>SPI1_</prependToName>
<baseAddress>0x4002D000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x8C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI1</name>
<value>27</value>
</interrupt>
<registers>
<register>
<name>MCR</name>
<description>Module Configuration Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HALT</name>
<description>Halt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Start transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMPL_PT</name>
<description>Sample Point</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>0 protocol clock cycles between SCK edge and SIN sample</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>1 protocol clock cycle between SCK edge and SIN sample</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>2 protocol clock cycles between SCK edge and SIN sample</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLR_RXF</name>
<description>Flushes the RX FIFO</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not clear the RX FIFO counter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear the RX FIFO counter.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLR_TXF</name>
<description>Clear TX FIFO</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not clear the TX FIFO counter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear the TX FIFO counter.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIS_RXF</name>
<description>Disable Receive FIFO</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RX FIFO is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RX FIFO is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIS_TXF</name>
<description>Disable Transmit FIFO</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TX FIFO is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX FIFO is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDIS</name>
<description>Module Disable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enables the module clocks.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Allows external logic to disable the module clocks.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DOZE</name>
<description>Doze Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Doze mode has no effect on the module.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Doze mode disables the module.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCSIS</name>
<description>Peripheral Chip Select x Inactive State</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The inactive state of PCSx is low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The inactive state of PCSx is high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROOE</name>
<description>Receive FIFO Overflow Overwrite Enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Incoming data is ignored.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Incoming data is shifted into the shift register.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCSSE</name>
<description>Peripheral Chip Select Strobe Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PCS5/ PCSS is used as an active-low PCS Strobe signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MTFE</name>
<description>Modified Timing Format Enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Modified SPI transfer format disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Modified SPI transfer format enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRZ</name>
<description>Freeze</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not halt serial transfers in Debug mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Halt serial transfers in Debug mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCONF</name>
<description>SPI Configuration.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>SPI</description>
<value>#00</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CONT_SCKE</name>
<description>Continuous SCK Enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Continuous SCK disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Continuous SCK enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTR</name>
<description>Master/Slave Mode Select</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enables Slave mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables Master mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TCR</name>
<description>Transfer Count Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SPI_TCNT</name>
<description>SPI Transfer Counter</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>CTAR%s</name>
<description>Clock and Transfer Attributes Register (In Master Mode)</description>
<alternateGroup>SPI1</alternateGroup>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x78000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BR</name>
<description>Baud Rate Scaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DT</name>
<description>Delay After Transfer Scaler</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ASC</name>
<description>After SCK Delay Scaler</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CSSCK</name>
<description>PCS to SCK Delay Scaler</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PBR</name>
<description>Baud Rate Prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Baud Rate Prescaler value is 2.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Baud Rate Prescaler value is 3.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Baud Rate Prescaler value is 5.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Baud Rate Prescaler value is 7.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PDT</name>
<description>Delay after Transfer Prescaler</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Delay after Transfer Prescaler value is 1.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Delay after Transfer Prescaler value is 3.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Delay after Transfer Prescaler value is 5.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Delay after Transfer Prescaler value is 7.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PASC</name>
<description>After SCK Delay Prescaler</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Delay after Transfer Prescaler value is 1.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Delay after Transfer Prescaler value is 3.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Delay after Transfer Prescaler value is 5.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Delay after Transfer Prescaler value is 7.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCSSCK</name>
<description>PCS to SCK Delay Prescaler</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>PCS to SCK Prescaler value is 1.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>PCS to SCK Prescaler value is 3.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>PCS to SCK Prescaler value is 5.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>PCS to SCK Prescaler value is 7.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSBFE</name>
<description>LSB First</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data is transferred MSB first.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data is transferred LSB first.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock Phase</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Polarity</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The inactive state value of SCK is low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The inactive state value of SCK is high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMSZ</name>
<description>Frame Size</description>
<bitOffset>27</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DBR</name>
<description>Double Baud Rate</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The baud rate is computed normally with a 50/50 duty cycle.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CTAR_SLAVE</name>
<description>Clock and Transfer Attributes Register (In Slave Mode)</description>
<alternateGroup>SPI1</alternateGroup>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x78000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CPHA</name>
<description>Clock Phase</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock Polarity</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The inactive state value of SCK is low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The inactive state value of SCK is high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMSZ</name>
<description>Frame Size</description>
<bitOffset>27</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>Status Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POPNXTPTR</name>
<description>Pop Next Pointer</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXCTR</name>
<description>RX FIFO Counter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXNXTPTR</name>
<description>Transmit Next Pointer</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXCTR</name>
<description>TX FIFO Counter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RFDF</name>
<description>Receive FIFO Drain Flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RX FIFO is empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RX FIFO is not empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFOF</name>
<description>Receive FIFO Overflow Flag</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Rx FIFO overflow.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Rx FIFO overflow has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFFF</name>
<description>Transmit FIFO Fill Flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TX FIFO is full.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX FIFO is not full.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFUF</name>
<description>Transmit FIFO Underflow Flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No TX FIFO underflow.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX FIFO underflow has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOQF</name>
<description>End of Queue Flag</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>EOQ is not set in the executing command.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>EOQ is set in the executing SPI command.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRXS</name>
<description>TX and RX Status</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit and receive operations are disabled (The module is in Stopped state).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit and receive operations are enabled (The module is in Running state).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF</name>
<description>Transfer Complete Flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer not complete.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transfer complete.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RSER</name>
<description>DMA/Interrupt Request Select and Enable Register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFDF_DIRS</name>
<description>Receive FIFO Drain DMA or Interrupt Request Select</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt request.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA request.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFDF_RE</name>
<description>Receive FIFO Drain Request Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RFDF interrupt or DMA requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RFDF interrupt or DMA requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFOF_RE</name>
<description>Receive FIFO Overflow Request Enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RFOF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RFOF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFFF_DIRS</name>
<description>Transmit FIFO Fill DMA or Interrupt Request Select</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TFFF flag generates interrupt requests.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TFFF flag generates DMA requests.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFFF_RE</name>
<description>Transmit FIFO Fill Request Enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TFFF interrupts or DMA requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TFFF interrupts or DMA requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFUF_RE</name>
<description>Transmit FIFO Underflow Request Enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TFUF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TFUF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOQF_RE</name>
<description>Finished Request Enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>EOQF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>EOQF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF_RE</name>
<description>Transmission Complete Request Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TCF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TCF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PUSHR</name>
<description>PUSH TX FIFO Register In Master Mode</description>
<alternateGroup>SPI1</alternateGroup>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXDATA</name>
<description>Transmit Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PCS</name>
<description>Select which PCS signals are to be asserted for the transfer</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Negate the PCS[x] signal.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Assert the PCS[x] signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTCNT</name>
<description>Clear Transfer Counter</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not clear the TCR[TCNT] field.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear the TCR[TCNT] field.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EOQ</name>
<description>End Of Queue</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The SPI data is not the last data to transfer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The SPI data is the last data to transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTAS</name>
<description>Clock and Transfer Attributes Select</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>CTAR0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>CTAR1</description>
<value>#001</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CONT</name>
<description>Continuous Peripheral Chip Select Enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Return PCSn signals to their inactive state between transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Keep PCSn signals asserted between transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PUSHR_SLAVE</name>
<description>PUSH TX FIFO Register In Slave Mode</description>
<alternateGroup>SPI1</alternateGroup>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXDATA</name>
<description>Transmit Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>POPR</name>
<description>POP RX FIFO Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXDATA</name>
<description>Received Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TXFR%s</name>
<description>Transmit FIFO Registers</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXDATA</name>
<description>Transmit Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXCMD_TXDATA</name>
<description>Transmit Command or Transmit Data</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>RXFR%s</name>
<description>Receive FIFO Registers</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXDATA</name>
<description>Receive Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRC</name>
<description>Cyclic Redundancy Check</description>
<prependToName>CRC_</prependToName>
<baseAddress>0x40032000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DATA</name>
<description>CRC Data register</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LL</name>
<description>CRC Low Lower Byte</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LU</name>
<description>CRC Low Upper Byte</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HL</name>
<description>CRC High Lower Byte</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HU</name>
<description>CRC High Upper Byte</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATAL</name>
<description>CRC_DATAL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATAL</name>
<description>DATAL stores the lower 16 bits of the 16/32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATALL</name>
<description>CRC_DATALL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATALL</name>
<description>CRCLL stores the first 8 bits of the 32 bit DATA</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATALU</name>
<description>CRC_DATALU register.</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATALU</name>
<description>DATALL stores the second 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATAH</name>
<description>CRC_DATAH register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATAH</name>
<description>DATAH stores the high 16 bits of the 16/32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATAHL</name>
<description>CRC_DATAHL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATAHL</name>
<description>DATAHL stores the third 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATAHU</name>
<description>CRC_DATAHU register.</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATAHU</name>
<description>DATAHU stores the fourth 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLY</name>
<description>CRC Polynomial register</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1021</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LOW</name>
<description>Low Polynominal Half-word</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HIGH</name>
<description>High Polynominal Half-word</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYL</name>
<description>CRC_GPOLYL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>GPOLYL</name>
<description>POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYLL</name>
<description>CRC_GPOLYLL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GPOLYLL</name>
<description>POLYLL stores the first 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYLU</name>
<description>CRC_GPOLYLU register.</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GPOLYLU</name>
<description>POLYLL stores the second 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYH</name>
<description>CRC_GPOLYH register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>GPOLYH</name>
<description>POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYHL</name>
<description>CRC_GPOLYHL register.</description>
<alternateGroup>CRC</alternateGroup>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GPOLYHL</name>
<description>POLYHL stores the third 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPOLYHU</name>
<description>CRC_GPOLYHU register.</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GPOLYHU</name>
<description>POLYHU stores the fourth 8 bits of the 32 bit CRC</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>CRC Control register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCRC</name>
<description>Width of CRC protocol.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>16-bit CRC protocol.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>32-bit CRC protocol.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAS</name>
<description>Write CRC Data Register As Seed</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to the CRC data register are data values.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to the CRC data register are seed values.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FXOR</name>
<description>Complement Read Of CRC Data Register</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No XOR on reading.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Invert or complement the read value of the CRC Data register.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOTR</name>
<description>Type Of Transpose For Read</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No transposition.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bits in bytes are transposed; bytes are not transposed.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Both bits in bytes and bytes are transposed.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOT</name>
<description>Type Of Transpose For Writes</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No transposition.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bits in bytes are transposed; bytes are not transposed.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Both bits in bytes and bytes are transposed.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CTRLHU</name>
<description>CRC_CTRLHU register.</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TCRC</name>
<description>no description available</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>16-bit CRC protocol.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>32-bit CRC protocol.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAS</name>
<description>no description available</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Writes to CRC data register are data values.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writes to CRC data reguster are seed values.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FXOR</name>
<description>no description available</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No XOR on reading.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Invert or complement the read value of CRC data register.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOTR</name>
<description>no description available</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No Transposition.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bits in bytes are transposed, bytes are not transposed.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Both bits in bytes and bytes are transposed.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOT</name>
<description>no description available</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No Transposition.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bits in bytes are transposed, bytes are not transposed.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Both bits in bytes and bytes are transposed.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PDB0</name>
<description>Programmable Delay Block</description>
<prependToName>PDB0_</prependToName>
<baseAddress>0x40036000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x19C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PDB0</name>
<value>52</value>
</interrupt>
<registers>
<register>
<name>SC</name>
<description>Status and Control register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LDOK</name>
<description>Load OK</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CONT</name>
<description>Continuous Mode Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDB operation in One-Shot mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDB operation in Continuous mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MULT</name>
<description>Multiplication Factor Select for Prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Multiplication factor is 1.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Multiplication factor is 10.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Multiplication factor is 20.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Multiplication factor is 40.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PDBIE</name>
<description>PDB Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDB interrupt disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDB interrupt enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PDBIF</name>
<description>PDB Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PDBEN</name>
<description>PDB Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDB disabled. Counter is off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDB enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRGSEL</name>
<description>Trigger Input Source Select</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Trigger-In 0 is selected.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Trigger-In 1 is selected.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Trigger-In 2 is selected.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Trigger-In 3 is selected.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Trigger-In 4 is selected.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Trigger-In 5 is selected.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Trigger-In 6 is selected.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Trigger-In 7 is selected.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Trigger-In 8 is selected.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Trigger-In 9 is selected.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Trigger-In 10 is selected.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Trigger-In 11 is selected.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Trigger-In 12 is selected.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Trigger-In 13 is selected.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Trigger-In 14 is selected.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Software trigger is selected.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRESCALER</name>
<description>Prescaler Divider Select</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Counting uses the peripheral clock divided by multiplication factor selected by MULT.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWTRIG</name>
<description>Software Trigger</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>PDBEIE</name>
<description>PDB Sequence Error Interrupt Enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDB sequence error interrupt disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDB sequence error interrupt enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LDMOD</name>
<description>Load Mode Select</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MOD</name>
<description>Modulus register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MOD</name>
<description>PDB Modulus</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<description>Counter register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNT</name>
<description>PDB Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IDLY</name>
<description>Interrupt Delay register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IDLY</name>
<description>PDB Interrupt Delay</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x28</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>CH%sC1</name>
<description>Channel n Control register 1</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EN</name>
<description>PDB Channel Pre-Trigger Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDB channel&apos;s corresponding pre-trigger disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDB channel&apos;s corresponding pre-trigger enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOS</name>
<description>PDB Channel Pre-Trigger Output Select</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDB channel&apos;s corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDB channel&apos;s corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BB</name>
<description>PDB Channel Pre-Trigger Back-to-Back Operation Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDB channel&apos;s corresponding pre-trigger back-to-back operation disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDB channel&apos;s corresponding pre-trigger back-to-back operation enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x28</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>CH%sS</name>
<description>Channel n Status register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ERR</name>
<description>PDB Channel Sequence Error Flags</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Sequence error not detected on PDB channel&apos;s corresponding pre-trigger.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Sequence error detected on PDB channel&apos;s corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel&apos;s corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0&apos;s to clear the sequence error flags.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CF</name>
<description>PDB Channel Flags</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x28</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>CH%sDLY0</name>
<description>Channel n Delay 0 register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLY</name>
<description>PDB Channel Delay</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x28</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>CH%sDLY1</name>
<description>Channel n Delay 1 register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLY</name>
<description>PDB Channel Delay</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DACINTC</name>
<description>DAC Interval Trigger n Control register</description>
<addressOffset>0x150</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TOE</name>
<description>DAC Interval Trigger Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DAC interval trigger disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DAC interval trigger enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXT</name>
<description>DAC External Trigger Input Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DACINT</name>
<description>DAC Interval n register</description>
<addressOffset>0x154</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INT</name>
<description>DAC Interval</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>POEN</name>
<description>Pulse-Out n Enable register</description>
<addressOffset>0x190</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POEN</name>
<description>PDB Pulse-Out Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDB Pulse-Out disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDB Pulse-Out enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>PO%sDLY</name>
<description>Pulse-Out n Delay register</description>
<addressOffset>0x194</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DLY2</name>
<description>PDB Pulse-Out Delay 2</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DLY1</name>
<description>PDB Pulse-Out Delay 1</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PIT</name>
<description>Periodic Interrupt Timer</description>
<prependToName>PIT_</prependToName>
<baseAddress>0x40037000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x140</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PIT0</name>
<value>48</value>
</interrupt>
<interrupt>
<name>PIT1</name>
<value>49</value>
</interrupt>
<interrupt>
<name>PIT2</name>
<value>50</value>
</interrupt>
<interrupt>
<name>PIT3</name>
<value>51</value>
</interrupt>
<registers>
<register>
<name>MCR</name>
<description>PIT Module Control Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x6</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FRZ</name>
<description>Freeze</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timers continue to run in Debug mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timers are stopped in Debug mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDIS</name>
<description>Module Disable - (PIT section)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock for standard PIT timers is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock for standard PIT timers is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>LDVAL%s</name>
<description>Timer Load Value Register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TSV</name>
<description>Timer Start Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>CVAL%s</name>
<description>Current Timer Value Register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TVL</name>
<description>Current Timer Value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TCTRL%s</name>
<description>Timer Control Register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TEN</name>
<description>Timer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer n is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer n is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Timer Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt requests from Timer n are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt will be requested whenever TIF is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHN</name>
<description>Chain Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer is not chained.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x10</dimIncrement>
<dimIndex>0,1,2,3</dimIndex>
<name>TFLG%s</name>
<description>Timer Flag Register</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIF</name>
<description>Timer Interrupt Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timeout has not yet occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timeout has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FTM0</name>
<description>FlexTimer Module</description>
<groupName>FTM</groupName>
<prependToName>FTM0_</prependToName>
<baseAddress>0x40038000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x9C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FTM0</name>
<value>42</value>
</interrupt>
<registers>
<register>
<name>SC</name>
<description>Status And Control</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Prescale Factor Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Divide by 1</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Divide by 2</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Divide by 4</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Divide by 8</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Divide by 16</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Divide by 32</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Divide by 64</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Divide by 128</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKS</name>
<description>Clock Source Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No clock selected. This in effect disables the FTM counter.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>System clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Fixed frequency clock</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPWMS</name>
<description>Center-Aligned PWM Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter operates in Up Counting mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter operates in Up-Down Counting mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOIE</name>
<description>Timer Overflow Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable TOF interrupts. Use software polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter has not overflowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter has overflowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<description>Counter</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Counter Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MOD</name>
<description>Modulo</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MOD</name>
<description>Modulo Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>C%sSC</name>
<description>Channel (n) Status And Control</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable DMA transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable DMA transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ICRST</name>
<description>FTM counter reset by the selected input capture event.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter is not reset when the selected channel (n) input event is detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter is reset when the selected channel (n) input event is detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ELSA</name>
<description>Edge or Level Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ELSB</name>
<description>Edge or Level Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSA</name>
<description>Channel Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSB</name>
<description>Channel Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CHIE</name>
<description>Channel Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable channel interrupts. Use software polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable channel interrupts.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHF</name>
<description>Channel Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>C%sV</name>
<description>Channel (n) Value</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>Channel Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNTIN</name>
<description>Counter Initial Value</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INIT</name>
<description>Initial Value Of The FTM Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Capture And Compare Status</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0F</name>
<description>Channel 0 Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1F</name>
<description>Channel 1 Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2F</name>
<description>Channel 2 Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3F</name>
<description>Channel 3 Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4F</name>
<description>Channel 4 Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5F</name>
<description>Channel 5 Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6F</name>
<description>Channel 6 Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7F</name>
<description>Channel 7 Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODE</name>
<description>Features Mode Selection</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FTMEN</name>
<description>FTM Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM compatibility. Free running counter and synchronization compatible with TPM.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Free running counter and synchronization are different from TPM behavior.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INIT</name>
<description>Initialize The Channels Output</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WPDIS</name>
<description>Write Protection Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Write protection is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Write protection is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMSYNC</name>
<description>PWM Synchronization Mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAPTEST</name>
<description>Capture Test Mode Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Capture test mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Capture test mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTM</name>
<description>Fault Control Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Fault control is disabled for all channels.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Fault control is enabled for all channels, and the selected mode is the manual fault clearing.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTIE</name>
<description>Fault Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault control interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault control interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYNC</name>
<description>Synchronization</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNTMIN</name>
<description>Minimum Loading Point Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The minimum loading point is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The minimum loading point is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNTMAX</name>
<description>Maximum Loading Point Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The maximum loading point is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The maximum loading point is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REINIT</name>
<description>FTM Counter Reinitialization By Synchronization (FTM counter synchronization)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter continues to count normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter is updated with its initial value when the selected trigger is detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCHOM</name>
<description>Output Mask Synchronization</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>OUTMASK register is updated with the value of its buffer only by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG0</name>
<description>PWM Synchronization Hardware Trigger 0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG1</name>
<description>PWM Synchronization Hardware Trigger 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG2</name>
<description>PWM Synchronization Hardware Trigger 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWSYNC</name>
<description>PWM Synchronization Software Trigger</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Software trigger is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OUTINIT</name>
<description>Initial State For Channels Output</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0OI</name>
<description>Channel 0 Output Initialization Value</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OI</name>
<description>Channel 1 Output Initialization Value</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OI</name>
<description>Channel 2 Output Initialization Value</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OI</name>
<description>Channel 3 Output Initialization Value</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OI</name>
<description>Channel 4 Output Initialization Value</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OI</name>
<description>Channel 5 Output Initialization Value</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OI</name>
<description>Channel 6 Output Initialization Value</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OI</name>
<description>Channel 7 Output Initialization Value</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OUTMASK</name>
<description>Output Mask</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0OM</name>
<description>Channel 0 Output Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OM</name>
<description>Channel 1 Output Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OM</name>
<description>Channel 2 Output Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OM</name>
<description>Channel 3 Output Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OM</name>
<description>Channel 4 Output Mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OM</name>
<description>Channel 5 Output Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OM</name>
<description>Channel 6 Output Mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OM</name>
<description>Channel 7 Output Mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>COMBINE</name>
<description>Function For Linked Channels</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COMBINE0</name>
<description>Combine Channels For n = 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP0</name>
<description>Complement Of Channel (n) For n = 0</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN0</name>
<description>Dual Edge Capture Mode Enable For n = 0</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP0</name>
<description>Dual Edge Capture Mode Captures For n = 0</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN0</name>
<description>Deadtime Enable For n = 0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN0</name>
<description>Synchronization Enable For n = 0</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN0</name>
<description>Fault Control Enable For n = 0</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMBINE1</name>
<description>Combine Channels For n = 2</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP1</name>
<description>Complement Of Channel (n) For n = 2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN1</name>
<description>Dual Edge Capture Mode Enable For n = 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP1</name>
<description>Dual Edge Capture Mode Captures For n = 2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN1</name>
<description>Deadtime Enable For n = 2</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN1</name>
<description>Synchronization Enable For n = 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN1</name>
<description>Fault Control Enable For n = 2</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMBINE2</name>
<description>Combine Channels For n = 4</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP2</name>
<description>Complement Of Channel (n) For n = 4</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN2</name>
<description>Dual Edge Capture Mode Enable For n = 4</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP2</name>
<description>Dual Edge Capture Mode Captures For n = 4</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN2</name>
<description>Deadtime Enable For n = 4</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN2</name>
<description>Synchronization Enable For n = 4</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN2</name>
<description>Fault Control Enable For n = 4</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMBINE3</name>
<description>Combine Channels For n = 6</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP3</name>
<description>Complement Of Channel (n) for n = 6</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN3</name>
<description>Dual Edge Capture Mode Enable For n = 6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP3</name>
<description>Dual Edge Capture Mode Captures For n = 6</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN3</name>
<description>Deadtime Enable For n = 6</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN3</name>
<description>Synchronization Enable For n = 6</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN3</name>
<description>Fault Control Enable For n = 6</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DEADTIME</name>
<description>Deadtime Insertion Control</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTVAL</name>
<description>Deadtime Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DTPS</name>
<description>Deadtime Prescaler Value</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0x</name>
<description>Divide the system clock by 1.</description>
<value>#0x</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Divide the system clock by 4.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Divide the system clock by 16.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EXTTRIG</name>
<description>FTM External Trigger</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH2TRIG</name>
<description>Channel 2 Trigger Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3TRIG</name>
<description>Channel 3 Trigger Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4TRIG</name>
<description>Channel 4 Trigger Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5TRIG</name>
<description>Channel 5 Trigger Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH0TRIG</name>
<description>Channel 0 Trigger Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1TRIG</name>
<description>Channel 1 Trigger Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITTRIGEN</name>
<description>Initialization Trigger Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of initialization trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of initialization trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGF</name>
<description>Channel Trigger Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel trigger was generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel trigger was generated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>POL</name>
<description>Channels Polarity</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POL0</name>
<description>Channel 0 Polarity</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL1</name>
<description>Channel 1 Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL2</name>
<description>Channel 2 Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL3</name>
<description>Channel 3 Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL4</name>
<description>Channel 4 Polarity</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL5</name>
<description>Channel 5 Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL6</name>
<description>Channel 6 Polarity</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL7</name>
<description>Channel 7 Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FMS</name>
<description>Fault Mode Status</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FAULTF0</name>
<description>Fault Detection Flag 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF1</name>
<description>Fault Detection Flag 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF2</name>
<description>Fault Detection Flag 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF3</name>
<description>Fault Detection Flag 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTIN</name>
<description>Fault Inputs</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The logic OR of the enabled fault inputs is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The logic OR of the enabled fault inputs is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Write protection is disabled. Write protected bits can be written.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Write protection is enabled. Write protected bits cannot be written.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF</name>
<description>Fault Detection Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILTER</name>
<description>Input Capture Filter Control</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0FVAL</name>
<description>Channel 0 Input Filter</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH1FVAL</name>
<description>Channel 1 Input Filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH2FVAL</name>
<description>Channel 2 Input Filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH3FVAL</name>
<description>Channel 3 Input Filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FLTCTRL</name>
<description>Fault Control</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FAULT0EN</name>
<description>Fault Input 0 Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT1EN</name>
<description>Fault Input 1 Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT2EN</name>
<description>Fault Input 2 Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT3EN</name>
<description>Fault Input 3 Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR0EN</name>
<description>Fault Input 0 Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR1EN</name>
<description>Fault Input 1 Filter Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR2EN</name>
<description>Fault Input 2 Filter Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR3EN</name>
<description>Fault Input 3 Filter Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFVAL</name>
<description>Fault Input Filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>QDCTRL</name>
<description>Quadrature Decoder Control And Status</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>QUADEN</name>
<description>Quadrature Decoder Mode Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Quadrature Decoder mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Quadrature Decoder mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOFDIR</name>
<description>Timer Overflow Direction In Quadrature Decoder Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QUADIR</name>
<description>FTM Counter Direction In Quadrature Decoder Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counting direction is decreasing (FTM counter decrement).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counting direction is increasing (FTM counter increment).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QUADMODE</name>
<description>Quadrature Decoder Mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Phase A and phase B encoding mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count and direction encoding mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHBPOL</name>
<description>Phase B Input Polarity</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHAPOL</name>
<description>Phase A Input Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHBFLTREN</name>
<description>Phase B Input Filter Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Phase B input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Phase B input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHAFLTREN</name>
<description>Phase A Input Filter Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Phase A input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Phase A input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONF</name>
<description>Configuration</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NUMTOF</name>
<description>TOF Frequency</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BDMMODE</name>
<description>BDM Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GTBEEN</name>
<description>Global Time Base Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Use of an external global time base is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Use of an external global time base is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTBEOUT</name>
<description>Global Time Base Output</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A global time base signal generation is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A global time base signal generation is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FLTPOL</name>
<description>FTM Fault Input Polarity</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLT0POL</name>
<description>Fault Input 0 Polarity</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLT1POL</name>
<description>Fault Input 1 Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLT2POL</name>
<description>Fault Input 2 Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLT3POL</name>
<description>Fault Input 3 Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYNCONF</name>
<description>Synchronization Configuration</description>
<addressOffset>0x8C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWTRIGMODE</name>
<description>Hardware Trigger Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNTINC</name>
<description>CNTIN Register Synchronization</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CNTIN register is updated with its buffer value at all rising edges of system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CNTIN register is updated with its buffer value by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INVC</name>
<description>INVCTRL Register Synchronization</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INVCTRL register is updated with its buffer value at all rising edges of system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INVCTRL register is updated with its buffer value by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWOC</name>
<description>SWOCTRL Register Synchronization</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SWOCTRL register is updated with its buffer value at all rising edges of system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SWOCTRL register is updated with its buffer value by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCMODE</name>
<description>Synchronization Mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Legacy PWM synchronization is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enhanced PWM synchronization is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWRSTCNT</name>
<description>FTM counter synchronization is activated by the software trigger.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the FTM counter synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the FTM counter synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWWRBUF</name>
<description>MOD, CNTIN, and CV registers synchronization is activated by the software trigger.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates MOD, CNTIN, and CV registers synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWOM</name>
<description>Output mask synchronization is activated by the software trigger.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the OUTMASK register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the OUTMASK register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWINVC</name>
<description>Inverting control synchronization is activated by the software trigger.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the INVCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the INVCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWSOC</name>
<description>Software output control synchronization is activated by the software trigger.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the SWOCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the SWOCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWRSTCNT</name>
<description>FTM counter synchronization is activated by a hardware trigger.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the FTM counter synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the FTM counter synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWWRBUF</name>
<description>MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates MOD, CNTIN, and CV registers synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWOM</name>
<description>Output mask synchronization is activated by a hardware trigger.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the OUTMASK register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the OUTMASK register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWINVC</name>
<description>Inverting control synchronization is activated by a hardware trigger.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the INVCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the INVCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWSOC</name>
<description>Software output control synchronization is activated by a hardware trigger.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the SWOCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the SWOCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>INVCTRL</name>
<description>FTM Inverting Control</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INV0EN</name>
<description>Pair Channels 0 Inverting Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV1EN</name>
<description>Pair Channels 1 Inverting Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV2EN</name>
<description>Pair Channels 2 Inverting Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV3EN</name>
<description>Pair Channels 3 Inverting Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SWOCTRL</name>
<description>FTM Software Output Control</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0OC</name>
<description>Channel 0 Software Output Control Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OC</name>
<description>Channel 1 Software Output Control Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OC</name>
<description>Channel 2 Software Output Control Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OC</name>
<description>Channel 3 Software Output Control Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OC</name>
<description>Channel 4 Software Output Control Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OC</name>
<description>Channel 5 Software Output Control Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OC</name>
<description>Channel 6 Software Output Control Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OC</name>
<description>Channel 7 Software Output Control Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH0OCV</name>
<description>Channel 0 Software Output Control Value</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OCV</name>
<description>Channel 1 Software Output Control Value</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OCV</name>
<description>Channel 2 Software Output Control Value</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OCV</name>
<description>Channel 3 Software Output Control Value</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OCV</name>
<description>Channel 4 Software Output Control Value</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OCV</name>
<description>Channel 5 Software Output Control Value</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OCV</name>
<description>Channel 6 Software Output Control Value</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OCV</name>
<description>Channel 7 Software Output Control Value</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWMLOAD</name>
<description>FTM PWM Load</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0SEL</name>
<description>Channel 0 Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1SEL</name>
<description>Channel 1 Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2SEL</name>
<description>Channel 2 Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3SEL</name>
<description>Channel 3 Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4SEL</name>
<description>Channel 4 Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5SEL</name>
<description>Channel 5 Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6SEL</name>
<description>Channel 6 Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7SEL</name>
<description>Channel 7 Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LDOK</name>
<description>Load Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Loading updated values is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loading updated values is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FTM1</name>
<description>FlexTimer Module</description>
<groupName>FTM</groupName>
<prependToName>FTM1_</prependToName>
<baseAddress>0x40039000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x9C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FTM1</name>
<value>43</value>
</interrupt>
<registers>
<register>
<name>SC</name>
<description>Status And Control</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Prescale Factor Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Divide by 1</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Divide by 2</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Divide by 4</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Divide by 8</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Divide by 16</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Divide by 32</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Divide by 64</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Divide by 128</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKS</name>
<description>Clock Source Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No clock selected. This in effect disables the FTM counter.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>System clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Fixed frequency clock</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPWMS</name>
<description>Center-Aligned PWM Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter operates in Up Counting mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter operates in Up-Down Counting mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOIE</name>
<description>Timer Overflow Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable TOF interrupts. Use software polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter has not overflowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter has overflowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<description>Counter</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Counter Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MOD</name>
<description>Modulo</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MOD</name>
<description>Modulo Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>C%sSC</name>
<description>Channel (n) Status And Control</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable DMA transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable DMA transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ICRST</name>
<description>FTM counter reset by the selected input capture event.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter is not reset when the selected channel (n) input event is detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter is reset when the selected channel (n) input event is detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ELSA</name>
<description>Edge or Level Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ELSB</name>
<description>Edge or Level Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSA</name>
<description>Channel Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSB</name>
<description>Channel Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CHIE</name>
<description>Channel Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable channel interrupts. Use software polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable channel interrupts.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHF</name>
<description>Channel Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>C%sV</name>
<description>Channel (n) Value</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>Channel Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNTIN</name>
<description>Counter Initial Value</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INIT</name>
<description>Initial Value Of The FTM Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Capture And Compare Status</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0F</name>
<description>Channel 0 Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1F</name>
<description>Channel 1 Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2F</name>
<description>Channel 2 Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3F</name>
<description>Channel 3 Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4F</name>
<description>Channel 4 Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5F</name>
<description>Channel 5 Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6F</name>
<description>Channel 6 Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7F</name>
<description>Channel 7 Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODE</name>
<description>Features Mode Selection</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FTMEN</name>
<description>FTM Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM compatibility. Free running counter and synchronization compatible with TPM.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Free running counter and synchronization are different from TPM behavior.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INIT</name>
<description>Initialize The Channels Output</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WPDIS</name>
<description>Write Protection Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Write protection is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Write protection is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMSYNC</name>
<description>PWM Synchronization Mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAPTEST</name>
<description>Capture Test Mode Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Capture test mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Capture test mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTM</name>
<description>Fault Control Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Fault control is disabled for all channels.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Fault control is enabled for all channels, and the selected mode is the manual fault clearing.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTIE</name>
<description>Fault Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault control interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault control interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYNC</name>
<description>Synchronization</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNTMIN</name>
<description>Minimum Loading Point Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The minimum loading point is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The minimum loading point is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNTMAX</name>
<description>Maximum Loading Point Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The maximum loading point is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The maximum loading point is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REINIT</name>
<description>FTM Counter Reinitialization By Synchronization (FTM counter synchronization)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter continues to count normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter is updated with its initial value when the selected trigger is detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCHOM</name>
<description>Output Mask Synchronization</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>OUTMASK register is updated with the value of its buffer only by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG0</name>
<description>PWM Synchronization Hardware Trigger 0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG1</name>
<description>PWM Synchronization Hardware Trigger 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG2</name>
<description>PWM Synchronization Hardware Trigger 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWSYNC</name>
<description>PWM Synchronization Software Trigger</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Software trigger is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OUTINIT</name>
<description>Initial State For Channels Output</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0OI</name>
<description>Channel 0 Output Initialization Value</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OI</name>
<description>Channel 1 Output Initialization Value</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OI</name>
<description>Channel 2 Output Initialization Value</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OI</name>
<description>Channel 3 Output Initialization Value</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OI</name>
<description>Channel 4 Output Initialization Value</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OI</name>
<description>Channel 5 Output Initialization Value</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OI</name>
<description>Channel 6 Output Initialization Value</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OI</name>
<description>Channel 7 Output Initialization Value</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OUTMASK</name>
<description>Output Mask</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0OM</name>
<description>Channel 0 Output Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OM</name>
<description>Channel 1 Output Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OM</name>
<description>Channel 2 Output Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OM</name>
<description>Channel 3 Output Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OM</name>
<description>Channel 4 Output Mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OM</name>
<description>Channel 5 Output Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OM</name>
<description>Channel 6 Output Mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OM</name>
<description>Channel 7 Output Mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>COMBINE</name>
<description>Function For Linked Channels</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COMBINE0</name>
<description>Combine Channels For n = 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP0</name>
<description>Complement Of Channel (n) For n = 0</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN0</name>
<description>Dual Edge Capture Mode Enable For n = 0</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP0</name>
<description>Dual Edge Capture Mode Captures For n = 0</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN0</name>
<description>Deadtime Enable For n = 0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN0</name>
<description>Synchronization Enable For n = 0</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN0</name>
<description>Fault Control Enable For n = 0</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMBINE1</name>
<description>Combine Channels For n = 2</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP1</name>
<description>Complement Of Channel (n) For n = 2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN1</name>
<description>Dual Edge Capture Mode Enable For n = 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP1</name>
<description>Dual Edge Capture Mode Captures For n = 2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN1</name>
<description>Deadtime Enable For n = 2</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN1</name>
<description>Synchronization Enable For n = 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN1</name>
<description>Fault Control Enable For n = 2</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMBINE2</name>
<description>Combine Channels For n = 4</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP2</name>
<description>Complement Of Channel (n) For n = 4</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN2</name>
<description>Dual Edge Capture Mode Enable For n = 4</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP2</name>
<description>Dual Edge Capture Mode Captures For n = 4</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN2</name>
<description>Deadtime Enable For n = 4</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN2</name>
<description>Synchronization Enable For n = 4</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN2</name>
<description>Fault Control Enable For n = 4</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMBINE3</name>
<description>Combine Channels For n = 6</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP3</name>
<description>Complement Of Channel (n) for n = 6</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN3</name>
<description>Dual Edge Capture Mode Enable For n = 6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP3</name>
<description>Dual Edge Capture Mode Captures For n = 6</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN3</name>
<description>Deadtime Enable For n = 6</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN3</name>
<description>Synchronization Enable For n = 6</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN3</name>
<description>Fault Control Enable For n = 6</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DEADTIME</name>
<description>Deadtime Insertion Control</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTVAL</name>
<description>Deadtime Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DTPS</name>
<description>Deadtime Prescaler Value</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0x</name>
<description>Divide the system clock by 1.</description>
<value>#0x</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Divide the system clock by 4.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Divide the system clock by 16.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EXTTRIG</name>
<description>FTM External Trigger</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH2TRIG</name>
<description>Channel 2 Trigger Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3TRIG</name>
<description>Channel 3 Trigger Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4TRIG</name>
<description>Channel 4 Trigger Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5TRIG</name>
<description>Channel 5 Trigger Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH0TRIG</name>
<description>Channel 0 Trigger Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1TRIG</name>
<description>Channel 1 Trigger Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITTRIGEN</name>
<description>Initialization Trigger Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of initialization trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of initialization trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGF</name>
<description>Channel Trigger Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel trigger was generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel trigger was generated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>POL</name>
<description>Channels Polarity</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POL0</name>
<description>Channel 0 Polarity</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL1</name>
<description>Channel 1 Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL2</name>
<description>Channel 2 Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL3</name>
<description>Channel 3 Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL4</name>
<description>Channel 4 Polarity</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL5</name>
<description>Channel 5 Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL6</name>
<description>Channel 6 Polarity</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL7</name>
<description>Channel 7 Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FMS</name>
<description>Fault Mode Status</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FAULTF0</name>
<description>Fault Detection Flag 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF1</name>
<description>Fault Detection Flag 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF2</name>
<description>Fault Detection Flag 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF3</name>
<description>Fault Detection Flag 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTIN</name>
<description>Fault Inputs</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The logic OR of the enabled fault inputs is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The logic OR of the enabled fault inputs is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Write protection is disabled. Write protected bits can be written.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Write protection is enabled. Write protected bits cannot be written.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF</name>
<description>Fault Detection Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILTER</name>
<description>Input Capture Filter Control</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0FVAL</name>
<description>Channel 0 Input Filter</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH1FVAL</name>
<description>Channel 1 Input Filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH2FVAL</name>
<description>Channel 2 Input Filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH3FVAL</name>
<description>Channel 3 Input Filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FLTCTRL</name>
<description>Fault Control</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FAULT0EN</name>
<description>Fault Input 0 Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT1EN</name>
<description>Fault Input 1 Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT2EN</name>
<description>Fault Input 2 Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT3EN</name>
<description>Fault Input 3 Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR0EN</name>
<description>Fault Input 0 Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR1EN</name>
<description>Fault Input 1 Filter Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR2EN</name>
<description>Fault Input 2 Filter Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR3EN</name>
<description>Fault Input 3 Filter Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFVAL</name>
<description>Fault Input Filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>QDCTRL</name>
<description>Quadrature Decoder Control And Status</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>QUADEN</name>
<description>Quadrature Decoder Mode Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Quadrature Decoder mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Quadrature Decoder mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOFDIR</name>
<description>Timer Overflow Direction In Quadrature Decoder Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QUADIR</name>
<description>FTM Counter Direction In Quadrature Decoder Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counting direction is decreasing (FTM counter decrement).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counting direction is increasing (FTM counter increment).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QUADMODE</name>
<description>Quadrature Decoder Mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Phase A and phase B encoding mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count and direction encoding mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHBPOL</name>
<description>Phase B Input Polarity</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHAPOL</name>
<description>Phase A Input Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHBFLTREN</name>
<description>Phase B Input Filter Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Phase B input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Phase B input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHAFLTREN</name>
<description>Phase A Input Filter Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Phase A input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Phase A input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONF</name>
<description>Configuration</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NUMTOF</name>
<description>TOF Frequency</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BDMMODE</name>
<description>BDM Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GTBEEN</name>
<description>Global Time Base Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Use of an external global time base is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Use of an external global time base is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTBEOUT</name>
<description>Global Time Base Output</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A global time base signal generation is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A global time base signal generation is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FLTPOL</name>
<description>FTM Fault Input Polarity</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLT0POL</name>
<description>Fault Input 0 Polarity</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLT1POL</name>
<description>Fault Input 1 Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLT2POL</name>
<description>Fault Input 2 Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLT3POL</name>
<description>Fault Input 3 Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYNCONF</name>
<description>Synchronization Configuration</description>
<addressOffset>0x8C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWTRIGMODE</name>
<description>Hardware Trigger Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNTINC</name>
<description>CNTIN Register Synchronization</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CNTIN register is updated with its buffer value at all rising edges of system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CNTIN register is updated with its buffer value by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INVC</name>
<description>INVCTRL Register Synchronization</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INVCTRL register is updated with its buffer value at all rising edges of system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INVCTRL register is updated with its buffer value by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWOC</name>
<description>SWOCTRL Register Synchronization</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SWOCTRL register is updated with its buffer value at all rising edges of system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SWOCTRL register is updated with its buffer value by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCMODE</name>
<description>Synchronization Mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Legacy PWM synchronization is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enhanced PWM synchronization is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWRSTCNT</name>
<description>FTM counter synchronization is activated by the software trigger.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the FTM counter synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the FTM counter synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWWRBUF</name>
<description>MOD, CNTIN, and CV registers synchronization is activated by the software trigger.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates MOD, CNTIN, and CV registers synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWOM</name>
<description>Output mask synchronization is activated by the software trigger.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the OUTMASK register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the OUTMASK register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWINVC</name>
<description>Inverting control synchronization is activated by the software trigger.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the INVCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the INVCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWSOC</name>
<description>Software output control synchronization is activated by the software trigger.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the SWOCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the SWOCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWRSTCNT</name>
<description>FTM counter synchronization is activated by a hardware trigger.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the FTM counter synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the FTM counter synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWWRBUF</name>
<description>MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates MOD, CNTIN, and CV registers synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWOM</name>
<description>Output mask synchronization is activated by a hardware trigger.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the OUTMASK register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the OUTMASK register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWINVC</name>
<description>Inverting control synchronization is activated by a hardware trigger.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the INVCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the INVCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWSOC</name>
<description>Software output control synchronization is activated by a hardware trigger.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the SWOCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the SWOCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>INVCTRL</name>
<description>FTM Inverting Control</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INV0EN</name>
<description>Pair Channels 0 Inverting Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV1EN</name>
<description>Pair Channels 1 Inverting Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV2EN</name>
<description>Pair Channels 2 Inverting Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV3EN</name>
<description>Pair Channels 3 Inverting Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SWOCTRL</name>
<description>FTM Software Output Control</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0OC</name>
<description>Channel 0 Software Output Control Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OC</name>
<description>Channel 1 Software Output Control Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OC</name>
<description>Channel 2 Software Output Control Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OC</name>
<description>Channel 3 Software Output Control Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OC</name>
<description>Channel 4 Software Output Control Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OC</name>
<description>Channel 5 Software Output Control Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OC</name>
<description>Channel 6 Software Output Control Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OC</name>
<description>Channel 7 Software Output Control Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH0OCV</name>
<description>Channel 0 Software Output Control Value</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OCV</name>
<description>Channel 1 Software Output Control Value</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OCV</name>
<description>Channel 2 Software Output Control Value</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OCV</name>
<description>Channel 3 Software Output Control Value</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OCV</name>
<description>Channel 4 Software Output Control Value</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OCV</name>
<description>Channel 5 Software Output Control Value</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OCV</name>
<description>Channel 6 Software Output Control Value</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OCV</name>
<description>Channel 7 Software Output Control Value</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWMLOAD</name>
<description>FTM PWM Load</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0SEL</name>
<description>Channel 0 Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1SEL</name>
<description>Channel 1 Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2SEL</name>
<description>Channel 2 Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3SEL</name>
<description>Channel 3 Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4SEL</name>
<description>Channel 4 Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5SEL</name>
<description>Channel 5 Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6SEL</name>
<description>Channel 6 Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7SEL</name>
<description>Channel 7 Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LDOK</name>
<description>Load Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Loading updated values is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loading updated values is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FTM2</name>
<description>FlexTimer Module</description>
<groupName>FTM</groupName>
<prependToName>FTM2_</prependToName>
<baseAddress>0x4003A000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x9C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FTM2</name>
<value>44</value>
</interrupt>
<registers>
<register>
<name>SC</name>
<description>Status And Control</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Prescale Factor Selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Divide by 1</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Divide by 2</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Divide by 4</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Divide by 8</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Divide by 16</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Divide by 32</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Divide by 64</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Divide by 128</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKS</name>
<description>Clock Source Selection</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>No clock selected. This in effect disables the FTM counter.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>System clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Fixed frequency clock</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPWMS</name>
<description>Center-Aligned PWM Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter operates in Up Counting mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter operates in Up-Down Counting mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOIE</name>
<description>Timer Overflow Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable TOF interrupts. Use software polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOF</name>
<description>Timer Overflow Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter has not overflowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter has overflowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<description>Counter</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Counter Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MOD</name>
<description>Modulo</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MOD</name>
<description>Modulo Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>C%sSC</name>
<description>Channel (n) Status And Control</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable DMA transfers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable DMA transfers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ICRST</name>
<description>FTM counter reset by the selected input capture event.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter is not reset when the selected channel (n) input event is detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter is reset when the selected channel (n) input event is detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ELSA</name>
<description>Edge or Level Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ELSB</name>
<description>Edge or Level Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSA</name>
<description>Channel Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSB</name>
<description>Channel Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CHIE</name>
<description>Channel Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable channel interrupts. Use software polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable channel interrupts.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHF</name>
<description>Channel Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x8</dimIncrement>
<dimIndex>0,1</dimIndex>
<name>C%sV</name>
<description>Channel (n) Value</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>Channel Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNTIN</name>
<description>Counter Initial Value</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INIT</name>
<description>Initial Value Of The FTM Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Capture And Compare Status</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0F</name>
<description>Channel 0 Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1F</name>
<description>Channel 1 Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2F</name>
<description>Channel 2 Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3F</name>
<description>Channel 3 Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4F</name>
<description>Channel 4 Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5F</name>
<description>Channel 5 Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6F</name>
<description>Channel 6 Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7F</name>
<description>Channel 7 Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel event has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel event has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODE</name>
<description>Features Mode Selection</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FTMEN</name>
<description>FTM Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TPM compatibility. Free running counter and synchronization compatible with TPM.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Free running counter and synchronization are different from TPM behavior.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INIT</name>
<description>Initialize The Channels Output</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WPDIS</name>
<description>Write Protection Disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Write protection is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Write protection is disabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMSYNC</name>
<description>PWM Synchronization Mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CAPTEST</name>
<description>Capture Test Mode Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Capture test mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Capture test mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTM</name>
<description>Fault Control Mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Fault control is disabled for all channels.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Fault control is enabled for all channels, and the selected mode is the manual fault clearing.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTIE</name>
<description>Fault Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault control interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault control interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYNC</name>
<description>Synchronization</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNTMIN</name>
<description>Minimum Loading Point Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The minimum loading point is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The minimum loading point is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNTMAX</name>
<description>Maximum Loading Point Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The maximum loading point is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The maximum loading point is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REINIT</name>
<description>FTM Counter Reinitialization By Synchronization (FTM counter synchronization)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM counter continues to count normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM counter is updated with its initial value when the selected trigger is detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCHOM</name>
<description>Output Mask Synchronization</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>OUTMASK register is updated with the value of its buffer only by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG0</name>
<description>PWM Synchronization Hardware Trigger 0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG1</name>
<description>PWM Synchronization Hardware Trigger 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIG2</name>
<description>PWM Synchronization Hardware Trigger 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWSYNC</name>
<description>PWM Synchronization Software Trigger</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software trigger is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Software trigger is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OUTINIT</name>
<description>Initial State For Channels Output</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0OI</name>
<description>Channel 0 Output Initialization Value</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OI</name>
<description>Channel 1 Output Initialization Value</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OI</name>
<description>Channel 2 Output Initialization Value</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OI</name>
<description>Channel 3 Output Initialization Value</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OI</name>
<description>Channel 4 Output Initialization Value</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OI</name>
<description>Channel 5 Output Initialization Value</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OI</name>
<description>Channel 6 Output Initialization Value</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OI</name>
<description>Channel 7 Output Initialization Value</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The initialization value is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The initialization value is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OUTMASK</name>
<description>Output Mask</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0OM</name>
<description>Channel 0 Output Mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OM</name>
<description>Channel 1 Output Mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OM</name>
<description>Channel 2 Output Mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OM</name>
<description>Channel 3 Output Mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OM</name>
<description>Channel 4 Output Mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OM</name>
<description>Channel 5 Output Mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OM</name>
<description>Channel 6 Output Mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OM</name>
<description>Channel 7 Output Mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel output is not masked. It continues to operate normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel output is masked. It is forced to its inactive state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>COMBINE</name>
<description>Function For Linked Channels</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COMBINE0</name>
<description>Combine Channels For n = 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP0</name>
<description>Complement Of Channel (n) For n = 0</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN0</name>
<description>Dual Edge Capture Mode Enable For n = 0</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP0</name>
<description>Dual Edge Capture Mode Captures For n = 0</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN0</name>
<description>Deadtime Enable For n = 0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN0</name>
<description>Synchronization Enable For n = 0</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN0</name>
<description>Fault Control Enable For n = 0</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMBINE1</name>
<description>Combine Channels For n = 2</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP1</name>
<description>Complement Of Channel (n) For n = 2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN1</name>
<description>Dual Edge Capture Mode Enable For n = 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP1</name>
<description>Dual Edge Capture Mode Captures For n = 2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN1</name>
<description>Deadtime Enable For n = 2</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN1</name>
<description>Synchronization Enable For n = 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN1</name>
<description>Fault Control Enable For n = 2</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMBINE2</name>
<description>Combine Channels For n = 4</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP2</name>
<description>Complement Of Channel (n) For n = 4</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN2</name>
<description>Dual Edge Capture Mode Enable For n = 4</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP2</name>
<description>Dual Edge Capture Mode Captures For n = 4</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN2</name>
<description>Deadtime Enable For n = 4</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN2</name>
<description>Synchronization Enable For n = 4</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN2</name>
<description>Fault Control Enable For n = 4</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMBINE3</name>
<description>Combine Channels For n = 6</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channels (n) and (n+1) are independent.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channels (n) and (n+1) are combined.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COMP3</name>
<description>Complement Of Channel (n) for n = 6</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel (n+1) output is the same as the channel (n) output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAPEN3</name>
<description>Dual Edge Capture Mode Enable For n = 6</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The Dual Edge Capture mode in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The Dual Edge Capture mode in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DECAP3</name>
<description>Dual Edge Capture Mode Captures For n = 6</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dual edge captures are inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dual edge captures are active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTEN3</name>
<description>Deadtime Enable For n = 6</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The deadtime insertion in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The deadtime insertion in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCEN3</name>
<description>Synchronization Enable For n = 6</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PWM synchronization in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PWM synchronization in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTEN3</name>
<description>Fault Control Enable For n = 6</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault control in this pair of channels is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault control in this pair of channels is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DEADTIME</name>
<description>Deadtime Insertion Control</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTVAL</name>
<description>Deadtime Value</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DTPS</name>
<description>Deadtime Prescaler Value</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0x</name>
<description>Divide the system clock by 1.</description>
<value>#0x</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Divide the system clock by 4.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Divide the system clock by 16.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EXTTRIG</name>
<description>FTM External Trigger</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH2TRIG</name>
<description>Channel 2 Trigger Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3TRIG</name>
<description>Channel 3 Trigger Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4TRIG</name>
<description>Channel 4 Trigger Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5TRIG</name>
<description>Channel 5 Trigger Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH0TRIG</name>
<description>Channel 0 Trigger Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1TRIG</name>
<description>Channel 1 Trigger Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of the channel trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of the channel trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITTRIGEN</name>
<description>Initialization Trigger Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The generation of initialization trigger is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The generation of initialization trigger is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGF</name>
<description>Channel Trigger Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No channel trigger was generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A channel trigger was generated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>POL</name>
<description>Channels Polarity</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POL0</name>
<description>Channel 0 Polarity</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL1</name>
<description>Channel 1 Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL2</name>
<description>Channel 2 Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL3</name>
<description>Channel 3 Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL4</name>
<description>Channel 4 Polarity</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL5</name>
<description>Channel 5 Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL6</name>
<description>Channel 6 Polarity</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POL7</name>
<description>Channel 7 Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel polarity is active high.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel polarity is active low.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FMS</name>
<description>Fault Mode Status</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FAULTF0</name>
<description>Fault Detection Flag 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF1</name>
<description>Fault Detection Flag 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF2</name>
<description>Fault Detection Flag 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF3</name>
<description>Fault Detection Flag 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected at the fault input.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected at the fault input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTIN</name>
<description>Fault Inputs</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The logic OR of the enabled fault inputs is 0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The logic OR of the enabled fault inputs is 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WPEN</name>
<description>Write Protection Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Write protection is disabled. Write protected bits can be written.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Write protection is enabled. Write protected bits cannot be written.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULTF</name>
<description>Fault Detection Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No fault condition was detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A fault condition was detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILTER</name>
<description>Input Capture Filter Control</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0FVAL</name>
<description>Channel 0 Input Filter</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH1FVAL</name>
<description>Channel 1 Input Filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH2FVAL</name>
<description>Channel 2 Input Filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CH3FVAL</name>
<description>Channel 3 Input Filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FLTCTRL</name>
<description>Fault Control</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FAULT0EN</name>
<description>Fault Input 0 Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT1EN</name>
<description>Fault Input 1 Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT2EN</name>
<description>Fault Input 2 Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAULT3EN</name>
<description>Fault Input 3 Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR0EN</name>
<description>Fault Input 0 Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR1EN</name>
<description>Fault Input 1 Filter Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR2EN</name>
<description>Fault Input 2 Filter Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFLTR3EN</name>
<description>Fault Input 3 Filter Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fault input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fault input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FFVAL</name>
<description>Fault Input Filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>QDCTRL</name>
<description>Quadrature Decoder Control And Status</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>QUADEN</name>
<description>Quadrature Decoder Mode Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Quadrature Decoder mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Quadrature Decoder mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOFDIR</name>
<description>Timer Overflow Direction In Quadrature Decoder Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QUADIR</name>
<description>FTM Counter Direction In Quadrature Decoder Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counting direction is decreasing (FTM counter decrement).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counting direction is increasing (FTM counter increment).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QUADMODE</name>
<description>Quadrature Decoder Mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Phase A and phase B encoding mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Count and direction encoding mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHBPOL</name>
<description>Phase B Input Polarity</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHAPOL</name>
<description>Phase A Input Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHBFLTREN</name>
<description>Phase B Input Filter Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Phase B input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Phase B input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PHAFLTREN</name>
<description>Phase A Input Filter Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Phase A input filter is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Phase A input filter is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONF</name>
<description>Configuration</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NUMTOF</name>
<description>TOF Frequency</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BDMMODE</name>
<description>BDM Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GTBEEN</name>
<description>Global Time Base Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Use of an external global time base is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Use of an external global time base is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTBEOUT</name>
<description>Global Time Base Output</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A global time base signal generation is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A global time base signal generation is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FLTPOL</name>
<description>FTM Fault Input Polarity</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLT0POL</name>
<description>Fault Input 0 Polarity</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLT1POL</name>
<description>Fault Input 1 Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLT2POL</name>
<description>Fault Input 2 Polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLT3POL</name>
<description>Fault Input 3 Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SYNCONF</name>
<description>Synchronization Configuration</description>
<addressOffset>0x8C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWTRIGMODE</name>
<description>Hardware Trigger Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNTINC</name>
<description>CNTIN Register Synchronization</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CNTIN register is updated with its buffer value at all rising edges of system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CNTIN register is updated with its buffer value by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INVC</name>
<description>INVCTRL Register Synchronization</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INVCTRL register is updated with its buffer value at all rising edges of system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INVCTRL register is updated with its buffer value by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWOC</name>
<description>SWOCTRL Register Synchronization</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SWOCTRL register is updated with its buffer value at all rising edges of system clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SWOCTRL register is updated with its buffer value by the PWM synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SYNCMODE</name>
<description>Synchronization Mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Legacy PWM synchronization is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enhanced PWM synchronization is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWRSTCNT</name>
<description>FTM counter synchronization is activated by the software trigger.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the FTM counter synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the FTM counter synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWWRBUF</name>
<description>MOD, CNTIN, and CV registers synchronization is activated by the software trigger.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates MOD, CNTIN, and CV registers synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWOM</name>
<description>Output mask synchronization is activated by the software trigger.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the OUTMASK register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the OUTMASK register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWINVC</name>
<description>Inverting control synchronization is activated by the software trigger.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the INVCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the INVCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWSOC</name>
<description>Software output control synchronization is activated by the software trigger.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software trigger does not activate the SWOCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software trigger activates the SWOCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWRSTCNT</name>
<description>FTM counter synchronization is activated by a hardware trigger.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the FTM counter synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the FTM counter synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWWRBUF</name>
<description>MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates MOD, CNTIN, and CV registers synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWOM</name>
<description>Output mask synchronization is activated by a hardware trigger.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the OUTMASK register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the OUTMASK register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWINVC</name>
<description>Inverting control synchronization is activated by a hardware trigger.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the INVCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the INVCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HWSOC</name>
<description>Software output control synchronization is activated by a hardware trigger.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A hardware trigger does not activate the SWOCTRL register synchronization.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A hardware trigger activates the SWOCTRL register synchronization.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>INVCTRL</name>
<description>FTM Inverting Control</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INV0EN</name>
<description>Pair Channels 0 Inverting Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV1EN</name>
<description>Pair Channels 1 Inverting Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV2EN</name>
<description>Pair Channels 2 Inverting Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV3EN</name>
<description>Pair Channels 3 Inverting Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverting is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverting is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SWOCTRL</name>
<description>FTM Software Output Control</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0OC</name>
<description>Channel 0 Software Output Control Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OC</name>
<description>Channel 1 Software Output Control Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OC</name>
<description>Channel 2 Software Output Control Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OC</name>
<description>Channel 3 Software Output Control Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OC</name>
<description>Channel 4 Software Output Control Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OC</name>
<description>Channel 5 Software Output Control Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OC</name>
<description>Channel 6 Software Output Control Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OC</name>
<description>Channel 7 Software Output Control Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The channel output is not affected by software output control.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The channel output is affected by software output control.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH0OCV</name>
<description>Channel 0 Software Output Control Value</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1OCV</name>
<description>Channel 1 Software Output Control Value</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2OCV</name>
<description>Channel 2 Software Output Control Value</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3OCV</name>
<description>Channel 3 Software Output Control Value</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4OCV</name>
<description>Channel 4 Software Output Control Value</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5OCV</name>
<description>Channel 5 Software Output Control Value</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6OCV</name>
<description>Channel 6 Software Output Control Value</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7OCV</name>
<description>Channel 7 Software Output Control Value</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The software output control forces 0 to the channel output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The software output control forces 1 to the channel output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWMLOAD</name>
<description>FTM PWM Load</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0SEL</name>
<description>Channel 0 Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1SEL</name>
<description>Channel 1 Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2SEL</name>
<description>Channel 2 Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3SEL</name>
<description>Channel 3 Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4SEL</name>
<description>Channel 4 Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5SEL</name>
<description>Channel 5 Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6SEL</name>
<description>Channel 6 Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7SEL</name>
<description>Channel 7 Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not include the channel in the matching process.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Include the channel in the matching process.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LDOK</name>
<description>Load Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Loading updated values is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loading updated values is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DAC0</name>
<description>12-Bit Digital-to-Analog Converter</description>
<prependToName>DAC0_</prependToName>
<baseAddress>0x4003F000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x24</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DAC0</name>
<value>56</value>
</interrupt>
<registers>
<register>
<dim>16</dim>
<dimIncrement>0x2</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
<name>DAT%sL</name>
<description>DAC Data Low Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA is mapped to the 16-word buffer</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>0x2</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
<name>DAT%sH</name>
<description>DAC Data High Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA1</name>
<description>When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>DAC Status Register</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DACBFRPBF</name>
<description>DAC Buffer Read Pointer Bottom Position Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC buffer read pointer is not equal to C2[DACBFUP].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC buffer read pointer is equal to C2[DACBFUP].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACBFRPTF</name>
<description>DAC Buffer Read Pointer Top Position Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC buffer read pointer is not zero.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC buffer read pointer is zero.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACBFWMF</name>
<description>DAC Buffer Watermark Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC buffer read pointer has not reached the watermark level.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC buffer read pointer has reached the watermark level.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C0</name>
<description>DAC Control Register</description>
<addressOffset>0x21</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DACBBIEN</name>
<description>DAC Buffer Read Pointer Bottom Flag Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC buffer read pointer bottom flag interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC buffer read pointer bottom flag interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACBTIEN</name>
<description>DAC Buffer Read Pointer Top Flag Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC buffer read pointer top flag interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC buffer read pointer top flag interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACBWIEN</name>
<description>DAC Buffer Watermark Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC buffer watermark interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC buffer watermark interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPEN</name>
<description>DAC Low Power Control</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>High-Power mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-Power mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACSWTRG</name>
<description>DAC Software Trigger</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC soft trigger is not valid.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC soft trigger is valid.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACTRGSEL</name>
<description>DAC Trigger Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC hardware trigger is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC software trigger is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACRFS</name>
<description>DAC Reference Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC selects DACREF_1 as the reference voltage.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC selects DACREF_2 as the reference voltage.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACEN</name>
<description>DAC Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The DAC system is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The DAC system is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>DAC Control Register 1</description>
<addressOffset>0x22</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DACBFEN</name>
<description>DAC Buffer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Buffer read pointer is disabled. The converted data is always the first word of the buffer.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACBFMD</name>
<description>DAC Buffer Work Mode Select</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Normal mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Swing mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>One-Time Scan mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>FIFO mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACBFWM</name>
<description>DAC Buffer Watermark Select</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining in FIFO will set watermark status bit.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data remaining in FIFO will set watermark status bit.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data remaining in FIFO will set watermark status bit.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data remaining in FIFO will set watermark status bit.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>DAC Control Register 2</description>
<addressOffset>0x23</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DACBFUP</name>
<description>DAC Buffer Upper Limit</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DACBFRP</name>
<description>DAC Buffer Read Pointer</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LPTMR0</name>
<description>Low Power Timer</description>
<prependToName>LPTMR0_</prependToName>
<baseAddress>0x40040000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LPTMR0</name>
<value>58</value>
</interrupt>
<registers>
<register>
<name>CSR</name>
<description>Low Power Timer Control Status Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TEN</name>
<description>Timer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LPTMR is disabled and internal logic is reset.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LPTMR is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMS</name>
<description>Timer Mode Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time Counter mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pulse Counter mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFC</name>
<description>Timer Free-Running Counter</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CNR is reset whenever TCF is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CNR is reset on overflow.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPP</name>
<description>Timer Pin Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPS</name>
<description>Timer Pin Select</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Pulse counter input 0 is selected.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Pulse counter input 1 is selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Pulse counter input 2 is selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Pulse counter input 3 is selected.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Timer Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer interrupt disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer interrupt enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF</name>
<description>Timer Compare Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The value of CNR is not equal to CMR and increments.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The value of CNR is equal to CMR and increments.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSR</name>
<description>Low Power Timer Prescale Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PCS</name>
<description>Prescaler Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Prescaler/glitch filter clock 0 selected.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Prescaler/glitch filter clock 1 selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Prescaler/glitch filter clock 2 selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Prescaler/glitch filter clock 3 selected.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PBYP</name>
<description>Prescaler Bypass</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Prescaler/glitch filter is enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Prescaler/glitch filter is bypassed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRESCALE</name>
<description>Prescale Value</description>
<bitOffset>3</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CMR</name>
<description>Low Power Timer Compare Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COMPARE</name>
<description>Compare Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNR</name>
<description>Low Power Timer Counter Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER</name>
<description>Counter Value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RFSYS</name>
<description>System register file</description>
<prependToName>RFSYS_</prependToName>
<baseAddress>0x40041000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
<name>REG%s</name>
<description>Register file register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LL</name>
<description>Low lower byte</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LH</name>
<description>Low higher byte</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HL</name>
<description>High lower byte</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HH</name>
<description>High higher byte</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SIM</name>
<description>System Integration Module</description>
<prependToName>SIM_</prependToName>
<baseAddress>0x40047000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1064</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SOPT1</name>
<description>System Options Register 1</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x1FFF0FC0</resetMask>
<fields>
<field>
<name>RAMSIZE</name>
<description>RAM size</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0001</name>
<description>8 KB</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>16 KB</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>24 KB</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>32 KB</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>48 KB</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>64 KB</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>96 KB</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>128 KB</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>256 KB</description>
<value>#1011</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSC32KOUT</name>
<description>32K Oscillator Clock Output</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>ERCLK32K is not output.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>ERCLK32K is output on PTE0.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>ERCLK32K is output on PTE26.</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSC32KSEL</name>
<description>32K oscillator clock select</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>System oscillator (OSC32KCLK)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>LPO 1 kHz</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOPT1CFG</name>
<description>SOPT1 Configuration Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
</register>
<register>
<name>SOPT2</name>
<description>System Options Register 2</description>
<addressOffset>0x1004</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKOUTSEL</name>
<description>CLKOUT select</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>010</name>
<description>Flash clock</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>LPO clock (1 kHz)</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>MCGIRCLK</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>OSCERCLK0</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>IRC 48 MHz clock</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRACECLKSEL</name>
<description>Debug trace clock select</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MCGOUTCLK</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Core/system clock</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLFLLSEL</name>
<description>PLL/FLL clock select</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>MCGFLLCLK clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>IRC48 MHz clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPUARTSRC</name>
<description>LPUART clock source select</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Clock disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>MCGFLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL].</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>OSCERCLK clock</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>MCGIRCLK clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOPT4</name>
<description>System Options Register 4</description>
<addressOffset>0x100C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FTM0FLT0</name>
<description>FTM0 Fault 0 Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM0_FLT0 pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMP0 out</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0FLT1</name>
<description>FTM0 Fault 1 Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM0_FLT1 pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMP1 out</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM1FLT0</name>
<description>FTM1 Fault 0 Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM1_FLT0 pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMP0 out</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM2FLT0</name>
<description>FTM2 Fault 0 Select</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM2_FLT0 pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMP0 out</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM1CH0SRC</name>
<description>FTM1 channel 0 input capture source select</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>FTM1_CH0 signal</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>CMP0 output</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>CMP1 output</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM2CH0SRC</name>
<description>FTM2 channel 0 input capture source select</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>FTM2_CH0 signal</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>CMP0 output</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>CMP1 output</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM2CH1SRC</name>
<description>FTM2 channel 1 input capture source select</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM2_CH1 signal</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0CLKSEL</name>
<description>FlexTimer 0 External Clock Pin Select</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM_CLK0 pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM_CLK1 pin</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM1CLKSEL</name>
<description>FTM1 External Clock Pin Select</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM_CLK0 pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM_CLK1 pin</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM2CLKSEL</name>
<description>FlexTimer 2 External Clock Pin Select</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM2 external clock driven by FTM_CLK0 pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM2 external clock driven by FTM_CLK1 pin.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0TRG0SRC</name>
<description>FlexTimer 0 Hardware Trigger 0 Source Select</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>HSCMP0 output drives FTM0 hardware trigger 0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM1 channel match drives FTM0 hardware trigger 0</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0TRG1SRC</name>
<description>FlexTimer 0 Hardware Trigger 1 Source Select</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDB output trigger 1 drives FTM0 hardware trigger 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM2 channel match drives FTM0 hardware trigger 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOPT5</name>
<description>System Options Register 5</description>
<addressOffset>0x1010</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UART0TXSRC</name>
<description>UART 0 transmit data source select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>UART0_TX pin</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>UART0_TX pin modulated with FTM1 channel 0 output</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>UART0_TX pin modulated with FTM2 channel 0 output</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0RXSRC</name>
<description>UART 0 receive data source select</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>UART0_RX pin</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>CMP0</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>CMP1</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART1TXSRC</name>
<description>UART 1 transmit data source select</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>UART1_TX pin</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>UART1_TX pin modulated with FTM1 channel 0 output</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>UART1_TX pin modulated with FTM2 channel 0 output</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART1RXSRC</name>
<description>UART 1 receive data source select</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>UART1_RX pin</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>CMP0</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>CMP1</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPUART0RXSRC</name>
<description>LPUART0 receive data source select</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>LPUART0_RX pin</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>CMP0 output</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>CMP1 output</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOPT7</name>
<description>System Options Register 7</description>
<addressOffset>0x1018</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADC0TRGSEL</name>
<description>ADC0 trigger select</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>PDB external trigger pin input (PDB0_EXTRG)</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>High speed comparator 0 output</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>High speed comparator 1 output</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>PIT trigger 0</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>PIT trigger 1</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>PIT trigger 2</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>PIT trigger 3</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>FTM0 trigger</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>FTM1 trigger</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>FTM2 trigger</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Low-power timer (LPTMR) trigger</description>
<value>#1110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC0PRETRGSEL</name>
<description>ADC0 pretrigger select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pre-trigger A</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pre-trigger B</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC0ALTTRGEN</name>
<description>ADC0 alternate trigger enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDB trigger selected for ADC0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Alternate trigger selected for ADC0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC1TRGSEL</name>
<description>ADC1 trigger select</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>PDB external trigger pin input (PDB0_EXTRG)</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>High speed comparator 0 output</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>High speed comparator 1 output</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>PIT trigger 0</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>PIT trigger 1</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>PIT trigger 2</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>PIT trigger 3</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>FTM0 trigger</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>FTM1 trigger</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>FTM2 trigger</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Low-power timer (LPTMR) trigger</description>
<value>#1110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC1PRETRGSEL</name>
<description>ADC1 pre-trigger select</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pre-trigger A selected for ADC1.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pre-trigger B selected for ADC1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC1ALTTRGEN</name>
<description>ADC1 alternate trigger enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDB trigger selected for ADC1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SOPT8</name>
<description>System Options Register 8</description>
<addressOffset>0x101C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FTM0SYNCBIT</name>
<description>FTM0 Hardware Trigger 0 Software Synchronization</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM1SYNCBIT</name>
<description>FTM1 Hardware Trigger 0 Software Synchronization</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM2SYNCBIT</name>
<description>FTM2 Hardware Trigger 0 Software Synchronization</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0OCH0SRC</name>
<description>FTM0 channel 0 output source</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM0_CH0 pin is output of FTM0 channel 0 output</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0OCH1SRC</name>
<description>FTM0 channel 1 output source</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM0_CH1 pin is output of FTM0 channel 1 output</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0OCH2SRC</name>
<description>FTM0 channel 2 output source</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM0_CH2 pin is output of FTM0 channel 2 output</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0OCH3SRC</name>
<description>FTM0 channel 3 output source</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM0_CH3 pin is output of FTM0 channel 3 output</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0OCH4SRC</name>
<description>FTM0 channel 4 output source</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM0_CH4 pin is output of FTM0 channel 4 output</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0OCH5SRC</name>
<description>FTM0 channel 5 output source</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM0_CH5 pin is output of FTM0 channel 5 output</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0OCH6SRC</name>
<description>FTM0 channel 6 output source</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM0_CH6 pin is output of FTM0 channel 6 output</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0OCH7SRC</name>
<description>FTM0 channel 7 output source</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FTM0_CH7 pin is output of FTM0 channel 7 output</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SDID</name>
<description>System Device Identification Register</description>
<addressOffset>0x1024</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x6F0</resetValue>
<resetMask>0xF0FF0</resetMask>
<fields>
<field>
<name>PINID</name>
<description>Pincount identification</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0010</name>
<description>32-pin</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>48-pin</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>64-pin</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>80-pin</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>81-pin or 121-pin</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>100-pin</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>121-pin</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>144-pin</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Custom pinout (WLCSP)</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>169-pin</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>256-pin</description>
<value>#1110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIEID</name>
<description>Device die number</description>
<bitOffset>7</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
</field>
<field>
<name>REVID</name>
<description>Device revision number</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SERIESID</name>
<description>Kinetis Series ID</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Kinetis K series</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Kinetis L series</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Kinetis W series</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Kinetis V series</description>
<value>#0110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SUBFAMID</name>
<description>Kinetis Sub-Family ID</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>KVx0 Subfamily</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>KVx1 Subfamily</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>KVx2 Subfamily</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>KVx3 Subfamily</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>KVx4 Subfamily</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>KVx5 Subfamily</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>KVx6 Subfamily</description>
<value>#0110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAMILYID</name>
<description>Kinetis Family ID</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0001</name>
<description>KV1x Family</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>KV2x Family</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>KV3x Family</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>KV4x Family</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>KV6x Family</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>KV7x Family</description>
<value>#0111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC4</name>
<description>System Clock Gating Control Register 4</description>
<addressOffset>0x1034</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0100030</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EWM</name>
<description>EWM Clock Gate Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C0</name>
<description>I2C0 Clock Gate Control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C1</name>
<description>I2C1 Clock Gate Control</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0</name>
<description>UART0 Clock Gate Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART1</name>
<description>UART1 Clock Gate Control</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART2</name>
<description>UART2 Clock Gate Control</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP</name>
<description>Comparator Clock Gate Control</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREF</name>
<description>VREF Clock Gate Control</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC5</name>
<description>System Clock Gating Control Register 5</description>
<addressOffset>0x1038</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40182</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LPTMR</name>
<description>Low Power Timer Access Control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Access disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Access enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTA</name>
<description>Port A Clock Gate Control</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTB</name>
<description>Port B Clock Gate Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTC</name>
<description>Port C Clock Gate Control</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTD</name>
<description>Port D Clock Gate Control</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORTE</name>
<description>Port E Clock Gate Control</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC6</name>
<description>System Clock Gating Control Register 6</description>
<addressOffset>0x103C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FTF</name>
<description>Flash Memory Clock Gate Control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAMUX</name>
<description>DMA Mux Clock Gate Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC1</name>
<description>ADC1 Clock Gate Control</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPUART0</name>
<description>LPUART0 Clock Gate Control</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI0</name>
<description>SPI0 Clock Gate Control</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI1</name>
<description>SPI1 Clock Gate Control</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRC</name>
<description>CRC Clock Gate Control</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PDB</name>
<description>PDB Clock Gate Control</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PIT</name>
<description>PIT Clock Gate Control</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM0</name>
<description>FTM0 Clock Gate Control</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM1</name>
<description>FTM1 Clock Gate Control</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FTM2</name>
<description>FTM2 Clock Gate Control</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC0</name>
<description>ADC0 Clock Gate Control</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DAC0</name>
<description>DAC0 Clock Gate Control</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SCGC7</name>
<description>System Clock Gating Control Register 7</description>
<addressOffset>0x1040</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMA</name>
<description>DMA Clock Gate Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLKDIV1</name>
<description>System Clock Divider Register 1</description>
<addressOffset>0x1044</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OUTDIV4</name>
<description>Clock 4 output divider value</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Divide-by-1.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Divide-by-2.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Divide-by-3.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Divide-by-4.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Divide-by-5.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Divide-by-6.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Divide-by-7.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Divide-by-8.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Divide-by-9.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Divide-by-10.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Divide-by-11.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Divide-by-12.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Divide-by-13.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Divide-by-14.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Divide-by-15.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Divide-by-16.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUTDIV2</name>
<description>Clock 2 output divider value</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Divide-by-1.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Divide-by-2.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Divide-by-3.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Divide-by-4.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Divide-by-5.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Divide-by-6.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Divide-by-7.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Divide-by-8.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Divide-by-9.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Divide-by-10.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Divide-by-11.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Divide-by-12.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Divide-by-13.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Divide-by-14.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Divide-by-15.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Divide-by-16.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUTDIV1</name>
<description>Clock 1 output divider value</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Divide-by-1.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>Divide-by-2.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>Divide-by-3.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>Divide-by-4.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0100</name>
<description>Divide-by-5.</description>
<value>#0100</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>Divide-by-6.</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0110</name>
<description>Divide-by-7.</description>
<value>#0110</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>Divide-by-8.</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Divide-by-9.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Divide-by-10.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Divide-by-11.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Divide-by-12.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Divide-by-13.</description>
<value>#1100</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>Divide-by-14.</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1110</name>
<description>Divide-by-15.</description>
<value>#1110</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Divide-by-16.</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FCFG1</name>
<description>Flash Configuration Register 1</description>
<addressOffset>0x104C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0F0F00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLASHDIS</name>
<description>Flash Disable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Flash is enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Flash is disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASHDOZE</name>
<description>Flash Doze</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Flash remains enabled during Wait mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Flash is disabled for the duration of Wait mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFSIZE</name>
<description>Program flash size</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0011</name>
<description>32 KB of program flash memory</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>0101</name>
<description>64 KB of program flash memory</description>
<value>#0101</value>
</enumeratedValue>
<enumeratedValue>
<name>0111</name>
<description>128 KB of program flash memory</description>
<value>#0111</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>256 KB of program flash memory</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>512 KB of program flash memory</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1101</name>
<description>1024 KB of program flash memory</description>
<value>#1101</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>128 KB of program flash memory</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FCFG2</name>
<description>Flash Configuration Register 2</description>
<addressOffset>0x1050</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x7FFF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MAXADDR1</name>
<description>Max address block 1</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MAXADDR0</name>
<description>Max address block 0</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UIDH</name>
<description>Unique Identification Register High</description>
<addressOffset>0x1054</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UID</name>
<description>Unique Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UIDMH</name>
<description>Unique Identification Register Mid-High</description>
<addressOffset>0x1058</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UID</name>
<description>Unique Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UIDML</name>
<description>Unique Identification Register Mid Low</description>
<addressOffset>0x105C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UID</name>
<description>Unique Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UIDL</name>
<description>Unique Identification Register Low</description>
<addressOffset>0x1060</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UID</name>
<description>Unique Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTA</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTA_</prependToName>
<baseAddress>0x40049000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTA</name>
<value>59</value>
</interrupt>
<registers>
<register>
<dim>32</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x702</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ODE</name>
<description>Open Drain Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Open drain output is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTB</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTB_</prependToName>
<baseAddress>0x4004A000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTB</name>
<value>60</value>
</interrupt>
<registers>
<register>
<dim>32</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ODE</name>
<description>Open Drain Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Open drain output is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTC</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTC_</prependToName>
<baseAddress>0x4004B000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTC</name>
<value>61</value>
</interrupt>
<registers>
<register>
<dim>32</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ODE</name>
<description>Open Drain Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Open drain output is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTD</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTD_</prependToName>
<baseAddress>0x4004C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xCC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTD</name>
<value>62</value>
</interrupt>
<registers>
<register>
<dim>32</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ODE</name>
<description>Open Drain Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Open drain output is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFER</name>
<description>Digital Filter Enable Register</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFE</name>
<description>Digital Filter Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFCR</name>
<description>Digital Filter Clock Register</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CS</name>
<description>Clock Source</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Digital filters are clocked by the bus clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Digital filters are clocked by the 1 kHz LPO clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DFWR</name>
<description>Digital Filter Width Register</description>
<addressOffset>0xC8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FILT</name>
<description>Filter Length</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PORTE</name>
<description>Pin Control and Interrupts</description>
<groupName>PORT</groupName>
<prependToName>PORTE_</prependToName>
<baseAddress>0x4004D000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTE</name>
<value>63</value>
</interrupt>
<registers>
<register>
<dim>32</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
<name>PCR%s</name>
<description>Pin Control Register n</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS</name>
<description>Pull Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Pull Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRE</name>
<description>Slew Rate Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFE</name>
<description>Passive Filter Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Passive input filter is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ODE</name>
<description>Open Drain Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Open drain output is disabled on the corresponding pin.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSE</name>
<description>Drive Strength Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUX</name>
<description>Pin Mux Control</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Pin disabled (analog).</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Alternative 1 (GPIO).</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Alternative 2 (chip-specific).</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Alternative 3 (chip-specific).</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Alternative 4 (chip-specific).</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Alternative 5 (chip-specific).</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Alternative 6 (chip-specific).</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Alternative 7 (chip-specific).</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LK</name>
<description>Lock Register</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Control Register fields [15:0] are not locked.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQC</name>
<description>Interrupt Configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Interrupt/DMA request disabled.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>0001</name>
<description>DMA request on rising edge.</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>0010</name>
<description>DMA request on falling edge.</description>
<value>#0010</value>
</enumeratedValue>
<enumeratedValue>
<name>0011</name>
<description>DMA request on either edge.</description>
<value>#0011</value>
</enumeratedValue>
<enumeratedValue>
<name>1000</name>
<description>Interrupt when logic 0.</description>
<value>#1000</value>
</enumeratedValue>
<enumeratedValue>
<name>1001</name>
<description>Interrupt on rising-edge.</description>
<value>#1001</value>
</enumeratedValue>
<enumeratedValue>
<name>1010</name>
<description>Interrupt on falling-edge.</description>
<value>#1010</value>
</enumeratedValue>
<enumeratedValue>
<name>1011</name>
<description>Interrupt on either edge.</description>
<value>#1011</value>
</enumeratedValue>
<enumeratedValue>
<name>1100</name>
<description>Interrupt when logic 1.</description>
<value>#1100</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCLR</name>
<description>Global Pin Control Low Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GPCHR</name>
<description>Global Pin Control High Register</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPWD</name>
<description>Global Pin Write Data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
<field>
<name>GPWE</name>
<description>Global Pin Write Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISFR</name>
<description>Interrupt Status Flag Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISF</name>
<description>Interrupt Status Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configured interrupt is not detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WDOG</name>
<description>Generation 2008 Watchdog Timer</description>
<prependToName>WDOG_</prependToName>
<baseAddress>0x40052000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WDOG_EWM</name>
<value>22</value>
</interrupt>
<registers>
<register>
<name>STCTRLH</name>
<description>Watchdog Status and Control Register High</description>
<addressOffset>0</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x1D3</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WDOGEN</name>
<description>Enables or disables the WDOG&apos;s operation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKSRC</name>
<description>Selects clock source for the WDOG timer and other internal timing operations.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG clock sourced from LPO .</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG clock sourced from alternate clock source.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRQRSTEN</name>
<description>Used to enable the debug breadcrumbs feature</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG time-out generates reset only.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG time-out initially generates an interrupt. After WCT, it generates a reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WINEN</name>
<description>Enables Windowing mode.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Windowing mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Windowing mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALLOWUPDATE</name>
<description>Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window (WCT) closes, through unlock sequence</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No further updates allowed to WDOG write-once registers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG write-once registers can be unlocked for updating.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGEN</name>
<description>Enables or disables WDOG in Debug mode.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG is disabled in CPU Debug mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG is enabled in CPU Debug mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPEN</name>
<description>Enables or disables WDOG in Stop mode.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG is disabled in CPU Stop mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG is enabled in CPU Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAITEN</name>
<description>Enables or disables WDOG in Wait mode.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG is disabled in CPU Wait mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG is enabled in CPU Wait mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TESTWDOG</name>
<description>Puts the watchdog in the functional test mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TESTSEL</name>
<description>Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BYTESEL</name>
<description>This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Byte 0 selected</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Byte 1 selected</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Byte 2 selected</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Byte 3 selected</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DISTESTWDOG</name>
<description>Allows the WDOG&apos;s functional test mode to be disabled permanently</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WDOG functional test mode is not disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WDOG functional test mode is disabled permanently until reset.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STCTRLL</name>
<description>Watchdog Status and Control Register Low</description>
<addressOffset>0x2</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>INTFLG</name>
<description>Interrupt flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TOVALH</name>
<description>Watchdog Time-out Value Register High</description>
<addressOffset>0x4</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x4C</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TOVALHIGH</name>
<description>Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TOVALL</name>
<description>Watchdog Time-out Value Register Low</description>
<addressOffset>0x6</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x4B4C</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TOVALLOW</name>
<description>Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WINH</name>
<description>Watchdog Window Register High</description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WINHIGH</name>
<description>Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WINL</name>
<description>Watchdog Window Register Low</description>
<addressOffset>0xA</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WINLOW</name>
<description>Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>REFRESH</name>
<description>Watchdog Refresh register</description>
<addressOffset>0xC</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xB480</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WDOGREFRESH</name>
<description>Watchdog refresh register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UNLOCK</name>
<description>Watchdog Unlock register</description>
<addressOffset>0xE</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0xD928</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WDOGUNLOCK</name>
<description>Writing the unlock sequence values to this register to makes the watchdog write-once registers writable again</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TMROUTH</name>
<description>Watchdog Timer Output Register High</description>
<addressOffset>0x10</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TIMEROUTHIGH</name>
<description>Shows the value of the upper 16 bits of the watchdog timer.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TMROUTL</name>
<description>Watchdog Timer Output Register Low</description>
<addressOffset>0x12</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TIMEROUTLOW</name>
<description>Shows the value of the lower 16 bits of the watchdog timer.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RSTCNT</name>
<description>Watchdog Reset Count register</description>
<addressOffset>0x14</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RSTCNT</name>
<description>Counts the number of times the watchdog resets the system</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<description>Watchdog Prescaler register</description>
<addressOffset>0x16</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0x400</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PRESCVAL</name>
<description>3-bit prescaler for the watchdog clock source</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>EWM</name>
<description>External Watchdog Monitor</description>
<prependToName>EWM_</prependToName>
<baseAddress>0x40061000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x6</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WDOG_EWM</name>
<value>22</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>Control Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EWMEN</name>
<description>EWM enable.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ASSIN</name>
<description>EWM_in&apos;s Assertion State Select.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INEN</name>
<description>Input Enable.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INTEN</name>
<description>Interrupt Enable.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SERV</name>
<description>Service Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SERVICE</name>
<description>The EWM service mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CMPL</name>
<description>Compare Low Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>COMPAREL</name>
<description>To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum service time is required</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMPH</name>
<description>Compare High Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>COMPAREH</name>
<description>To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum service time is required</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLKPRESCALER</name>
<description>Clock Prescaler Register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CLK_DIV</name>
<description>Selected low power source for running the EWM counter can be prescaled as below</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MCG</name>
<description>Multipurpose Clock Generator module</description>
<prependToName>MCG_</prependToName>
<baseAddress>0x40064000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xE</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>C1</name>
<description>MCG Control 1 Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IREFSTEN</name>
<description>Internal Reference Stop Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal reference clock is disabled in Stop mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IRCLKEN</name>
<description>Internal Reference Clock Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>MCGIRCLK inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MCGIRCLK active.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IREFS</name>
<description>Internal Reference Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock is selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The slow internal reference clock is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FRDIV</name>
<description>FLL External Reference Divider</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKS</name>
<description>Clock Source Select</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Output of FLL is selected.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - Internal reference clock is selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Encoding 2 - External reference clock is selected.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Encoding 3 - Reserved.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>MCG Control 2 Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IRCS</name>
<description>Internal Reference Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slow internal reference clock selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fast internal reference clock selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LP</name>
<description>Low Power Select</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FLL is not disabled in bypass modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FLL is disabled in bypass modes (lower power)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EREFS</name>
<description>External Reference Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock requested.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Oscillator requested.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HGO</name>
<description>High Gain Oscillator Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Configure crystal oscillator for low-power operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Configure crystal oscillator for high-gain operation.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RANGE</name>
<description>Frequency Range Select</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Low frequency range selected for the crystal oscillator .</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - High frequency range selected for the crystal oscillator .</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FCFTRIM</name>
<description>Fast Internal Reference Clock Fine Trim</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LOCRE0</name>
<description>Loss of Clock Reset Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt request is generated on a loss of OSC0 external reference clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Generate a reset request on a loss of OSC0 external reference clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>MCG Control 3 Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>SCTRIM</name>
<description>Slow Internal Reference Clock Trim Setting</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>MCG Control 4 Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xE0</resetMask>
<fields>
<field>
<name>SCFTRIM</name>
<description>Slow Internal Reference Clock Fine Trim</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FCTRIM</name>
<description>Fast Internal Reference Clock Trim Setting</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DRST_DRS</name>
<description>DCO Range Select</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Low range (reset default).</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - Mid range.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Encoding 2 - Mid-high range.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Encoding 3 - High range.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMX32</name>
<description>DCO Maximum Frequency with 32.768 kHz Reference</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DCO has a default range of 25%.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DCO is fine-tuned for maximum frequency with 32.768 kHz reference.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C5</name>
<description>MCG Control 5 Register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
</register>
<register>
<name>C6</name>
<description>MCG Control 6 Register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CME</name>
<description>Clock Monitor Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External clock monitor is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Generate a reset request on loss of external clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S</name>
<description>MCG Status Register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x10</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IRCST</name>
<description>Internal Reference Clock Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Source of internal reference clock is the slow clock (32 kHz IRC).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Source of internal reference clock is the fast clock (4 MHz IRC).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSCINIT0</name>
<description>OSC Initialization</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CLKST</name>
<description>Clock Mode Status</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Encoding 0 - Output of the FLL is selected (reset default).</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Encoding 1 - Internal reference clock is selected.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Encoding 2 - External reference clock is selected.</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IREFST</name>
<description>Internal Reference Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Source of FLL reference clock is the external reference clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Source of FLL reference clock is the internal reference clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SC</name>
<description>MCG Status and Control Register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LOCS0</name>
<description>OSC0 Loss of Clock Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Loss of OSC0 has not occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loss of OSC0 has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FCRDIV</name>
<description>Fast Clock Internal Reference Divider</description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Divide Factor is 1</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Divide Factor is 2.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Divide Factor is 4.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Divide Factor is 8.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Divide Factor is 16</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Divide Factor is 32</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Divide Factor is 64</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>Divide Factor is 128.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLTPRSRV</name>
<description>FLL Filter Preserve Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FLL filter and FLL frequency will reset on changes to currect clock mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Fll filter and FLL frequency retain their previous values during new clock mode change.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATMF</name>
<description>Automatic Trim Machine Fail Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Automatic Trim Machine completed normally.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Automatic Trim Machine failed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATMS</name>
<description>Automatic Trim Machine Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>32 kHz Internal Reference Clock selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>4 MHz Internal Reference Clock selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATME</name>
<description>Automatic Trim Machine Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Auto Trim Machine disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Auto Trim Machine enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ATCVH</name>
<description>MCG Auto Trim Compare Value High Register</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ATCVH</name>
<description>ATM Compare Value High</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ATCVL</name>
<description>MCG Auto Trim Compare Value Low Register</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ATCVL</name>
<description>ATM Compare Value Low</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C7</name>
<description>MCG Control 7 Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>OSCSEL</name>
<description>MCG OSC Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Selects Oscillator (OSCCLK0).</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Selects 32 kHz RTC Oscillator.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Selects Oscillator (OSCCLK1).</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C8</name>
<description>MCG Control 8 Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LOCS1</name>
<description>RTC Loss of Clock Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Loss of RTC has not occur.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loss of RTC has occur</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CME1</name>
<description>Clock Monitor Enable1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External clock monitor is disabled for RTC clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External clock monitor is enabled for RTC clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCRE1</name>
<description>Loss of Clock Reset Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt request is generated on a loss of RTC external reference clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Generate a reset request on a loss of RTC external reference clock</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OSC</name>
<description>Oscillator</description>
<prependToName>OSC_</prependToName>
<baseAddress>0x40065000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x3</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR</name>
<description>OSC Control Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SC16P</name>
<description>Oscillator 16 pF Capacitor Load Configure</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 16 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC8P</name>
<description>Oscillator 8 pF Capacitor Load Configure</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 8 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC4P</name>
<description>Oscillator 4 pF Capacitor Load Configure</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 4 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SC2P</name>
<description>Oscillator 2 pF Capacitor Load Configure</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable the selection.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Add 2 pF capacitor to the oscillator load.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EREFSTEN</name>
<description>External Reference Stop Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock is disabled in Stop mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERCLKEN</name>
<description>External Reference Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External reference clock is inactive.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External reference clock is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DIV</name>
<description>OSC_DIV</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ERPS</name>
<description>ERCLK prescaler</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>The divisor ratio is 1.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>The divisor ratio is 2.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>The divisor ratio is 4.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>The divisor ratio is 8.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C0</name>
<description>Inter-Integrated Circuit</description>
<groupName>I2C</groupName>
<prependToName>I2C0_</prependToName>
<baseAddress>0x40066000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C0</name>
<value>24</value>
</interrupt>
<registers>
<register>
<name>A1</name>
<description>I2C Address Register 1</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>F</name>
<description>I2C Frequency Divider register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ICR</name>
<description>ClockRate</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MULT</name>
<description>Multiplier Factor</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>mul = 1</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>mul = 2</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>mul = 4</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>I2C Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DMAEN</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All DMA signalling disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUEN</name>
<description>Wakeup Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the wakeup function in low power mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTA</name>
<description>Repeat START</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXAK</name>
<description>Transmit Acknowledge Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TX</name>
<description>Transmit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MST</name>
<description>Master Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Master mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIE</name>
<description>I2C Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICEN</name>
<description>I2C Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S</name>
<description>I2C Status register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXAK</name>
<description>Receive Acknowledge</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIF</name>
<description>Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt pending</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt pending</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRW</name>
<description>Slave Read/Write</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave receive, master writing to slave</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave transmit, master reading from slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM</name>
<description>Range Address Match</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ARBL</name>
<description>Arbitration Lost</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Standard bus operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loss of arbitration.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSY</name>
<description>Bus Busy</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus is idle</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus is busy</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IAAS</name>
<description>Addressed As A Slave</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF</name>
<description>Transfer Complete Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer in progress</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transfer complete</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>I2C Data I/O register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>I2C Control Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Slave Address</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RMEN</name>
<description>Range Address Matching Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SBRC</name>
<description>Slave Baud Rate Control</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave baud rate is independent of the master baud rate</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HDRS</name>
<description>High Drive Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal drive mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADEXT</name>
<description>Address Extension</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>7-bit address scheme</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>10-bit address scheme</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GCAEN</name>
<description>General Call Address Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FLT</name>
<description>I2C Programmable Input Glitch Filter register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FLT</name>
<description>I2C Programmable Filter Factor</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No filter/bypass</description>
<value>#0000</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STARTF</name>
<description>I2C Bus Start Detect Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No start happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Start detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIE</name>
<description>I2C Bus Stop or Start Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop or start detection interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop or start detection interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPF</name>
<description>I2C Bus Stop Detect Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No stop happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHEN</name>
<description>Stop Hold Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop holdoff is disabled. The MCU&apos;s entry to stop mode is not gated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop holdoff is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RA</name>
<description>I2C Range Address register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAD</name>
<description>Range Slave Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SMB</name>
<description>I2C SMBus Control and Status register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SHTF2IE</name>
<description>SHTF2 Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SHTF2 interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SHTF2 interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF2</name>
<description>SCL High Timeout Flag 2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF1</name>
<description>SCL High Timeout Flag 1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA high timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA high timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLTF</name>
<description>SCL Low Timeout Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCKSEL</name>
<description>Timeout Counter Clock Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timeout counter counts at the frequency of the I2C module clock / 64</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timeout counter counts at the frequency of the I2C module clock</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SIICAEN</name>
<description>Second I2C Address Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C address register 2 matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C address register 2 matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALERTEN</name>
<description>SMBus Alert Response Address Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SMBus alert response address matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SMBus alert response address matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FACK</name>
<description>Fast NACK/ACK Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An ACK or NACK is sent on the following receiving data byte</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>A2</name>
<description>I2C Address Register 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC2</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SAD</name>
<description>SMBus Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTH</name>
<description>I2C SCL Low Timeout Register High</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>Most significant byte of SCL low timeout value that determines the timeout period of SCL low.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTL</name>
<description>I2C SCL Low Timeout Register Low</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>Least significant byte of SCL low timeout value that determines the timeout period of SCL low.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C1</name>
<description>Inter-Integrated Circuit</description>
<groupName>I2C</groupName>
<prependToName>I2C1_</prependToName>
<baseAddress>0x40067000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C1</name>
<value>25</value>
</interrupt>
<registers>
<register>
<name>A1</name>
<description>I2C Address Register 1</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>F</name>
<description>I2C Frequency Divider register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ICR</name>
<description>ClockRate</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MULT</name>
<description>Multiplier Factor</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>mul = 1</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>mul = 2</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>mul = 4</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>I2C Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DMAEN</name>
<description>DMA Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All DMA signalling disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUEN</name>
<description>Wakeup Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation. No interrupt generated when address matching in low power mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables the wakeup function in low power mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTA</name>
<description>Repeat START</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXAK</name>
<description>Transmit Acknowledge Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TX</name>
<description>Transmit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MST</name>
<description>Master Mode Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Master mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIE</name>
<description>I2C Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICEN</name>
<description>I2C Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S</name>
<description>I2C Status register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXAK</name>
<description>Receive Acknowledge</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Acknowledge signal was received after the completion of one byte of data transmission on the bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No acknowledge signal detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IICIF</name>
<description>Interrupt Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt pending</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt pending</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRW</name>
<description>Slave Read/Write</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave receive, master writing to slave</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave transmit, master reading from slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM</name>
<description>Range Address Match</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ARBL</name>
<description>Arbitration Lost</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Standard bus operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loss of arbitration.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSY</name>
<description>Bus Busy</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bus is idle</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus is busy</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IAAS</name>
<description>Addressed As A Slave</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not addressed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Addressed as a slave</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCF</name>
<description>Transfer Complete Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer in progress</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transfer complete</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>I2C Data I/O register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>I2C Control Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AD</name>
<description>Slave Address</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RMEN</name>
<description>Range Address Matching Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SBRC</name>
<description>Slave Baud Rate Control</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The slave baud rate follows the master baud rate and clock stretching may occur</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave baud rate is independent of the master baud rate</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HDRS</name>
<description>High Drive Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal drive mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High drive mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADEXT</name>
<description>Address Extension</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>7-bit address scheme</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>10-bit address scheme</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GCAEN</name>
<description>General Call Address Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FLT</name>
<description>I2C Programmable Input Glitch Filter register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FLT</name>
<description>I2C Programmable Filter Factor</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No filter/bypass</description>
<value>#0000</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STARTF</name>
<description>I2C Bus Start Detect Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No start happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Start detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSIE</name>
<description>I2C Bus Stop or Start Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop or start detection interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop or start detection interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPF</name>
<description>I2C Bus Stop Detect Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No stop happens on I2C bus</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop detected on I2C bus</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHEN</name>
<description>Stop Hold Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stop holdoff is disabled. The MCU&apos;s entry to stop mode is not gated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Stop holdoff is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RA</name>
<description>I2C Range Address register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAD</name>
<description>Range Slave Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SMB</name>
<description>I2C SMBus Control and Status register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SHTF2IE</name>
<description>SHTF2 Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SHTF2 interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SHTF2 interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF2</name>
<description>SCL High Timeout Flag 2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SHTF1</name>
<description>SCL High Timeout Flag 1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No SCL high and SDA high timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SCL high and SDA high timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLTF</name>
<description>SCL Low Timeout Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No low timeout occurs</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low timeout occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCKSEL</name>
<description>Timeout Counter Clock Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timeout counter counts at the frequency of the I2C module clock / 64</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timeout counter counts at the frequency of the I2C module clock</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SIICAEN</name>
<description>Second I2C Address Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C address register 2 matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C address register 2 matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALERTEN</name>
<description>SMBus Alert Response Address Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SMBus alert response address matching is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SMBus alert response address matching is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FACK</name>
<description>Fast NACK/ACK Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>An ACK or NACK is sent on the following receiving data byte</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>A2</name>
<description>I2C Address Register 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC2</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SAD</name>
<description>SMBus Address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTH</name>
<description>I2C SCL Low Timeout Register High</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>Most significant byte of SCL low timeout value that determines the timeout period of SCL low.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLTL</name>
<description>I2C SCL Low Timeout Register Low</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SSLT</name>
<description>Least significant byte of SCL low timeout value that determines the timeout period of SCL low.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART0</name>
<description>Serial Communication Interface</description>
<groupName>UART</groupName>
<prependToName>UART0_</prependToName>
<baseAddress>0x4006A000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x40</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART0_RX_TX</name>
<value>31</value>
</interrupt>
<interrupt>
<name>UART0_ERR</name>
<value>32</value>
</interrupt>
<registers>
<register>
<name>BDH</name>
<description>UART Baud Rate Registers: High</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXEDGIE</name>
<description>RxD Input Active Edge Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from RXEDGIF disabled using polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXEDGIF interrupt request enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIE</name>
<description>LIN Break Detect Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LBKDIF interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LBKDIF interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BDL</name>
<description>UART Baud Rate Registers: Low</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>UART Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PT</name>
<description>Parity Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Even parity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Odd parity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Parity function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILT</name>
<description>Idle Line Type Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle character bit count starts after start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle character bit count starts after stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Receiver Wakeup Method Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle line wakeup.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address mark wakeup.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M</name>
<description>9-bit or 8-bit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRC</name>
<description>Receiver Source Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Selects internal loop back mode. The receiver input is internally connected to transmitter output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UARTSWAI</name>
<description>UART Stops in Wait Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART clock continues to run in Wait mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART clock freezes while CPU is in Wait mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOPS</name>
<description>Loop Mode Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>UART Control Register 2</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBK</name>
<description>Send Break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal transmitter operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Queue break characters to be sent.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver Wakeup Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILIE</name>
<description>Idle Line Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IDLE interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IDLE interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIE</name>
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RDRF interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RDRF interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission Complete Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TC interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TC interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TDRE interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TDRE interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S1</name>
<description>UART Status Register 1</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PF</name>
<description>Parity Error Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No framing error detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Framing error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NF</name>
<description>Noise Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OR</name>
<description>Receiver Overrun Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLE</name>
<description>Idle Line Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC</name>
<description>Transmit Complete Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter active (sending data, a preamble, or a break).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter idle (transmission activity complete).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S2</name>
<description>UART Status Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAF</name>
<description>Receiver Active Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART receiver idle/inactive waiting for a start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver active, RxD input not idle.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDE</name>
<description>LIN Break Detection Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character detection is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRK13</name>
<description>Break Transmit Character Length</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is 10, 11, or 12 bits long.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is 13 or 14 bits long.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWUID</name>
<description>Receive Wakeup Idle Detect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>S1[IDLE] is not set upon detection of an idle character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>S1[IDLE] is set upon detection of an idle character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXINV</name>
<description>Receive Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSBF</name>
<description>Most Significant Bit First</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIF</name>
<description>RxD Pin Active Edge Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No active edge on the receive pin has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An active edge on the receive pin has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIF</name>
<description>LIN Break Detect Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No LIN break character detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LIN break character detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>UART Control Register 3</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PEIE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FE interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FE interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEIE</name>
<description>Noise Error Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>NF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OR interrupts are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>OR interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXINV</name>
<description>Transmit Data Inversion.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIR</name>
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXD pin is an input in single wire mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXD pin is an output in single wire mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T8</name>
<description>Transmit Bit 8</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8</name>
<description>Received Bit 8</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>UART Data Register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RT</name>
<description>Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA1</name>
<description>UART Match Address Registers 1</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA2</name>
<description>UART Match Address Registers 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>UART Control Register 4</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BRFA</name>
<description>Baud Rate Fine Adjust</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M10</name>
<description>10-bit Mode select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The parity bit is the ninth bit in the serial transmission.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The parity bit is the tenth bit in the serial transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN2</name>
<description>Match Address Mode Enable 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN1</name>
<description>Match Address Mode Enable 1</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C5</name>
<description>UART Control Register 5</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RDMAS</name>
<description>Receiver Full DMA Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAS</name>
<description>Transmitter DMA Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ED</name>
<description>UART Extended Data Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PARITYE</name>
<description>The current received dataword contained in D and C3[R8] was received with a parity error.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dataword was received with a parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOISY</name>
<description>The current received dataword contained in D and C3[R8] was received with noise.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The data was received with noise.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODEM</name>
<description>UART Modem Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCTSE</name>
<description>Transmitter clear-to-send enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS has no effect on the transmitter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSE</name>
<description>Transmitter request-to-send enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The transmitter has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSPOL</name>
<description>Transmitter request-to-send polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter RTS is active low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter RTS is active high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXRTSE</name>
<description>Receiver request-to-send enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The receiver has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IR</name>
<description>UART Infrared Register</description>
<addressOffset>0xE</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TNP</name>
<description>Transmitter narrow pulse</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>3/16.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>1/16.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>1/32.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>1/4.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IREN</name>
<description>Infrared enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IR disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IR enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PFIFO</name>
<description>UART FIFO Parameters</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXFIFOSIZE</name>
<description>Receive FIFO. Buffer Depth</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Receive FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Receive FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Receive FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Receive FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Receive FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Receive FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Receive FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFE</name>
<description>Receive FIFO Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFIFOSIZE</name>
<description>Transmit FIFO. Buffer Depth</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Transmit FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Transmit FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Transmit FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Transmit FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Transmit FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Transmit FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Transmit FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFIFO</name>
<description>UART FIFO Control Register</description>
<addressOffset>0x11</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUFE</name>
<description>Receive FIFO Underflow Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXUF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXUF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOFE</name>
<description>Transmit FIFO Overflow Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOFE</name>
<description>Receive FIFO Overflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFLUSH</name>
<description>Receive FIFO/Buffer Flush</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the receive FIFO/buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFLUSH</name>
<description>Transmit FIFO/Buffer Flush</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SFIFO</name>
<description>UART FIFO Status Register</description>
<addressOffset>0x12</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUF</name>
<description>Receiver Buffer Underflow Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOF</name>
<description>Transmitter Buffer Overflow Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOF</name>
<description>Receiver Buffer Overflow Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEMPT</name>
<description>Receive Buffer/FIFO Empty</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXEMPT</name>
<description>Transmit Buffer/FIFO Empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TWFIFO</name>
<description>UART FIFO Transmit Watermark</description>
<addressOffset>0x13</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXWATER</name>
<description>Transmit Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCFIFO</name>
<description>UART FIFO Transmit Count</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCOUNT</name>
<description>Transmit Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RWFIFO</name>
<description>UART FIFO Receive Watermark</description>
<addressOffset>0x15</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXWATER</name>
<description>Receive Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCFIFO</name>
<description>UART FIFO Receive Count</description>
<addressOffset>0x16</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXCOUNT</name>
<description>Receive Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>C7816</name>
<description>UART 7816 Control Register</description>
<addressOffset>0x18</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ISO_7816E</name>
<description>ISO-7816 Functionality Enabled</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ISO-7816 functionality is turned off/not enabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ISO-7816 functionality is turned on/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TTYPE</name>
<description>Transfer Type</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>T = 0 per the ISO-7816 specification.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>T = 1 per the ISO-7816 specification.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INIT</name>
<description>Detect Initial Character</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operating mode. Receiver does not seek to identify initial character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver searches for initial character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ANACK</name>
<description>Generate NACK on Error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No NACK is automatically generated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONACK</name>
<description>Generate NACK on Overflow</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The received data does not generate a NACK when the receipt of the data results in an overflow event.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If the receiver buffer overflows, a NACK is automatically sent on a received character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IE7816</name>
<description>UART 7816 Interrupt Enable Register</description>
<addressOffset>0x19</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXTE</name>
<description>Receive Threshold Exceeded Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[RXT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[RXT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXTE</name>
<description>Transmit Threshold Exceeded Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[TXT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[TXT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTVE</name>
<description>Guard Timer Violated Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[GTV] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[GTV] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADTE</name>
<description>ATR Duration Timer Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[ADT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[ADT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITDE</name>
<description>Initial Character Detected Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[INITD] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[INITD] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BWTE</name>
<description>Block Wait Timer Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[BWT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[BWT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CWTE</name>
<description>Character Wait Timer Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[CWT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[CWT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WTE</name>
<description>Wait Timer Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The assertion of IS7816[WT] does not result in the generation of an interrupt.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The assertion of IS7816[WT] results in the generation of an interrupt.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IS7816</name>
<description>UART 7816 Interrupt Status Register</description>
<addressOffset>0x1A</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXT</name>
<description>Receive Threshold Exceeded Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXT</name>
<description>Transmit Threshold Exceeded Interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GTV</name>
<description>Guard Timer Violated Interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A guard time (GT, CGT, or BGT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A guard time (GT, CGT, or BGT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADT</name>
<description>ATR Duration Time Interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ATR Duration time (ADT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ATR Duration time (ADT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INITD</name>
<description>Initial Character Detected Interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A valid initial character has not been received.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A valid initial character has been received.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BWT</name>
<description>Block Wait Timer Interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Block wait time (BWT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Block wait time (BWT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CWT</name>
<description>Character Wait Timer Interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Character wait time (CWT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Character wait time (CWT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WT</name>
<description>Wait Timer Interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Wait time (WT) has not been violated.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wait time (WT) has been violated.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WP7816</name>
<description>UART 7816 Wait Parameter Register</description>
<addressOffset>0x1B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WTX</name>
<description>Wait Time Multiplier (C7816[TTYPE] = 1)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WN7816</name>
<description>UART 7816 Wait N Register</description>
<addressOffset>0x1C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GTN</name>
<description>Guard Band N</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WF7816</name>
<description>UART 7816 Wait FD Register</description>
<addressOffset>0x1D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>GTFD</name>
<description>FD Multiplier</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ET7816</name>
<description>UART 7816 Error Threshold Register</description>
<addressOffset>0x1E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXTHRESHOLD</name>
<description>Receive NACK Threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXTHRESHOLD</name>
<description>Transmit NACK Threshold</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXT asserts on the first NACK that is received.</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXT asserts on the second NACK that is received.</description>
<value>#0001</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TL7816</name>
<description>UART 7816 Transmit Length Register</description>
<addressOffset>0x1F</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TLEN</name>
<description>Transmit Length</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>AP7816A_T0</name>
<description>UART 7816 ATR Duration Timer Register A</description>
<addressOffset>0x3A</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ADTI_H</name>
<description>ATR Duration Time Integer High (C7816[TTYPE] = 0)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>AP7816B_T0</name>
<description>UART 7816 ATR Duration Timer Register B</description>
<addressOffset>0x3B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ADTI_L</name>
<description>ATR Duration Time Integer Low (C7816[TTYPE] = 0)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WP7816A_T0</name>
<description>UART 7816 Wait Parameter Register A</description>
<alternateGroup>UART0</alternateGroup>
<addressOffset>0x3C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WI_H</name>
<description>Wait Time Integer High (C7816[TTYPE] = 0)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WP7816A_T1</name>
<description>UART 7816 Wait Parameter Register A</description>
<alternateGroup>UART0</alternateGroup>
<addressOffset>0x3C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BWI_H</name>
<description>Block Wait Time Integer High (C7816[TTYPE] = 1)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WP7816B_T0</name>
<description>UART 7816 Wait Parameter Register B</description>
<alternateGroup>UART0</alternateGroup>
<addressOffset>0x3D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x14</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WI_L</name>
<description>Wait Time Integer Low (C7816[TTYPE] = 0)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WP7816B_T1</name>
<description>UART 7816 Wait Parameter Register B</description>
<alternateGroup>UART0</alternateGroup>
<addressOffset>0x3D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x14</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BWI_L</name>
<description>Block Wait Time Integer Low (C7816[TTYPE] = 1)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WGP7816_T1</name>
<description>UART 7816 Wait and Guard Parameter Register</description>
<addressOffset>0x3E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x6</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BGI</name>
<description>Block Guard Time Integer (C7816[TTYPE] = 1)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CWI1</name>
<description>Character Wait Time Integer 1 (C7816[TTYPE] = 1)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WP7816C_T1</name>
<description>UART 7816 Wait Parameter Register C</description>
<addressOffset>0x3F</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xB</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CWI2</name>
<description>Character Wait Time Integer 2 (C7816[TTYPE] = 1)</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART1</name>
<description>Serial Communication Interface</description>
<groupName>UART</groupName>
<prependToName>UART1_</prependToName>
<baseAddress>0x4006B000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x17</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART1_RX_TX</name>
<value>33</value>
</interrupt>
<interrupt>
<name>UART1_ERR</name>
<value>34</value>
</interrupt>
<registers>
<register>
<name>BDH</name>
<description>UART Baud Rate Registers: High</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXEDGIE</name>
<description>RxD Input Active Edge Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from RXEDGIF disabled using polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXEDGIF interrupt request enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIE</name>
<description>LIN Break Detect Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LBKDIF interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LBKDIF interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BDL</name>
<description>UART Baud Rate Registers: Low</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>UART Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PT</name>
<description>Parity Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Even parity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Odd parity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Parity function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILT</name>
<description>Idle Line Type Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle character bit count starts after start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle character bit count starts after stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Receiver Wakeup Method Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle line wakeup.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address mark wakeup.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M</name>
<description>9-bit or 8-bit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRC</name>
<description>Receiver Source Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Selects internal loop back mode. The receiver input is internally connected to transmitter output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UARTSWAI</name>
<description>UART Stops in Wait Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART clock continues to run in Wait mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART clock freezes while CPU is in Wait mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOPS</name>
<description>Loop Mode Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>UART Control Register 2</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBK</name>
<description>Send Break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal transmitter operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Queue break characters to be sent.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver Wakeup Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILIE</name>
<description>Idle Line Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IDLE interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IDLE interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIE</name>
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RDRF interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RDRF interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission Complete Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TC interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TC interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TDRE interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TDRE interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S1</name>
<description>UART Status Register 1</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PF</name>
<description>Parity Error Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No framing error detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Framing error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NF</name>
<description>Noise Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OR</name>
<description>Receiver Overrun Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLE</name>
<description>Idle Line Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC</name>
<description>Transmit Complete Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter active (sending data, a preamble, or a break).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter idle (transmission activity complete).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S2</name>
<description>UART Status Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAF</name>
<description>Receiver Active Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART receiver idle/inactive waiting for a start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver active, RxD input not idle.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDE</name>
<description>LIN Break Detection Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character detection is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRK13</name>
<description>Break Transmit Character Length</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is 10, 11, or 12 bits long.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is 13 or 14 bits long.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWUID</name>
<description>Receive Wakeup Idle Detect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>S1[IDLE] is not set upon detection of an idle character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>S1[IDLE] is set upon detection of an idle character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXINV</name>
<description>Receive Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSBF</name>
<description>Most Significant Bit First</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIF</name>
<description>RxD Pin Active Edge Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No active edge on the receive pin has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An active edge on the receive pin has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIF</name>
<description>LIN Break Detect Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No LIN break character detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LIN break character detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>UART Control Register 3</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PEIE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FE interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FE interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEIE</name>
<description>Noise Error Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>NF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OR interrupts are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>OR interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXINV</name>
<description>Transmit Data Inversion.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIR</name>
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXD pin is an input in single wire mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXD pin is an output in single wire mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T8</name>
<description>Transmit Bit 8</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8</name>
<description>Received Bit 8</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>UART Data Register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RT</name>
<description>Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA1</name>
<description>UART Match Address Registers 1</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA2</name>
<description>UART Match Address Registers 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>UART Control Register 4</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BRFA</name>
<description>Baud Rate Fine Adjust</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M10</name>
<description>10-bit Mode select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The parity bit is the ninth bit in the serial transmission.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The parity bit is the tenth bit in the serial transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN2</name>
<description>Match Address Mode Enable 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN1</name>
<description>Match Address Mode Enable 1</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C5</name>
<description>UART Control Register 5</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RDMAS</name>
<description>Receiver Full DMA Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAS</name>
<description>Transmitter DMA Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ED</name>
<description>UART Extended Data Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PARITYE</name>
<description>The current received dataword contained in D and C3[R8] was received with a parity error.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dataword was received with a parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOISY</name>
<description>The current received dataword contained in D and C3[R8] was received with noise.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The data was received with noise.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODEM</name>
<description>UART Modem Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCTSE</name>
<description>Transmitter clear-to-send enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS has no effect on the transmitter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSE</name>
<description>Transmitter request-to-send enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The transmitter has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSPOL</name>
<description>Transmitter request-to-send polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter RTS is active low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter RTS is active high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXRTSE</name>
<description>Receiver request-to-send enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The receiver has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IR</name>
<description>UART Infrared Register</description>
<addressOffset>0xE</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TNP</name>
<description>Transmitter narrow pulse</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>3/16.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>1/16.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>1/32.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>1/4.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IREN</name>
<description>Infrared enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IR disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IR enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PFIFO</name>
<description>UART FIFO Parameters</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXFIFOSIZE</name>
<description>Receive FIFO. Buffer Depth</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Receive FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Receive FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Receive FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Receive FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Receive FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Receive FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Receive FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFE</name>
<description>Receive FIFO Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFIFOSIZE</name>
<description>Transmit FIFO. Buffer Depth</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Transmit FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Transmit FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Transmit FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Transmit FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Transmit FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Transmit FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Transmit FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFIFO</name>
<description>UART FIFO Control Register</description>
<addressOffset>0x11</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUFE</name>
<description>Receive FIFO Underflow Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXUF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXUF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOFE</name>
<description>Transmit FIFO Overflow Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOFE</name>
<description>Receive FIFO Overflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFLUSH</name>
<description>Receive FIFO/Buffer Flush</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the receive FIFO/buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFLUSH</name>
<description>Transmit FIFO/Buffer Flush</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SFIFO</name>
<description>UART FIFO Status Register</description>
<addressOffset>0x12</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUF</name>
<description>Receiver Buffer Underflow Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOF</name>
<description>Transmitter Buffer Overflow Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOF</name>
<description>Receiver Buffer Overflow Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEMPT</name>
<description>Receive Buffer/FIFO Empty</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXEMPT</name>
<description>Transmit Buffer/FIFO Empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TWFIFO</name>
<description>UART FIFO Transmit Watermark</description>
<addressOffset>0x13</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXWATER</name>
<description>Transmit Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCFIFO</name>
<description>UART FIFO Transmit Count</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCOUNT</name>
<description>Transmit Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RWFIFO</name>
<description>UART FIFO Receive Watermark</description>
<addressOffset>0x15</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXWATER</name>
<description>Receive Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCFIFO</name>
<description>UART FIFO Receive Count</description>
<addressOffset>0x16</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXCOUNT</name>
<description>Receive Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART2</name>
<description>Serial Communication Interface</description>
<groupName>UART</groupName>
<prependToName>UART2_</prependToName>
<baseAddress>0x4006C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x17</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART2_RX_TX</name>
<value>35</value>
</interrupt>
<interrupt>
<name>UART2_ERR</name>
<value>36</value>
</interrupt>
<registers>
<register>
<name>BDH</name>
<description>UART Baud Rate Registers: High</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXEDGIE</name>
<description>RxD Input Active Edge Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupts from RXEDGIF disabled using polling.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXEDGIF interrupt request enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIE</name>
<description>LIN Break Detect Interrupt Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LBKDIF interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LBKDIF interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BDL</name>
<description>UART Baud Rate Registers: Low</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBR</name>
<description>UART Baud Rate Bits</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C1</name>
<description>UART Control Register 1</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PT</name>
<description>Parity Type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Even parity.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Odd parity.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Parity Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Parity function disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity function enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILT</name>
<description>Idle Line Type Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle character bit count starts after start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Idle character bit count starts after stop bit.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Receiver Wakeup Method Select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle line wakeup.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address mark wakeup.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>M</name>
<description>9-bit or 8-bit Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRC</name>
<description>Receiver Source Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Selects internal loop back mode. The receiver input is internally connected to transmitter output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Single wire UART mode where the receiver input is connected to the transmit pin input signal.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UARTSWAI</name>
<description>UART Stops in Wait Mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART clock continues to run in Wait mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART clock freezes while CPU is in Wait mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOOPS</name>
<description>Loop Mode Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C2</name>
<description>UART Control Register 2</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SBK</name>
<description>Send Break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal transmitter operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Queue break characters to be sent.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver Wakeup Control</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Normal operation.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter off.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter on.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ILIE</name>
<description>Idle Line Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IDLE interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IDLE interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIE</name>
<description>Receiver Full Interrupt or DMA Transfer Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RDRF interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RDRF interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission Complete Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TC interrupt requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TC interrupt requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Transmitter Interrupt or DMA Transfer Enable.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TDRE interrupt and DMA transfer requests disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TDRE interrupt or DMA transfer requests enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S1</name>
<description>UART Status Register 1</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PF</name>
<description>Parity Error Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with a parity error since the last time this flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FE</name>
<description>Framing Error Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No framing error detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Framing error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NF</name>
<description>Noise Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one dataword was received with noise detected since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OR</name>
<description>Receiver Overrun Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDLE</name>
<description>Idle Line Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver input is either active now or has never become active since the IDLE flag was last cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver input has become idle or the flag has not been cleared since it last asserted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDRF</name>
<description>Receive Data Register Full Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The number of datawords in the receive buffer is less than the number indicated by RXWATER.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TC</name>
<description>Transmit Complete Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter active (sending data, a preamble, or a break).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter idle (transmission activity complete).</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDRE</name>
<description>Transmit Data Register Empty Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>S2</name>
<description>UART Status Register 2</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RAF</name>
<description>Receiver Active Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART receiver idle/inactive waiting for a start bit.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART receiver active, RxD input not idle.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDE</name>
<description>LIN Break Detection Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character detection is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRK13</name>
<description>Break Transmit Character Length</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Break character is 10, 11, or 12 bits long.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Break character is 13 or 14 bits long.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RWUID</name>
<description>Receive Wakeup Idle Detect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>S1[IDLE] is not set upon detection of an idle character.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>S1[IDLE] is set upon detection of an idle character.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXINV</name>
<description>Receive Data Inversion</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSBF</name>
<description>Most Significant Bit First</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEDGIF</name>
<description>RxD Pin Active Edge Interrupt Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No active edge on the receive pin has occurred.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>An active edge on the receive pin has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBKDIF</name>
<description>LIN Break Detect Interrupt Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No LIN break character detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LIN break character detected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C3</name>
<description>UART Control Register 3</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PEIE</name>
<description>Parity Error Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEIE</name>
<description>Framing Error Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FE interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FE interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEIE</name>
<description>Noise Error Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NF interrupt requests are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>NF interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIE</name>
<description>Overrun Error Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>OR interrupts are disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>OR interrupt requests are enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXINV</name>
<description>Transmit Data Inversion.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data is not inverted.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit data is inverted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXDIR</name>
<description>Transmitter Pin Data Direction in Single-Wire mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXD pin is an input in single wire mode.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXD pin is an output in single wire mode.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T8</name>
<description>Transmit Bit 8</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>R8</name>
<description>Received Bit 8</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>D</name>
<description>UART Data Register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RT</name>
<description>Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA1</name>
<description>UART Match Address Registers 1</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MA2</name>
<description>UART Match Address Registers 2</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MA</name>
<description>Match Address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C4</name>
<description>UART Control Register 4</description>
<addressOffset>0xA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BRFA</name>
<description>Baud Rate Fine Adjust</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>M10</name>
<description>10-bit Mode select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The parity bit is the ninth bit in the serial transmission.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The parity bit is the tenth bit in the serial transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN2</name>
<description>Match Address Mode Enable 2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN1 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MAEN1</name>
<description>Match Address Mode Enable 1</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All data received is transferred to the data buffer if MAEN2 is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>C5</name>
<description>UART Control Register 5</description>
<addressOffset>0xB</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RDMAS</name>
<description>Receiver Full DMA Select</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAS</name>
<description>Transmitter DMA Select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ED</name>
<description>UART Extended Data Register</description>
<addressOffset>0xC</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PARITYE</name>
<description>The current received dataword contained in D and C3[R8] was received with a parity error.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without a parity error.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The dataword was received with a parity error.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOISY</name>
<description>The current received dataword contained in D and C3[R8] was received with noise.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The dataword was received without noise.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The data was received with noise.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODEM</name>
<description>UART Modem Register</description>
<addressOffset>0xD</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCTSE</name>
<description>Transmitter clear-to-send enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS has no effect on the transmitter.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSE</name>
<description>Transmitter request-to-send enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The transmitter has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXRTSPOL</name>
<description>Transmitter request-to-send polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitter RTS is active low.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitter RTS is active high.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXRTSE</name>
<description>Receiver request-to-send enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The receiver has no effect on RTS.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IR</name>
<description>UART Infrared Register</description>
<addressOffset>0xE</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TNP</name>
<description>Transmitter narrow pulse</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>3/16.</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>1/16.</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>1/32.</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>1/4.</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IREN</name>
<description>Infrared enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IR disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IR enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PFIFO</name>
<description>UART FIFO Parameters</description>
<addressOffset>0x10</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXFIFOSIZE</name>
<description>Receive FIFO. Buffer Depth</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Receive FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Receive FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Receive FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Receive FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Receive FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Receive FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Receive FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFE</name>
<description>Receive FIFO Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFIFOSIZE</name>
<description>Transmit FIFO. Buffer Depth</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Transmit FIFO/Buffer depth = 1 dataword.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>Transmit FIFO/Buffer depth = 4 datawords.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Transmit FIFO/Buffer depth = 8 datawords.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Transmit FIFO/Buffer depth = 16 datawords.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Transmit FIFO/Buffer depth = 32 datawords.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>Transmit FIFO/Buffer depth = 64 datawords.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Transmit FIFO/Buffer depth = 128 datawords.</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFIFO</name>
<description>UART FIFO Control Register</description>
<addressOffset>0x11</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUFE</name>
<description>Receive FIFO Underflow Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXUF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXUF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOFE</name>
<description>Transmit FIFO Overflow Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOFE</name>
<description>Receive FIFO Overflow Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RXOF flag does not generate an interrupt to the host.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RXOF flag generates an interrupt to the host.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFLUSH</name>
<description>Receive FIFO/Buffer Flush</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the receive FIFO/buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFLUSH</name>
<description>Transmit FIFO/Buffer Flush</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No flush operation occurs.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SFIFO</name>
<description>UART FIFO Status Register</description>
<addressOffset>0x12</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0xC0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXUF</name>
<description>Receiver Buffer Underflow Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOF</name>
<description>Transmitter Buffer Overflow Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXOF</name>
<description>Receiver Buffer Overflow Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>At least one receive buffer overflow has occurred since the last time the flag was cleared.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXEMPT</name>
<description>Receive Buffer/FIFO Empty</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXEMPT</name>
<description>Transmit Buffer/FIFO Empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit buffer is not empty.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit buffer is empty.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TWFIFO</name>
<description>UART FIFO Transmit Watermark</description>
<addressOffset>0x13</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXWATER</name>
<description>Transmit Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCFIFO</name>
<description>UART FIFO Transmit Count</description>
<addressOffset>0x14</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TXCOUNT</name>
<description>Transmit Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RWFIFO</name>
<description>UART FIFO Receive Watermark</description>
<addressOffset>0x15</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXWATER</name>
<description>Receive Watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RCFIFO</name>
<description>UART FIFO Receive Count</description>
<addressOffset>0x16</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RXCOUNT</name>
<description>Receive Counter</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CMP0</name>
<description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
<groupName>CMP</groupName>
<prependToName>CMP0_</prependToName>
<baseAddress>0x40073000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x6</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CMP0</name>
<value>40</value>
</interrupt>
<registers>
<register>
<name>CR0</name>
<description>CMP Control Register 0</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>HYSTCTR</name>
<description>Comparator hard block hysteresis control</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Level 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Level 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Level 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Level 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTER_CNT</name>
<description>Filter Sample Count</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>One sample must agree. The comparator output is simply sampled.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>2 consecutive samples must agree.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>3 consecutive samples must agree.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>4 consecutive samples must agree.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>5 consecutive samples must agree.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>6 consecutive samples must agree.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>7 consecutive samples must agree.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<description>CMP Control Register 1</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EN</name>
<description>Comparator Module Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Analog Comparator is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Analog Comparator is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPE</name>
<description>Comparator Output Pin Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COS</name>
<description>Comparator Output Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Set the filtered comparator output (CMPO) to equal COUT.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Set the unfiltered comparator output (CMPO) to equal COUTA.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Comparator INVERT</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Does not invert the comparator output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverts the comparator output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMODE</name>
<description>Power Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGM</name>
<description>Trigger Mode Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WE</name>
<description>Windowing Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Windowing mode is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Windowing mode is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SE</name>
<description>Sample Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Sampling mode is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Sampling mode is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FPR</name>
<description>CMP Filter Period Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FILT_PER</name>
<description>Filter Sample Period</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<description>CMP Status and Control Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>COUT</name>
<description>Analog Comparator Output</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CFF</name>
<description>Analog Comparator Flag Falling</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Falling-edge on COUT has not been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Falling-edge on COUT has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFR</name>
<description>Analog Comparator Flag Rising</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Rising-edge on COUT has not been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Rising-edge on COUT has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IEF</name>
<description>Comparator Interrupt Enable Falling</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IER</name>
<description>Comparator Interrupt Enable Rising</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable Control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DACCR</name>
<description>DAC Control Register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VOSEL</name>
<description>DAC Output Voltage Select</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VRSEL</name>
<description>Supply Voltage Reference Source Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Vin1 is selected as resistor ladder network supply reference.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Vin2 is selected as resistor ladder network supply reference.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACEN</name>
<description>DAC Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DAC is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DAC is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MUXCR</name>
<description>MUX Control Register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MSEL</name>
<description>Minus Input Mux Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>IN0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>IN1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>IN2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>IN3</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>IN4</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>IN5</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>IN6</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>IN7</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSEL</name>
<description>Plus Input Mux Control</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>IN0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>IN1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>IN2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>IN3</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>IN4</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>IN5</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>IN6</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>IN7</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CMP1</name>
<description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
<groupName>CMP</groupName>
<prependToName>CMP1_</prependToName>
<baseAddress>0x40073008</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x6</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CMP1</name>
<value>41</value>
</interrupt>
<registers>
<register>
<name>CR0</name>
<description>CMP Control Register 0</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>HYSTCTR</name>
<description>Comparator hard block hysteresis control</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Level 0</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Level 1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Level 2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Level 3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTER_CNT</name>
<description>Filter Sample Count</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>One sample must agree. The comparator output is simply sampled.</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>2 consecutive samples must agree.</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>3 consecutive samples must agree.</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>4 consecutive samples must agree.</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>5 consecutive samples must agree.</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>6 consecutive samples must agree.</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>7 consecutive samples must agree.</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<description>CMP Control Register 1</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EN</name>
<description>Comparator Module Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Analog Comparator is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Analog Comparator is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPE</name>
<description>Comparator Output Pin Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COS</name>
<description>Comparator Output Select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Set the filtered comparator output (CMPO) to equal COUT.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Set the unfiltered comparator output (CMPO) to equal COUTA.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Comparator INVERT</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Does not invert the comparator output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverts the comparator output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMODE</name>
<description>Power Mode Select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGM</name>
<description>Trigger Mode Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Trigger mode is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Trigger mode is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WE</name>
<description>Windowing Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Windowing mode is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Windowing mode is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SE</name>
<description>Sample Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Sampling mode is not selected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Sampling mode is selected.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FPR</name>
<description>CMP Filter Period Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FILT_PER</name>
<description>Filter Sample Period</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<description>CMP Status and Control Register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>COUT</name>
<description>Analog Comparator Output</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CFF</name>
<description>Analog Comparator Flag Falling</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Falling-edge on COUT has not been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Falling-edge on COUT has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFR</name>
<description>Analog Comparator Flag Rising</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Rising-edge on COUT has not been detected.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Rising-edge on COUT has occurred.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IEF</name>
<description>Comparator Interrupt Enable Falling</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IER</name>
<description>Comparator Interrupt Enable Rising</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable Control</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DMA is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DMA is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DACCR</name>
<description>DAC Control Register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VOSEL</name>
<description>DAC Output Voltage Select</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VRSEL</name>
<description>Supply Voltage Reference Source Select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Vin1 is selected as resistor ladder network supply reference.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Vin2 is selected as resistor ladder network supply reference.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACEN</name>
<description>DAC Enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DAC is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DAC is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MUXCR</name>
<description>MUX Control Register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MSEL</name>
<description>Minus Input Mux Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>IN0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>IN1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>IN2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>IN3</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>IN4</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>IN5</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>IN6</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>IN7</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSEL</name>
<description>Plus Input Mux Control</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>IN0</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>IN1</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>IN2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>IN3</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>IN4</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>101</name>
<description>IN5</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>IN6</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>111</name>
<description>IN7</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>VREF</name>
<description>Voltage Reference</description>
<prependToName>VREF_</prependToName>
<baseAddress>0x40074000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x2</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>TRM</name>
<description>VREF Trim Register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x40</resetMask>
<fields>
<field>
<name>TRIM</name>
<description>Trim bits</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000000</name>
<description>Min</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>111111</name>
<description>Max</description>
<value>#111111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHOPEN</name>
<description>Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Chop oscillator is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Chop oscillator is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SC</name>
<description>VREF Status and Control Register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODE_LV</name>
<description>Buffer Mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Bandgap on only, for stabilization and startup</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>High power buffer mode enabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Low-power buffer mode enabled</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFST</name>
<description>Internal Voltage Reference stable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The module is disabled or not stable.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The module is stable.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ICOMPEN</name>
<description>Second order curvature compensation enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REGEN</name>
<description>Regulator enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal 1.75 V regulator is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal 1.75 V regulator is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFEN</name>
<description>Internal Voltage Reference enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The module is disabled.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The module is enabled.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LLWU</name>
<description>Low leakage wakeup unit</description>
<prependToName>LLWU_</prependToName>
<baseAddress>0x4007C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LLWU</name>
<value>21</value>
</interrupt>
<registers>
<register>
<name>PE1</name>
<description>LLWU Pin Enable 1 register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE0</name>
<description>Wakeup Pin Enable For LLWU_P0</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE1</name>
<description>Wakeup Pin Enable For LLWU_P1</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE2</name>
<description>Wakeup Pin Enable For LLWU_P2</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE3</name>
<description>Wakeup Pin Enable For LLWU_P3</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PE2</name>
<description>LLWU Pin Enable 2 register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE4</name>
<description>Wakeup Pin Enable For LLWU_P4</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE5</name>
<description>Wakeup Pin Enable For LLWU_P5</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE6</name>
<description>Wakeup Pin Enable For LLWU_P6</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE7</name>
<description>Wakeup Pin Enable For LLWU_P7</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PE3</name>
<description>LLWU Pin Enable 3 register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE8</name>
<description>Wakeup Pin Enable For LLWU_P8</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE9</name>
<description>Wakeup Pin Enable For LLWU_P9</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE10</name>
<description>Wakeup Pin Enable For LLWU_P10</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE11</name>
<description>Wakeup Pin Enable For LLWU_P11</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PE4</name>
<description>LLWU Pin Enable 4 register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUPE12</name>
<description>Wakeup Pin Enable For LLWU_P12</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE13</name>
<description>Wakeup Pin Enable For LLWU_P13</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE14</name>
<description>Wakeup Pin Enable For LLWU_P14</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUPE15</name>
<description>Wakeup Pin Enable For LLWU_P15</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>External input pin disabled as wakeup input</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>External input pin enabled with rising edge detection</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>External input pin enabled with falling edge detection</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>External input pin enabled with any change detection</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ME</name>
<description>LLWU Module Enable register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUME0</name>
<description>Wakeup Module Enable For Module 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME1</name>
<description>Wakeup Module Enable for Module 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME2</name>
<description>Wakeup Module Enable For Module 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME3</name>
<description>Wakeup Module Enable For Module 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME4</name>
<description>Wakeup Module Enable For Module 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME5</name>
<description>Wakeup Module Enable For Module 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME6</name>
<description>Wakeup Module Enable For Module 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUME7</name>
<description>Wakeup Module Enable For Module 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal module flag not used as wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal module flag used as wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>F1</name>
<description>LLWU Flag 1 register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUF0</name>
<description>Wakeup Flag For LLWU_P0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P0 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P0 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF1</name>
<description>Wakeup Flag For LLWU_P1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P1 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P1 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF2</name>
<description>Wakeup Flag For LLWU_P2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P2 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P2 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF3</name>
<description>Wakeup Flag For LLWU_P3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P3 input was not a wake-up source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P3 input was a wake-up source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF4</name>
<description>Wakeup Flag For LLWU_P4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P4 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P4 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF5</name>
<description>Wakeup Flag For LLWU_P5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P5 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P5 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF6</name>
<description>Wakeup Flag For LLWU_P6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P6 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P6 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF7</name>
<description>Wakeup Flag For LLWU_P7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P7 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P7 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>F2</name>
<description>LLWU Flag 2 register</description>
<addressOffset>0x6</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WUF8</name>
<description>Wakeup Flag For LLWU_P8</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P8 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P8 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF9</name>
<description>Wakeup Flag For LLWU_P9</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P9 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P9 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF10</name>
<description>Wakeup Flag For LLWU_P10</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P10 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P10 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF11</name>
<description>Wakeup Flag For LLWU_P11</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P11 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P11 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF12</name>
<description>Wakeup Flag For LLWU_P12</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P12 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P12 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF13</name>
<description>Wakeup Flag For LLWU_P13</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P13 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P13 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF14</name>
<description>Wakeup Flag For LLWU_P14</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P14 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P14 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WUF15</name>
<description>Wakeup Flag For LLWU_P15</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LLWU_P15 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LLWU_P15 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>F3</name>
<description>LLWU Flag 3 register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MWUF0</name>
<description>Wakeup flag For module 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 0 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 0 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF1</name>
<description>Wakeup flag For module 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 1 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 1 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF2</name>
<description>Wakeup flag For module 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 2 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 2 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF3</name>
<description>Wakeup flag For module 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 3 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 3 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF4</name>
<description>Wakeup flag For module 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 4 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 4 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF5</name>
<description>Wakeup flag For module 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 5 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 5 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF6</name>
<description>Wakeup flag For module 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 6 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 6 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MWUF7</name>
<description>Wakeup flag For module 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Module 7 input was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Module 7 input was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILT1</name>
<description>LLWU Pin Filter 1 register</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FILTSEL</name>
<description>Filter Pin Select</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Select LLWU_P0 for filter</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Select LLWU_P15 for filter</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTE</name>
<description>Digital Filter On External Pin</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Filter disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Filter posedge detect enabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Filter negedge detect enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Filter any edge detect enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTF</name>
<description>Filter Detect Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Filter 1 was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Filter 1 was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FILT2</name>
<description>LLWU Pin Filter 2 register</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FILTSEL</name>
<description>Filter Pin Select</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0000</name>
<description>Select LLWU_P0 for filter</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>1111</name>
<description>Select LLWU_P15 for filter</description>
<value>#1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTE</name>
<description>Digital Filter On External Pin</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Filter disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Filter posedge detect enabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Filter negedge detect enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>Filter any edge detect enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTF</name>
<description>Filter Detect Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin Filter 2 was not a wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin Filter 2 was a wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PMC</name>
<description>Power Management Controller</description>
<prependToName>PMC_</prependToName>
<baseAddress>0x4007D000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x3</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LVD_LVW</name>
<value>20</value>
</interrupt>
<registers>
<register>
<name>LVDSC1</name>
<description>Low Voltage Detect Status And Control 1 register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LVDV</name>
<description>Low-Voltage Detect Voltage Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Low trip point selected (V LVD = V LVDL )</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>High trip point selected (V LVD = V LVDH )</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVDRE</name>
<description>Low-Voltage Detect Reset Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LVDF does not generate hardware resets</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Force an MCU reset when LVDF = 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVDIE</name>
<description>Low-Voltage Detect Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupt disabled (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request a hardware interrupt when LVDF = 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVDACK</name>
<description>Low-Voltage Detect Acknowledge</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>LVDF</name>
<description>Low-Voltage Detect Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low-voltage event not detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-voltage event detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LVDSC2</name>
<description>Low Voltage Detect Status And Control 2 register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LVWV</name>
<description>Low-Voltage Warning Voltage Select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Low trip point selected (VLVW = VLVW1)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Mid 1 trip point selected (VLVW = VLVW2)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Mid 2 trip point selected (VLVW = VLVW3)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>High trip point selected (VLVW = VLVW4)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVWIE</name>
<description>Low-Voltage Warning Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Hardware interrupt disabled (use polling)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request a hardware interrupt when LVWF = 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVWACK</name>
<description>Low-Voltage Warning Acknowledge</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>LVWF</name>
<description>Low-Voltage Warning Flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low-voltage warning event not detected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low-voltage warning event detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>REGSC</name>
<description>Regulator Status And Control register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BGBE</name>
<description>Bandgap Buffer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bandgap buffer not enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bandgap buffer enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REGONS</name>
<description>Regulator In Run Regulation Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Regulator is in stop regulation or in transition to/from it</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Regulator is in run regulation</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKISO</name>
<description>Acknowledge Isolation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Peripherals and I/O pads are in normal run state.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Certain peripherals and I/O pads are in an isolated and latched state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BGEN</name>
<description>Bandgap Enable In VLPx Operation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SMC</name>
<description>System Mode Controller</description>
<prependToName>SMC_</prependToName>
<baseAddress>0x4007E000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PMPROT</name>
<description>Power Mode Protection register</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AVLLS</name>
<description>Allow Very-Low-Leakage Stop Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Any VLLSx mode is not allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Any VLLSx mode is allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALLS</name>
<description>Allow Low-Leakage Stop Mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Any LLSx mode is not allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Any LLSx mode is allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AVLP</name>
<description>Allow Very-Low-Power Modes</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>VLPR, VLPW, and VLPS are not allowed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>VLPR, VLPW, and VLPS are allowed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AHSRUN</name>
<description>Allow High Speed Run mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>HSRUN is not allowed</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>HSRUN is allowed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PMCTRL</name>
<description>Power Mode Control register</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>STOPM</name>
<description>Stop Mode Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>Normal Stop (STOP)</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>Very-Low-Power Stop (VLPS)</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>Low-Leakage Stop (LLSx)</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>100</name>
<description>Very-Low-Leakage Stop (VLLSx)</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>110</name>
<description>Reseved</description>
<value>#110</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOPA</name>
<description>Stop Aborted</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The previous stop mode entry was successsful.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The previous stop mode entry was aborted.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RUNM</name>
<description>Run Mode Control</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>Normal Run mode (RUN)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>Very-Low-Power Run mode (VLPR)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>11</name>
<description>High Speed Run mode (HSRUN)</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STOPCTRL</name>
<description>Stop Control Register</description>
<addressOffset>0x2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x3</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>LLSM</name>
<description>LLS or VLLS Mode Control</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>000</name>
<description>VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>001</name>
<description>VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>010</name>
<description>VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>011</name>
<description>VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx</description>
<value>#011</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORPO</name>
<description>POR Power Option</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>POR detect circuit is enabled in VLLS0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>POR detect circuit is disabled in VLLS0</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSTOPO</name>
<description>Partial Stop Option</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>STOP - Normal Stop mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>PSTOP1 - Partial Stop with both system and bus clocks disabled</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>PSTOP2 - Partial Stop with system clock disabled and bus clock enabled</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PMSTAT</name>
<description>Power Mode Status register</description>
<addressOffset>0x3</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PMSTAT</name>
<description>When debug is enabled, the PMSTAT will not update to STOP or VLPS When a PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RCM</name>
<description>Reset Control Module</description>
<prependToName>RCM_</prependToName>
<baseAddress>0x4007F000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xA</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SRS0</name>
<description>System Reset Status Register 0</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0x82</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WAKEUP</name>
<description>Low Leakage Wakeup Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by LLWU module wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by LLWU module wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LVD</name>
<description>Low-Voltage Detect Reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by LVD trip or POR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by LVD trip or POR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOC</name>
<description>Loss-of-Clock Reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by a loss of external clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by a loss of external clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDOG</name>
<description>Watchdog</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by watchdog timeout</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by watchdog timeout</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PIN</name>
<description>External Reset Pin</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by external reset pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by external reset pin</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POR</name>
<description>Power-On Reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by POR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by POR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SRS1</name>
<description>System Reset Status Register 1</description>
<addressOffset>0x1</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>JTAG</name>
<description>JTAG Generated Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by JTAG</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by JTAG</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCKUP</name>
<description>Core Lockup</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by core LOCKUP event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by core LOCKUP event</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SW</name>
<description>Software</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by software setting of SYSRESETREQ bit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by software setting of SYSRESETREQ bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDM_AP</name>
<description>MDM-AP System Reset Request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by host debugger system setting of the System Reset Request bit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by host debugger system setting of the System Reset Request bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EZPT</name>
<description>EzPort Reset</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by EzPort receiving the RESET command while the device is in EzPort mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SACKERR</name>
<description>Stop Mode Acknowledge Error Reset</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by peripheral failure to acknowledge attempt to enter stop mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by peripheral failure to acknowledge attempt to enter stop mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RPFC</name>
<description>Reset Pin Filter Control register</description>
<addressOffset>0x4</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RSTFLTSRW</name>
<description>Reset Pin Filter Select in Run and Wait Modes</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00</name>
<description>All filtering disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>01</name>
<description>Bus clock filter enabled for normal operation</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>10</name>
<description>LPO clock filter enabled for normal operation</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTFLTSS</name>
<description>Reset Pin Filter Select in Stop Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>All filtering disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LPO clock filter enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RPFW</name>
<description>Reset Pin Filter Width register</description>
<addressOffset>0x5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RSTFLTSEL</name>
<description>Reset Pin Filter Bus Clock Select</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>00000</name>
<description>Bus clock filter count is 1</description>
<value>#00000</value>
</enumeratedValue>
<enumeratedValue>
<name>00001</name>
<description>Bus clock filter count is 2</description>
<value>#00001</value>
</enumeratedValue>
<enumeratedValue>
<name>00010</name>
<description>Bus clock filter count is 3</description>
<value>#00010</value>
</enumeratedValue>
<enumeratedValue>
<name>00011</name>
<description>Bus clock filter count is 4</description>
<value>#00011</value>
</enumeratedValue>
<enumeratedValue>
<name>00100</name>
<description>Bus clock filter count is 5</description>
<value>#00100</value>
</enumeratedValue>
<enumeratedValue>
<name>00101</name>
<description>Bus clock filter count is 6</description>
<value>#00101</value>
</enumeratedValue>
<enumeratedValue>
<name>00110</name>
<description>Bus clock filter count is 7</description>
<value>#00110</value>
</enumeratedValue>
<enumeratedValue>
<name>00111</name>
<description>Bus clock filter count is 8</description>
<value>#00111</value>
</enumeratedValue>
<enumeratedValue>
<name>01000</name>
<description>Bus clock filter count is 9</description>
<value>#01000</value>
</enumeratedValue>
<enumeratedValue>
<name>01001</name>
<description>Bus clock filter count is 10</description>
<value>#01001</value>
</enumeratedValue>
<enumeratedValue>
<name>01010</name>
<description>Bus clock filter count is 11</description>
<value>#01010</value>
</enumeratedValue>
<enumeratedValue>
<name>01011</name>
<description>Bus clock filter count is 12</description>
<value>#01011</value>
</enumeratedValue>
<enumeratedValue>
<name>01100</name>
<description>Bus clock filter count is 13</description>
<value>#01100</value>
</enumeratedValue>
<enumeratedValue>
<name>01101</name>
<description>Bus clock filter count is 14</description>
<value>#01101</value>
</enumeratedValue>
<enumeratedValue>
<name>01110</name>
<description>Bus clock filter count is 15</description>
<value>#01110</value>
</enumeratedValue>
<enumeratedValue>
<name>01111</name>
<description>Bus clock filter count is 16</description>
<value>#01111</value>
</enumeratedValue>
<enumeratedValue>
<name>10000</name>
<description>Bus clock filter count is 17</description>
<value>#10000</value>
</enumeratedValue>
<enumeratedValue>
<name>10001</name>
<description>Bus clock filter count is 18</description>
<value>#10001</value>
</enumeratedValue>
<enumeratedValue>
<name>10010</name>
<description>Bus clock filter count is 19</description>
<value>#10010</value>
</enumeratedValue>
<enumeratedValue>
<name>10011</name>
<description>Bus clock filter count is 20</description>
<value>#10011</value>
</enumeratedValue>
<enumeratedValue>
<name>10100</name>
<description>Bus clock filter count is 21</description>
<value>#10100</value>
</enumeratedValue>
<enumeratedValue>
<name>10101</name>
<description>Bus clock filter count is 22</description>
<value>#10101</value>
</enumeratedValue>
<enumeratedValue>
<name>10110</name>
<description>Bus clock filter count is 23</description>
<value>#10110</value>
</enumeratedValue>
<enumeratedValue>
<name>10111</name>
<description>Bus clock filter count is 24</description>
<value>#10111</value>
</enumeratedValue>
<enumeratedValue>
<name>11000</name>
<description>Bus clock filter count is 25</description>
<value>#11000</value>
</enumeratedValue>
<enumeratedValue>
<name>11001</name>
<description>Bus clock filter count is 26</description>
<value>#11001</value>
</enumeratedValue>
<enumeratedValue>
<name>11010</name>
<description>Bus clock filter count is 27</description>
<value>#11010</value>
</enumeratedValue>
<enumeratedValue>
<name>11011</name>
<description>Bus clock filter count is 28</description>
<value>#11011</value>
</enumeratedValue>
<enumeratedValue>
<name>11100</name>
<description>Bus clock filter count is 29</description>
<value>#11100</value>
</enumeratedValue>
<enumeratedValue>
<name>11101</name>
<description>Bus clock filter count is 30</description>
<value>#11101</value>
</enumeratedValue>
<enumeratedValue>
<name>11110</name>
<description>Bus clock filter count is 31</description>
<value>#11110</value>
</enumeratedValue>
<enumeratedValue>
<name>11111</name>
<description>Bus clock filter count is 32</description>
<value>#11111</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MR</name>
<description>Mode Register</description>
<addressOffset>0x7</addressOffset>
<size>8</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EZP_MS</name>
<description>EZP_MS_B pin state</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin deasserted (logic 1)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin asserted (logic 0)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SSRS0</name>
<description>Sticky System Reset Status Register 0</description>
<addressOffset>0x8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0x82</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SWAKEUP</name>
<description>Sticky Low Leakage Wakeup Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by LLWU module wakeup source</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by LLWU module wakeup source</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVD</name>
<description>Sticky Low-Voltage Detect Reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by LVD trip or POR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by LVD trip or POR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLOC</name>
<description>Sticky Loss-of-Clock Reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by a loss of external clock.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by a loss of external clock.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWDOG</name>
<description>Sticky Watchdog</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by watchdog timeout</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by watchdog timeout</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIN</name>
<description>Sticky External Reset Pin</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by external reset pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by external reset pin</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPOR</name>
<description>Sticky Power-On Reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by POR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by POR</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SSRS1</name>
<description>Sticky System Reset Status Register 1</description>
<addressOffset>0x9</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SJTAG</name>
<description>Sticky JTAG Generated Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by JTAG</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by JTAG</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLOCKUP</name>
<description>Sticky Core Lockup</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by core LOCKUP event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by core LOCKUP event</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSW</name>
<description>Sticky Software</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by software setting of SYSRESETREQ bit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by software setting of SYSRESETREQ bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMDM_AP</name>
<description>Sticky MDM-AP System Reset Request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by host debugger system setting of the System Reset Request bit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by host debugger system setting of the System Reset Request bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEZPT</name>
<description>Sticky EzPort Reset</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by EzPort receiving the RESET command while the device is in EzPort mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSACKERR</name>
<description>Sticky Stop Mode Acknowledge Error Reset</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reset not caused by peripheral failure to acknowledge attempt to enter stop mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset caused by peripheral failure to acknowledge attempt to enter stop mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PTA</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOA_</prependToName>
<baseAddress>0x400FF000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTA</name>
<value>59</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PTB</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOB_</prependToName>
<baseAddress>0x400FF040</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTB</name>
<value>60</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PTC</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOC_</prependToName>
<baseAddress>0x400FF080</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTC</name>
<value>61</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PTD</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOD_</prependToName>
<baseAddress>0x400FF0C0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTD</name>
<value>62</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PTE</name>
<description>General Purpose Input/Output</description>
<groupName>GPIO</groupName>
<prependToName>GPIOE_</prependToName>
<baseAddress>0x400FF100</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PORTE</name>
<value>63</value>
</interrupt>
<registers>
<register>
<name>PDOR</name>
<description>Port Data Output Register</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDO</name>
<description>Port Data Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PSOR</name>
<description>Port Set Output Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTSO</name>
<description>Port Set Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PCOR</name>
<description>Port Clear Output Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTCO</name>
<description>Port Clear Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PTOR</name>
<description>Port Toggle Output Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PTTO</name>
<description>Port Toggle Output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding bit in PDORn does not change.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDIR</name>
<description>Port Data Input Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDI</name>
<description>Port Data Input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin logic level is logic 1.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PDDR</name>
<description>Port Data Direction Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDD</name>
<description>Port Data Direction</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MCM</name>
<description>Core Platform Miscellaneous Control Module</description>
<prependToName>MCM_</prependToName>
<baseAddress>0xE0080000</baseAddress>
<addressBlock>
<offset>0x8</offset>
<size>0x3C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>MCM</name>
<value>17</value>
</interrupt>
<registers>
<register>
<name>PLASC</name>
<description>Crossbar Switch (AXBS) Slave Configuration</description>
<addressOffset>0x8</addressOffset>
<size>16</size>
<access>read-only</access>
<resetValue>0xF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ASC</name>
<description>Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch&apos;s slave input port.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A bus slave connection to AXBS input port n is absent</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A bus slave connection to AXBS input port n is present</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PLAMC</name>
<description>Crossbar Switch (AXBS) Master Configuration</description>
<addressOffset>0xA</addressOffset>
<size>16</size>
<access>read-only</access>
<resetValue>0x17</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>AMC</name>
<description>Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A bus master connection to AXBS input port n is absent</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A bus master connection to AXBS input port n is present</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PLACR</name>
<description>Crossbar Switch (AXBS) Control Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ARB</name>
<description>Arbitration select</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Fixed-priority arbitration for the crossbar masters</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Round-robin arbitration for the crossbar masters</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISCR</name>
<description>Interrupt Status and Control Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FIOC</name>
<description>FPU invalid operation interrupt status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FDZC</name>
<description>FPU divide-by-zero interrupt status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FOFC</name>
<description>FPU overflow interrupt status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FUFC</name>
<description>FPU underflow interrupt status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIXC</name>
<description>FPU inexact interrupt status</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIDC</name>
<description>FPU input denormal interrupt status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIOCE</name>
<description>FPU invalid operation interrupt enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FDZCE</name>
<description>FPU divide-by-zero interrupt enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FOFCE</name>
<description>FPU overflow interrupt enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FUFCE</name>
<description>FPU underflow interrupt enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIXCE</name>
<description>FPU inexact interrupt enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIDCE</name>
<description>FPU input denormal interrupt enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disable interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CPO</name>
<description>Compute Operation Control Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CPOREQ</name>
<description>Compute Operation request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Request is cleared.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Request Compute Operation.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOACK</name>
<description>Compute Operation acknowledge</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Compute operation entry has not completed or compute operation exit has completed.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Compute operation entry has completed or compute operation exit has not completed.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPOWOI</name>
<description>Compute Operation wakeup on interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When set, the CPOREQ is cleared on any interrupt or exception vector fetch.</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>