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<?xml version="1.0" encoding="utf-8"?>
<!-- Generator version: 1.2.0.117 -->
<!-- Database revision: rev#1034984 -->
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<vendor>Cypress Semiconductor</vendor>
<vendorID>Cypress</vendorID>
<name>psoc63</name>
<series>psoc63</series>
<version>1.0</version>
<description>PSoC 63 (Connectivity Line): Dual-core Cortex-M4/M0+ MCU series with programmable digital and analog peripherals, advanced graphics, CapSense, crypto and secure boot security, with integrated high-speed wired and wireless connectivity.</description>
<licenseText>Copyright 2016-2018 Cypress Semiconductor Corporation \n \n
Licensed under the Apache License, Version 2.0 (the "License"); \n
you may not use this file except in compliance with the License. \n
You may obtain a copy of the License at \n \n
http://www.apache.org/licenses/LICENSE-2.0 \n
Unless required by applicable law or agreed to in writing, software \n
distributed under the License is distributed on an "AS IS" BASIS, \n
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. \n
See the License for the specific language governing permissions and \n
limitations under the License.</licenseText>
<cpu>
<name>CM4</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>true</fpuPresent>
<vtorPresent>1</vtorPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>0</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>PERI</name>
<description>Peripheral interconnect</description>
<baseAddress>0x40010000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<dim>11</dim>
<dimIncrement>64</dimIncrement>
<name>GR[%s]</name>
<description>Peripheral group structure</description>
<addressOffset>0x00000000</addressOffset>
<register>
<name>CLOCK_CTL</name>
<description>Clock control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF00</resetMask>
<fields>
<field>
<name>INT8_DIV</name>
<description>Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256].
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SL_CTL</name>
<description>Slave control</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ENABLED_0</name>
<description>Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ENABLED_1</name>
<description>Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_2</name>
<description>Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_3</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_4</name>
<description>N/A</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_5</name>
<description>N/A</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_6</name>
<description>N/A</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_7</name>
<description>N/A</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_8</name>
<description>N/A</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_9</name>
<description>N/A</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_10</name>
<description>N/A</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_11</name>
<description>N/A</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_12</name>
<description>N/A</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_13</name>
<description>N/A</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_14</name>
<description>N/A</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED_15</name>
<description>N/A</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TIMEOUT_CTL</name>
<description>Timeout control</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TIMEOUT</name>
<description>This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)).
'0x0000'-'0xfffe': Number of peripheral group clock cycles.
'0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
<register>
<name>DIV_CMD</name>
<description>Divider command register</description>
<addressOffset>0x400</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xC000FFFF</resetMask>
<fields>
<field>
<name>DIV_SEL</name>
<description>(TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed.
If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated.</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TYPE_SEL</name>
<description>Specifies the divider type of the divider on which the command is performed:
0: 8.0 (integer) clock dividers.
1: 16.0 (integer) clock dividers.
2: 16.5 (fractional) clock dividers.
3: 24.5 (fractional) clock dividers.</description>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PA_DIV_SEL</name>
<description>(PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times.
If PA_DIV_SEL is '63' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference.</description>
<bitRange>[13:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PA_TYPE_SEL</name>
<description>Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:
0: 8.0 (integer) clock dividers.
1: 16.0 (integer) clock dividers.
2: 16.5 (fractional) clock dividers.
3: 24.5 (fractional) clock dividers.</description>
<bitRange>[15:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DISABLE</name>
<description>Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'.
The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled.
The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE</name>
<description>Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps:
0: Disable the divider using the DIV_CMD.DISABLE field.
1: Configure the divider's DIV_XXX_CTL register.
2: Enable the divider using the DIV_CMD_ENABLE field.
The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider.
The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider.
The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>64</dim>
<dimIncrement>4</dimIncrement>
<name>DIV_8_CTL[%s]</name>
<description>Divider control register (for 8.0 divider)</description>
<addressOffset>0x800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF01</resetMask>
<fields>
<field>
<name>EN</name>
<description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INT8_DIV</name>
<description>Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division.
For the generation of a divided clock, the integer division range is restricted to [2, 256].
For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions.
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>64</dim>
<dimIncrement>4</dimIncrement>
<name>DIV_16_CTL[%s]</name>
<description>Divider control register (for 16.0 divider)</description>
<addressOffset>0x900</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF01</resetMask>
<fields>
<field>
<name>EN</name>
<description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INT16_DIV</name>
<description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division.
For the generation of a divided clock, the integer division range is restricted to [2, 65,536].
For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions.
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
<bitRange>[23:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>64</dim>
<dimIncrement>4</dimIncrement>
<name>DIV_16_5_CTL[%s]</name>
<description>Divider control register (for 16.5 divider)</description>
<addressOffset>0xA00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFF9</resetMask>
<fields>
<field>
<name>EN</name>
<description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>FRAC5_DIV</name>
<description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods.
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
<bitRange>[7:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INT16_DIV</name>
<description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments.
For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32].
For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536].
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
<bitRange>[23:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>63</dim>
<dimIncrement>4</dimIncrement>
<name>DIV_24_5_CTL[%s]</name>
<description>Divider control register (for 24.5 divider)</description>
<addressOffset>0xB00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFF9</resetMask>
<fields>
<field>
<name>EN</name>
<description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>FRAC5_DIV</name>
<description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods.
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
<bitRange>[7:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INT24_DIV</name>
<description>Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments.
For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32].
For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216].
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>128</dim>
<dimIncrement>4</dimIncrement>
<name>CLOCK_CTL[%s]</name>
<description>Clock control register</description>
<addressOffset>0xC00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DIV_SEL</name>
<description>Specifies one of the dividers of the divider type specified by TYPE_SEL.
If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated.
When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TYPE_SEL</name>
<description>Specifies divider type:
0: 8.0 (integer) clock dividers.
1: 16.0 (integer) clock dividers.
2: 16.5 (fractional) clock dividers.
3: 24.5 (fractional) clock dividers.</description>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TR_CMD</name>
<description>Trigger command register</description>
<addressOffset>0x1000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC0FF0FFF</resetMask>
<fields>
<field>
<name>TR_SEL</name>
<description>Specifies the activated trigger when ACTIVATE is '1'. OUT_SEL specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (ACTIVATE is '1'), SW should not modify this register field. If the specified trigger is not present, the trigger activation has no effect.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>GROUP_SEL</name>
<description>Specifies the trigger group.</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>COUNT</name>
<description>Amount of 'clk_peri' cycles a specific trigger is activated. During activation (ACTIVATE is '1'), HW decrements this field to '0' using a cycle counter. During activation, SW should not modify this register field. A value of 255 is a special case: HW does NOT decrement this field to '0' and trigger activation is under direct control of ACTIVATE when ACTIVATE is '1' the trigger is activated and when ACTIVATE is '0' the trigger is deactivated.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT_SEL</name>
<description>Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only.
'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer.
'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACTIVATE</name>
<description>SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SEL and OUT_SEL for COUNT cycles. HW sets this field to '0' when the cycle counter is decremented to '0'. Note: a COUNT value of 255 is a special case and trigger activation is under direct control of the ACTIVATE field (the counter is not decremented).</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<cluster>
<dim>15</dim>
<dimIncrement>512</dimIncrement>
<name>TR_GR[%s]</name>
<description>Trigger group</description>
<addressOffset>0x00002000</addressOffset>
<register>
<dim>128</dim>
<dimIncrement>4</dimIncrement>
<name>TR_OUT_CTL[%s]</name>
<description>Trigger control register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>TR_SEL</name>
<description>Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TR_INV</name>
<description>Specifies if the output trigger is inverted.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TR_EDGE</name>
<description>Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger.
'0': level sensitive.
'1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
<cluster>
<dim>16</dim>
<dimIncrement>64</dimIncrement>
<name>PPU_PR[%s]</name>
<description>PPU structure with programmable address</description>
<addressOffset>0x00004000</addressOffset>
<register>
<name>ADDR0</name>
<description>PPU region address 0 (slave structure)</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>SUBREGION_DISABLE</name>
<description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
Bit 0: subregion 0 disable.
Bit 1: subregion 1 disable.
Bit 2: subregion 2 disable.
Bit 3: subregion 3 disable.
Bit 4: subregion 4 disable.
Bit 5: subregion 5 disable.
Bit 6: subregion 6 disable.
Bit 7: subregion 7 disable.
E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADDR24</name>
<description>This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ATT0</name>
<description>PPU region attributes 0 (slave structure)</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x124</resetValue>
<resetMask>0x80000124</resetMask>
<fields>
<field>
<name>UR</name>
<description>User read enable:
'0': Disabled (user, read acceses are NOT allowed).
'1': Enabled (user, read acceses are allowed).</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UW</name>
<description>User write enable:
'0': Disabled (user, write acceses are NOT allowed).
'1': Enabled (user, write acceses are allowed).</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UX</name>
<description>User execute enable:
'0': Disabled (user, execute acceses are NOT allowed).
'1': Enabled (user, execute acceses are allowed).</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PR</name>
<description>Privileged read enable:
'0': Disabled (privileged, read acceses are NOT allowed).
'1': Enabled (privileged, read acceses are allowed).</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PW</name>
<description>Privileged write enable:
'0': Disabled (privileged, write acceses are NOT allowed).
'1': Enabled (privileged, write acceses are allowed).</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PX</name>
<description>Privileged execute enable:
'0': Disabled (privileged, execute acceses are NOT allowed).
'1': Enabled (privileged, execute acceses are allowed).</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NS</name>
<description>Non-secure:
'0': Secure (secure accesses allowed, non-secure access NOT allowed).
'1': Non-secure (both secure and non-secure accesses allowed).</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>This field specifies protection context identifier based access control for protection context '0'.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>This field specifies protection context identifier based access control.
Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
<bitRange>[23:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REGION_SIZE</name>
<description>This field specifies the region size:
'0'-'6': Undefined.
'7': 256 B region
'8': 512 B region
'9': 1 KB region
'10': 2 KB region
'11': 4 KB region
'12': 8 KB region
'13': 16 KB region
'14': 32 KB region
'15': 64 KB region
'16': 128 KB region
'17': 256 KB region
'18': 512 KB region
'19': 1 MB region
'20': 2 MB region
'21': 4 MB region
'22': 8 MB region
'23': 16 MB region
'24': 32 MB region
'25': 64 MB region
'26': 128 MB region
'27': 256 MB region
'28': 512 MB region
'39': 1 GB region
'30': 2 GB region
'31': 4 GB region</description>
<bitRange>[28:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MATCH</name>
<description>This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:
'0': PC field participates in 'access evalution'.
'1': PC field participates in 'matching'.
Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Region enable:
'0': Disabled. A disabled region will never result in a match on the bus transfer address.
'1': Enabled.
Note: a disabled address region performs logic gating to reduce dynamic power consumption.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADDR1</name>
<description>PPU region address 1 (master structure)</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SUBREGION_DISABLE</name>
<description>See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only.</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ADDR24</name>
<description>See corresponding field for PPU structure with programmable address.
'ADDR_DEF1': base address of structure.
Note: this field is read-only.</description>
<bitRange>[31:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ATT1</name>
<description>PPU region attributes 1 (master structure)</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7000109</resetValue>
<resetMask>0x9F00012D</resetMask>
<fields>
<field>
<name>UR</name>
<description>See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>UW</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UX</name>
<description>See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PR</name>
<description>See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PW</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PX</name>
<description>See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NS</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[23:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REGION_SIZE</name>
<description>See corresponding field for PPU structure with programmable address.
'7': 256 B region</description>
<bitRange>[28:24]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MATCH</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
<cluster>
<dim>11</dim>
<dimIncrement>64</dimIncrement>
<name>PPU_GR[%s]</name>
<description>PPU structure with fixed/constant address for a peripheral group</description>
<addressOffset>0x00005000</addressOffset>
<register>
<name>ADDR0</name>
<description>PPU region address 0 (slave structure)</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SUBREGION_DISABLE</name>
<description>See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific.</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ADDR24</name>
<description>See corresponding field for PPU structure with programmable address.
'ADDR_DEF1': address of protected region.
Note: this field is read-only. Its value is chip specific.</description>
<bitRange>[31:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ATT0</name>
<description>PPU region attributes 0 (slave structure)</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x124</resetValue>
<resetMask>0x9F000124</resetMask>
<fields>
<field>
<name>UR</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UW</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UX</name>
<description>See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PR</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PW</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PX</name>
<description>See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NS</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[23:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REGION_SIZE</name>
<description>See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific.</description>
<bitRange>[28:24]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MATCH</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADDR1</name>
<description>PPU region address 1 (master structure)</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SUBREGION_DISABLE</name>
<description>See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only.</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ADDR24</name>
<description>See corresponding field for PPU structure with programmable address.
'ADDR_DEF1': base address of structure.
Note: this field is read-only.</description>
<bitRange>[31:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ATT1</name>
<description>PPU region attributes 1 (master structure)</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7000109</resetValue>
<resetMask>0x9F00012D</resetMask>
<fields>
<field>
<name>UR</name>
<description>See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>UW</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UX</name>
<description>See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PR</name>
<description>See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PW</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PX</name>
<description>See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NS</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[23:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REGION_SIZE</name>
<description>See corresponding field for PPU structure with programmable address.
'7': 256 B region</description>
<bitRange>[28:24]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MATCH</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>See corresponding field for PPU structure with programmable address.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>CPUSS</name>
<description>CPU subsystem (CPUSS)</description>
<baseAddress>0x40210000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ioss_interrupts_gpio_0</name>
<description>GPIO Port Interrupt #0</description>
<value>0</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_1</name>
<description>GPIO Port Interrupt #1</description>
<value>1</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_2</name>
<description>GPIO Port Interrupt #2</description>
<value>2</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_3</name>
<description>GPIO Port Interrupt #3</description>
<value>3</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_4</name>
<description>GPIO Port Interrupt #4</description>
<value>4</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_5</name>
<description>GPIO Port Interrupt #5</description>
<value>5</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_6</name>
<description>GPIO Port Interrupt #6</description>
<value>6</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_7</name>
<description>GPIO Port Interrupt #7</description>
<value>7</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_8</name>
<description>GPIO Port Interrupt #8</description>
<value>8</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_9</name>
<description>GPIO Port Interrupt #9</description>
<value>9</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_10</name>
<description>GPIO Port Interrupt #10</description>
<value>10</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_11</name>
<description>GPIO Port Interrupt #11</description>
<value>11</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_12</name>
<description>GPIO Port Interrupt #12</description>
<value>12</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_13</name>
<description>GPIO Port Interrupt #13</description>
<value>13</value>
</interrupt>
<interrupt>
<name>ioss_interrupts_gpio_14</name>
<description>GPIO Port Interrupt #14</description>
<value>14</value>
</interrupt>
<interrupt>
<name>ioss_interrupt_gpio</name>
<description>GPIO All Ports</description>
<value>15</value>
</interrupt>
<interrupt>
<name>ioss_interrupt_vdd</name>
<description>GPIO Supply Detect Interrupt</description>
<value>16</value>
</interrupt>
<interrupt>
<name>lpcomp_interrupt</name>
<description>Low Power Comparator Interrupt</description>
<value>17</value>
</interrupt>
<interrupt>
<name>scb_8_interrupt</name>
<description>Serial Communication Block #8 (DeepSleep capable)</description>
<value>18</value>
</interrupt>
<interrupt>
<name>srss_interrupt_mcwdt_0</name>
<description>Multi Counter Watchdog Timer interrupt</description>
<value>19</value>
</interrupt>
<interrupt>
<name>srss_interrupt_mcwdt_1</name>
<description>Multi Counter Watchdog Timer interrupt</description>
<value>20</value>
</interrupt>
<interrupt>
<name>srss_interrupt_backup</name>
<description>Backup domain interrupt</description>
<value>21</value>
</interrupt>
<interrupt>
<name>srss_interrupt</name>
<description>Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)</description>
<value>22</value>
</interrupt>
<interrupt>
<name>pass_interrupt_ctbs</name>
<description>CTBm Interrupt (all CTBms)</description>
<value>23</value>
</interrupt>
<interrupt>
<name>bless_interrupt</name>
<description>Bluetooth Radio interrupt</description>
<value>24</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_0</name>
<description>CPUSS Inter Process Communication Interrupt #0</description>
<value>25</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_1</name>
<description>CPUSS Inter Process Communication Interrupt #1</description>
<value>26</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_2</name>
<description>CPUSS Inter Process Communication Interrupt #2</description>
<value>27</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_3</name>
<description>CPUSS Inter Process Communication Interrupt #3</description>
<value>28</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_4</name>
<description>CPUSS Inter Process Communication Interrupt #4</description>
<value>29</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_5</name>
<description>CPUSS Inter Process Communication Interrupt #5</description>
<value>30</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_6</name>
<description>CPUSS Inter Process Communication Interrupt #6</description>
<value>31</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_7</name>
<description>CPUSS Inter Process Communication Interrupt #7</description>
<value>32</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_8</name>
<description>CPUSS Inter Process Communication Interrupt #8</description>
<value>33</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_9</name>
<description>CPUSS Inter Process Communication Interrupt #9</description>
<value>34</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_10</name>
<description>CPUSS Inter Process Communication Interrupt #10</description>
<value>35</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_11</name>
<description>CPUSS Inter Process Communication Interrupt #11</description>
<value>36</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_12</name>
<description>CPUSS Inter Process Communication Interrupt #12</description>
<value>37</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_13</name>
<description>CPUSS Inter Process Communication Interrupt #13</description>
<value>38</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_14</name>
<description>CPUSS Inter Process Communication Interrupt #14</description>
<value>39</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_ipc_15</name>
<description>CPUSS Inter Process Communication Interrupt #15</description>
<value>40</value>
</interrupt>
<interrupt>
<name>scb_0_interrupt</name>
<description>Serial Communication Block #0</description>
<value>41</value>
</interrupt>
<interrupt>
<name>scb_1_interrupt</name>
<description>Serial Communication Block #1</description>
<value>42</value>
</interrupt>
<interrupt>
<name>scb_2_interrupt</name>
<description>Serial Communication Block #2</description>
<value>43</value>
</interrupt>
<interrupt>
<name>scb_3_interrupt</name>
<description>Serial Communication Block #3</description>
<value>44</value>
</interrupt>
<interrupt>
<name>scb_4_interrupt</name>
<description>Serial Communication Block #4</description>
<value>45</value>
</interrupt>
<interrupt>
<name>scb_5_interrupt</name>
<description>Serial Communication Block #5</description>
<value>46</value>
</interrupt>
<interrupt>
<name>scb_6_interrupt</name>
<description>Serial Communication Block #6</description>
<value>47</value>
</interrupt>
<interrupt>
<name>scb_7_interrupt</name>
<description>Serial Communication Block #7</description>
<value>48</value>
</interrupt>
<interrupt>
<name>csd_interrupt</name>
<description>CSD (Capsense) interrupt</description>
<value>49</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_0</name>
<description>CPUSS DataWire #0, Channel #0</description>
<value>50</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_1</name>
<description>CPUSS DataWire #0, Channel #1</description>
<value>51</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_2</name>
<description>CPUSS DataWire #0, Channel #2</description>
<value>52</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_3</name>
<description>CPUSS DataWire #0, Channel #3</description>
<value>53</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_4</name>
<description>CPUSS DataWire #0, Channel #4</description>
<value>54</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_5</name>
<description>CPUSS DataWire #0, Channel #5</description>
<value>55</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_6</name>
<description>CPUSS DataWire #0, Channel #6</description>
<value>56</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_7</name>
<description>CPUSS DataWire #0, Channel #7</description>
<value>57</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_8</name>
<description>CPUSS DataWire #0, Channel #8</description>
<value>58</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_9</name>
<description>CPUSS DataWire #0, Channel #9</description>
<value>59</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_10</name>
<description>CPUSS DataWire #0, Channel #10</description>
<value>60</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_11</name>
<description>CPUSS DataWire #0, Channel #11</description>
<value>61</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_12</name>
<description>CPUSS DataWire #0, Channel #12</description>
<value>62</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_13</name>
<description>CPUSS DataWire #0, Channel #13</description>
<value>63</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_14</name>
<description>CPUSS DataWire #0, Channel #14</description>
<value>64</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw0_15</name>
<description>CPUSS DataWire #0, Channel #15</description>
<value>65</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_0</name>
<description>CPUSS DataWire #1, Channel #0</description>
<value>66</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_1</name>
<description>CPUSS DataWire #1, Channel #1</description>
<value>67</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_2</name>
<description>CPUSS DataWire #1, Channel #2</description>
<value>68</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_3</name>
<description>CPUSS DataWire #1, Channel #3</description>
<value>69</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_4</name>
<description>CPUSS DataWire #1, Channel #4</description>
<value>70</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_5</name>
<description>CPUSS DataWire #1, Channel #5</description>
<value>71</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_6</name>
<description>CPUSS DataWire #1, Channel #6</description>
<value>72</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_7</name>
<description>CPUSS DataWire #1, Channel #7</description>
<value>73</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_8</name>
<description>CPUSS DataWire #1, Channel #8</description>
<value>74</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_9</name>
<description>CPUSS DataWire #1, Channel #9</description>
<value>75</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_10</name>
<description>CPUSS DataWire #1, Channel #10</description>
<value>76</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_11</name>
<description>CPUSS DataWire #1, Channel #11</description>
<value>77</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_12</name>
<description>CPUSS DataWire #1, Channel #12</description>
<value>78</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_13</name>
<description>CPUSS DataWire #1, Channel #13</description>
<value>79</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_14</name>
<description>CPUSS DataWire #1, Channel #14</description>
<value>80</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_dw1_15</name>
<description>CPUSS DataWire #1, Channel #15</description>
<value>81</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_fault_0</name>
<description>CPUSS Fault Structure Interrupt #0</description>
<value>82</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_fault_1</name>
<description>CPUSS Fault Structure Interrupt #1</description>
<value>83</value>
</interrupt>
<interrupt>
<name>cpuss_interrupt_crypto</name>
<description>CRYPTO Accelerator Interrupt</description>
<value>84</value>
</interrupt>
<interrupt>
<name>cpuss_interrupt_fm</name>
<description>FLASH Macro Interrupt</description>
<value>85</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_cm0_cti_0</name>
<description>CM0+ CTI #0</description>
<value>86</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_cm0_cti_1</name>
<description>CM0+ CTI #1</description>
<value>87</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_cm4_cti_0</name>
<description>CM4 CTI #0</description>
<value>88</value>
</interrupt>
<interrupt>
<name>cpuss_interrupts_cm4_cti_1</name>
<description>CM4 CTI #1</description>
<value>89</value>
</interrupt>
<interrupt>
<name>tcpwm_0_interrupts_0</name>
<description>TCPWM #0, Counter #0</description>
<value>90</value>
</interrupt>
<interrupt>
<name>tcpwm_0_interrupts_1</name>
<description>TCPWM #0, Counter #1</description>
<value>91</value>
</interrupt>
<interrupt>
<name>tcpwm_0_interrupts_2</name>
<description>TCPWM #0, Counter #2</description>
<value>92</value>
</interrupt>
<interrupt>
<name>tcpwm_0_interrupts_3</name>
<description>TCPWM #0, Counter #3</description>
<value>93</value>
</interrupt>
<interrupt>
<name>tcpwm_0_interrupts_4</name>
<description>TCPWM #0, Counter #4</description>
<value>94</value>
</interrupt>
<interrupt>
<name>tcpwm_0_interrupts_5</name>
<description>TCPWM #0, Counter #5</description>
<value>95</value>
</interrupt>
<interrupt>
<name>tcpwm_0_interrupts_6</name>
<description>TCPWM #0, Counter #6</description>
<value>96</value>
</interrupt>
<interrupt>
<name>tcpwm_0_interrupts_7</name>
<description>TCPWM #0, Counter #7</description>
<value>97</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_0</name>
<description>TCPWM #1, Counter #0</description>
<value>98</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_1</name>
<description>TCPWM #1, Counter #1</description>
<value>99</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_2</name>
<description>TCPWM #1, Counter #2</description>
<value>100</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_3</name>
<description>TCPWM #1, Counter #3</description>
<value>101</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_4</name>
<description>TCPWM #1, Counter #4</description>
<value>102</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_5</name>
<description>TCPWM #1, Counter #5</description>
<value>103</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_6</name>
<description>TCPWM #1, Counter #6</description>
<value>104</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_7</name>
<description>TCPWM #1, Counter #7</description>
<value>105</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_8</name>
<description>TCPWM #1, Counter #8</description>
<value>106</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_9</name>
<description>TCPWM #1, Counter #9</description>
<value>107</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_10</name>
<description>TCPWM #1, Counter #10</description>
<value>108</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_11</name>
<description>TCPWM #1, Counter #11</description>
<value>109</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_12</name>
<description>TCPWM #1, Counter #12</description>
<value>110</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_13</name>
<description>TCPWM #1, Counter #13</description>
<value>111</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_14</name>
<description>TCPWM #1, Counter #14</description>
<value>112</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_15</name>
<description>TCPWM #1, Counter #15</description>
<value>113</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_16</name>
<description>TCPWM #1, Counter #16</description>
<value>114</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_17</name>
<description>TCPWM #1, Counter #17</description>
<value>115</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_18</name>
<description>TCPWM #1, Counter #18</description>
<value>116</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_19</name>
<description>TCPWM #1, Counter #19</description>
<value>117</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_20</name>
<description>TCPWM #1, Counter #20</description>
<value>118</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_21</name>
<description>TCPWM #1, Counter #21</description>
<value>119</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_22</name>
<description>TCPWM #1, Counter #22</description>
<value>120</value>
</interrupt>
<interrupt>
<name>tcpwm_1_interrupts_23</name>
<description>TCPWM #1, Counter #23</description>
<value>121</value>
</interrupt>
<interrupt>
<name>udb_interrupts_0</name>
<description>UDB Interrupt #0</description>
<value>122</value>
</interrupt>
<interrupt>
<name>udb_interrupts_1</name>
<description>UDB Interrupt #1</description>
<value>123</value>
</interrupt>
<interrupt>
<name>udb_interrupts_2</name>
<description>UDB Interrupt #2</description>
<value>124</value>
</interrupt>
<interrupt>
<name>udb_interrupts_3</name>
<description>UDB Interrupt #3</description>
<value>125</value>
</interrupt>
<interrupt>
<name>udb_interrupts_4</name>
<description>UDB Interrupt #4</description>
<value>126</value>
</interrupt>
<interrupt>
<name>udb_interrupts_5</name>
<description>UDB Interrupt #5</description>
<value>127</value>
</interrupt>
<interrupt>
<name>udb_interrupts_6</name>
<description>UDB Interrupt #6</description>
<value>128</value>
</interrupt>
<interrupt>
<name>udb_interrupts_7</name>
<description>UDB Interrupt #7</description>
<value>129</value>
</interrupt>
<interrupt>
<name>udb_interrupts_8</name>
<description>UDB Interrupt #8</description>
<value>130</value>
</interrupt>
<interrupt>
<name>udb_interrupts_9</name>
<description>UDB Interrupt #9</description>
<value>131</value>
</interrupt>
<interrupt>
<name>udb_interrupts_10</name>
<description>UDB Interrupt #10</description>
<value>132</value>
</interrupt>
<interrupt>
<name>udb_interrupts_11</name>
<description>UDB Interrupt #11</description>
<value>133</value>
</interrupt>
<interrupt>
<name>udb_interrupts_12</name>
<description>UDB Interrupt #12</description>
<value>134</value>
</interrupt>
<interrupt>
<name>udb_interrupts_13</name>
<description>UDB Interrupt #13</description>
<value>135</value>
</interrupt>
<interrupt>
<name>udb_interrupts_14</name>
<description>UDB Interrupt #14</description>
<value>136</value>
</interrupt>
<interrupt>
<name>udb_interrupts_15</name>
<description>UDB Interrupt #15</description>
<value>137</value>
</interrupt>
<interrupt>
<name>pass_interrupt_sar</name>
<description>SAR ADC interrupt</description>
<value>138</value>
</interrupt>
<interrupt>
<name>audioss_interrupt_i2s</name>
<description>I2S Audio interrupt</description>
<value>139</value>
</interrupt>
<interrupt>
<name>audioss_interrupt_pdm</name>
<description>PDM/PCM Audio interrupt</description>
<value>140</value>
</interrupt>
<interrupt>
<name>profile_interrupt</name>
<description>Energy Profiler interrupt</description>
<value>141</value>
</interrupt>
<interrupt>
<name>smif_interrupt</name>
<description>Serial Memory Interface interrupt</description>
<value>142</value>
</interrupt>
<interrupt>
<name>usb_interrupt_hi</name>
<description>USB Interrupt</description>
<value>143</value>
</interrupt>
<interrupt>
<name>usb_interrupt_med</name>
<description>USB Interrupt</description>
<value>144</value>
</interrupt>
<interrupt>
<name>usb_interrupt_lo</name>
<description>USB Interrupt</description>
<value>145</value>
</interrupt>
<interrupt>
<name>pass_interrupt_dacs</name>
<description>Consolidated interrrupt for all DACs</description>
<value>146</value>
</interrupt>
<registers>
<register>
<name>CM0_CTL</name>
<description>CM0+ control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFA050002</resetValue>
<resetMask>0xFFFF0003</resetMask>
<fields>
<field>
<name>SLV_STALL</name>
<description>Processor debug access control:
'0': Access.
'1': Stall access.
This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Processor enable:
'0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot.
'1': Enabled.
Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented).
Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details).</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key (to prevent accidental writes).
- Should be written with a 0x05fa key value for the write to take effect.
- Always reads as 0xfa05.</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CM0_STATUS</name>
<description>CM0+ status</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>SLEEPING</name>
<description>Specifies if the CPU is in Active, Sleep or DeepSleep power mode:
- Active power mode: SLEEPING is '0'.
- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'.
- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SLEEPDEEP</name>
<description>Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CM0_CLOCK_CTL</name>
<description>CM0+ clock control</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1000000</resetValue>
<resetMask>0xFF00FF00</resetMask>
<fields>
<field>
<name>SLOW_INT_DIV</name>
<description>Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]).
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PERI_INT_DIV</name>
<description>Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]).
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
Note that Fperi &lt;= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'.</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_INT_CTL0</name>
<description>CM0+ interrupt control 0</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0F0F0F0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MUX0_SEL</name>
<description>System interrupt select for CPU interrupt source 0. If the field value is 240, no system interrupt is connected and the CPU interrupt source is always '0'/de-activated.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX1_SEL</name>
<description>System interrupt select for CPU interrupt source 1.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX2_SEL</name>
<description>System interrupt select for CPU interrupt source 2.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX3_SEL</name>
<description>System interrupt select for CPU interrupt source 3.</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_INT_CTL1</name>
<description>CM0+ interrupt control 1</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0F0F0F0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MUX0_SEL</name>
<description>System interrupt select for CPU interrupt source 4.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX1_SEL</name>
<description>System interrupt select for CPU interrupt source 5.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX2_SEL</name>
<description>System interrupt select for CPU interrupt source 6.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX3_SEL</name>
<description>System interrupt select for CPU interrupt source 7.</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_INT_CTL2</name>
<description>CM0+ interrupt control 2</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0F0F0F0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MUX0_SEL</name>
<description>System interrupt select for CPU interrupt source 8.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX1_SEL</name>
<description>System interrupt select for CPU interrupt source 9.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX2_SEL</name>
<description>System interrupt select for CPU interrupt source 10.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX3_SEL</name>
<description>System interrupt select for CPU interrupt source 11.</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_INT_CTL3</name>
<description>CM0+ interrupt control 3</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0F0F0F0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MUX0_SEL</name>
<description>System interrupt select for CPU interrupt source 12.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX1_SEL</name>
<description>System interrupt select for CPU interrupt source 13.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX2_SEL</name>
<description>System interrupt select for CPU interrupt source 14.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX3_SEL</name>
<description>System interrupt select for CPU interrupt source 15.</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_INT_CTL4</name>
<description>CM0+ interrupt control 4</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0F0F0F0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MUX0_SEL</name>
<description>System interrupt select for CPU interrupt source 16.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX1_SEL</name>
<description>System interrupt select for CPU interrupt source 17.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX2_SEL</name>
<description>System interrupt select for CPU interrupt source 18.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX3_SEL</name>
<description>System interrupt select for CPU interrupt source 19.</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_INT_CTL5</name>
<description>CM0+ interrupt control 5</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0F0F0F0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MUX0_SEL</name>
<description>System interrupt select for CPU interrupt source 20.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX1_SEL</name>
<description>System interrupt select for CPU interrupt source 21.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX2_SEL</name>
<description>System interrupt select for CPU interrupt source 22.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX3_SEL</name>
<description>System interrupt select for CPU interrupt source 23.</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_INT_CTL6</name>
<description>CM0+ interrupt control 6</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0F0F0F0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MUX0_SEL</name>
<description>System interrupt select for CPU interrupt source 24.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX1_SEL</name>
<description>System interrupt select for CPU interrupt source 25.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX2_SEL</name>
<description>System interrupt select for CPU interrupt source 26.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX3_SEL</name>
<description>System interrupt select for CPU interrupt source 27.</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_INT_CTL7</name>
<description>CM0+ interrupt control 7</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0F0F0F0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MUX0_SEL</name>
<description>System interrupt select for CPU interrupt source 28.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX1_SEL</name>
<description>System interrupt select for CPU interrupt source 29.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX2_SEL</name>
<description>System interrupt select for CPU interrupt source 30.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX3_SEL</name>
<description>System interrupt select for CPU interrupt source 31.</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM4_PWR_CTL</name>
<description>CM4 power control</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFA050001</resetValue>
<resetMask>0xFFFF0003</resetMask>
<fields>
<field>
<name>PWR_MODE</name>
<description>Set Power mode for CM4</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Switch CM4 off
Power off, clock off, isolate, reset and no retain.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET</name>
<description>Reset CM4
Clock off, no isolated, no retain and reset.
Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RETAINED</name>
<description>Put CM4 in Retained mode
This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached.
Power off, clock off, isolate, no reset and retain.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Switch CM4 on.
Power on, clock on, no isolate, no reset and no retain.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key (to prevent accidental writes).
- Should be written with a 0x05fa key value for the write to take effect.
- Always reads as 0xfa05.</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CM4_PWR_DELAY_CTL</name>
<description>CM4 power control</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x12C</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>UP</name>
<description>Number clock cycles delay needed after power domain power up</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM4_STATUS</name>
<description>CM4 status</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x13</resetValue>
<resetMask>0x13</resetMask>
<fields>
<field>
<name>SLEEPING</name>
<description>Specifies if the CPU is in Active, Sleep or DeepSleep power mode:
- Active power mode: SLEEPING is '0'.
- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'.
- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SLEEPDEEP</name>
<description>Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PWR_DONE</name>
<description>After a PWR_MODE change this flag indicates if the new power mode has taken effect or not.
Note: this flag can also change as a result of a change in debug power up req</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CM4_CLOCK_CTL</name>
<description>CM4 clock control</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF00</resetMask>
<fields>
<field>
<name>FAST_INT_DIV</name>
<description>Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]).
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM4_NMI_CTL</name>
<description>CM4 NMI control</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MUX0_SEL</name>
<description>System interrupt select for CPU NMI. The reset value ensure that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RAM0_CTL0</name>
<description>RAM 0 control 0</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0x303</resetMask>
<fields>
<field>
<name>SLOW_WS</name>
<description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FAST_WS</name>
<description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>4</dimIncrement>
<name>RAM0_PWR_MACRO_CTL[%s]</name>
<description>RAM 0 power control</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFA050003</resetValue>
<resetMask>0xFFFF0003</resetMask>
<fields>
<field>
<name>PWR_MODE</name>
<description>Set Power mode for 1 SRAM0 Macro</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>See CM4_PWR_CTL</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>undefined</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RETAINED</name>
<description>See CM4_PWR_CTL</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>See CM4_PWR_CTL</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key (to prevent accidental writes).
- Should be written with a 0x05fa key value for the write to take effect.
- Always reads as 0xfa05.</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RAM1_CTL0</name>
<description>RAM 1 control 0</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0x303</resetMask>
<fields>
<field>
<name>SLOW_WS</name>
<description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FAST_WS</name>
<description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RAM1_PWR_CTL</name>
<description>RAM1 power control</description>
<addressOffset>0x190</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFA050003</resetValue>
<resetMask>0xFFFF0003</resetMask>
<fields>
<field>
<name>PWR_MODE</name>
<description>Set Power mode for SRAM1</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>See CM4_PWR_CTL</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>undefined</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RETAINED</name>
<description>See CM4_PWR_CTL</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>See CM4_PWR_CTL</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key (to prevent accidental writes).
- Should be written with a 0x05fa key value for the write to take effect.
- Always reads as 0xfa05.</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RAM2_CTL0</name>
<description>RAM 2 control 0</description>
<addressOffset>0x1A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0x303</resetMask>
<fields>
<field>
<name>SLOW_WS</name>
<description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FAST_WS</name>
<description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RAM2_PWR_CTL</name>
<description>RAM2 power control</description>
<addressOffset>0x1B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFA050003</resetValue>
<resetMask>0xFFFF0003</resetMask>
<fields>
<field>
<name>PWR_MODE</name>
<description>Set Power mode for SRAM2</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>See CM4_PWR_CTL</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>undefined</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RETAINED</name>
<description>See CM4_PWR_CTL</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>See CM4_PWR_CTL</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key (to prevent accidental writes).
- Should be written with a 0x05fa key value for the write to take effect.
- Always reads as 0xfa05.</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RAM_PWR_DELAY_CTL</name>
<description>Power up delay used for all SRAM power domains</description>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x96</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>UP</name>
<description>Number clock cycles delay needed after power domain power up</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ROM_CTL</name>
<description>ROM control</description>
<addressOffset>0x1D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0x303</resetMask>
<fields>
<field>
<name>SLOW_WS</name>
<description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different 'clk_hf' frequencies.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FAST_WS</name>
<description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UDB_PWR_CTL</name>
<description>UDB power control</description>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFA050001</resetValue>
<resetMask>0xFFFF0003</resetMask>
<fields>
<field>
<name>PWR_MODE</name>
<description>Set Power mode for UDBs</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>See CM4_PWR_CTL</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET</name>
<description>See CM4_PWR_CTL</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RETAINED</name>
<description>See CM4_PWR_CTL</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>See CM4_PWR_CTL</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key (to prevent accidental writes).
- Should be written with a 0x05fa key value for the write to take effect.
- Always reads as 0xfa05.</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UDB_PWR_DELAY_CTL</name>
<description>UDB power control</description>
<addressOffset>0x1F4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x12C</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>UP</name>
<description>Number clock cycles delay needed after power domain power up</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DP_STATUS</name>
<description>Debug port status</description>
<addressOffset>0x208</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x4</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>SWJ_CONNECTED</name>
<description>Specifies if the SWJ debug port is connected; i.e. debug host interface is active:
'0': Not connected/not active.
'1': Connected/active.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SWJ_DEBUG_EN</name>
<description>Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:
'0': Disabled.
'1': Enabled.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SWJ_JTAG_SEL</name>
<description>Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected).
'0': SWD selected.
'1': JTAG selected.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BUFF_CTL</name>
<description>Buffer control</description>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>WRITE_BUFF</name>
<description>Specifies if write transfer can be buffered in the bus infrastructure bridges:
'0': Write transfers are not buffered, independent of the transfer's bufferable attribute.
'1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DDFT_CTL</name>
<description>DDFT control</description>
<addressOffset>0x230</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F1F</resetMask>
<fields>
<field>
<name>DDFT_OUT0_SEL</name>
<description>Select signal for CPUSS DDFT[0]
0: clk_r of the Main flash (which is clk_hf for SONOS Flash)
1: Flash data output bit '0' (r_q[0])
2: Flash data output bit '32' (r_q[32])
3: Flash data output bit '64' (r_q[64])
4: Flash data output bit '127' (r_q[127])
5: bist_fm_enabled
6: bist_fail
7: cm0_sleeping
8: cm0_sleepdeep
9: cm0_sleep_hold_ack_n
10: cm4_sleeping
11: cm4_sleepdeep
12: cm4_sleep_hold_ack_n
13: cm4_power
14: cm4_act_retain_n
15: cm4_act_isolate_n
16: cm4_enabled
17: cm4_reset_n
18: cm4_pwr_done
19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0)
20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0)
21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0)</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DDFT_OUT1_SEL</name>
<description>Select signal for CPUSS DDFT[0]
0: clk_r of the Main flash (which is clk_hf for SONOS Flash)
1: Flash data output bit '0' (r_q[0])
2: Flash data output bit '32' (r_q[32])
3: Flash data output bit '64' (r_q[64])
4: Flash data output bit '127' (r_q[127])
5: bist_fm_enabled
6: bist_fail
7: cm0_sleeping
8: cm0_sleepdeep
9: cm0_sleep_hold_ack_n
10: cm4_sleeping
11: cm4_sleepdeep
12: cm4_sleep_hold_ack_n
13: cm4_power
14: cm4_act_retain_n
15: cm4_act_isolate_n
16: cm4_enabled
17: cm4_reset_n
18: cm4_pwr_done
19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0)
20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0)
21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0)</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SYSTICK_CTL</name>
<description>SysTick timer control</description>
<addressOffset>0x240</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40000147</resetValue>
<resetMask>0xC3FFFFFF</resetMask>
<fields>
<field>
<name>TENMS</name>
<description>Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327.</description>
<bitRange>[23:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLOCK_SOURCE</name>
<description>Specifies an external clock source:
'0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise).
'1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock.
o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected.
'3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo').
Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used.
Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source.</description>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SKEW</name>
<description>Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:
'0': Precise.
'1': Imprecise.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NOREF</name>
<description>Specifies if an external clock source is provided:
'0': An external clock source is provided.
'1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_VECTOR_TABLE_BASE</name>
<description>CM0+ vector table base</description>
<addressOffset>0x2B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFF00</resetMask>
<fields>
<field>
<name>ADDR24</name>
<description>Address of CM0+ vector table.
Note: the CM0+ vector table is at an address that is a 256 B multiple.</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM4_VECTOR_TABLE_BASE</name>
<description>CM4 vector table base</description>
<addressOffset>0x2C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFC00</resetMask>
<fields>
<field>
<name>ADDR22</name>
<description>Address of CM4 vector table.
Note: the CM4 vector table is at an address that is a 1024 B multiple.</description>
<bitRange>[31:10]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_PC0_HANDLER</name>
<description>CM0+ protection context 0 handler</description>
<addressOffset>0x320</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADDR</name>
<description>Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IDENTITY</name>
<description>Identity</description>
<addressOffset>0x400</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>P</name>
<description>This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NS</name>
<description>This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC</name>
<description>This field specifies the protection context of the transfer that reads the register.</description>
<bitRange>[7:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MS</name>
<description>This field specifies the bus master identifier of the transfer that reads the register.</description>
<bitRange>[11:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PROTECTION</name>
<description>Protection status</description>
<addressOffset>0x500</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>STATE</name>
<description>Protection state:
'0': UNKNOWN.
'1': VIRGIN.
'2': NORMAL.
'3': SECURE.
'4': DEAD.
The following state transistions are allowed (and enforced by HW):
- UNKNOWN =&gt; VIRGIN/NORMAL/SECURE/DEAD
- NORMAL =&gt; DEAD
- SECURE =&gt; DEAD
An attempt to make a NOT allowed state transition will NOT affect this register field.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_NMI_CTL</name>
<description>CM0+ NMI control</description>
<addressOffset>0x520</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MUX0_SEL</name>
<description>System interrupt select for CPU NMI. The reset value ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MBIST_STAT</name>
<description>Memory BIST status</description>
<addressOffset>0x5A0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>SFP_READY</name>
<description>Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SFP_FAIL</name>
<description>Report status of the BIST run, only valid if SFP_READY=1</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TRIM_ROM_CTL</name>
<description>ROM trim control</description>
<addressOffset>0xF000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>RM</name>
<description>N/A</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RME</name>
<description>Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external pin Read-Write margin settting.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TRIM_RAM_CTL</name>
<description>RAM trim control</description>
<addressOffset>0xF004</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x6002</resetValue>
<resetMask>0x73FF</resetMask>
<fields>
<field>
<name>RM</name>
<description>N/A</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RME</name>
<description>Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external RM[3:0] Read-Write margin settting.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WPULSE</name>
<description>Write Assist Pulse to control pulse width of negative voltage on SRAM bitline.</description>
<bitRange>[7:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RA</name>
<description>Read Assist control for WL under-drive.</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WA</name>
<description>Write assist enable control (Active High).
- WA[1:0] Write Assist pins to control negative voltage on SRAM bitline.</description>
<bitRange>[14:12]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FAULT</name>
<description>Fault structures</description>
<baseAddress>0x40220000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<dim>2</dim>
<dimIncrement>256</dimIncrement>
<name>STRUCT[%s]</name>
<description>Fault structure</description>
<addressOffset>0x00000000</addressOffset>
<register>
<name>CTL</name>
<description>Fault control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>TR_EN</name>
<description>Trigger output enable:
'0': Disabled. The trigger output 'tr_fault' is '0'.
'1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3).</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT_EN</name>
<description>IO output signal enable:
'0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'.
'1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_REQ_EN</name>
<description>Reset request enable:
'0': Disabled.
'1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis).
The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Fault status</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000000</resetMask>
<fields>
<field>
<name>IDX</name>
<description>The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below.
Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'.</description>
<bitRange>[6:0]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>MPU_0</name>
<description>Bus master 0 MPU/SMPU.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0' MPU violation; '1': SMPU violation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_1</name>
<description>Bus master 1 MPU. See MPU_0 description.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_2</name>
<description>Bus master 2 MPU. See MPU_0 description.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_3</name>
<description>Bus master 3 MPU. See MPU_0 description.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_4</name>
<description>Bus master 4 MPU. See MPU_0 description.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_5</name>
<description>Bus master 5 MPU. See MPU_0 description.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_6</name>
<description>Bus master 6 MPU. See MPU_0 description.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_7</name>
<description>Bus master 7 MPU. See MPU_0 description.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_8</name>
<description>Bus master 8 MPU. See MPU_0 description.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_9</name>
<description>Bus master 9 MPU. See MPU_0 description.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_10</name>
<description>Bus master 10 MPU. See MPU_0 description.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_11</name>
<description>Bus master 11 MPU. See MPU_0 description.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_12</name>
<description>Bus master 12 MPU. See MPU_0 description.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_13</name>
<description>Bus master 13 MPU. See MPU_0 description.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_14</name>
<description>Bus master 14 MPU. See MPU_0 description.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>MPU_15</name>
<description>Bus master 15 MPU. See MPU_0 description.</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>CM4_SYS_MPU</name>
<description>CM4 system bus AHB-Lite interface MPU. See MPU_0 description.</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>MS_PPU_0</name>
<description>Peripheral master interface 0 PPU.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0': PPU violation, '1': peripheral bus error.</description>
<value>28</value>
</enumeratedValue>
<enumeratedValue>
<name>MS_PPU_1</name>
<description>Peripheral master interface 0 PPU. See MS_PPU_0 description.</description>
<value>29</value>
</enumeratedValue>
<enumeratedValue>
<name>MS_PPU_2</name>
<description>Peripheral master interface 1 PPU. See MS_PPU_0 description.</description>
<value>30</value>
</enumeratedValue>
<enumeratedValue>
<name>MS_PPU_3</name>
<description>Peripheral master interface 2 PPU. See MS_PPU_0 description.</description>
<value>31</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_0</name>
<description>Peripheral group 0 PPU.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:30]: '0': PPU violation, '1': timeout detected, '2': peripheral bus error.</description>
<value>32</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_1</name>
<description>Peripheral group 1 PPU. See GROUP_PPU_0 description.</description>
<value>33</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_2</name>
<description>Peripheral group 2 PPU. See GROUP_PPU_0 description.</description>
<value>34</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_3</name>
<description>Peripheral group 3 PPU. See GROUP_PPU_0 description.</description>
<value>35</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_4</name>
<description>Peripheral group 4 PPU. See GROUP_PPU_0 description.</description>
<value>36</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_5</name>
<description>Peripheral group 5 PPU. See GROUP_PPU_0 description.</description>
<value>37</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_6</name>
<description>Peripheral group 6 PPU. See GROUP_PPU_0 description.</description>
<value>38</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_7</name>
<description>Peripheral group 7 PPU. See GROUP_PPU_0 description.</description>
<value>39</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_8</name>
<description>Peripheral group 8 PPU. See GROUP_PPU_0 description.</description>
<value>40</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_9</name>
<description>Peripheral group 9 PPU. See GROUP_PPU_0 description.</description>
<value>41</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_10</name>
<description>Peripheral group 10 PPU. See GROUP_PPU_0 description.</description>
<value>42</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_11</name>
<description>Peripheral group 11 PPU. See GROUP_PPU_0 description.</description>
<value>43</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_12</name>
<description>Peripheral group 12 PPU. See GROUP_PPU_0 description.</description>
<value>44</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_13</name>
<description>Peripheral group 13 PPU. See GROUP_PPU_0 description.</description>
<value>45</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_14</name>
<description>Peripheral group 14 PPU. See GROUP_PPU_0 description.</description>
<value>46</value>
</enumeratedValue>
<enumeratedValue>
<name>GROUP_PPU_15</name>
<description>Peripheral group 15 PPU. See GROUP_PPU_0 description.</description>
<value>47</value>
</enumeratedValue>
<enumeratedValue>
<name>FLASHC_MAIN_BUS_ERROR</name>
<description>Flash controller, main interface, bus error:
FAULT_DATA0[31:0]: Violating address.
FAULT_DATA1[31]: '0': FLASH macro interface bus error; '1': memory hole.
FAULT_DATA1[15:12]: Protection context identifier.
FAULT_DATA1[11:8]: Master identifier.</description>
<value>50</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VALID</name>
<description>Valid indication:
'0': Invalid.
'1': Valid. HW sets this field to '1' when new fault source data is captured. New fault source data is ONLY captured when VALID is '0'. SW can clear this field to '0' when the fault is handled (by SW).</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>DATA[%s]</name>
<description>Fault data</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Captured fault source data.
Note: the fault source index STATUS.IDX specifies the format of the DATA registers.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PENDING0</name>
<description>Fault pending 0</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>This field specifies the following sources:
Bit 0: CM0 MPU.
Bit 1: CRYPTO MPU.
Bit 2: DW 0 MPU.
Bit 3: DW 1 MPU.
...
Bit 14: CM4 code bus MPU.
Bit 15: DAP MPU.
Bit 16: CM4 s+G92ystem bus MPU.
Bit 28: Peripheral master interface 0 PPU.
Bit 29: Peripheral master interface 1 PPU.
Bit 30: Peripheral master interface 2 PPU.
Bit 31: Peripheral master interface 3 PPU.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PENDING1</name>
<description>Fault pending 1</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>This field specifies the following sources:
Bit 0: Peripheral group 0 PPU.
Bit 1: Peripheral group 1 PPU.
Bit 2: Peripheral group 2 PPU.
Bit 3: Peripheral group 3 PPU.
Bit 4: Peripheral group 4 PPU.
Bit 5: Peripheral group 5 PPU.
Bit 6: Peripheral group 6 PPU.
Bit 7: Peripheral group 7 PPU.
...
Bit 15: Peripheral group 15 PPU.
Bit 18: Flash controller, main interface, bus error.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PENDING2</name>
<description>Fault pending 2</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>This field specifies the following sources:
Bit 0 - 31: TBD.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MASK0</name>
<description>Fault mask 0</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>Fault source enables:
Bits 31-0: Fault sources 31 to 0.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MASK1</name>
<description>Fault mask 1</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>Fault source enables:
Bits 31-0: Fault sources 63 to 32.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MASK2</name>
<description>Fault mask 2</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SOURCE</name>
<description>Fault source enables:
Bits 31-0: Fault sources 95 to 64.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Interrupt</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>FAULT</name>
<description>This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured:
- STATUS.VALID is set to '1'.
- STATUS.IDX specifies the fault source index.
- DATA0 through DATA3 captures the fault source dara.
SW writes a '1' to these field to clear the interrupt cause to '0'.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt set</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>FAULT</name>
<description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt mask</description>
<addressOffset>0xC8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>FAULT</name>
<description>Mask bit for corresponding field in the INTR register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt masked</description>
<addressOffset>0xCC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>FAULT</name>
<description>Logical and of corresponding INTR and INTR_MASK fields.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>IPC</name>
<description>IPC</description>
<baseAddress>0x40230000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<dim>16</dim>
<dimIncrement>32</dimIncrement>
<name>STRUCT[%s]</name>
<description>IPC structure</description>
<addressOffset>0x00000000</addressOffset>
<register>
<name>ACQUIRE</name>
<description>IPC acquire</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000000</resetMask>
<fields>
<field>
<name>P</name>
<description>User/privileged access control:
'0': user mode.
'1': privileged mode.
This field is set with the user/privileged access control of the access that successfully acquired the lock.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NS</name>
<description>Secure/on-secure access control:
'0': secure.
'1': non-secure.
This field is set with the secure/non-secure access control of the access that successfully acquired the lock.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC</name>
<description>This field specifies the protection context that successfully acquired the lock.</description>
<bitRange>[7:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MS</name>
<description>This field specifies the bus master identifier that successfully acquired the lock.</description>
<bitRange>[11:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SUCCESS</name>
<description>Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):
'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access.
'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access.
Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RELEASE</name>
<description>IPC release</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>INTR_RELEASE</name>
<description>This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'.
SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
<bitRange>[15:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>NOTIFY</name>
<description>IPC notification</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>INTR_NOTIFY</name>
<description>This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'.
SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
<bitRange>[15:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description>IPC data</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LOCK_STATUS</name>
<description>IPC lock status</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000000</resetMask>
<fields>
<field>
<name>P</name>
<description>This field specifies the user/privileged access control:
'0': user mode.
'1': privileged mode.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NS</name>
<description>This field specifies the cecure/on-secure access control:
'0': secure.
'1': non-secure.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC</name>
<description>This field specifies the protection context that successfully acquired the lock.</description>
<bitRange>[7:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MS</name>
<description>This field specifies the bus master identifier that successfully acquired the lock.</description>
<bitRange>[11:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ACQUIRED</name>
<description>Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</cluster>
<cluster>
<dim>16</dim>
<dimIncrement>32</dimIncrement>
<name>INTR_STRUCT[%s]</name>
<description>IPC interrupt structure</description>
<addressOffset>0x00001000</addressOffset>
<register>
<name>INTR</name>
<description>Interrupt</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RELEASE</name>
<description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NOTIFY</name>
<description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt set</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RELEASE</name>
<description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NOTIFY</name>
<description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt mask</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RELEASE</name>
<description>Mask bit for corresponding field in the INTR register.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NOTIFY</name>
<description>Mask bit for corresponding field in the INTR register.</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt masked</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RELEASE</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NOTIFY</name>
<description>Logical and of corresponding INTR and INTR_MASK fields.</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>PROT</name>
<description>Protection</description>
<baseAddress>0x40240000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<name>SMPU</name>
<description>SMPU</description>
<addressOffset>0x00000000</addressOffset>
<register>
<name>MS0_CTL</name>
<description>Master 0 protection context control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>Privileged setting ('0': user mode; '1': privileged mode).
Notes:
This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute.
The default/reset field value provides privileged mode access capabilities.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>Security setting ('0': secure mode; '1': non-secure mode).
Notes:
This field is ONLY used for masters that do NOT provide their own secure/non-escure access control attribute.
Note that the default/reset field value provides non-secure mode access capabilities to all masters.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority).
Notes:
The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth).
The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency).
Masters with the same priority setting form a 'priority group'. Within a 'priority group', roundrobin arbitration is performed.</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>Protection context mask for protection context '0'. This field is a constant '0':
- PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>Protection context mask for protection contexts '15' downto '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1':
- PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed.
- PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'.
Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]).</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS1_CTL</name>
<description>Master 1 protection context control</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS2_CTL</name>
<description>Master 2 protection context control</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS3_CTL</name>
<description>Master 3 protection context control</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS4_CTL</name>
<description>Master 4 protection context control</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS5_CTL</name>
<description>Master 5 protection context control</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS6_CTL</name>
<description>Master 6 protection context control</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS7_CTL</name>
<description>Master 7 protection context control</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS8_CTL</name>
<description>Master 8 protection context control</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS9_CTL</name>
<description>Master 9 protection context control</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS10_CTL</name>
<description>Master 10 protection context control</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS11_CTL</name>
<description>Master 11 protection context control</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS12_CTL</name>
<description>Master 12 protection context control</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS13_CTL</name>
<description>Master 13 protection context control</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS14_CTL</name>
<description>Master 14 protection context control</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MS15_CTL</name>
<description>Master 15 protection context control</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x303</resetValue>
<resetMask>0xFFFF0303</resetMask>
<fields>
<field>
<name>P</name>
<description>See MS0_CTL.P.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>See MS0_CTL.NS.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>See MS0_CTL.PRIO</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>See MS0_CTL.PC_MASK_0.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>See MS0_CTL.PC_MASK_15_TO_1.</description>
<bitRange>[31:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<cluster>
<dim>16</dim>
<dimIncrement>64</dimIncrement>
<name>SMPU_STRUCT[%s]</name>
<description>SMPU structure</description>
<addressOffset>0x00002000</addressOffset>
<register>
<name>ADDR0</name>
<description>SMPU region address 0 (slave structure)</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>SUBREGION_DISABLE</name>
<description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
Bit 0: subregion 0 disable.
Bit 1: subregion 1 disable.
Bit 2: subregion 2 disable.
Bit 3: subregion 3 disable.
Bit 4: subregion 4 disable.
Bit 5: subregion 5 disable.
Bit 6: subregion 6 disable.
Bit 7: subregion 7 disable.
E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADDR24</name>
<description>This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ATT0</name>
<description>SMPU region attributes 0 (slave structure)</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x100</resetValue>
<resetMask>0x80000100</resetMask>
<fields>
<field>
<name>UR</name>
<description>User read enable:
'0': Disabled (user, read acceses are NOT allowed).
'1': Enabled (user, read acceses are allowed).</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UW</name>
<description>User write enable:
'0': Disabled (user, write acceses are NOT allowed).
'1': Enabled (user, write acceses are allowed).</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UX</name>
<description>User execute enable:
'0': Disabled (user, execute acceses are NOT allowed).
'1': Enabled (user, execute acceses are allowed).</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PR</name>
<description>Privileged read enable:
'0': Disabled (privileged, read acceses are NOT allowed).
'1': Enabled (privileged, read acceses are allowed).</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PW</name>
<description>Privileged write enable:
'0': Disabled (privileged, write acceses are NOT allowed).
'1': Enabled (privileged, write acceses are allowed).</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PX</name>
<description>Privileged execute enable:
'0': Disabled (privileged, execute acceses are NOT allowed).
'1': Enabled (privileged, execute acceses are allowed).</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>Non-secure:
'0': Secure (secure accesses allowed, non-secure access NOT allowed).
'1': Non-secure (both secure and non-secure accesses allowed).</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>This field specifies protection context identifier based access control for protection context '0'.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>This field specifies protection context identifier based access control.
Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
<bitRange>[23:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REGION_SIZE</name>
<description>This field specifies the region size:
'0'-'6': Undefined.
'7': 256 B region
'8': 512 B region
'9': 1 KB region
'10': 2 KB region
'11': 4 KB region
'12': 8 KB region
'13': 16 KB region
'14': 32 KB region
'15': 64 KB region
'16': 128 KB region
'17': 256 KB region
'18': 512 KB region
'19': 1 MB region
'20': 2 MB region
'21': 4 MB region
'22': 8 MB region
'23': 16 MB region
'24': 32 MB region
'25': 64 MB region
'26': 128 MB region
'27': 256 MB region
'28': 512 MB region
'39': 1 GB region
'30': 2 GB region
'31': 4 GB region</description>
<bitRange>[28:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MATCH</name>
<description>This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:
'0': PC field participates in 'access evalution'.
'1': PC field participates in 'matching'.
Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Region enable:
'0': Disabled. A disabled region will never result in a match on the bus transfer address.
'1': Enabled.
Note: a disabled address region performs logic gating to reduce dynamic power consumption.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADDR1</name>
<description>SMPU region address 1 (master structure)</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SUBREGION_DISABLE</name>
<description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
Bit 0: subregion 0 disable.
Bit 1: subregion 1 disable.
Bit 2: subregion 2 disable.
Bit 3: subregion 3 disable.
Bit 4: subregion 4 disable.
Bit 5: subregion 5 disable.
Bit 6: subregion 6 disable.
Bit 7: subregion 7 disable.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only.</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ADDR24</name>
<description>This field specifies the most significant bits of the 32-bit address of an address region.
'ADDR_DEF1': base address of structure.
Note: this field is read-only.</description>
<bitRange>[31:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ATT1</name>
<description>SMPU region attributes 1 (master structure)</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7000109</resetValue>
<resetMask>0x9F00012D</resetMask>
<fields>
<field>
<name>UR</name>
<description>User read enable:
'0': Disabled (user, read acceses are NOT allowed).
'1': Enabled (user, read acceses are allowed).
Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>UW</name>
<description>User write enable:
'0': Disabled (user, write acceses are NOT allowed).
'1': Enabled (user, write acceses are allowed).</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UX</name>
<description>User execute enable:
'0': Disabled (user, execute acceses are NOT allowed).
'1': Enabled (user, execute acceses are allowed).
Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PR</name>
<description>Privileged read enable:
'0': Disabled (privileged, read acceses are NOT allowed).
'1': Enabled (privileged, read acceses are allowed).
Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PW</name>
<description>Privileged write enable:
'0': Disabled (privileged, write acceses are NOT allowed).
'1': Enabled (privileged, write acceses are allowed).</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PX</name>
<description>Privileged execute enable:
'0': Disabled (privileged, execute acceses are NOT allowed).
'1': Enabled (privileged, execute acceses are allowed).
Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NS</name>
<description>Non-secure:
'0': Secure (secure accesses allowed, non-secure access NOT allowed).
'1': Non-secure (both secure and non-secure accesses allowed).</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_MASK_0</name>
<description>This field specifies protection context identifier based access control for protection context '0'.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MASK_15_TO_1</name>
<description>This field specifies protection context identifier based access control.
Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
<bitRange>[23:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REGION_SIZE</name>
<description>This field specifies the region size:
'7': 256 B region (8 32 B subregions)
Note: this field is read-only.</description>
<bitRange>[28:24]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC_MATCH</name>
<description>This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:
'0': PC field participates in 'access evalution'.
'1': PC field participates in 'matching'.
Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Region enable:
'0': Disabled. A disabled region will never result in a match on the bus transfer address.
'1': Enabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
</cluster>
<cluster>
<dim>16</dim>
<dimIncrement>1024</dimIncrement>
<name>MPU[%s]</name>
<description>MPU</description>
<addressOffset>0x00004000</addressOffset>
<register>
<name>MS_CTL</name>
<description>Master control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF000F</resetMask>
<fields>
<field>
<name>PC</name>
<description>N/A</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC_SAVED</name>
<description>Saved protection context. Modifications to this field are constrained by the associated MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields.</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<cluster>
<dim>8</dim>
<dimIncrement>32</dimIncrement>
<name>MPU_STRUCT[%s]</name>
<description>MPU structure</description>
<addressOffset>0x00000200</addressOffset>
<register>
<name>ADDR</name>
<description>MPU region address</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>SUBREGION_DISABLE</name>
<description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
Bit 0: subregion 0 disable.
Bit 1: subregion 1 disable.
Bit 2: subregion 2 disable.
Bit 3: subregion 3 disable.
Bit 4: subregion 4 disable.
Bit 5: subregion 5 disable.
Bit 6: subregion 6 disable.
Bit 7: subregion 7 disable.
E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADDR24</name>
<description>This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ATT</name>
<description>MPU region attrributes</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000000</resetMask>
<fields>
<field>
<name>UR</name>
<description>User read enable:
'0': Disabled (user, read acceses are NOT allowed).
'1': Enabled (user, read acceses are allowed).</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UW</name>
<description>User write enable:
'0': Disabled (user, write acceses are NOT allowed).
'1': Enabled (user, write acceses are allowed).</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UX</name>
<description>User execute enable:
'0': Disabled (user, execute acceses are NOT allowed).
'1': Enabled (user, execute acceses are allowed).</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PR</name>
<description>Privileged read enable:
'0': Disabled (privileged, read acceses are NOT allowed).
'1': Enabled (privileged, read acceses are allowed).</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PW</name>
<description>Privileged write enable:
'0': Disabled (privileged, write acceses are NOT allowed).
'1': Enabled (privileged, write acceses are allowed).</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PX</name>
<description>Privileged execute enable:
'0': Disabled (privileged, execute acceses are NOT allowed).
'1': Enabled (privileged, execute acceses are allowed).</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>Non-secure:
'0': Secure (secure accesses allowed, non-secure access NOT allowed).
'1': Non-secure (both secure and non-secure accesses allowed).</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REGION_SIZE</name>
<description>This field specifies the region size:
'0'-'6': Undefined.
'7': 256 B region
'8': 512 B region
'9': 1 KB region
'10': 2 KB region
'11': 4 KB region
'12': 8 KB region
'13': 16 KB region
'14': 32 KB region
'15': 64 KB region
'16': 128 KB region
'17': 256 KB region
'18': 512 KB region
'19': 1 MB region
'20': 2 MB region
'21': 4 MB region
'22': 8 MB region
'23': 16 MB region
'24': 32 MB region
'25': 64 MB region
'26': 128 MB region
'27': 256 MB region
'28': 512 MB region
'39': 1 GB region
'30': 2 GB region
'31': 4 GB region</description>
<bitRange>[28:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Region enable:
'0': Disabled. A disabled region will never result in a match on the bus transfer address.
'1': Enabled.
Note: a disabled address region performs logic gating to reduce dynamic power consumption.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>FLASHC</name>
<description>Flash controller</description>
<baseAddress>0x40250000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>FLASH_CTL</name>
<description>Control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x10F</resetMask>
<fields>
<field>
<name>MAIN_WS</name>
<description>FLASH macro main interface wait states:
'0': 0 wait states.
...
'15': 15 wait states</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REMAP</name>
<description>Specifies remapping of FLASH macro main region.
'0': No remapping.
'1': Remapping. The highest address bit of the FLASH main region is inverted. This effectively remaps the location of FLASH main region physical sectors in the logical address space. In other words, the higher half physical sectors are swapped with the lower half physical sectors.
Note: remapping only affects reading of the FLASH main region (over the R interface). It does NOT affect programming/erasing of the FLASH memory region (over the C interface).
E.g., for a 512 KB / 4 Mb main region, the logical address space ranges from [0x1000:0000, 0x1007:ffff] (the highest bit if the FLASH main region is bit 18). The memory has four physical sectors: sectors 0, 1, 2 and 3. If REMAP is '0', the physical regions logical addresses are as follows:
- The physical region 0: [0x1000:0000, 0x1001:ffff].
- The physical region 1: [0x1002:0000, 0x1003:ffff].
- The physical region 2: [0x1004:0000, 0x1005:ffff].
- The physical region 3: [0x1006:0000, 0x1007:ffff].
If REMAP is '1', the physical regions logical addresses are as follows:
- The physical region 0: [0x1004:0000, 0x1005:ffff].
- The physical region 1: [0x1006:0000, 0x1007:ffff].
- The physical region 2: [0x1000:0000, 0x1001:ffff].
- The physical region 3: [0x1002:0000, 0x1003:ffff].
Note: when the REMAP is changed, SW should invalidate the caches and buffers.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FLASH_PWR_CTL</name>
<description>Flash power control</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description>Controls 'enable' pin of the Flash memory.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE_HV</name>
<description>Controls 'enable_hv' pin of the Flash memory.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FLASH_CMD</name>
<description>Command</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INV</name>
<description>FLASH cache and buffer invalidation for ALL cache and buffers. SW writes a '1' to clear the cache and buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BIST_CTL</name>
<description>BIST control</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>OPCODE</name>
<description>This field specifies how the data check should be performed after reading the data from Flash memory.
'0': Read the Flash and compare the output to BIST_DATA (R0).
'1': Read the Flash and compare the output to the binary complement of BIST_DATA (R1).
'2': Read the Flash and compare with BIST_DATA[] and compliment of BIST_DATA alternately (R01). The expected data of the first read is BIST_DATA, expected data of the second read is binary compliment of BIST_DATA, third read expected data is BIST_DATA, fourth read expected data is binary compliment of BIST_DATA and so on.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UP</name>
<description>Specifies direction in which Flash BIST steps through addresses:
''0': BIST steps through the Flash from the maximum row and column addresses (as specified by a design time configurtion parameter when ADDR_START_ENABLED is '0' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is '1') to the minimum row and column addresses.
'1': BIST steps through the Flash from the minimum row and column addresses ('0' when ADDR_START_ENABLED is '0' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is '1') to the maximum row and column addresses.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ROW_FIRST</name>
<description>Specifies how the Flash BIST addresses are generated:
'0': Column address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its mimimum/maximum value and only then is the row address incremented/decremented.
'1': Row address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its mimimum/maximum value and only then is the column address incremented/decremented.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADDR_START_ENABLED</name>
<description>Specifies Flash BIST start addresses:
'0': Row and column addresses start with their maximum/minimum values.
'1': Row and column addresses start with their values as specified by BIST_ADDR_START.
This feature is supported only for simple increment/decrement patterns. It is not supported with address compliment pattern (BIST_CTL.ADDR_COMPLIMENT_ENABLED) or address pattern which increments/decrements both row address and column address (BIST_CTL.INCR_DECR_BOTH) for every read.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADDR_COMPLIMENT_ENABLED</name>
<description>Specifies to generate address compliment patterns.
'0': Generate normal increment/decrement patterns.
'1': Generate address patterns which interleaves compliment of previous address in between.
Example: The following is an exaple pattern, With UP=1 and ROW_FIRST =0
00_00
11_11
00_01
11_10
00_10
11_01
...</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INCR_DECR_BOTH</name>
<description>Specifies to generate patterns where both column address and row address are incremented/decremented simultaneously.
'0': Generate normal increment/decrement patterns.
'1': Generate address patterns with both row and column address changing.
Example: With UP = 1 and ROW_FIRST = 0
00_00
01_01
10_10
11_11
00_01
01_10
10_11
11_00
00_10
...</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STOP_ON_ERROR</name>
<description>Specifies the BIST to continue indefinitely, regardless of occurrence of errors or not.
'0': BIST controller doesn't stop on the data failures, it continues regardless of the errors.
'1': BIST controller stops on when the first data failure is encounted.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BIST_CMD</name>
<description>BIST command</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>START</name>
<description>1': Start FLASH BIST. Hardware set this field to '0' when BIST is completed.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BIST_ADDR_START</name>
<description>BIST address start register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COL_ADDR_START</name>
<description>Column start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of columns of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with n columns, the legal range is [0, n-1].</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ROW_ADDR_START</name>
<description>Row start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of rows of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with m columns, the legal range is [0, m-1].</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>BIST_DATA[%s]</name>
<description>BIST data register(s)</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>BIST data register to store the expected value for data comparison.
For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>BIST_DATA_ACT[%s]</name>
<description>BIST data actual register(s)</description>
<addressOffset>0x12C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>This field specified the actual Flash data output that caused the BIST failure.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>BIST_DATA_EXP[%s]</name>
<description>BIST data expected register(s)</description>
<addressOffset>0x14C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>This field specified the expected Flash data output.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BIST_ADDR</name>
<description>BIST address register</description>
<addressOffset>0x16C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>COL_ADDR</name>
<description>Current column address.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ROW_ADDR</name>
<description>Current row address.</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BIST_STATUS</name>
<description>BIST status register</description>
<addressOffset>0x170</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>FAIL</name>
<description>0': BIST passed.
'1': BIST failed.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_CA_CTL0</name>
<description>CM0+ cache control</description>
<addressOffset>0x400</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<resetMask>0xC7030000</resetMask>
<fields>
<field>
<name>WAY</name>
<description>Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_ADDR</name>
<description>Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2.</description>
<bitRange>[26:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PREF_EN</name>
<description>Prefetch enable:
'0': Disabled.
'1': Enabled.
Prefetching requires the cache to be enabled; i.e. ENABLED is '1'.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Cache enable:
'0': Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way).
'1': Enabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_CA_CTL1</name>
<description>CM0+ cache control</description>
<addressOffset>0x404</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFA050003</resetValue>
<resetMask>0xFFFF0003</resetMask>
<fields>
<field>
<name>PWR_MODE</name>
<description>Set Power mode for CM0 cache</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>See CM4_PWR_CTL</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>undefined</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RETAINED</name>
<description>See CM4_PWR_CTL</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>See CM4_PWR_CTL</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key (to prevent accidental writes).
- Should be written with a 0x05fa key value for the write to take effect.
- Always reads as 0xfa05.</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CM0_CA_CTL2</name>
<description>CM0+ cache control</description>
<addressOffset>0x408</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x12C</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>PWRUP_DELAY</name>
<description>Number clock cycles delay needed after power domain power up</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_CA_CMD</name>
<description>CM0+ cache command</description>
<addressOffset>0x40C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INV</name>
<description>FLASH cache invalidation. SW writes a '1' to clear the cache. W sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The cache's LRU structure is also reset to its default state.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM0_CA_STATUS0</name>
<description>CM0+ cache status 0</description>
<addressOffset>0x440</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>VALID16</name>
<description>Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CM0_CA_STATUS1</name>
<description>CM0+ cache status 1</description>
<addressOffset>0x444</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>TAG</name>
<description>Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CM0_CA_STATUS2</name>
<description>CM0+ cache status 2</description>
<addressOffset>0x448</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>LRU</name>
<description>Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y):
Bit 5: 0_LRU_1: way 0 less recently used than way 1.
Bit 4: 0_LRU_2.
Bit 3: 0_LRU_3.
Bit 2: 1_LRU_2.
Bit 1: 1_LRU_3.
Bit 0: 2_LRU_3.</description>
<bitRange>[5:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CM4_CA_CTL0</name>
<description>CM4 cache control</description>
<addressOffset>0x480</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<resetMask>0xC7030000</resetMask>
<fields>
<field>
<name>WAY</name>
<description>See CM0_CA_CTL.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_ADDR</name>
<description>See CM0_CA_CTL.</description>
<bitRange>[26:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PREF_EN</name>
<description>See CM0_CA_CTL.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>See CM0_CA_CTL.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM4_CA_CTL1</name>
<description>CM4 cache control</description>
<addressOffset>0x484</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFA050003</resetValue>
<resetMask>0xFFFF0003</resetMask>
<fields>
<field>
<name>PWR_MODE</name>
<description>Set Power mode for CM4 cache</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>See CM4_PWR_CTL</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>undefined</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RETAINED</name>
<description>See CM4_PWR_CTL</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>See CM4_PWR_CTL</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key (to prevent accidental writes).
- Should be written with a 0x05fa key value for the write to take effect.
- Always reads as 0xfa05.</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CM4_CA_CTL2</name>
<description>CM4 cache control</description>
<addressOffset>0x488</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x12C</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>PWRUP_DELAY</name>
<description>Number clock cycles delay needed after power domain power up</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM4_CA_CMD</name>
<description>CM4 cache command</description>
<addressOffset>0x48C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INV</name>
<description>See CM0_CA_CMD.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CM4_CA_STATUS0</name>
<description>CM4 cache status 0</description>
<addressOffset>0x4C0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>VALID16</name>
<description>See CM0_CA_STATUS0.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CM4_CA_STATUS1</name>
<description>CM4 cache status 1</description>
<addressOffset>0x4C4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>TAG</name>
<description>See CM0_CA_STATUS1.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CM4_CA_STATUS2</name>
<description>CM4 cache status 2</description>
<addressOffset>0x4C8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>LRU</name>
<description>See CM0_CA_STATUS2.</description>
<bitRange>[5:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_BUFF_CTL</name>
<description>Cryptography buffer control</description>
<addressOffset>0x500</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<resetMask>0xC0000000</resetMask>
<fields>
<field>
<name>PREF_EN</name>
<description>Prefetch enable:
'0': Disabled.
'1': Enabled.
Prefetching requires the buffer to be enabled; i.e. ENABLED is '1'.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Cache enable:
'0': Disabled.
'1': Enabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_BUFF_CMD</name>
<description>Cryptography buffer command</description>
<addressOffset>0x508</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INV</name>
<description>FLASH buffer invalidation. SW writes a '1' to clear the buffer. HW sets this field to '0' when the operation is completed.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DW0_BUFF_CTL</name>
<description>Datawire 0 buffer control</description>
<addressOffset>0x580</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<resetMask>0xC0000000</resetMask>
<fields>
<field>
<name>PREF_EN</name>
<description>See CRYPTO_BUFF_CTL.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>See CRYPTO_BUFF_CTL.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DW0_BUFF_CMD</name>
<description>Datawire 0 buffer command</description>
<addressOffset>0x588</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INV</name>
<description>See CRYPTO_BUFF_CMD.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DW1_BUFF_CTL</name>
<description>Datawire 1 buffer control</description>
<addressOffset>0x600</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<resetMask>0xC0000000</resetMask>
<fields>
<field>
<name>PREF_EN</name>
<description>See CRYPTO_BUFF_CTL.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>See CRYPTO_BUFF_CTL.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DW1_BUFF_CMD</name>
<description>Datawire 1 buffer command</description>
<addressOffset>0x608</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INV</name>
<description>See CRYPTO_BUFF_CMD.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DAP_BUFF_CTL</name>
<description>Debug access port buffer control</description>
<addressOffset>0x680</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<resetMask>0xC0000000</resetMask>
<fields>
<field>
<name>PREF_EN</name>
<description>See CRYPTO_BUFF_CTL.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>See CRYPTO_BUFF_CTL.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DAP_BUFF_CMD</name>
<description>Debug access port buffer command</description>
<addressOffset>0x688</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INV</name>
<description>See CRYPTO_BUFF_CMD.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EXT_MS0_BUFF_CTL</name>
<description>External master 0 buffer control</description>
<addressOffset>0x700</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<resetMask>0xC0000000</resetMask>
<fields>
<field>
<name>PREF_EN</name>
<description>See CRYPTO_BUFF_CTL.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>See CRYPTO_BUFF_CTL.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EXT_MS0_BUFF_CMD</name>
<description>External master 0 buffer command</description>
<addressOffset>0x708</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INV</name>
<description>See CRYPTO_BUFF_CMD.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EXT_MS1_BUFF_CTL</name>
<description>External master 1 buffer control</description>
<addressOffset>0x780</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<resetMask>0xC0000000</resetMask>
<fields>
<field>
<name>PREF_EN</name>
<description>See CRYPTO_BUFF_CTL.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>See CRYPTO_BUFF_CTL.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EXT_MS1_BUFF_CMD</name>
<description>External master 1 buffer command</description>
<addressOffset>0x788</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INV</name>
<description>See CRYPTO_BUFF_CMD.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<cluster>
<name>FM_CTL</name>
<description>Flash Macro Registers</description>
<addressOffset>0x0000F000</addressOffset>
<register>
<name>FM_CTL</name>
<description>Flash macro control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x37F030F</resetMask>
<fields>
<field>
<name>FM_MODE</name>
<description>Flash macro mode selection:
'0': Normal functional mode.
'1': Sets 'pre-program control bit' for soft pre-program operation of all selected SONOS cells. the control bit is cleared by the HW after any program operation.
'2': Sets
...
'15': TBD</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FM_SEQ</name>
<description>Flash macro sequence select:
'0': TBD
'1': TBD
'2': TBD
'3': TBD</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DAA_MUX_SEL</name>
<description>Direct memory cell access address.</description>
<bitRange>[22:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IF_SEL</name>
<description>Interface selection. Specifies the interface that is used for flash memory read operations:
'0': R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface.
'1': C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WR_EN</name>
<description>'0': normal mode
'1': Fm Write Enable</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Status</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>HV_TIMER_RUNNING</name>
<description>Indicates if the high voltage timer is running:
'0': not running
'1': running</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>HV_REGS_ISOLATED</name>
<description>Indicates the isolation status at HV trim and redundancy registers inputs
'0' - Not isolated, writing permitted
'1' - isolated writing disabled</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ILLEGAL_HVOP</name>
<description>Indicates a bulk,sector erase, program has been requested when axa=1
'0' - no error
'1' - illegal HV operation error</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TURBO_N</name>
<description>After FM power up indicates the analog blocks currents are boosted to faster reach their functional state..
Used in the testchip boot only as an 'FM READY' flag.
'0' - turbo mode
'1' - normal mode</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WR_EN_MON</name>
<description>FM_CTL.WR_EN bit after being synchronized in clk_r domain</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IF_SEL_MON</name>
<description>FM_CTL.IF_SEL bit after being synchronized in clk_r domain</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FM_ADDR</name>
<description>Flash macro address</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FFFFFF</resetMask>
<fields>
<field>
<name>RA</name>
<description>Row address.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BA</name>
<description>Bank address.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AXA</name>
<description>Auxiliairy address field:
'0': regular flash memory.
'1': supervisory flash memory.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GEOMETRY</name>
<description>Regular flash geometry</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WORD_SIZE_LOG2</name>
<description>Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access:
'0': 1 Byte
'1': 2 Bytes
'2': 4 Bytes
...
'7': 128 Bytes
The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively.</description>
<bitRange>[3:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PAGE_SIZE_LOG2</name>
<description>Number of Bytes per page (log 2):
'0': 1 Byte
'1': 2 Bytes
'2': 4 Bytes
...
'15': 32768 Bytes
The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively.</description>
<bitRange>[7:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ROW_COUNT</name>
<description>Number of rows (minus 1):
'0': 1 row
'1': 2 rows
'2': 3 rows
...
'65535': 65536 rows</description>
<bitRange>[23:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BANK_COUNT</name>
<description>Number of banks (minus 1):
'0': 1 bank
'1': 2 banks
...
'255': 256 banks</description>
<bitRange>[31:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GEOMETRY_SUPERVISORY</name>
<description>Supervisory flash geometry</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WORD_SIZE_LOG2</name>
<description>Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2.</description>
<bitRange>[3:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PAGE_SIZE_LOG2</name>
<description>Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2.</description>
<bitRange>[7:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ROW_COUNT</name>
<description>Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT</description>
<bitRange>[23:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BANK_COUNT</name>
<description>Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT.</description>
<bitRange>[31:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TIMER_CTL</name>
<description>Timer control</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4000000</resetValue>
<resetMask>0xE701FFFF</resetMask>
<fields>
<field>
<name>PERIOD</name>
<description>Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCALE</name>
<description>Timer tick scale:
'0': 1 microsecond.
'1': 100 microseconds.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PUMP_CLOCK_SEL</name>
<description>Pump clock select:
'0': internal clock.
'1': external clock.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRE_PROG</name>
<description>'1' during pre-program operation</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRE_PROG_CSL</name>
<description>'0' CSL lines driven by CSL_DAC
'1' CSL lines driven by VNEG_G</description>
<bitRange>[26:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PUMP_EN</name>
<description>Pump enable:
'0': disabled
'1': enabled (also requires FM_CTL.IF_SEL to be '1', this additional restriction is reuired to prevent non intential clearing of the FM).
SW sets this field to '1' to generate a single PE pulse.
HW clears this field when timer is expired.</description>
<bitRange>[29:29]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACLK_EN</name>
<description>ACLK enable (generates a single cycle pulse for the FM):
'0': disabled
'1': enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TIMER_EN</name>
<description>Timer enable:
'0': disabled
'1': enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ANA_CTL0</name>
<description>Analog control 0</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x400</resetValue>
<resetMask>0x9000700</resetMask>
<fields>
<field>
<name>CSLDAC</name>
<description>Trimming of common source line DAC.</description>
<bitRange>[10:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VCC_SEL</name>
<description>Vcc select:
'0': 1.2 V : LP reset value
'1': 0.95 V: ULP reset value
Note: the flash macro compiler has a configuration option that specifies the default/reset value of this field.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FLIP_AMUXBUS_AB</name>
<description>Flips amuxbusa and amuxbusb
'0': amuxbusa, amuxbusb
'1': amuxbusb, amuxbusb</description>
<bitRange>[27:27]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ANA_CTL1</name>
<description>Analog control 1</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x6060000</resetValue>
<resetMask>0x7F0F00FF</resetMask>
<fields>
<field>
<name>MDAC</name>
<description>Trimming of the output margin Voltage as a function of Vpos and Vneg.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PDAC</name>
<description>Trimming of positive pump output Voltage:</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NDAC</name>
<description>Trimming of negative pump output Voltage:</description>
<bitRange>[27:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VPROT_OVERRIDE</name>
<description>'0': vprot = BG.vprot.
'1': vprot = vcc</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>R_GRANT_CTL</name>
<description>r_grant control:
'0': r_grant normal functionality
'1': forces r_grant LO synchronized on clk_r</description>
<bitRange>[29:29]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RST_SFT_HVPL</name>
<description>'1': Page Latches Soft Reset</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GEOMETRY_GEN</name>
<description>N/A, DNU</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xE</resetMask>
<fields>
<field>
<name>DNU_0X20_1</name>
<description>N/A</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DNU_0X20_2</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DNU_0X20_3</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TEST_CTL</name>
<description>Test mode control</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80070F1F</resetMask>
<fields>
<field>
<name>TEST_MODE</name>
<description>Test mode control:
'0'-'31': TBD</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PN_CTL</name>
<description>Postive/negative margin mode control:
'0': negative margin control
'1': positive margin control</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TM_PE</name>
<description>PUMP_EN override: Pump Enable =PUMP_EN | PE_TM</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TM_DISPOS</name>
<description>Test mode positive pump disable</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TM_DISNEG</name>
<description>Test mode negative pump disable</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EN_CLK_MON</name>
<description>1: enables the oscillator output monitor</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CSL_DEBUG</name>
<description>Engineering Debug Register</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE_OSC</name>
<description>0': the oscillator enable logic has control over the internal oscillator
'1': forces oscillator enable HI</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UNSCRAMBLE_WA</name>
<description>See BSN-242 memo
'0': normal
'1': disables the Word Address scrambling</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WAIT_CTL</name>
<description>Wiat State control</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x30B09</resetValue>
<resetMask>0x70F0F</resetMask>
<fields>
<field>
<name>WAIT_FM_MEM_RD</name>
<description>Number of C interface wait cycles (on 'clk_c') for a read from the memory</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WAIT_FM_HV_RD</name>
<description>Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches.
Common for reading HV Page Latches and the DATA_COMP_RESULT bit</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WAIT_FM_HV_WR</name>
<description>Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches.</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MONITOR_STATUS</name>
<description>Monitor Status</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x4</resetValue>
<resetMask>0x6</resetMask>
<fields>
<field>
<name>POS_PUMP_VLO</name>
<description>POS pump VLO</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NEG_PUMP_VHI</name>
<description>NEG pump VHI</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SCRATCH_CTL</name>
<description>Scratch Control</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DUMMY32</name>
<description>Scratchpad register fields. Provided for test purposes.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HV_CTL</name>
<description>High voltage control</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x32</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TIMER_CLOCK_FREQ</name>
<description>Specifies the frequency in MHz of the timer clock 'clk_t' as provide to the flash macro. E.g., if '4', the timer clock 'clk_t' has a frequency of 4 MHz.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ACLK_CTL</name>
<description>Aclk control</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>ACLK_GEN</name>
<description>A write to this register generates a ACLK pulse for the flash macro (also requires FM_CTL.IF_SEL to be '1').</description>
<bitRange>[0:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Interrupt</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>TIMER_EXPIRED</name>
<description>Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt set</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>TIMER_EXPIRED</name>
<description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt mask</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>TIMER_EXPIRED</name>
<description>Mask for corresponding field in INTR register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt masked</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>TIMER_EXPIRED</name>
<description>Logical and of corresponding request and mask fields.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FM_HV_DATA_ALL</name>
<description>Flash macro high Voltage page latches data (for all page latches)</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA32</name>
<description>Write all high Voltage page latches with the same 32-bit data in a single write cycle</description>
<bitRange>[31:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CAL_CTL0</name>
<description>Cal control BG LO trim bits</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x88F8F</resetValue>
<resetMask>0xFFFFF</resetMask>
<fields>
<field>
<name>VCT_TRIM_LO_HV</name>
<description>LO Bandgap Voltage Temperature Compensation trim control.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CDAC_LO_HV</name>
<description>LO Temperature compensated trim DAC. To control Vcstat slope for Vpos.</description>
<bitRange>[7:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VBG_TRIM_LO_HV</name>
<description>LO Bandgap Voltage trim control.</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VBG_TC_TRIM_LO_HV</name>
<description>LO Bandgap Voltage Temperature Compensation trim control</description>
<bitRange>[15:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IPREF_TRIM_LO_HV</name>
<description>LO Bandgap IPTAT trim control.</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CAL_CTL1</name>
<description>Cal control BG HI trim bits</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x88F8F</resetValue>
<resetMask>0xFFFFF</resetMask>
<fields>
<field>
<name>VCT_TRIM_HI_HV</name>
<description>HI Bandgap Voltage Temperature Compensation trim control.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CDAC_HI_HV</name>
<description>HI Temperature compensated trim DAC. To control Vcstat slope for Vpos.</description>
<bitRange>[7:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VBG_TRIM_HI_HV</name>
<description>HI Bandgap Voltage trim control.</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VBG_TC_TRIM_HI_HV</name>
<description>HI Bandgap Voltage Temperature Compensation trim control.</description>
<bitRange>[15:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IPREF_TRIM_HI_HV</name>
<description>HI Bandgap IPTAT trim control.</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CAL_CTL2</name>
<description>Cal control BG LO&amp;HI ipref trim, ref sel, fm_active, turbo_ext</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x7070</resetValue>
<resetMask>0xFFFFF</resetMask>
<fields>
<field>
<name>ICREF_TRIM_LO_HV</name>
<description>LO Bandgap Current trim control.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ICREF_TC_TRIM_LO_HV</name>
<description>LO Bandgap Current Temperature Compensation trim control</description>
<bitRange>[7:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ICREF_TRIM_HI_HV</name>
<description>HI Bandgap Current trim control.</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ICREF_TC_TRIM_HI_HV</name>
<description>HI Bandgap Current Temperature Compensation trim control.</description>
<bitRange>[15:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREF_SEL_HV</name>
<description>Voltage reference:
'0': internal bandgap reference
'1': external voltage reference</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IREF_SEL_HV</name>
<description>Current reference:
'0': internal current reference
'1': external current reference</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FM_ACTIVE_HV</name>
<description>0: No Action
1: Forces FM SYS in active mode</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TURBO_EXT_HV</name>
<description>0: turbo signal generated internally
1: turbo cleared by clk_pump_ext HI</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CAL_CTL3</name>
<description>Cal control osc trim bits, idac, sdac, itim, bdac.</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA504</resetValue>
<resetMask>0xFFFFF</resetMask>
<fields>
<field>
<name>OSC_TRIM_HV</name>
<description>Flash macro pump clock trim control.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OSC_RANGE_TRIM_HV</name>
<description>0: Oscillator High Frequency Range
1: Oscillator Low Frequency range</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IDAC_HV</name>
<description>N/A</description>
<bitRange>[8:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SDAC_HV</name>
<description>N/A</description>
<bitRange>[10:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ITIM_HV</name>
<description>Trimming of timing current</description>
<bitRange>[14:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VDDHI_HV</name>
<description>0': vdd&lt;2.3V
'1': vdd&gt;=2.3V</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TURBO_PULSEW_HV</name>
<description>Turbo pulse width trim</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BGLO_EN_HV</name>
<description>LO Bandgap Enable</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BGHI_EN_HV</name>
<description>HI Bandgap Enable</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BOOKMARK</name>
<description>Bookmark register - keeps the current FW HV seq</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BOOKMARK</name>
<description>Used by FW. Keeps the Current HV cycle sequence</description>
<bitRange>[31:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>RED_CTL01</name>
<description>Redundancy Control normal sectors 0,1</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF01FF</resetMask>
<fields>
<field>
<name>RED_ADDR_0</name>
<description>Bad Row Pair Address for Sector 0</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RED_EN_0</name>
<description>'1': Redundancy Enable for Sector 0</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RED_ADDR_1</name>
<description>Bad Row Pair Address for Sector 1</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RED_EN_1</name>
<description>'1': Redundancy Enable for Sector 1</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RED_CTL23</name>
<description>Redundancy Controll normal sectors 2,3</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF01FF</resetMask>
<fields>
<field>
<name>RED_ADDR_2</name>
<description>Bad Row Pair Address for Sector 2</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RED_EN_2</name>
<description>1': Redundancy Enable for Sector 2</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RED_ADDR_3</name>
<description>Bad Row Pair Address for Sector 3</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RED_EN_3</name>
<description>1': Redundancy Enable for Sector 3</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RED_CTL45</name>
<description>Redundancy Controll normal sectors 4,5</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF01FF</resetMask>
<fields>
<field>
<name>DNU_45_1</name>
<description>Not Used</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REG_ACT_HV</name>
<description>Forces the VBST regulator in active mode all the time</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DNU_45_3</name>
<description>Not Used</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FDIV_TRIM_HV_0</name>
<description>'2b00' F = 1MHz see fdiv_trim_hv&lt;1&gt; value as well
'2b01' F = 0.5MHz
'2b10' F = 2MHz
'2b11' F = 4Mhz</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DNU_45_5</name>
<description>Not Used</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FDIV_TRIM_HV_1</name>
<description>'2b00' F = 1MHz see fdiv_trim_hv&lt;0&gt; value as well
'2b01' F = 0.5MHz
'2b10' F = 2MHz
'2b11' F = 4Mhz</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DNU_45_6</name>
<description>Not Used</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VLIM_TRIM_HV_0</name>
<description>'2b00' V2 = 650mV see vlim_trim_hv&lt;1&gt; value as well
'2b01' V2 = 600mV
'2b10' V2 = 750mV
'2b11' V2 = 700mV</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DNU_45_8</name>
<description>Not Used</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DNU_45_23_16</name>
<description>Not Used</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RED_CTL67</name>
<description>Redundancy Controll normal sectors 6,7</description>
<addressOffset>0x8C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF01FF</resetMask>
<fields>
<field>
<name>VLIM_TRIM_HV_1</name>
<description>'2b00' V2 = 650mV see vlim_trim_hv&lt;0&gt; value as well
'2b01' V2 = 600mV
'2b10' V2 = 750mV
'2b11' V2 = 700mV</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DNU_67_1</name>
<description>Not Used</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VPROT_ACT_HV</name>
<description>Forces VPROT in active mode all the time</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DNU_67_3</name>
<description>Not Used</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IPREF_TC_HV</name>
<description>Reduces the IPREF Tempco by not subtracting ICREF form IPREF - IPREF will be 1uA</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DNU_67_5</name>
<description>Not Used</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IPREF_TRIMA_HI_HV</name>
<description>Adds 200-300nA boost on IPREF_HI</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DNU_67_7</name>
<description>Not Used</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IPREF_TRIMA_LO_HV</name>
<description>Adds 200-300nA boost on IPREF_LO</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DNU_67_23_16</name>
<description>Not Used</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RED_CTL_SM01</name>
<description>Redundancy Controll special sectors 0,1</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC1FF01FF</resetMask>
<fields>
<field>
<name>RED_ADDR_SM0</name>
<description>Bad Row Pair Address for Special Sector 0</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RED_EN_SM0</name>
<description>Redundancy Enable for Special Sector 0</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RED_ADDR_SM1</name>
<description>Bad Row Pair Address for Special Sector 1</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RED_EN_SM1</name>
<description>Redundancy Enable for Special Sector 1</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TRKD</name>
<description>Sense Amp Control tracking delay</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>R_GRANT_EN</name>
<description>'0': r_grant handshake disabled, r_grant always 1.
'1': r_grand handshake enabled</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>32</dim>
<dimIncrement>4</dimIncrement>
<name>TM_CMPR[%s]</name>
<description>Do Not Use</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>DATA_COMP_RESULT</name>
<description>The result of a comparison between the flash macro data output and the content of the high voltage page latches.
The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number.
The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD.
'0': FALSE (not equal)
'1': TRUE (equal)</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>256</dim>
<dimIncrement>4</dimIncrement>
<name>FM_HV_DATA[%s]</name>
<description>Flash macro high Voltage page latches data</description>
<addressOffset>0x800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA32</name>
<description>Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1').
Note: the high Voltage page latches are readable for test mode functionality.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>256</dim>
<dimIncrement>4</dimIncrement>
<name>FM_MEM_DATA[%s]</name>
<description>Flash macro memory sense amplifier and column decoder data</description>
<addressOffset>0xC00</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA32</name>
<description>Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL:
- IF_SEL is '0': data as specified by the R interface address
- IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>SRSS</name>
<description>SRSS Core Registers</description>
<baseAddress>0x40260000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PWR_CTL</name>
<description>Power Mode Control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFC0033</resetMask>
<fields>
<field>
<name>POWER_MODE</name>
<description>Current power mode of the device. LPACTIVE/LPSLEEP are implemented as firmware configuration of multiple registers and are reported here as ACTIVE/SLEEP, respectively. Note that this field cannot be read in all power modes on actual silicon.</description>
<bitRange>[1:0]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESET</name>
<description>System is resetting.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>At least one CPU is running.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SLEEP</name>
<description>No CPUs are running. Peripherals may be running.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DEEPSLEEP</name>
<description>Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEBUG_SESSION</name>
<description>Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_SESSION</name>
<description>No debug session active</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SESSION_ACTIVE</name>
<description>Debug session is active. Power modes behave differently to keep the debug session active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPM_READY</name>
<description>Indicates whether certain low power functions are ready. The low current circuits take longer to startup after POR/XRES/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode.
1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IREF_LPMODE</name>
<description>Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less.
1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREFBUF_OK</name>
<description>Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1.</description>
<bitRange>[19:19]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DPSLP_REG_DIS</name>
<description>Disable the DeepSleep regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0: DeepSleep Regulator is on.
1: DeepSleep Regulator is off.</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RET_REG_DIS</name>
<description>Disable the Retention regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0: Retention Regulator is on.
1: Retention Regulator is off.</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NWELL_REG_DIS</name>
<description>Disable the Nwell regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0: Nwell Regulator is on.
1: Nwell Regulator is off.</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LINREG_DIS</name>
<description>Disable the linear Core Regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0: Linear regulator is on.
1: Linear regulator is off.</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LINREG_LPMODE</name>
<description>Control the power mode of the ULP Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0: ULP Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product.
1: ULP Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PORBOD_LPMODE</name>
<description>Control the power mode of the ULP POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0: ULP POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less.
1: ULP POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BGREF_LPMODE</name>
<description>Control the power mode of the ULP Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0: ULP Active Bandgap Voltage and Current Reference operates in normal mode. They work for vddd ramp rates of 100mV/us or less.
1: ULP Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0.</description>
<bitRange>[26:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PLL_LS_BYPASS</name>
<description>Bypass level shifter inside the PLL.
0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage.
1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current.</description>
<bitRange>[27:27]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREFBUF_LPMODE</name>
<description>Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1.
0: ULP Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
1: ULP Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREFBUF_DIS</name>
<description>Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.</description>
<bitRange>[29:29]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_REF_DIS</name>
<description>Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0: Active Reference is enabled
1: Active Reference is disabled</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_REF_OK</name>
<description>Indicates that the normal mode of the Active Reference is ready.</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PWR_HIBERNATE</name>
<description>HIBERNATE Mode Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xCFFEFFFF</resetMask>
<fields>
<field>
<name>TOKEN</name>
<description>Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UNLOCK</name>
<description>This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FREEZE</name>
<description>Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write.</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MASK_HIBALARM</name>
<description>When set, HIBERNATE will wakeup for a RTC interrupt</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MASK_HIBWDT</name>
<description>When set, HIBERNATE will wakeup if WDT matches</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>POLARITY_HIBPIN</name>
<description>Each bit sets the active polarity of the corresponding wakeup pin.
0: Pin input of 0 will wakeup the part from HIBERNATE
1: Pin input of 1 will wakeup the part from HIBERNATE</description>
<bitRange>[23:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MASK_HIBPIN</name>
<description>When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins.</description>
<bitRange>[27:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HIBERNATE_DISABLE</name>
<description>Hibernate disable bit.
0: Normal operation, HIBERNATE works as described
1: Further writes to this register are ignored
Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written..</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HIBERNATE</name>
<description>Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_LVD_CTL</name>
<description>Low Voltage Detector (LVD) Configuration Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>HVLVD1_TRIPSEL</name>
<description>Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold.
0: rise=1.225V (nom), fall=1.2V (nom)
1: rise=1.425V (nom), fall=1.4V (nom)
2: rise=1.625V (nom), fall=1.6V (nom)
3: rise=1.825V (nom), fall=1.8V (nom)
4: rise=2.025V (nom), fall=2V (nom)
5: rise=2.125V (nom), fall=2.1V (nom)
6: rise=2.225V (nom), fall=2.2V (nom)
7: rise=2.325V (nom), fall=2.3V (nom)
8: rise=2.425V (nom), fall=2.4V (nom)
9: rise=2.525V (nom), fall=2.5V (nom)
10: rise=2.625V (nom), fall=2.6V (nom)
11: rise=2.725V (nom), fall=2.7V (nom)
12: rise=2.825V (nom), fall=2.8V (nom)
13: rise=2.925V (nom), fall=2.9V (nom)
14: rise=3.025V (nom), fall=3.0V (nom)
15: rise=3.125V (nom), fall=3.1V (nom)</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLVD1_SRCSEL</name>
<description>Source selection for HVLVD1</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>VDDD</name>
<description>Select VDDD</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AMUXBUSA</name>
<description>Select AMUXBUSA (VDDD branch)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>VDDIO</name>
<description>N/A</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>AMUXBUSB</name>
<description>Select AMUXBUSB (VDDD branch)</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HVLVD1_EN</name>
<description>Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it further recommended to read the realted PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_BUCK_CTL</name>
<description>Buck Control Register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x5</resetValue>
<resetMask>0xC0000007</resetMask>
<fields>
<field>
<name>BUCK_OUT1_SEL</name>
<description>Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current.
0: 0.85V
1: 0.875V
2: 0.90V
3: 0.95V
4: 1.05V
5: 1.10V
6: 1.15V
7: 1.20V</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUCK_EN</name>
<description>Master enable for buck converter. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUCK_OUT1_EN</name>
<description>Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The SAS specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_BUCK_CTL2</name>
<description>Buck Control Register 2</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC0000007</resetMask>
<fields>
<field>
<name>BUCK_OUT2_SEL</name>
<description>Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current.
0: 1.15V
1: 1.20V
2: 1.25V
3: 1.30V
4: 1.35V
5: 1.40V
6: 1.45V
7: 1.50V</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUCK_OUT2_HW_SEL</name>
<description>Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUCK_OUT2_EN</name>
<description>Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_LVD_STATUS</name>
<description>Low Voltage Detector (LVD) Status Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>HVLVD1_OK</name>
<description>HVLVD1 output.
0: below voltage threshold
1: above voltage threshold</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>4</dimIncrement>
<name>PWR_HIB_DATA[%s]</name>
<description>HIBERNATE Data Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HIB_DATA</name>
<description>Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WDT_CTL</name>
<description>Watchdog Counter Control Register</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000001</resetValue>
<resetMask>0xC0000001</resetMask>
<fields>
<field>
<name>WDT_EN</name>
<description>Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_LOCK</name>
<description>Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle.
Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes.</description>
<bitRange>[31:30]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_CHG</name>
<description>No effect</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLR0</name>
<description>Clears bit 0</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLR1</name>
<description>Clears bit 1</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SET01</name>
<description>Sets both bits 0 and 1</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WDT_CNT</name>
<description>Watchdog Counter Count Register</description>
<addressOffset>0x184</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>COUNTER</name>
<description>Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WDT_MATCH</name>
<description>Watchdog Counter Match Register</description>
<addressOffset>0x188</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1000</resetValue>
<resetMask>0xFFFFF</resetMask>
<fields>
<field>
<name>MATCH</name>
<description>Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match).</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IGNORE_BITS</name>
<description>The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings &gt;12 behave like a setting of 12.</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<cluster>
<dim>2</dim>
<dimIncrement>64</dimIncrement>
<name>MCWDT_STRUCT[%s]</name>
<description>Multi-Counter Watchdog Timer</description>
<headerStructName>MCWDT_STRUCT</headerStructName>
<addressOffset>0x00000200</addressOffset>
<register>
<name>MCWDT_CNTLOW</name>
<description>Multi-Counter Watchdog Sub-counters 0/1</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDT_CTR0</name>
<description>Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_CTR1</name>
<description>Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MCWDT_CNTHIGH</name>
<description>Multi-Counter Watchdog Sub-counter 2</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDT_CTR2</name>
<description>Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MCWDT_MATCH</name>
<description>Multi-Counter Watchdog Counter Match Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDT_MATCH0</name>
<description>Match value for sub-counter 0 of this MCWDT</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_MATCH1</name>
<description>Match value for sub-counter 1 of this MCWDT</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MCWDT_CONFIG</name>
<description>Multi-Counter Watchdog Counter Configuration</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F010F0F</resetMask>
<fields>
<field>
<name>WDT_MODE0</name>
<description>Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0).</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOTHING</name>
<description>Do nothing</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INT</name>
<description>Assert WDT_INTx</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET</name>
<description>Assert WDT Reset</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>INT_THEN_RESET</name>
<description>Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDT_CLEAR0</name>
<description>Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1).
0: Free running counter
1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_CASCADE0_1</name>
<description>Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0.
0: Independent counters
1: Cascaded counters</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_MODE1</name>
<description>Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1).</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOTHING</name>
<description>Do nothing</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INT</name>
<description>Assert WDT_INTx</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET</name>
<description>Assert WDT Reset</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>INT_THEN_RESET</name>
<description>Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDT_CLEAR1</name>
<description>Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1).
0: Free running counter
1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_CASCADE1_2</name>
<description>Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters.
0: Independent counters
1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1.</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_MODE2</name>
<description>Watchdog Counter 2 Mode.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NOTHING</name>
<description>Free running counter with no interrupt requests</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INT</name>
<description>Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDT_BITS2</name>
<description>Bit to observe for WDT_INT2:
0: Assert after bit0 of WDT_CTR2 toggles (one int every tick)
..
31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks)</description>
<bitRange>[28:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MCWDT_CTL</name>
<description>Multi-Counter Watchdog Counter Control</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xB0B0B</resetMask>
<fields>
<field>
<name>WDT_ENABLE0</name>
<description>Enable subcounter 0. May take up to 2 LFCLK cycles to take effect.
0: Counter is disabled (not clocked)
1: Counter is enabled (counting up)</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_ENABLED0</name>
<description>Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WDT_RESET0</name>
<description>Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_ENABLE1</name>
<description>Enable subcounter 1. May take up to 2 LFCLK cycles to take effect.
0: Counter is disabled (not clocked)
1: Counter is enabled (counting up)</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_ENABLED1</name>
<description>Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles.</description>
<bitRange>[9:9]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WDT_RESET1</name>
<description>Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_ENABLE2</name>
<description>Enable subcounter 2. May take up to 2 LFCLK cycles to take effect.
0: Counter is disabled (not clocked)
1: Counter is enabled (counting up)</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WDT_ENABLED2</name>
<description>Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles.</description>
<bitRange>[17:17]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WDT_RESET2</name>
<description>Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MCWDT_INTR</name>
<description>Multi-Counter Watchdog Counter Interrupt Register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>MCWDT_INT0</name>
<description>MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MCWDT_INT1</name>
<description>MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MCWDT_INT2</name>
<description>MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MCWDT_INTR_SET</name>
<description>Multi-Counter Watchdog Counter Interrupt Set Register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>MCWDT_INT0</name>
<description>Set interrupt for MCWDT_INT0</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MCWDT_INT1</name>
<description>Set interrupt for MCWDT_INT1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MCWDT_INT2</name>
<description>Set interrupt for MCWDT_INT2</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MCWDT_INTR_MASK</name>
<description>Multi-Counter Watchdog Counter Interrupt Mask Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>MCWDT_INT0</name>
<description>Mask for sub-counter 0</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MCWDT_INT1</name>
<description>Mask for sub-counter 1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MCWDT_INT2</name>
<description>Mask for sub-counter 2</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MCWDT_INTR_MASKED</name>
<description>Multi-Counter Watchdog Counter Interrupt Masked Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>MCWDT_INT0</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MCWDT_INT1</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MCWDT_INT2</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MCWDT_LOCK</name>
<description>Multi-Counter Watchdog Counter Lock Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC0000000</resetMask>
<fields>
<field>
<name>MCWDT_LOCK</name>
<description>Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock.
Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that.</description>
<bitRange>[31:30]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_CHG</name>
<description>No effect</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLR0</name>
<description>Clears bit 0</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLR1</name>
<description>Clears bit 1</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SET01</name>
<description>Sets both bits 0 and 1</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</cluster>
<register>
<dim>16</dim>
<dimIncrement>4</dimIncrement>
<name>CLK_DSI_SELECT[%s]</name>
<description>Clock DSI Select Register</description>
<addressOffset>0x300</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>DSI_MUX</name>
<description>Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH&lt;i&gt; using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DSI_OUT0</name>
<description>DSI0 - dsi_out[0]</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT1</name>
<description>DSI1 - dsi_out[1]</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT2</name>
<description>DSI2 - dsi_out[2]</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT3</name>
<description>DSI3 - dsi_out[3]</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT4</name>
<description>DSI4 - dsi_out[4]</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT5</name>
<description>DSI5 - dsi_out[5]</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT6</name>
<description>DSI6 - dsi_out[6]</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT7</name>
<description>DSI7 - dsi_out[7]</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT8</name>
<description>DSI8 - dsi_out[8]</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT9</name>
<description>DSI9 - dsi_out[9]</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT10</name>
<description>DSI10 - dsi_out[10]</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT11</name>
<description>DSI11 - dsi_out[11]</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT12</name>
<description>DSI12 - dsi_out[12]</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT13</name>
<description>DSI13 - dsi_out[13]</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT14</name>
<description>DSI14 - dsi_out[14]</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_OUT15</name>
<description>DSI15 - dsi_out[15]</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>ILO</name>
<description>ILO - Internal Low-speed Oscillator</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>WCO</name>
<description>WCO - Watch-Crystal Oscillator</description>
<value>17</value>
</enumeratedValue>
<enumeratedValue>
<name>ALTLF</name>
<description>ALTLF - Alternate Low-Frequency Clock</description>
<value>18</value>
</enumeratedValue>
<enumeratedValue>
<name>PILO</name>
<description>PILO - Precision Internal Low-speed Oscillator</description>
<value>19</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>4</dimIncrement>
<name>CLK_PATH_SELECT[%s]</name>
<description>Clock Path Select Register</description>
<addressOffset>0x340</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>PATH_MUX</name>
<description>Selects a source for clock PATH&lt;i&gt;. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>IMO</name>
<description>IMO - Internal R/C Oscillator</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTCLK</name>
<description>EXTCLK - External Clock Pin</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ECO</name>
<description>ECO - External-Crystal Oscillator</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ALTHF</name>
<description>ALTHF - Alternate High-Frequency clock input (product-specific clock)</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_MUX</name>
<description>DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>4</dimIncrement>
<name>CLK_ROOT_SELECT[%s]</name>
<description>Clock Root Select Register</description>
<addressOffset>0x380</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x8000003F</resetMask>
<fields>
<field>
<name>ROOT_MUX</name>
<description>Selects a clock path as the root of HFCLK&lt;k&gt; and for SRSS DSI input &lt;k&gt;. Use CLK_SELECT_PATH[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>PATH0</name>
<description>Select PATH0 (can be configured for FLL)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH1</name>
<description>Select PATH1 (can be configured for PLL0, if available in the product)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH2</name>
<description>Select PATH2 (can be configured for PLL1, if available in the product)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH3</name>
<description>Select PATH3 (can be configured for PLL2, if available in the product)</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH4</name>
<description>Select PATH4 (can be configured for PLL3, if available in the product)</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH5</name>
<description>Select PATH5 (can be configured for PLL4, if available in the product)</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH6</name>
<description>Select PATH6 (can be configured for PLL5, if available in the product)</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH7</name>
<description>Select PATH7 (can be configured for PLL6, if available in the product)</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH8</name>
<description>Select PATH8 (can be configured for PLL7, if available in the product)</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH9</name>
<description>Select PATH9 (can be configured for PLL8, if available in the product)</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH10</name>
<description>Select PATH10 (can be configured for PLL9, if available in the product)</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH11</name>
<description>Select PATH11 (can be configured for PLL10, if available in the product)</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH12</name>
<description>Select PATH12 (can be configured for PLL11, if available in the product)</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH13</name>
<description>Select PATH13 (can be configured for PLL12, if available in the product)</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH14</name>
<description>Select PATH14 (can be configured for PLL13, if available in the product)</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH15</name>
<description>Select PATH15 (can be configured for PLL14, if available in the product)</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROOT_DIV</name>
<description>Selects predivider value for this clock root and DSI input.</description>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_DIV</name>
<description>Transparent mode, feed through selected clock source w/o dividing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV_BY_2</name>
<description>Divide selected clock source by 2</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV_BY_4</name>
<description>Divide selected clock source by 4</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV_BY_8</name>
<description>Divide selected clock source by 8</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENABLE</name>
<description>Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_SELECT</name>
<description>Clock selection register</description>
<addressOffset>0x500</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF03</resetMask>
<fields>
<field>
<name>LFCLK_SEL</name>
<description>Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ILO</name>
<description>ILO - Internal Low-speed Oscillator</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WCO</name>
<description>WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ALTLF</name>
<description>ALTLF - Alternate Low-Frequency Clock. Capability is product-specific</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>PILO</name>
<description>PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PUMP_SEL</name>
<description>Selects clock PATH&lt;k&gt;, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux.</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PUMP_DIV</name>
<description>Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source.</description>
<bitRange>[14:12]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_DIV</name>
<description>Transparent mode, feed through selected clock source w/o dividing.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV_BY_2</name>
<description>Divide selected clock source by 2</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV_BY_4</name>
<description>Divide selected clock source by 4</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV_BY_8</name>
<description>Divide selected clock source by 8</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV_BY_16</name>
<description>Divide selected clock source by 16</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PUMP_ENABLE</name>
<description>Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following:
1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV.
2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0.
3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV.</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_TIMER_CTL</name>
<description>Timer Clock Control Register</description>
<addressOffset>0x504</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x70000</resetValue>
<resetMask>0x80FF0301</resetMask>
<fields>
<field>
<name>TIMER_SEL</name>
<description>Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>IMO</name>
<description>IMO - Internal Main Oscillator</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HF0_DIV</name>
<description>Select the output of the predivider configured by TIMER_HF0_DIV.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMER_HF0_DIV</name>
<description>Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock.</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_DIV</name>
<description>Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV_BY_2</name>
<description>Divide HFCLK0 by 2.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV_BY_4</name>
<description>Divide HFCLK0 by 4.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV_BY_8</name>
<description>Divide HFCLK0 by 8.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMER_DIV</name>
<description>Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE</name>
<description>Enable for TIMERCLK.
0: TIMERCLK is off
1: TIMERCLK is enabled</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_ILO_CONFIG</name>
<description>ILO Configuration</description>
<addressOffset>0x50C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80000000</resetValue>
<resetMask>0x80000001</resetMask>
<fields>
<field>
<name>ILO_BACKUP</name>
<description>If backup domain is present, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.
0: ILO turns off at XRES/BOD event or HIBERNATE entry.
1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE</name>
<description>Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_IMO_CONFIG</name>
<description>IMO Configuration</description>
<addressOffset>0x510</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80000000</resetValue>
<resetMask>0x80000000</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description>Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during DEEPSLEEP, HIBERNATE, and XRES.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_OUTPUT_FAST</name>
<description>Fast Clock Output Select Register</description>
<addressOffset>0x514</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFF0FFF</resetMask>
<fields>
<field>
<name>FAST_SEL0</name>
<description>Select signal for fast clock output #0</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NC</name>
<description>Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ECO</name>
<description>External Crystal Oscillator (ECO)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTCLK</name>
<description>External clock input (EXTCLK)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ALTHF</name>
<description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMERCLK</name>
<description>Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH_SEL0</name>
<description>Selects the clock path chosen by PATH_SEL0 field</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>HFCLK_SEL0</name>
<description>Selects the output of the HFCLK_SEL0 mux</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>SLOW_SEL0</name>
<description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PATH_SEL0</name>
<description>Selects a clock path to use in fast clock output #0 logic. For FLL path, it connects after the bypass mux. For PLL path(s), it connects after the CLK_PLL_DDFT mux.
0: FLL output
1-15: PLL output on path1-path15 (if available)</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HFCLK_SEL0</name>
<description>Selects a HFCLK tree for use in fast clock output #0</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FAST_SEL1</name>
<description>Select signal for fast clock output #1</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NC</name>
<description>Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ECO</name>
<description>External Crystal Oscillator (ECO)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTCLK</name>
<description>External clock input (EXTCLK)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ALTHF</name>
<description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMERCLK</name>
<description>Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>PATH_SEL1</name>
<description>Selects the clock path chosen by PATH_SEL1 field</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>HFCLK_SEL1</name>
<description>Selects the output of the HFCLK_SEL1 mux</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>SLOW_SEL1</name>
<description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PATH_SEL1</name>
<description>Selects a clock path to use in fast clock output #1 logic. For FLL path, it connects after the bypass mux. For PLL path(s), it connects after the CLK_PLL_DDFT mux.
1-15: PLL output on path1-path15 (if available)</description>
<bitRange>[23:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HFCLK_SEL1</name>
<description>Selects a HFCLK tree for use in fast clock output #1 logic</description>
<bitRange>[27:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_OUTPUT_SLOW</name>
<description>Slow Clock Output Select Register</description>
<addressOffset>0x518</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SLOW_SEL0</name>
<description>Select signal for slow clock output #0</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NC</name>
<description>Disabled - output is 0. For power savings, clocks are blocked before entering any muxes.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ILO</name>
<description>Internal Low Speed Oscillator (ILO)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>WCO</name>
<description>Watch-Crystal Oscillator (WCO)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BAK</name>
<description>Root of the Backup domain clock tree (BAK)</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ALTLF</name>
<description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>LFCLK</name>
<description>Root of the low-speed clock tree (LFCLK)</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>IMO</name>
<description>Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>SLPCTRL</name>
<description>Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>PILO</name>
<description>Precision Internal Low Speed Oscillator (PILO)</description>
<value>8</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLOW_SEL1</name>
<description>Select signal for slow clock output #1</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NC</name>
<description>Disabled - output is 0. For power savings, clocks are blocked before entering any muxes.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ILO</name>
<description>Internal Low Speed Oscillator (ILO)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>WCO</name>
<description>Watch-Crystal Oscillator (WCO)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BAK</name>
<description>Root of the Backup domain clock tree (BAK)</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ALTLF</name>
<description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>LFCLK</name>
<description>Root of the low-speed clock tree (LFCLK)</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>IMO</name>
<description>Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>SLPCTRL</name>
<description>Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>PILO</name>
<description>Precision Internal Low Speed Oscillator (PILO)</description>
<value>8</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLK_CAL_CNT1</name>
<description>Clock Calibration Counter 1</description>
<addressOffset>0x51C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80000000</resetValue>
<resetMask>0x80FFFFFF</resetMask>
<fields>
<field>
<name>CAL_COUNTER1</name>
<description>Down-counter clocked on fast DDFT output #0 (see TST_DDFT_FAST_CTL). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1.</description>
<bitRange>[23:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CAL_COUNTER_DONE</name>
<description>Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CLK_CAL_CNT2</name>
<description>Clock Calibration Counter 2</description>
<addressOffset>0x520</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>CAL_COUNTER2</name>
<description>Up-counter clocked on fast DDFT output #1 (see TST_DDFT_FAST_CTL). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER)</description>
<bitRange>[23:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CLK_ECO_CONFIG</name>
<description>ECO Configuration Register</description>
<addressOffset>0x52C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0x80000002</resetMask>
<fields>
<field>
<name>AGC_EN</name>
<description>Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and will grow until it saturates to the supply rail (1.8V nom). WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ECO_EN</name>
<description>Master enable for ECO oscillator.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_ECO_STATUS</name>
<description>ECO Status Register</description>
<addressOffset>0x530</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>ECO_OK</name>
<description>Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ECO_READY</name>
<description>Indicates the ECO internal oscillator circuit has fully stabilized.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CLK_PILO_CONFIG</name>
<description>Precision ILO Configuration Register</description>
<addressOffset>0x53C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xE00003FF</resetMask>
<fields>
<field>
<name>PILO_FFREQ</name>
<description>Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PILO_CLK_EN</name>
<description>Enable the PILO clock output. See PILO_EN field for required sequencing.</description>
<bitRange>[29:29]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PILO_RESET_N</name>
<description>Reset the PILO. See PILO_EN field for required sequencing.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PILO_EN</name>
<description>Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_FLL_CONFIG</name>
<description>FLL Configuration Register</description>
<addressOffset>0x580</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1000000</resetValue>
<resetMask>0x8103FFFF</resetMask>
<fields>
<field>
<name>FLL_MULT</name>
<description>Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref).
Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1)</description>
<bitRange>[17:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FLL_OUTPUT_DIV</name>
<description>Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled.
0: no division
1: divide by 2</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FLL_ENABLE</name>
<description>Master enable for FLL. Do not enable until the reference clock has stabilized.
0: Block is powered off
1: Block is powered on</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_FLL_CONFIG2</name>
<description>FLL Configuration Register 2</description>
<addressOffset>0x584</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20001</resetValue>
<resetMask>0x1FF1FFF</resetMask>
<fields>
<field>
<name>FLL_REF_DIV</name>
<description>Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled.
0: illegal (undefined behavior)
1: divide by 1
...
8191: divide by 8191</description>
<bitRange>[12:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LOCK_TOL</name>
<description>Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value.
0: tolerate error of 1 count value
1: tolerate error of 2 count values
...
511: tolerate error of 512 count values</description>
<bitRange>[24:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_FLL_CONFIG3</name>
<description>FLL Configuration Register 3</description>
<addressOffset>0x588</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2800</resetValue>
<resetMask>0x301FFFFF</resetMask>
<fields>
<field>
<name>FLL_LF_IGAIN</name>
<description>FLL Loop Filter Integral Gain Setting
0: 1/256
1: 1/128
2: 1/64
3: 1/32
4: 1/16
5: 1/8
6: 1/4
7: 1/2
8: 1.0
9: 2.0
10: 4.0
11: 8.0
&gt;=12: illegal</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FLL_LF_PGAIN</name>
<description>FLL Loop Filter Proportional Gain Setting
0: 1/256
1: 1/128
2: 1/64
3: 1/32
4: 1/16
5: 1/8
6: 1/4
7: 1/2
8: 1.0
9: 2.0
10: 4.0
11: 8.0
&gt;=12: illegal</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SETTLING_COUNT</name>
<description>Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case.
0: no settling time
1: wait one reference clock cycle
...
8191: wait 8191 reference clock cycles</description>
<bitRange>[20:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BYPASS_SEL</name>
<description>Bypass mux located just after FLL output.</description>
<bitRange>[29:28]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>AUTO</name>
<description>Automatic using lock indicator. When unlocked, automatically selects FLL reference input (bypass mode). When locked, automatically selects FLL output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTO1</name>
<description>Same as AUTO</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FLL_REF</name>
<description>Select FLL reference input (bypass mode). Ignores lock indicator</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>FLL_OUT</name>
<description>Select FLL output. Ignores lock indicator.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLK_FLL_CONFIG4</name>
<description>FLL Configuration Register 4</description>
<addressOffset>0x58C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xC1FF07FF</resetMask>
<fields>
<field>
<name>CCO_LIMIT</name>
<description>Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CCO_RANGE</name>
<description>Frequency range of CCO</description>
<bitRange>[10:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RANGE0</name>
<description>Target frequency is in range [48, 64) MHz</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE1</name>
<description>Target frequency is in range [64, 85) MHz</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE2</name>
<description>Target frequency is in range [85, 113) MHz</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE3</name>
<description>Target frequency is in range [113, 150) MHz</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE4</name>
<description>Target frequency is in range [150, 200] MHz</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCO_FREQ</name>
<description>CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range.</description>
<bitRange>[24:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CCO_HW_UPDATE_DIS</name>
<description>Disable CCO frequency update by FLL hardware
0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation.
1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CCO_ENABLE</name>
<description>Enable the CCO. It is required to enable the CCO before using the FLL.
0: Block is powered off
1: Block is powered on</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_FLL_STATUS</name>
<description>FLL Status Register</description>
<addressOffset>0x590</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>LOCKED</name>
<description>FLL Lock Indicator</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>UNLOCK_OCCURRED</name>
<description>N/A</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CCO_READY</name>
<description>This indicates that the CCO is internally settled and ready to use.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>15</dim>
<dimIncrement>4</dimIncrement>
<name>CLK_PLL_CONFIG[%s]</name>
<description>PLL Configuration Register</description>
<addressOffset>0x600</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20116</resetValue>
<resetMask>0xB81F1F7F</resetMask>
<fields>
<field>
<name>FEEDBACK_DIV</name>
<description>Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
0-21: illegal (undefined behavior)
22: divide by 22
...
112: divide by 112
&gt;112: illegal (undefined behavior)</description>
<bitRange>[6:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REFERENCE_DIV</name>
<description>Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
0: illegal (undefined behavior)
1: divide by 1
...
20: divide by 20
others: illegal (undefined behavior)</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUTPUT_DIV</name>
<description>Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
0: illegal (undefined behavior)
1: illegal (undefined behavior)
2: divide by 2. Suitable for direct usage as HFCLK source.
...
16: divide by 16. Suitable for direct usage as HFCLK source.
&gt;16: illegal (undefined behavior)</description>
<bitRange>[20:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PLL_LF_MODE</name>
<description>VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled.
0: VCO frequency is [200MHz, 400MHz]
1: VCO frequency is [170MHz, 200MHz)</description>
<bitRange>[27:27]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BYPASS_SEL</name>
<description>Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.</description>
<bitRange>[29:28]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>AUTO</name>
<description>Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTO1</name>
<description>Same as AUTO</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>PLL_REF</name>
<description>Select PLL reference input (bypass mode). Ignores lock indicator</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>PLL_OUT</name>
<description>Select PLL output. Ignores lock indicator.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENABLE</name>
<description>Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1.
Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV)
0: Block is disabled
1: Block is enabled</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>15</dim>
<dimIncrement>4</dimIncrement>
<name>CLK_PLL_STATUS[%s]</name>
<description>PLL Status Register</description>
<addressOffset>0x640</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>LOCKED</name>
<description>PLL Lock Indicator</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>UNLOCK_OCCURRED</name>
<description>This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SRSS_INTR</name>
<description>SRSS Interrupt Register</description>
<addressOffset>0x700</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x23</resetMask>
<fields>
<field>
<name>WDT_MATCH</name>
<description>WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLVD1</name>
<description>Interrupt for low voltage detector HVLVD1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLK_CAL</name>
<description>Clock calibration counter is done</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SRSS_INTR_SET</name>
<description>SRSS Interrupt Set Register</description>
<addressOffset>0x704</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x23</resetMask>
<fields>
<field>
<name>WDT_MATCH</name>
<description>Set interrupt for low voltage detector WDT_MATCH</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLVD1</name>
<description>Set interrupt for low voltage detector HVLVD1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLK_CAL</name>
<description>Set interrupt for clock calibration counter done</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SRSS_INTR_MASK</name>
<description>SRSS Interrupt Mask Register</description>
<addressOffset>0x708</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x23</resetMask>
<fields>
<field>
<name>WDT_MATCH</name>
<description>Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLVD1</name>
<description>Mask for low voltage detector HVLVD1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLK_CAL</name>
<description>Mask for clock calibration done</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SRSS_INTR_MASKED</name>
<description>SRSS Interrupt Masked Register</description>
<addressOffset>0x70C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x23</resetMask>
<fields>
<field>
<name>WDT_MATCH</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>HVLVD1</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CLK_CAL</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SRSS_INTR_CFG</name>
<description>SRSS Interrupt Configuration Register</description>
<addressOffset>0x710</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>HVLVD1_EDGE_SEL</name>
<description>Sets which edge(s) will trigger an IRQ for HVLVD1</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edge</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH</name>
<description>Both rising and falling edges</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RES_CAUSE</name>
<description>Reset Cause Observation Register</description>
<addressOffset>0x800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>RESET_WDT</name>
<description>A basic WatchDog Timer (WDT) reset has occurred since last power cycle.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_ACT_FAULT</name>
<description>Fault logging system requested a reset from its Active logic.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_DPSLP_FAULT</name>
<description>Fault logging system requested a reset from its DeepSleep logic.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_CSV_WCO_LOSS</name>
<description>Clock supervision logic requested a reset due to loss of a watch-crystal clock.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_SOFT</name>
<description>A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_MCWDT0</name>
<description>Multi-Counter Watchdog timer reset #0 has occurred since last power cycle.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_MCWDT1</name>
<description>Multi-Counter Watchdog timer reset #1 has occurred since last power cycle.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_MCWDT2</name>
<description>Multi-Counter Watchdog timer reset #2 has occurred since last power cycle.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_MCWDT3</name>
<description>Multi-Counter Watchdog timer reset #3 has occurred since last power cycle.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RES_CAUSE2</name>
<description>Reset Cause Observation Register 2</description>
<addressOffset>0x804</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RESET_CSV_HF_LOSS</name>
<description>Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK&lt;K&gt;. Unimplemented clock bits return zero.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_CSV_HF_FREQ</name>
<description>Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK&lt;K&gt;. Unimplemented clock bits return zero.</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_TRIM_REF_CTL</name>
<description>Reference Trim Register</description>
<addressOffset>0x7F00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x70F00000</resetValue>
<resetMask>0xF1FF5FFF</resetMask>
<fields>
<field>
<name>ACT_REF_TCTRIM</name>
<description>Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0 -&gt; default setting at POR; not for trimming use
others -&gt; normal trim range</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_REF_ITRIM</name>
<description>Active-Reference current trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0 -&gt; default setting at POR; not for trimming use
others -&gt; normal trim range</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_REF_ABSTRIM</name>
<description>Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0 -&gt; default setting at POR; not for trimming use
others -&gt; normal trim range</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_REF_IBOOST</name>
<description>Active-Reference current boost. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0: normal operation
others: risk mitigation</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DPSLP_REF_TCTRIM</name>
<description>DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
0 -&gt; default setting at POR; not for trimming use
others -&gt; normal trim range</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DPSLP_REF_ABSTRIM</name>
<description>DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.</description>
<bitRange>[24:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DPSLP_REF_ITRIM</name>
<description>DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.</description>
<bitRange>[31:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_TRIM_BODOVP_CTL</name>
<description>BOD/OVP Trim Register</description>
<addressOffset>0x7F04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40D04</resetValue>
<resetMask>0xFDFF7</resetMask>
<fields>
<field>
<name>HVPORBOD_TRIPSEL</name>
<description>HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVPORBOD_OFSTRIM</name>
<description>HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVPORBOD_ITRIM</name>
<description>HVPORBOD current trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.</description>
<bitRange>[9:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LVPORBOD_TRIPSEL</name>
<description>LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.</description>
<bitRange>[12:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LVPORBOD_OFSTRIM</name>
<description>LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.</description>
<bitRange>[16:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LVPORBOD_ITRIM</name>
<description>LVPORBOD current trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.</description>
<bitRange>[19:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_TRIM_CCO_CTL</name>
<description>CCO Trim Register</description>
<addressOffset>0x7F08</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA7000020</resetValue>
<resetMask>0xBF00003F</resetMask>
<fields>
<field>
<name>CCO_RCSTRIM</name>
<description>CCO reference current source trim.</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CCO_STABLE_CNT</name>
<description>Terminal count for the stabilization counter from CCO_ENABLE until stable.</description>
<bitRange>[29:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE_CNT</name>
<description>Enables the automatic stabilization counter.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_TRIM_CCO_CTL2</name>
<description>CCO Trim Register 2</description>
<addressOffset>0x7F0C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x884110</resetValue>
<resetMask>0x1FFFFFF</resetMask>
<fields>
<field>
<name>CCO_FCTRIM1</name>
<description>CCO frequency 1st range calibration</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CCO_FCTRIM2</name>
<description>CCO frequency 2nd range calibration</description>
<bitRange>[9:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CCO_FCTRIM3</name>
<description>CCO frequency 3rd range calibration</description>
<bitRange>[14:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CCO_FCTRIM4</name>
<description>CCO frequency 4th range calibration</description>
<bitRange>[19:15]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CCO_FCTRIM5</name>
<description>CCO frequency 5th range calibration</description>
<bitRange>[24:20]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_TRIM_WAKE_CTL</name>
<description>Wakeup Trim Register</description>
<addressOffset>0x7F30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WAKE_DELAY</name>
<description>Wakeup holdoff. Spec (fastest) wake time is achieve with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_TRIM_LVD_CTL</name>
<description>LVD Trim Register</description>
<addressOffset>0xFF10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0x77</resetMask>
<fields>
<field>
<name>HVLVD1_OFSTRIM</name>
<description>HVLVD1 offset trim</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLVD1_ITRIM</name>
<description>HVLVD1 current trim</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_TRIM_ILO_CTL</name>
<description>ILO Trim Register</description>
<addressOffset>0xFF18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2C</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>ILO_FTRIM</name>
<description>ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency.</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PWR_TRIM_PWRSYS_CTL</name>
<description>Power System Trim Register</description>
<addressOffset>0xFF1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x17</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>ACT_REG_TRIM</name>
<description>Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula:
5'h07: 900mV (nominal)
5'h17: 1100mV (nominal)</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_REG_BOOST</name>
<description>Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting:
2'b00: 50uA
2'b01: 100uA
2'b10: 150uA
2'b11: 200uA
The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip.
50mA chip: 2'b00 (default);
100mA chip: 2'b00 (default);
150mA chip: 50..100mA app =&gt; 2'b00, 150mA app =&gt; 2'b01 (default);
200mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01, 200mA app =&gt; 2'b10 (default);
250mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01, 200..250mA app =&gt; 2'b10 (default);
300mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01, 200..250mA app =&gt; 2'b10, 300mA app =&gt; 2'b11 (default);
This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.</description>
<bitRange>[31:30]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_TRIM_ECO_CTL</name>
<description>ECO Trim Register</description>
<addressOffset>0xFF20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1F0003</resetValue>
<resetMask>0x3F3FF7</resetMask>
<fields>
<field>
<name>WDTRIM</name>
<description>Watch Dog Trim - Delta voltage below stead state level
0x0 - 50mV
0x1 - 75mV
0x2 - 100mV
0x3 - 125mV
0x4 - 150mV
0x5 - 175mV
0x6 - 200mV
0x7 - 225mV</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ATRIM</name>
<description>Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal.
0x0 - 150mV
0x1 - 175mV
0x2 - 200mV
0x3 - 225mV
0x4 - 250mV
0x5 - 275mV
0x6 - 300mV
0x7 - 325mV
0x8 - 350mV
0x9 - 375mV
0xA - 400mV
0xB - 425mV
0xC - 450mV
0xD - 475mV
0xE - 500mV
0xF - 525mV</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FTRIM</name>
<description>Filter Trim - 3rd harmonic oscillation</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RTRIM</name>
<description>Feedback resistor Trim</description>
<bitRange>[11:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>GTRIM</name>
<description>Gain Trim - Startup time</description>
<bitRange>[13:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ITRIM</name>
<description>Current Trim</description>
<bitRange>[21:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_TRIM_PILO_CTL</name>
<description>PILO Trim Register</description>
<addressOffset>0xFF24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x108500F</resetValue>
<resetMask>0x7DFF703F</resetMask>
<fields>
<field>
<name>PILO_CFREQ</name>
<description>Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz.</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PILO_OSC_TRIM</name>
<description>Trim for current in oscillator block.</description>
<bitRange>[14:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PILO_COMP_TRIM</name>
<description>Trim for comparator bias current.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PILO_NBIAS_TRIM</name>
<description>Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier</description>
<bitRange>[19:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PILO_RES_TRIM</name>
<description>Trim for beta-multiplier branch current</description>
<bitRange>[24:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PILO_ISLOPE_TRIM</name>
<description>Trim for beta-multiplier current slope</description>
<bitRange>[27:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PILO_VTDIFF_TRIM</name>
<description>Trim for VT-DIFF output (internal power supply)</description>
<bitRange>[30:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_TRIM_PILO_CTL2</name>
<description>PILO Trim Register 2</description>
<addressOffset>0xFF28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xDA10E0</resetValue>
<resetMask>0xFF1FFF</resetMask>
<fields>
<field>
<name>PILO_VREF_TRIM</name>
<description>Trim for voltage reference</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PILO_IREFBM_TRIM</name>
<description>Trim for beta-multiplier current reference</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PILO_IREF_TRIM</name>
<description>Trim for current reference</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLK_TRIM_PILO_CTL3</name>
<description>PILO Trim Register 3</description>
<addressOffset>0xFF2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4800</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PILO_ENGOPT</name>
<description>Engineering options for PILO circuits
0: Short vdda to vpwr
1: Beta:mult current change
2: Iref generation Ptat current addition
3: Disable current path in secondary Beta:mult startup circuit
4: Double oscillator current
5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block
6: Spare
7: Ptat component increase in Iref
8: vpwr_rc and vpwr_dig_rc shorting testmode
9: Switch b/w psub connection for cascode nfet for vref generation
10: Switch between sub:threshold and deep:sub:threshold stacks in comparator.
15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>BACKUP</name>
<description>SRSS Backup Domain</description>
<baseAddress>0x40270000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTL</name>
<description>Control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF0F3308</resetMask>
<fields>
<field>
<name>WCO_EN</name>
<description>Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes.
After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLK_SEL</name>
<description>Clock select for BAK clock</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>WCO</name>
<description>Watch-crystal oscillator input.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ALTBAK</name>
<description>This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRESCALER</name>
<description>N/A</description>
<bitRange>[13:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WCO_BYPASS</name>
<description>Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1.
0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins.
1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VDDBAK_CTL</name>
<description>Controls the behavior of the switch that generates vddbak from vbackup or vddd.
0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup.
1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage.</description>
<bitRange>[18:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VBACKUP_MEAS</name>
<description>Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled by 40 percent so it is within the supply range of the ADC.</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EN_CHARGE_KEY</name>
<description>When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY.</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RTC_RW</name>
<description>RTC Read Write register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>READ</name>
<description>Read bit
When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running.
Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WRITE</name>
<description>Write bit
Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set.
The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers.
Only user RTC registers that were written to will get copied, others will not be affected.
When the SECONDS field is updated then TICKS will also be reset (WDT is not affected).
When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost.
Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CAL_CTL</name>
<description>Oscillator calibration for absolute frequency</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x8000007F</resetMask>
<fields>
<field>
<name>CALIB_VAL</name>
<description>Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)).
Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field)
Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments.</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CALIB_SIGN</name>
<description>Calibration sign:
0= Negative sign: remove pulses (it takes more clock ticks to count one second)
1= Positive sign: add pulses (it takes less clock ticks to count one second)</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CAL_OUT</name>
<description>Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Status</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x5</resetMask>
<fields>
<field>
<name>RTC_BUSY</name>
<description>pending RTC write</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WCO_OK</name>
<description>Indicates that output has transitioned.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RTC_TIME</name>
<description>Calendar Seconds, Minutes, Hours, Day of Week</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1000000</resetValue>
<resetMask>0x77F7F7F</resetMask>
<fields>
<field>
<name>RTC_SEC</name>
<description>Calendar seconds in BCD, 0-59</description>
<bitRange>[6:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RTC_MIN</name>
<description>Calendar minutes in BCD, 0-59</description>
<bitRange>[14:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RTC_HOUR</name>
<description>Calendar hours in BCD, value depending on 12/24HR mode
0=24HR: [21:16]=0-23
1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12</description>
<bitRange>[21:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTRL_12HR</name>
<description>Select 12/24HR mode: 1=12HR, 0=24HR</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RTC_DAY</name>
<description>Calendar Day of the week in BCD, 1-7
It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
<bitRange>[26:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RTC_DATE</name>
<description>Calendar Day of Month, Month, Year</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x101</resetValue>
<resetMask>0xFF1F3F</resetMask>
<fields>
<field>
<name>RTC_DATE</name>
<description>Calendar Day of the Month in BCD, 1-31
Automatic Leap Year Correction</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RTC_MON</name>
<description>Calendar Month in BCD, 1-12</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RTC_YEAR</name>
<description>Calendar year in BCD, 0-99</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ALM1_TIME</name>
<description>Alarm 1 Seconds, Minute, Hours, Day of Week</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1000000</resetValue>
<resetMask>0x87BFFFFF</resetMask>
<fields>
<field>
<name>ALM_SEC</name>
<description>Alarm seconds in BCD, 0-59</description>
<bitRange>[6:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_SEC_EN</name>
<description>Alarm second enable: 0=ignore, 1=match</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_MIN</name>
<description>Alarm minutes in BCD, 0-59</description>
<bitRange>[14:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_MIN_EN</name>
<description>Alarm minutes enable: 0=ignore, 1=match</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_HOUR</name>
<description>Alarm hours in BCD, value depending on 12/24HR mode
12HR: [5]:0=AM, 1=PM, [4:0]=1-12
24HR: [5:0]=0-23</description>
<bitRange>[21:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_HOUR_EN</name>
<description>Alarm hour enable: 0=ignore, 1=match</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_DAY</name>
<description>Alarm Day of the week in BCD, 1-7
It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
<bitRange>[26:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_DAY_EN</name>
<description>Alarm Day of the Week enable: 0=ignore, 1=match</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ALM1_DATE</name>
<description>Alarm 1 Day of Month, Month</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x101</resetValue>
<resetMask>0x80009FBF</resetMask>
<fields>
<field>
<name>ALM_DATE</name>
<description>Alarm Day of the Month in BCD, 1-31
Leap Year corrected</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_DATE_EN</name>
<description>Alarm Day of the Month enable: 0=ignore, 1=match</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_MON</name>
<description>Alarm Month in BCD, 1-12</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_MON_EN</name>
<description>Alarm Month enable: 0=ignore, 1=match</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_EN</name>
<description>Master enable for alarm 1.
0: Alarm 1 is disabled. Fields for date and time are ignored.
1: Alarm 1 is enabled. If none of the date and time fields are enabled, then this alarm triggers once every second.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ALM2_TIME</name>
<description>Alarm 2 Seconds, Minute, Hours, Day of Week</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1000000</resetValue>
<resetMask>0x87BFFFFF</resetMask>
<fields>
<field>
<name>ALM_SEC</name>
<description>Alarm seconds in BCD, 0-59</description>
<bitRange>[6:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_SEC_EN</name>
<description>Alarm second enable: 0=ignore, 1=match</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_MIN</name>
<description>Alarm minutes in BCD, 0-59</description>
<bitRange>[14:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_MIN_EN</name>
<description>Alarm minutes enable: 0=ignore, 1=match</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_HOUR</name>
<description>Alarm hours in BCD, value depending on 12/24HR mode
12HR: [5]:0=AM, 1=PM, [4:0]=1-12
24HR: [5:0]=0-23</description>
<bitRange>[21:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_HOUR_EN</name>
<description>Alarm hour enable: 0=ignore, 1=match</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_DAY</name>
<description>Alarm Day of the week in BCD, 1-7
It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
<bitRange>[26:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_DAY_EN</name>
<description>Alarm Day of the Week enable: 0=ignore, 1=match</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ALM2_DATE</name>
<description>Alarm 2 Day of Month, Month</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x101</resetValue>
<resetMask>0x80009FBF</resetMask>
<fields>
<field>
<name>ALM_DATE</name>
<description>Alarm Day of the Month in BCD, 1-31
Leap Year corrected</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_DATE_EN</name>
<description>Alarm Day of the Month enable: 0=ignore, 1=match</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_MON</name>
<description>Alarm Month in BCD, 1-12</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_MON_EN</name>
<description>Alarm Month enable: 0=ignore, 1=match</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALM_EN</name>
<description>Master enable for alarm 2.
0: Alarm 2 is disabled. Fields for date and time are ignored.
1: Alarm 2 is enabled. If none of the date and time fields are enabled, then this alarm triggers once every second.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Interrupt request register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>ALARM1</name>
<description>Alarm 1 Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALARM2</name>
<description>Alarm 2 Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CENTURY</name>
<description>Century overflow interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt set request register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>ALARM1</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALARM2</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CENTURY</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt mask register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>ALARM1</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALARM2</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CENTURY</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt masked request register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>ALARM1</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ALARM2</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CENTURY</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OSCCNT</name>
<description>32kHz oscillator counter</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CNT32KHZ</name>
<description>32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written.</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TICKS</name>
<description>128Hz tick counter</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>CNT128HZ</name>
<description>128Hz counter (msb=2Hz)
When SECONDS is written this field will be reset.</description>
<bitRange>[5:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PMIC_CTL</name>
<description>PMIC control register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA0000000</resetValue>
<resetMask>0xE001FF00</resetMask>
<fields>
<field>
<name>UNLOCK</name>
<description>This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>POLARITY</name>
<description>0: Pin input of 0 will set PMIC_EN.
1: Pin input of 1 will set PMIC_EN.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PMIC_EN_OUTEN</name>
<description>Output enable for the output driver in the PMIC_EN pad.
0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present
1: Output pad is enabled for PMIC_EN pin.</description>
<bitRange>[29:29]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PMIC_ALWAYSEN</name>
<description>Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware.
0: Normal operation, PMIC_EN and PMIC_OUTEN work as described
1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled.
Note: This bit is a write-once bit until the next backup reset.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PMIC_EN</name>
<description>Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RESET</name>
<description>Backup reset register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000000</resetMask>
<fields>
<field>
<name>RESET</name>
<description>Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>64</dim>
<dimIncrement>4</dimIncrement>
<name>BREG[%s]</name>
<description>Backup register region</description>
<addressOffset>0x1000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BREG</name>
<description>Backup memory that contains application-specific data. Memory is retained on vbackup supply.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TRIM</name>
<description>Trim Register</description>
<addressOffset>0xFF00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>TRIM</name>
<description>WCO trim</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DW0</name>
<description>Datawire Controller</description>
<headerStructName>DW</headerStructName>
<baseAddress>0x40280000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>4096</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTL</name>
<description>Control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000000</resetMask>
<fields>
<field>
<name>ENABLED</name>
<description>IP enable:
'0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected).
'1': Enabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Status</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x80700000</resetMask>
<fields>
<field>
<name>P</name>
<description>Active channel, user/privileged access control:
'0': user mode.
'1': privileged mode.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NS</name>
<description>Active channel, secure/non-secure access control:
'0': secure.
'1': non-secure.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>B</name>
<description>Active channel, non-bufferable/bufferable access control:
'0': non-bufferable
'1': bufferable.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PC</name>
<description>Active channel protection context.</description>
<bitRange>[7:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CH_IDX</name>
<description>Active channel index.</description>
<bitRange>[12:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PRIO</name>
<description>Active channel priority.</description>
<bitRange>[17:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PREEMPTABLE</name>
<description>Active channel preemptable.</description>
<bitRange>[18:18]</bitRange>
<access>read-only</access>
</field>
<field>
<name>STATE</name>
<description>State of the DW controller.
'0': Default/inactive state.
'1': Loading descriptor.
'2': Loading data element from source location.
'3': Storing data element to destination location.
'4': Update of active control information (e.g. source and destination addresses).
'5': Wait for trigger de-activation.</description>
<bitRange>[22:20]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ACTIVE</name>
<description>Active channel present:
'0': No.
'1': Yes.</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PENDING</name>
<description>Pending channels</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH_PENDING</name>
<description>Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)).</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>STATUS_INTR</name>
<description>System interrupt control</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH</name>
<description>Reflects the INTR.CH bit fields of all channels.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>STATUS_INTR_MASKED</name>
<description>Status of interrupts masked</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH</name>
<description>Reflects the INTR_MASKED.CH bit fields of all channels.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ACT_DESCR_CTL</name>
<description>Active descriptor control</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Copy of DESCR_CTL of the currently active descriptor.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ACT_DESCR_SRC</name>
<description>Active descriptor source</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Copy of DESCR_SRC of the currently active descriptor.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ACT_DESCR_DST</name>
<description>Active descriptor destination</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Copy of DESCR_DST of the currently active descriptor.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ACT_DESCR_X_CTL</name>
<description>Active descriptor X loop control</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Copy of DESCR_X_CTL of the currently active descriptor.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ACT_DESCR_Y_CTL</name>
<description>Active descriptor Y loop control</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Copy of DESCR_Y_CTL of the currently active descriptor.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ACT_DESCR_NEXT_PTR</name>
<description>Active descriptor next pointer</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>ADDR</name>
<description>Copy of DESCR_NEXT_PTR of the currently active descriptor.</description>
<bitRange>[31:2]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ACT_SRC</name>
<description>Active source</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>SRC_ADDR</name>
<description>Current address of source location.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ACT_DST</name>
<description>Active destination</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DST_ADDR</name>
<description>Current address of destination location.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<cluster>
<dim>16</dim>
<dimIncrement>32</dimIncrement>
<name>CH_STRUCT[%s]</name>
<description>DW channel structure</description>
<addressOffset>0x00000800</addressOffset>
<register>
<name>CH_CTL</name>
<description>Channel control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0x800700F7</resetMask>
<fields>
<field>
<name>P</name>
<description>User/privileged access control:
'0': user mode.
'1': privileged mode.
This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NS</name>
<description>Secure/on-secure access control:
'0': secure.
'1': non-secure.
This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>B</name>
<description>Non-bufferable/bufferable access control:
'0': non-bufferable.
'1': bufferable.
This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data.
All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PC</name>
<description>Protection context.
This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
All transactions for this channel uses the PC field for the protection context.</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIO</name>
<description>Channel priority:
'0': highest priority.
'1'
'2'
'3': lowest priority.
Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PREEMPTABLE</name>
<description>Specifies if the channel is preemptable.
'0': Not preemptable.
'1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Channel enable:
'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed).
'1': Enabled.
SW sets this field to '1' to enable a specific channel.
HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CH_STATUS</name>
<description>Channel status</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>INTR_CAUSE</name>
<description>Specifies the source of the interrupt cause:
'0': NO_INTR
'1': COMPLETION
'2': SRC_BUS_ERROR
'3': DST_BUS_ERROR
'4': SRC_MISAL
'5': DST_MISAL
'6': CURR_PTR_NULL
'7': ACTIVE_CH_DISABLED
'8': DESCR_BUS_ERROR
'9'-'15': Not used.
For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').</description>
<bitRange>[3:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CH_IDX</name>
<description>Channel current indices</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>X_IDX</name>
<description>Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor.
Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>Y_IDX</name>
<description>Specifies the Y loop index, with X_COUNT taken from the current descriptor.
Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CH_CURR_PTR</name>
<description>Channel current descriptor pointer</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>ADDR</name>
<description>Address of current descriptor. When this field is '0', there is no valid descriptor.
Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.</description>
<bitRange>[31:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Interrupt</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>CH</name>
<description>Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt set</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>CH</name>
<description>Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt mask</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>CH</name>
<description>Mask for corresponding field in INTR register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt masked</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>CH</name>
<description>Logical and of corresponding INTR and INTR_MASK fields.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral derivedFrom="DW0">
<name>DW1</name>
<baseAddress>0x40281000</baseAddress>
</peripheral>
<peripheral>
<name>EFUSE</name>
<description>EFUSE MXS40 registers</description>
<baseAddress>0x402C0000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>128</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTL</name>
<description>Control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000000</resetMask>
<fields>
<field>
<name>ENABLED</name>
<description>IP enable:
'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.
'1': Enabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMD</name>
<description>Command</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0x800F1F71</resetMask>
<fields>
<field>
<name>BIT_DATA</name>
<description>Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BIT_ADDR</name>
<description>Bit address. This field specifies a bit within a Byte.</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BYTE_ADDR</name>
<description>Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B).</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MACRO_ADDR</name>
<description>Macro address. This field specifies an eFUSE macro.</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>START</name>
<description>FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed.
Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown.
Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous.
Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_DEFAULT</name>
<description>Sequencer Default value</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1D0000</resetValue>
<resetMask>0x7F0000</resetMask>
<fields>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_READ_CTL_0</name>
<description>Sequencer read control 0</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80560001</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_READ_CTL_1</name>
<description>Sequencer read control 1</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x540004</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_READ_CTL_2</name>
<description>Sequencer read control 2</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x560001</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_READ_CTL_3</name>
<description>Sequencer read control 3</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x540003</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_READ_CTL_4</name>
<description>Sequencer read control 4</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80150001</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_READ_CTL_5</name>
<description>Sequencer read control 5</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x310004</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_PROGRAM_CTL_0</name>
<description>Sequencer program control 0</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x200001</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_a</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_PROGRAM_CTL_1</name>
<description>Sequencer program control 1</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x220020</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_a</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_PROGRAM_CTL_2</name>
<description>Sequencer program control 2</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x200001</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_a</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_PROGRAM_CTL_3</name>
<description>Sequencer program control 3</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x310005</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_a</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_PROGRAM_CTL_4</name>
<description>Sequencer program control 4</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80350006</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_a</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_PROGRAM_CTL_5</name>
<description>Sequencer program control 5</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x803D0019</resetValue>
<resetMask>0x807F03FF</resetMask>
<fields>
<field>
<name>CYCLES</name>
<description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_A</name>
<description>Specifies value of eFUSE control signal strobe_a</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_B</name>
<description>Specifies value of eFUSEcontrol signal strobe_b</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_C</name>
<description>Specifies value of eFUSE control signal strobe_c</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_D</name>
<description>Specifies value of eFUSE control signal strobe_d</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_E</name>
<description>Specifies value of eFUSE control signal strobe_e</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_F</name>
<description>Specifies value of eFUSE control signal strobe_f</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STROBE_G</name>
<description>Specifies value of eFUSE control signal strobe_g</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DONE</name>
<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PROFILE</name>
<description>Energy Profiler IP</description>
<baseAddress>0x402D0000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTL</name>
<description>Profile control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000001</resetMask>
<fields>
<field>
<name>WIN_MODE</name>
<description>Specifies the profiling time window mode:
'0': Start / stop mode. The profiling time window is started when a rising edge of the start trigger signal occurs and stopped when a rising edge of the stop trigger signal occurs.
In case both rising edges (of start and stop trigger signals) occur in the same cycle, the profiling time window is stopped.
'1': Enable mode. The profiling time window is active as long as the start 'trigger' signal is active. The stop trigger signal has no effect.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Enables the profiling block:
'0': Disabled.
'1': Enabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Profile status</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>WIN_ACTIVE</name>
<description>Indicates if the profiling time window is active.
'0': Not active.
'1': Active.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CMD</name>
<description>Profile command</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x103</resetMask>
<fields>
<field>
<name>START_TR</name>
<description>Software start trigger for the profiling time window. When written with '1', the profiling time window is started.
Can only be used in start / stop mode (PROFILE_WIN_MODE=0).
Has no effect in enable mode (PROFILE_WIN_MODE=1).</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STOP_TR</name>
<description>Software stop trigger for the profiling time window. When written with '1', the profiling time window is stopped.
Can only be used in start / stop mode (PROFILE_WIN_MODE=0).
Has no effect in enable mode (PROFILE_WIN_MODE=1).</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLR_ALL_CNT</name>
<description>Counter clear. When written with '1', all profiling counter registers are cleared to 0x00.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Profile interrupt</description>
<addressOffset>0x7C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNT_OVFLW</name>
<description>This interrupt cause field is activated (HW sets the field to '1') when an profiling counter overflow (from 0xFFFFFFFF to 0x00000000) is captured. There is one bit per profling counter.
SW writes a '1' to a bit of this field to clear this bit to '0' (writing 0xFFFFFFFF clears all interrupt causes to '0').</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Profile interrupt set</description>
<addressOffset>0x7C4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNT_OVFLW</name>
<description>SW writes a '1' to a bit of this field to set the corresponding bit in the INTR register.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Profile interrupt mask</description>
<addressOffset>0x7C8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNT_OVFLW</name>
<description>Mask bit for corresponding field in the INTR register.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Profile interrupt masked</description>
<addressOffset>0x7CC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNT_OVFLW</name>
<description>Logical and of corresponding INTR and INTR_MASK fields.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<cluster>
<dim>8</dim>
<dimIncrement>16</dimIncrement>
<name>CNT_STRUCT[%s]</name>
<description>Profile counter structure</description>
<addressOffset>0x00000800</addressOffset>
<register>
<name>CTL</name>
<description>Profile counter configuration</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x807F0071</resetMask>
<fields>
<field>
<name>CNT_DURATION</name>
<description>This field specifies if events (edges) or a duration of the monitor signal is counted.
'0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted.
'1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter.
Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REF_CLK_SEL</name>
<description>This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0.</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CLK_TIMER</name>
<description>Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_IMO</name>
<description>IMO - Internal Main Oscillator</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_ECO</name>
<description>ECO - External-Crystal Oscillator</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_LF</name>
<description>Low frequency clock (ILO, WCO or ALTLF).
Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_HF</name>
<description>High frequuency clock ('clk_hfx').</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CLK_PERI</name>
<description>Peripheral clock ('clk_peri').</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD_6</name>
<description>N/A</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD_7</name>
<description>N/A</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MON_SEL</name>
<description>This field specifies the montior input signal to be observed by the profiling counter.
The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details.</description>
<bitRange>[22:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Enables the profiling counter:
'0': Disabled.
'1': Enabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<description>Profile counter value</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNT</name>
<description>This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>HSIOM</name>
<description>High Speed IO Matrix (HSIOM)</description>
<baseAddress>0x40310000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>16384</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<dim>15</dim>
<dimIncrement>16</dimIncrement>
<name>PRT[%s]</name>
<description>HSIOM port registers</description>
<addressOffset>0x00000000</addressOffset>
<register>
<name>PORT_SEL0</name>
<description>Port selection 0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F1F1F1F</resetMask>
<fields>
<field>
<name>IO0_SEL</name>
<description>Selects connection for IO pin 0 route.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>GPIO</name>
<description>GPIO controls 'out'</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GPIO_DSI</name>
<description>GPIO controls 'out', DSI controls 'output enable'</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_DSI</name>
<description>DSI controls 'out' and 'output enable'</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DSI_GPIO</name>
<description>DSI controls 'out', GPIO controls 'output enable'</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>AMUXA</name>
<description>Analog mux bus A</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>AMUXB</name>
<description>Analog mux bus B</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>AMUXA_DSI</name>
<description>Analog mux bus A, DSI control</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>AMUXB_DSI</name>
<description>Analog mux bus B, DSI control</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_0</name>
<description>Active functionality 0</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_1</name>
<description>Active functionality 1</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_2</name>
<description>Active functionality 2</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_3</name>
<description>Active functionality 3</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>DS_0</name>
<description>DeepSleep functionality 0</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>DS_1</name>
<description>DeepSleep functionality 1</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>DS_2</name>
<description>DeepSleep functionality 2</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>DS_3</name>
<description>DeepSleep functionality 3</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_4</name>
<description>Active functionality 4</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_5</name>
<description>Active functionality 5</description>
<value>17</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_6</name>
<description>Active functionality 6</description>
<value>18</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_7</name>
<description>Active functionality 7</description>
<value>19</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_8</name>
<description>Active functionality 8</description>
<value>20</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_9</name>
<description>Active functionality 9</description>
<value>21</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_10</name>
<description>Active functionality 10</description>
<value>22</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_11</name>
<description>Active functionality 11</description>
<value>23</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_12</name>
<description>Active functionality 12</description>
<value>24</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_13</name>
<description>Active functionality 13</description>
<value>25</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_14</name>
<description>Active functionality 14</description>
<value>26</value>
</enumeratedValue>
<enumeratedValue>
<name>ACT_15</name>
<description>Active functionality 15</description>
<value>27</value>
</enumeratedValue>
<enumeratedValue>
<name>DS_4</name>
<description>DeepSleep functionality 4</description>
<value>28</value>
</enumeratedValue>
<enumeratedValue>
<name>DS_5</name>
<description>DeepSleep functionality 5</description>
<value>29</value>
</enumeratedValue>
<enumeratedValue>
<name>DS_6</name>
<description>DeepSleep functionality 6</description>
<value>30</value>
</enumeratedValue>
<enumeratedValue>
<name>DS_7</name>
<description>DeepSleep functionality 7</description>
<value>31</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IO1_SEL</name>
<description>Selects connection for IO pin 1 route.</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IO2_SEL</name>
<description>Selects connection for IO pin 2 route.</description>
<bitRange>[20:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IO3_SEL</name>
<description>Selects connection for IO pin 3 route.</description>
<bitRange>[28:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PORT_SEL1</name>
<description>Port selection 1</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F1F1F1F</resetMask>
<fields>
<field>
<name>IO4_SEL</name>
<description>Selects connection for IO pin 4 route.
See PORT_SEL0 for connection details.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IO5_SEL</name>
<description>Selects connection for IO pin 5 route.</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IO6_SEL</name>
<description>Selects connection for IO pin 6 route.</description>
<bitRange>[20:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IO7_SEL</name>
<description>Selects connection for IO pin 7 route.</description>
<bitRange>[28:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
<register>
<dim>64</dim>
<dimIncrement>4</dimIncrement>
<name>AMUX_SPLIT_CTL[%s]</name>
<description>AMUX splitter cell control</description>
<addressOffset>0x2000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x77</resetMask>
<fields>
<field>
<name>SWITCH_AA_SL</name>
<description>T-switch control for Left AMUXBUSA switch:
'0': switch open.
'1': switch closed.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SWITCH_AA_SR</name>
<description>T-switch control for Right AMUXBUSA switch:
'0': switch open.
'1': switch closed.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SWITCH_AA_S0</name>
<description>T-switch control for AMUXBUSA vssa/ground switch:
'0': switch open.
'1': switch closed.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SWITCH_BB_SL</name>
<description>T-switch control for Left AMUXBUSB switch.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SWITCH_BB_SR</name>
<description>T-switch control for Right AMUXBUSB switch.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SWITCH_BB_S0</name>
<description>T-switch control for AMUXBUSB vssa/ground switch.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIO</name>
<description>GPIO port control/configuration</description>
<baseAddress>0x40320000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<dim>15</dim>
<dimIncrement>128</dimIncrement>
<name>PRT[%s]</name>
<description>GPIO port registers</description>
<addressOffset>0x00000000</addressOffset>
<register>
<name>OUT</name>
<description>Port output data register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>OUT0</name>
<description>IO output data for pin 0
'0': Output state set to '0'
'1': Output state set to '1'</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT1</name>
<description>IO output data for pin 1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT2</name>
<description>IO output data for pin 2</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT3</name>
<description>IO output data for pin 3</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT4</name>
<description>IO output data for pin 4</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT5</name>
<description>IO output data for pin 5</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT6</name>
<description>IO output data for pin 6</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT7</name>
<description>IO output data for pin 7</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OUT_CLR</name>
<description>Port output data set register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>OUT0</name>
<description>IO clear output for pin 0:
'0': Output state not affected.
'1': Output state set to '0'.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT1</name>
<description>IO clear output for pin 1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT2</name>
<description>IO clear output for pin 2</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT3</name>
<description>IO clear output for pin 3</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT4</name>
<description>IO clear output for pin 4</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT5</name>
<description>IO clear output for pin 5</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT6</name>
<description>IO clear output for pin 6</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT7</name>
<description>IO clear output for pin 7</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OUT_SET</name>
<description>Port output data clear register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>OUT0</name>
<description>IO set output for pin 0:
'0': Output state not affected.
'1': Output state set to '1'.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT1</name>
<description>IO set output for pin 1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT2</name>
<description>IO set output for pin 2</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT3</name>
<description>IO set output for pin 3</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT4</name>
<description>IO set output for pin 4</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT5</name>
<description>IO set output for pin 5</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT6</name>
<description>IO set output for pin 6</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT7</name>
<description>IO set output for pin 7</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OUT_INV</name>
<description>Port output data invert register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>OUT0</name>
<description>IO invert output for pin 0:
'0': Output state not affected.
'1': Output state inverted ('0' =&gt; '1', '1' =&gt; '0').</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT1</name>
<description>IO invert output for pin 1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT2</name>
<description>IO invert output for pin 2</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT3</name>
<description>IO invert output for pin 3</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT4</name>
<description>IO invert output for pin 4</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT5</name>
<description>IO invert output for pin 5</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT6</name>
<description>IO invert output for pin 6</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT7</name>
<description>IO invert output for pin 7</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IN</name>
<description>Port input state register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>IN0</name>
<description>IO pin state for pin 0
'0': Low logic level present on pin.
'1': High logic level present on pin.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN1</name>
<description>IO pin state for pin 1</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN2</name>
<description>IO pin state for pin 2</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN3</name>
<description>IO pin state for pin 3</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN4</name>
<description>IO pin state for pin 4</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN5</name>
<description>IO pin state for pin 5</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN6</name>
<description>IO pin state for pin 6</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN7</name>
<description>IO pin state for pin 7</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>FLT_IN</name>
<description>Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Port interrupt status register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF01FF</resetMask>
<fields>
<field>
<name>EDGE0</name>
<description>Edge detect for IO pin 0
'0': No edge was detected on pin.
'1': An edge was detected on pin.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE1</name>
<description>Edge detect for IO pin 1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE2</name>
<description>Edge detect for IO pin 2</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE3</name>
<description>Edge detect for IO pin 3</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE4</name>
<description>Edge detect for IO pin 4</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE5</name>
<description>Edge detect for IO pin 5</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE6</name>
<description>Edge detect for IO pin 6</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE7</name>
<description>Edge detect for IO pin 7</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FLT_EDGE</name>
<description>Edge detected on filtered pin selected by INTR_CFG.FLT_SEL</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IN_IN0</name>
<description>IO pin state for pin 0</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN_IN1</name>
<description>IO pin state for pin 1</description>
<bitRange>[17:17]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN_IN2</name>
<description>IO pin state for pin 2</description>
<bitRange>[18:18]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN_IN3</name>
<description>IO pin state for pin 3</description>
<bitRange>[19:19]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN_IN4</name>
<description>IO pin state for pin 4</description>
<bitRange>[20:20]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN_IN5</name>
<description>IO pin state for pin 5</description>
<bitRange>[21:21]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN_IN6</name>
<description>IO pin state for pin 6</description>
<bitRange>[22:22]</bitRange>
<access>read-only</access>
</field>
<field>
<name>IN_IN7</name>
<description>IO pin state for pin 7</description>
<bitRange>[23:23]</bitRange>
<access>read-only</access>
</field>
<field>
<name>FLT_IN_IN</name>
<description>Filtered pin state for pin selected by INTR_CFG.FLT_SEL</description>
<bitRange>[24:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Port interrupt mask register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>EDGE0</name>
<description>Masks edge interrupt on IO pin 0
'0': Pin interrupt forwarding disabled
'1': Pin interrupt forwarding enabled</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE1</name>
<description>Masks edge interrupt on IO pin 1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE2</name>
<description>Masks edge interrupt on IO pin 2</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE3</name>
<description>Masks edge interrupt on IO pin 3</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE4</name>
<description>Masks edge interrupt on IO pin 4</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE5</name>
<description>Masks edge interrupt on IO pin 5</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE6</name>
<description>Masks edge interrupt on IO pin 6</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE7</name>
<description>Masks edge interrupt on IO pin 7</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FLT_EDGE</name>
<description>Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Port interrupt masked status register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>EDGE0</name>
<description>Edge detected AND masked on IO pin 0
'0': Interrupt was not forwarded to CPU
'1': Interrupt occurred and was forwarded to CPU</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EDGE1</name>
<description>Edge detected and masked on IO pin 1</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EDGE2</name>
<description>Edge detected and masked on IO pin 2</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EDGE3</name>
<description>Edge detected and masked on IO pin 3</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EDGE4</name>
<description>Edge detected and masked on IO pin 4</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EDGE5</name>
<description>Edge detected and masked on IO pin 5</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EDGE6</name>
<description>Edge detected and masked on IO pin 6</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EDGE7</name>
<description>Edge detected and masked on IO pin 7</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>FLT_EDGE</name>
<description>Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Port interrupt set register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>EDGE0</name>
<description>Sets edge detect interrupt for IO pin 0
'0': Interrupt state not affected
'1': Interrupt set</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE1</name>
<description>Sets edge detect interrupt for IO pin 1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE2</name>
<description>Sets edge detect interrupt for IO pin 2</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE3</name>
<description>Sets edge detect interrupt for IO pin 3</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE4</name>
<description>Sets edge detect interrupt for IO pin 4</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE5</name>
<description>Sets edge detect interrupt for IO pin 5</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE6</name>
<description>Sets edge detect interrupt for IO pin 6</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE7</name>
<description>Sets edge detect interrupt for IO pin 7</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FLT_EDGE</name>
<description>Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_CFG</name>
<description>Port interrupt configuration register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FFFFF</resetMask>
<fields>
<field>
<name>EDGE0_SEL</name>
<description>Sets which edge will trigger an IRQ for IO pin 0</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edge</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH</name>
<description>Both rising and falling edges</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EDGE1_SEL</name>
<description>Sets which edge will trigger an IRQ for IO pin 1</description>
<bitRange>[3:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE2_SEL</name>
<description>Sets which edge will trigger an IRQ for IO pin 2</description>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE3_SEL</name>
<description>Sets which edge will trigger an IRQ for IO pin 3</description>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE4_SEL</name>
<description>Sets which edge will trigger an IRQ for IO pin 4</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE5_SEL</name>
<description>Sets which edge will trigger an IRQ for IO pin 5</description>
<bitRange>[11:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE6_SEL</name>
<description>Sets which edge will trigger an IRQ for IO pin 6</description>
<bitRange>[13:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EDGE7_SEL</name>
<description>Sets which edge will trigger an IRQ for IO pin 7</description>
<bitRange>[15:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FLT_EDGE_SEL</name>
<description>Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edge</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH</name>
<description>Both rising and falling edges</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLT_SEL</name>
<description>Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.</description>
<bitRange>[20:18]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CFG</name>
<description>Port configuration register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DRIVE_MODE0</name>
<description>The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode.
Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus.
Note: that peripherals other than GPIO &amp; UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0').
Note: D_OUT, D_OUT_EN are pins of GPIO cell.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>HIGHZ</name>
<description>Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULLUP</name>
<description>Resistive pull up
For GPIO &amp; UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO &amp; UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>PULLDOWN</name>
<description>Resistive pull down
For GPIO &amp; UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO &amp; UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>OD_DRIVESLOW</name>
<description>Open drain, drives low
For GPIO &amp; UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO &amp; UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>OD_DRIVESHIGH</name>
<description>Open drain, drives high
For GPIO &amp; UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO &amp; UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STRONG</name>
<description>Strong D_OUTput buffer
For GPIO &amp; UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO &amp; UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>PULLUP_DOWN</name>
<description>Pull up or pull down
For GPIO &amp; UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT &amp; DSI_DATA_OUT.
For peripherals other than GPIO &amp; UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IN_EN0</name>
<description>Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue.
'0': Input buffer disabled
'1': Input buffer enabled</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_MODE1</name>
<description>The GPIO drive mode for IO pin 1</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IN_EN1</name>
<description>Enables the input buffer for IO pin 1</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_MODE2</name>
<description>The GPIO drive mode for IO pin 2</description>
<bitRange>[10:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IN_EN2</name>
<description>Enables the input buffer for IO pin 2</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_MODE3</name>
<description>The GPIO drive mode for IO pin 3</description>
<bitRange>[14:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IN_EN3</name>
<description>Enables the input buffer for IO pin 3</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_MODE4</name>
<description>The GPIO drive mode for IO pin4</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IN_EN4</name>
<description>Enables the input buffer for IO pin 4</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_MODE5</name>
<description>The GPIO drive mode for IO pin 5</description>
<bitRange>[22:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IN_EN5</name>
<description>Enables the input buffer for IO pin 5</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_MODE6</name>
<description>The GPIO drive mode for IO pin 6</description>
<bitRange>[26:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IN_EN6</name>
<description>Enables the input buffer for IO pin 6</description>
<bitRange>[27:27]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_MODE7</name>
<description>The GPIO drive mode for IO pin 7</description>
<bitRange>[30:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IN_EN7</name>
<description>Enables the input buffer for IO pin 7</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CFG_IN</name>
<description>Port input buffer configuration register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VTRIP_SEL0_0</name>
<description>Configures the pin 0 input buffer mode (trip points and hysteresis)</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CMOS</name>
<description>Input buffer compatible with CMOS and I2C interfaces</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TTL</name>
<description>Input buffer compatible with TTL and MediaLB interfaces</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VTRIP_SEL1_0</name>
<description>Configures the pin 1 input buffer mode (trip points and hysteresis)</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL2_0</name>
<description>Configures the pin 2 input buffer mode (trip points and hysteresis)</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL3_0</name>
<description>Configures the pin 3 input buffer mode (trip points and hysteresis)</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL4_0</name>
<description>Configures the pin 4 input buffer mode (trip points and hysteresis)</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL5_0</name>
<description>Configures the pin 5 input buffer mode (trip points and hysteresis)</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL6_0</name>
<description>Configures the pin 6 input buffer mode (trip points and hysteresis)</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL7_0</name>
<description>Configures the pin 7 input buffer mode (trip points and hysteresis)</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CFG_OUT</name>
<description>Port output buffer configuration register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF00FF</resetMask>
<fields>
<field>
<name>SLOW0</name>
<description>Enables slow slew rate for IO pin 0
'0': Fast slew rate
'1': Slow slew rate</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLOW1</name>
<description>Enables slow slew rate for IO pin 1</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLOW2</name>
<description>Enables slow slew rate for IO pin 2</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLOW3</name>
<description>Enables slow slew rate for IO pin 3</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLOW4</name>
<description>Enables slow slew rate for IO pin 4</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLOW5</name>
<description>Enables slow slew rate for IO pin 5</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLOW6</name>
<description>Enables slow slew rate for IO pin 6</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLOW7</name>
<description>Enables slow slew rate for IO pin 7</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_SEL0</name>
<description>Sets the GPIO drive strength for IO pin 0</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FULL_DRIVE</name>
<description>Full drive strength: GPIO drives current at its max rated spec.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_HALF_DRIVE</name>
<description>1/2 drive strength: GPIO drives current at 1/2 of its max rated spec</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_QUARTER_DRIVE</name>
<description>1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_EIGHTH_DRIVE</name>
<description>1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DRIVE_SEL1</name>
<description>Sets the GPIO drive strength for IO pin 1</description>
<bitRange>[19:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_SEL2</name>
<description>Sets the GPIO drive strength for IO pin 2</description>
<bitRange>[21:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_SEL3</name>
<description>Sets the GPIO drive strength for IO pin 3</description>
<bitRange>[23:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_SEL4</name>
<description>Sets the GPIO drive strength for IO pin 4</description>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_SEL5</name>
<description>Sets the GPIO drive strength for IO pin 5</description>
<bitRange>[27:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_SEL6</name>
<description>Sets the GPIO drive strength for IO pin 6</description>
<bitRange>[29:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DRIVE_SEL7</name>
<description>Sets the GPIO drive strength for IO pin 7</description>
<bitRange>[31:30]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CFG_SIO</name>
<description>Port SIO configuration register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VREG_EN01</name>
<description>The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IBUF_SEL01</name>
<description>N/A</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL01</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREF_SEL01</name>
<description>N/A</description>
<bitRange>[4:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VOH_SEL01</name>
<description>Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):
0: input buffer functions as a CMOS input buffer.
1: input buffer functions as a LVTTL input buffer.
In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -&gt; Trip point=50 percent of vddio
b) VREF_SEL=01, VOH_SEL=000 -&gt; Trip point=Vohref (buffered)
c) VREF_SEL=01, VOH_SEL=[1-7] -&gt; Input buffer functions as CMOS input buffer.
d) VREF_SEL=10/11, VOH_SEL=000 -&gt; Trip_point=Amuxbus_a/b (buffered)
e) VREF_SEL=10/11, VOH_SEL=[1-7] -&gt; Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -&gt; Trip point=40 percent of vddio
b) VREF_SEL=01, VOH_SEL=000 -&gt; Trip point=0.5*Vohref
c) VREF_SEL=01, VOH_SEL=[1-7] -&gt; Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -&gt; Trip_point=0.5*Amuxbus_a/b (buffered)
e) VREF_SEL=10/11, VOH_SEL=[1-7] -&gt; Input buffer functions as LVTTL input buffer.</description>
<bitRange>[7:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREG_EN23</name>
<description>N/A</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IBUF_SEL23</name>
<description>N/A</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL23</name>
<description>N/A</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREF_SEL23</name>
<description>N/A</description>
<bitRange>[12:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VOH_SEL23</name>
<description>N/A</description>
<bitRange>[15:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREG_EN45</name>
<description>N/A</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IBUF_SEL45</name>
<description>N/A</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL45</name>
<description>N/A</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREF_SEL45</name>
<description>N/A</description>
<bitRange>[20:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VOH_SEL45</name>
<description>N/A</description>
<bitRange>[23:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREG_EN67</name>
<description>N/A</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IBUF_SEL67</name>
<description>N/A</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL67</name>
<description>N/A</description>
<bitRange>[26:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREF_SEL67</name>
<description>N/A</description>
<bitRange>[28:27]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VOH_SEL67</name>
<description>N/A</description>
<bitRange>[31:29]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CFG_IN_GPIO5V</name>
<description>Port GPIO5V input buffer configuration register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VTRIP_SEL0_1</name>
<description>Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field.
0: input buffer is not compatible with automative.
1: input buffer is compatible with automative.
Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Input buffer not compatible with automotive (elevated Vil) interfaces.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AUTO</name>
<description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VTRIP_SEL1_1</name>
<description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL2_1</name>
<description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL3_1</name>
<description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL4_1</name>
<description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL5_1</name>
<description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL6_1</name>
<description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VTRIP_SEL7_1</name>
<description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
<register>
<name>INTR_CAUSE0</name>
<description>Interrupt port cause register 0</description>
<addressOffset>0x4000</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PORT_INT</name>
<description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
'0': Port has no pending interrupt
'1': Port has pending interrupt</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_CAUSE1</name>
<description>Interrupt port cause register 1</description>
<addressOffset>0x4004</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PORT_INT</name>
<description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to deternine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
'0': Port has no pending interrupt
'1': Port has pending interrupt</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_CAUSE2</name>
<description>Interrupt port cause register 2</description>
<addressOffset>0x4008</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PORT_INT</name>
<description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to deternine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
'0': Port has no pending interrupt
'1': Port has pending interrupt</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_CAUSE3</name>
<description>Interrupt port cause register 3</description>
<addressOffset>0x400C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PORT_INT</name>
<description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to deternine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
'0': Port has no pending interrupt
'1': Port has pending interrupt</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>VDD_ACTIVE</name>
<description>Extern power supply detection register</description>
<addressOffset>0x4010</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xC000FFFF</resetMask>
<fields>
<field>
<name>VDDIO_ACTIVE</name>
<description>Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result.
'0': Supply is not present
'1': Supply is present
When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation.
For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below:
0: vbackup,
1: vddio_0,
2: vddio_1,
3: vddio_a,
4: vddio_r,
5: vddusb'</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>VDDA_ACTIVE</name>
<description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
<bitRange>[30:30]</bitRange>
<access>read-only</access>
</field>
<field>
<name>VDDD_ACTIVE</name>
<description>This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.)</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>VDD_INTR</name>
<description>Supply detection interrupt register</description>
<addressOffset>0x4014</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC000FFFF</resetMask>
<fields>
<field>
<name>VDDIO_ACTIVE</name>
<description>Supply state change detected.
'0': No change to supply detected
'1': Change to supply detected</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VDDA_ACTIVE</name>
<description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VDDD_ACTIVE</name>
<description>The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>VDD_INTR_MASK</name>
<description>Supply detection interrupt mask register</description>
<addressOffset>0x4018</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC000FFFF</resetMask>
<fields>
<field>
<name>VDDIO_ACTIVE</name>
<description>Masks supply interrupt on VDDIO.
'0': VDDIO interrupt forwarding disabled
'1': VDDIO interrupt forwarding enabled</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VDDA_ACTIVE</name>
<description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VDDD_ACTIVE</name>
<description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>VDD_INTR_MASKED</name>
<description>Supply detection interrupt masked register</description>
<addressOffset>0x401C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xC000FFFF</resetMask>
<fields>
<field>
<name>VDDIO_ACTIVE</name>
<description>Supply transistion detected AND masked
'0': Interrupt was not forwarded to CPU
'1': Interrupt occurred and was forwarded to CPU</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>VDDA_ACTIVE</name>
<description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
<bitRange>[30:30]</bitRange>
<access>read-only</access>
</field>
<field>
<name>VDDD_ACTIVE</name>
<description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>VDD_INTR_SET</name>
<description>Supply detection interrupt set register</description>
<addressOffset>0x4020</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC000FFFF</resetMask>
<fields>
<field>
<name>VDDIO_ACTIVE</name>
<description>Sets supply interrupt.
'0': Interrupt state not affected
'1': Interrupt set</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VDDA_ACTIVE</name>
<description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VDDD_ACTIVE</name>
<description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SMARTIO</name>
<description>Programmable IO configuration</description>
<baseAddress>0x40330000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<dim>10</dim>
<dimIncrement>256</dimIncrement>
<name>PRT[%s]</name>
<description>Programmable IO port registers</description>
<addressOffset>0x00000000</addressOffset>
<register>
<name>CTL</name>
<description>Control register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2001400</resetValue>
<resetMask>0x82001F00</resetMask>
<fields>
<field>
<name>BYPASS</name>
<description>Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed.
'0': No bypass (programmable SMARTIO fabric is exposed).
'1': Bypass (programmable SMARTIOIO fabric is hidden).</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLOCK_SRC</name>
<description>Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:
'0': io_data_in[0]/'1'.
...
'7': io_data_in[7]/'1'.
'8': chip_data[0]/'1'.
...
'15': chip_data[7]/'1'.
'16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'.
'17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'.
'18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality.
'19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements.
'20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption.
'31': asynchronous mode/'1'. Select this when clockless operation is configured.
NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking.</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HLD_OVR</name>
<description>IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO:
'0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr').
'1': The SMARTIO controls the IO cel hold override functionality:
- In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used.
- In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode).</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PIPELINE_EN</name>
<description>Enable for pipeline register:
'0': Disabled (register is bypassed).
'1': Enabled.</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:
'0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated.
If the IP is disabled:
- The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops.
- The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption.
'1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SYNC_CTL</name>
<description>Synchronization control register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>IO_SYNC_EN</name>
<description>Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i.
'0': No synchronization.
'1': Synchronization.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CHIP_SYNC_EN</name>
<description>Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i.
'0': No synchronization.
'1': Synchronization.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>LUT_SEL[%s]</name>
<description>LUT component input selection</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>LUT_TR0_SEL</name>
<description>LUT input signal 'tr0_in' source selection:
'0': Data unit output.
'1': LUT 1 output.
'2': LUT 2 output.
'3': LUT 3 output.
'4': LUT 4 output.
'5': LUT 5 output.
'6': LUT 6 output.
'7': LUT 7 output.
'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7).
'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7).
'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7).
'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7).
'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7).
'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7).
'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7).
'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7).</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LUT_TR1_SEL</name>
<description>LUT input signal 'tr1_in' source selection:
'0': LUT 0 output.
'1': LUT 1 output.
'2': LUT 2 output.
'3': LUT 3 output.
'4': LUT 4 output.
'5': LUT 5 output.
'6': LUT 6 output.
'7': LUT 7 output.
'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7).
'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7).
'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7).
'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7).
'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7).
'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7).
'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7).
'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7).</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LUT_TR2_SEL</name>
<description>LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL.</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>LUT_CTL[%s]</name>
<description>LUT component control register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>LUT</name>
<description>LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg).</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LUT_OPC</name>
<description>LUT opcode specifies the LUT operation:
'0': Combinatoral output, no feedback.
tr_out = LUT[{tr2_in, tr1_in, tr0_in}].
'1': Combinatorial output, feedback.
tr_out = LUT[{lut_reg, tr1_in, tr0_in}].
On clock:
lut_reg &lt;= tr_in2.
'2': Sequential output, no feedback.
temp = LUT[{tr2_in, tr1_in, tr0_in}].
tr_out = lut_reg.
On clock:
lut_reg &lt;= temp.
'3': Register with asynchronous set and reset.
tr_out = lut_reg.
enable = (tr2_in ^ LUT[4]) | LUT[5].
set = enable &amp; (tr1_in ^ LUT[2]) &amp; LUT[3].
clr = enable &amp; (tr0_in ^ LUT[0]) &amp; LUT[1].
Asynchronously (no clock required):
lut_reg &lt;= if (clr) '0' else if (set) '1'</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DU_SEL</name>
<description>Data unit component input selection</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DU_TR0_SEL</name>
<description>Data unit input signal 'tr0_in' source selection:
'0': Constant '0'.
'1': Constant '1'.
'2': Data unit output.
'10-3': LUT 7 - 0 outputs.
Otherwise: Undefined.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DU_TR1_SEL</name>
<description>Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL.</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DU_TR2_SEL</name>
<description>Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL.</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DU_DATA0_SEL</name>
<description>Data unit input data 'data0_in' source selection:
'0': Constant '0'.
'1': chip_data[7:0].
'2': io_data_in[7:0].
'3': DATA.DATA MMIO register field.</description>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DU_DATA1_SEL</name>
<description>Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL.</description>
<bitRange>[29:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DU_CTL</name>
<description>Data unit component control register</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DU_SIZE</name>
<description>Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DU_OPC</name>
<description>Data unit opcode specifies the data unit operation:
'1': INCR
'2': DECR
'3': INCR_WRAP
'4': DECR_WRAP
'5': INCR_DECR
'6': INCR_DECR_WRAP
'7': ROR
'8': SHR
'9': AND_OR
'10': SHR_MAJ3
'11': SHR_EQL.
Otherwise: Undefined.</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description>Data register</description>
<addressOffset>0xF0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data unit input data source.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>LPCOMP</name>
<description>Low Power Comparators</description>
<baseAddress>0x40350000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CONFIG</name>
<description>LPCOMP Configuration Register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC0000000</resetMask>
<fields>
<field>
<name>LPREF_EN</name>
<description>Enable the local reference generator circuit to generate the local Vref and ibias. This bit must be set for DeepSleep or Hibernate operation.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>- 0: IP disabled (put analog in power down, open all switches, all clocks off, leakage power only)
- 1: IP enabled</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>LPCOMP Status Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x10001</resetMask>
<fields>
<field>
<name>OUT0</name>
<description>Current output value of the comparator 0.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>OUT1</name>
<description>Current output value of the comparator 1.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>LPCOMP Interrupt request register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>COMP0</name>
<description>Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>COMP1</name>
<description>Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>LPCOMP Interrupt set register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>COMP0</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>COMP1</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>LPCOMP Interrupt request mask</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>COMP0_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>COMP1_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>LPCOMP Interrupt request masked</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>COMP0_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>COMP1_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CMP0_CTRL</name>
<description>Comparator 0 control Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xCE3</resetMask>
<fields>
<field>
<name>MODE0</name>
<description>Operating mode for the comparator</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Off</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ULP</name>
<description>Ultra lowpower operating mode (uses less power, &lt; 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>LP</name>
<description>Low Power operating mode (uses more power, &lt;10uA @@@ TBD). In this mode the iref from SRSS will be used.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal, full speed power operating mode (uses &lt;150uA). In this mode the iref from SRSS will be used.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYST0</name>
<description>Add 30mV hysteresis to the comparator
0= Disable Hysteresis
1= Enable Hysteresis</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INTTYPE0</name>
<description>Sets which edge will trigger an IRQ</description>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disabled, no interrupts will be detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edge</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH</name>
<description>Both rising and falling edges</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSI_BYPASS0</name>
<description>Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async).
Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_LEVEL0</name>
<description>Synchronous comparator DSI (trigger) output : 0=pulse, 1=level</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMP0_SW</name>
<description>Comparator 0 switch control</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF7</resetMask>
<fields>
<field>
<name>CMP0_IP0</name>
<description>Comparator 0 positive terminal isolation switch to GPIO</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_AP0</name>
<description>Comparator 0 positive terminal switch to amuxbusA</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_BP0</name>
<description>Comparator 0 positive terminal switch to amuxbusB</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_IN0</name>
<description>Comparator 0 negative terminal isolation switch to GPIO</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_AN0</name>
<description>Comparator 0 negative terminal switch to amuxbusA</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_BN0</name>
<description>Comparator 0 negative terminal switch to amuxbusB</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_VN0</name>
<description>Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set)</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMP0_SW_CLEAR</name>
<description>Comparator 0 switch control clear</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF7</resetMask>
<fields>
<field>
<name>CMP0_IP0</name>
<description>see corresponding bit in CMP0_SW</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_AP0</name>
<description>see corresponding bit in CMP0_SW</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_BP0</name>
<description>see corresponding bit in CMP0_SW</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_IN0</name>
<description>see corresponding bit in CMP0_SW</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_AN0</name>
<description>see corresponding bit in CMP0_SW</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_BN0</name>
<description>see corresponding bit in CMP0_SW</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP0_VN0</name>
<description>see corresponding bit in CMP0_SW</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMP1_CTRL</name>
<description>Comparator 1 control Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xCE3</resetMask>
<fields>
<field>
<name>MODE1</name>
<description>Operating mode for the comparator</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Off</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ULP</name>
<description>Ultra lowpower operating mode (uses less power, &lt; 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>LP</name>
<description>Low Power operating mode (uses more power, &lt;10uA @@@ TBD). In this mode the iref from SRSS will be used.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal, full speed power operating mode (uses &lt;150uA). In this mode the iref from SRSS will be used.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYST1</name>
<description>Add 30mV hysteresis to the comparator
0= Disable Hysteresis
1= Enable Hysteresis</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INTTYPE1</name>
<description>Sets which edge will trigger an IRQ</description>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disabled, no interrupts will be detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edge</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH</name>
<description>Both rising and falling edges</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSI_BYPASS1</name>
<description>Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async).
Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_LEVEL1</name>
<description>Synchronous comparator DSI (trigger) output : 0=pulse, 1=level</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMP1_SW</name>
<description>Comparator 1 switch control</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF7</resetMask>
<fields>
<field>
<name>CMP1_IP1</name>
<description>Comparator 1 positive terminal isolation switch to GPIO</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_AP1</name>
<description>Comparator 1 positive terminal switch to amuxbusA</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_BP1</name>
<description>Comparator 1 positive terminal switch to amuxbusB</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_IN1</name>
<description>Comparator 1 negative terminal isolation switch to GPIO</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_AN1</name>
<description>Comparator 1 negative terminal switch to amuxbusA</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_BN1</name>
<description>Comparator 1 negative terminal switch to amuxbusB</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_VN1</name>
<description>Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set)</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMP1_SW_CLEAR</name>
<description>Comparator 1 switch control clear</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF7</resetMask>
<fields>
<field>
<name>CMP1_IP1</name>
<description>see corresponding bit in CMP1_SW</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_AP1</name>
<description>see corresponding bit in CMP1_SW</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_BP1</name>
<description>see corresponding bit in CMP1_SW</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_IN1</name>
<description>see corresponding bit in CMP1_SW</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_AN1</name>
<description>see corresponding bit in CMP1_SW</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_BN1</name>
<description>see corresponding bit in CMP1_SW</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMP1_VN1</name>
<description>see corresponding bit in CMP1_SW</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CSD0</name>
<description>Capsense Controller</description>
<headerStructName>CSD</headerStructName>
<baseAddress>0x40360000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>4096</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CONFIG</name>
<description>Configuration and Control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4000000</resetValue>
<resetMask>0xCF0E1DF1</resetMask>
<fields>
<field>
<name>IREF_SEL</name>
<description>N/A</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>IREF_SRSS</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IREF_PASS</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FILTER_DELAY</name>
<description>Enables the digital filtering on the CSD comparator</description>
<bitRange>[8:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SHIELD_DELAY</name>
<description>Configures the delay between shield clock and sensor clock</description>
<bitRange>[11:10]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Delay line is off; sensor clock = shield clock</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>D5NS</name>
<description>shield clock is delayed by 5ns delay w.r.t sensor clock</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>D10NS</name>
<description>shield clock is delayed by 10ns delay w.r.t sensor clock</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>D20NS</name>
<description>shield clock is delayed by 20ns delay w.r.t sensor clock</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SENSE_EN</name>
<description>Enables the sensor and shield clocks, CSD modulator output and turns on the IDAC compensation current as selected by CSD_IDAC.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FULL_WAVE</name>
<description>N/A</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>HALFWAVE</name>
<description>Half Wave mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FULLWAVE</name>
<description>Full Wave mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MUTUAL_CAP</name>
<description>N/A</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SELFCAP</name>
<description>Self-cap mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MUTUALCAP</name>
<description>Mutual-cap mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSX_DUAL_CNT</name>
<description>N/A</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ONE</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TWO</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSI_COUNT_SEL</name>
<description>N/A</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CSD_RESULT</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADC_RESULT</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSI_SAMPLE_EN</name>
<description>DSI_SAMPLE_EN = 1 -&gt; COUNTER will count the samples generated by DSI
DSI_SAMPLE_EN = 0 -&gt; COUNTER will count the samples generated by CSD modulator</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SAMPLE_SYNC</name>
<description>N/A</description>
<bitRange>[26:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_SENSE_EN</name>
<description>DSI_SENSE_EN = 1-&gt; sensor clock is driven directly by DSI
DSI_SENSE_EN = 0-&gt; sensor clock is driven by PRS/divide-by-2/DIRECT_CLOCK</description>
<bitRange>[27:27]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LP_MODE</name>
<description>N/A</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE</name>
<description>N/A</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPARE</name>
<description>Spare MMIO</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>SPARE</name>
<description>Spare MMIO</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Status Register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xE</resetMask>
<fields>
<field>
<name>CSD_SENSE</name>
<description>Only for Debug/test purpose this internal signal (sensor clock) status can be read by CPU</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>HSCMP_OUT</name>
<description>Only for Debug/test purpose the output status of CSD comparator can be read by CPU</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>C_LT_VREF</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>C_GT_VREF</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CSDCMP_OUT</name>
<description>Only for Debug/test purpose the output status of CSD modulator can be read by CPU</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>STAT_SEQ</name>
<description>Current Sequencer status</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x70007</resetMask>
<fields>
<field>
<name>SEQ_STATE</name>
<description>CSD sequencer state</description>
<bitRange>[2:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ADC_STATE</name>
<description>ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started)</description>
<bitRange>[18:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>STAT_CNTS</name>
<description>Current status counts</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>NUM_CONV</name>
<description>Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles)</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>STAT_HCNT</name>
<description>Current count of the HSCMP counter</description>
<addressOffset>0x8C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CNT</name>
<description>Current value of HSCMP counter</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RESULT_VAL1</name>
<description>Result CSD/CSX accumulation counter value 1</description>
<addressOffset>0xD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>VALUE</name>
<description>Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap &amp; config.csx_dual_cnt) this counter counts when csd_sense is high.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BAD_CONVS</name>
<description>Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window, either because Vref was not crossed at all, or if the Vref was already crossed before the window started. This counter is reset when the sequencer is started and will saturate at 255 when more than 255 conversions are bad.</description>
<bitRange>[23:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RESULT_VAL2</name>
<description>Result CSX accumulation counter value 2</description>
<addressOffset>0xD4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>VALUE</name>
<description>Only used in case of Mutual cap with two counters (CSX = config.mutual_cap &amp; config.csx_dual_cnt), this counter counts when csd_sense is low.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ADC_RES</name>
<description>ADC measurement</description>
<addressOffset>0xE0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xC001FFFF</resetMask>
<fields>
<field>
<name>VIN_CNT</name>
<description>Count to source/sink Cref1 + Cref2 from Vin to Vrefhi.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>HSCMP_POL</name>
<description>Polarity used for IDACB for this last ADC result, 0= source, 1= sink</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ADC_OVERFLOW</name>
<description>This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low.</description>
<bitRange>[30:30]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ADC_ABORT</name>
<description>This flag is set when the ADC sequencer was aborted before tripping HSCMP.</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>CSD Interrupt Request Register</description>
<addressOffset>0xF0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x106</resetMask>
<fields>
<field>
<name>SAMPLE</name>
<description>A normal sample is complete</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT</name>
<description>Coarse initialization complete or Sample initialization complete (the latter is typically ignored)</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADC_RES</name>
<description>ADC Result ready</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>CSD Interrupt set register</description>
<addressOffset>0xF4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x106</resetMask>
<fields>
<field>
<name>SAMPLE</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADC_RES</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>CSD Interrupt mask register</description>
<addressOffset>0xF8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x106</resetMask>
<fields>
<field>
<name>SAMPLE</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADC_RES</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>CSD Interrupt masked register</description>
<addressOffset>0xFC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x106</resetMask>
<fields>
<field>
<name>SAMPLE</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INIT</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ADC_RES</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HSCMP</name>
<description>High Speed Comparator configuration</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000011</resetMask>
<fields>
<field>
<name>HSCMP_EN</name>
<description>High Speed Comparator enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Disable comparator, output is zero</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ON</name>
<description>On, regular operation. Note that CONFIG.LP_MODE determines the power mode level</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSCMP_INVERT</name>
<description>Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AZ_EN</name>
<description>Auto-Zero enable, allow the Sequencer to Auto-Zero this component</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>AMBUF</name>
<description>Reference Generator configuration</description>
<addressOffset>0x184</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>PWR_MODE</name>
<description>Amux buffer power level</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Disable buffer</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NORM</name>
<description>On, normal or low power level depending on CONFIG.LP_MODE.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>HI</name>
<description>On, high or low power level depending on CONFIG.LP_MODE.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>REFGEN</name>
<description>Reference Generator configuration</description>
<addressOffset>0x188</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x9F1F71</resetMask>
<fields>
<field>
<name>REFGEN_EN</name>
<description>Reference Generator Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Disable Reference Generator</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ON</name>
<description>On, regular operation. Note that CONFIG.LP_MODE determines the power mode level</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BYPASS</name>
<description>Bypass selected input reference unbuffered to Vrefhi</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VDDA_EN</name>
<description>Close Vdda switch to top of resistor string (or Vrefhi?)</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RES_EN</name>
<description>Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa)</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>GAIN</name>
<description>Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -&gt; gain=1 (only works if the resistor string is enabled; RES_EN=1)</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREFLO_SEL</name>
<description>Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1)</description>
<bitRange>[20:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREFLO_INT</name>
<description>Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1).</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CSDCMP</name>
<description>CSD Comparator configuration</description>
<addressOffset>0x18C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xB0000331</resetMask>
<fields>
<field>
<name>CSDCMP_EN</name>
<description>CSD Comparator Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Disable comparator, output is zero</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ON</name>
<description>On, regular operation. Note that CONFIG.LP_MODE determines the power mode level</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POLARITY_SEL</name>
<description>Select which IDAC polarity to use to detect CSDCMP triggering</description>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>IDACA_POL</name>
<description>Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IDACB_POL</name>
<description>Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DUAL_POL</name>
<description>Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP_PHASE</name>
<description>Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap).</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FULL</name>
<description>Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PHI1</name>
<description>Comparator is active during Phi1 only. Currently no known use-case.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>PHI2</name>
<description>Comparator is active during Phi2 only. Intended usage: CSD Low EMI.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>PHI1_2</name>
<description>Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP_MODE</name>
<description>Select which signal to output on dsi_sample_out.</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CSD</name>
<description>CSD mode: output the filtered sample signal on dsi_sample_out</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GP</name>
<description>General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FEEDBACK_MODE</name>
<description>This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out.</description>
<bitRange>[29:29]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FLOP</name>
<description>Use feedback from sampling flip-flop (used in most modes).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>COMP</name>
<description>Use feedback from comparator directly (used in single Cmod mutual cap sensing only)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AZ_EN</name>
<description>Auto-Zero enable, allow the Sequencer to Auto-Zero this component</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_RES</name>
<description>Switch Resistance configuration</description>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF00FF</resetMask>
<fields>
<field>
<name>RES_HCAV</name>
<description>Select resistance or low EMI (slow ramp) for the HCAV switch</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Low</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MED</name>
<description>Medium</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>LOWEMI</name>
<description>Low EMI (slow ramp: 3 switches closed by fixed delay line)</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RES_HCAG</name>
<description>Select resistance or low EMI for the corresponding switch</description>
<bitRange>[3:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RES_HCBV</name>
<description>Select resistance or low EMI for the corresponding switch</description>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RES_HCBG</name>
<description>Select resistance or low EMI for the corresponding switch</description>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RES_F1PM</name>
<description>Select resistance for the corresponding switch</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Low</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MED</name>
<description>Medium</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>N/A</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RES_F2PT</name>
<description>Select resistance for the corresponding switch</description>
<bitRange>[19:18]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SENSE_PERIOD</name>
<description>Sense clock period</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC000000</resetValue>
<resetMask>0xFF70FFF</resetMask>
<fields>
<field>
<name>SENSE_DIV</name>
<description>The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) .
Note this is the base divider, clock dithering may change the actual period length.
Note that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be &gt;=3.
In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value.</description>
<bitRange>[11:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LFSR_SIZE</name>
<description>Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set.</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Don't use clock dithering (=spreadspectrum) (LFSR output value is zero)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>6B</name>
<description>6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>7B</name>
<description>7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>9B</name>
<description>9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511)</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>10B</name>
<description>10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023)</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>8B</name>
<description>8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255)</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>12B</name>
<description>12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095)</description>
<value>6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LFSR_SCALE</name>
<description>Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set.
The clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT&lt;&lt;LFSR_SCALE)).
Note that the clock divider including the dithering term must fit in 12 bits, otherwise the result is undefined.</description>
<bitRange>[23:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LFSR_CLEAR</name>
<description>When set, forces the LFSR to it's initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used.
Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SEL_LFSR_MSB</name>
<description>Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled.</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LFSR_BITS</name>
<description>Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period.
Caveat make sure that SENSE_DIV &gt; the maximum absolute range (e.g. for 4B SENSE_DIV &gt; 8), otherwise results are undefined.</description>
<bitRange>[27:26]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>2B</name>
<description>use 2 bits: range = [-2,1]</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>3B</name>
<description>use 3 bits: range = [-4,3]</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>4B</name>
<description>use 4 bits: range = [-8,7]</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>5B</name>
<description>use 5 bits: range = [-16,15] (default)</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SENSE_DUTY</name>
<description>Sense clock duty cycle</description>
<addressOffset>0x204</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xD0FFF</resetMask>
<fields>
<field>
<name>SENSE_WIDTH</name>
<description>Defines the length of the first phase of the sense clock in clk_csd cycles.
A value of 0 disables this feature and the duty cycle of csd_sense will be 50 percent, which is equal to SENSE_WIDTH = (SENSE_DIV+1)/2, or when clock dithering is used that becomes [(SENSE_DIV+1) + (LFSR_OUT &lt;&lt; LSFR_SCALE)]/2. At all times it must be assured that the phases are at least 2 clk_csd cycles (1 for non overlap, if used), if this rule is violated the result is undefined.
Note that this feature is not available when SEL_LFSR_MSB (PRS) is selected.</description>
<bitRange>[11:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SENSE_POL</name>
<description>Polarity of the sense clock
0 = start with low phase (typical for regular negative transfer CSD)
1 = start with high phase</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERLAP_PHI1</name>
<description>NonOverlap or not for Phi1 (csd_sense=0).
0 = Non-overlap for Phi1, the Phi1 signal is csd_sense inverted except that the signal goes low 1 clk_sample before csd_sense goes high. Intended usage: new low EMI CSD/CSX with static GPIO.
1 = 'Overlap' (= not non-overlap) for Phi1, the Phi1 signal is csd_sense inverted. Intended usage: legacy CSD with GPIO switching, the GPIO internal circuit ensures that the switches are non-overlapping.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERLAP_PHI2</name>
<description>Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1).</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_HS_P_SEL</name>
<description>HSCMP Pos input switch Waveform selection</description>
<addressOffset>0x280</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x11111111</resetMask>
<fields>
<field>
<name>SW_HMPM</name>
<description>Set HMPM switch
0: static open
1: static closed</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HMPT</name>
<description>Set corresponding switch</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HMPS</name>
<description>Set corresponding switch</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HMMA</name>
<description>Set corresponding switch</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HMMB</name>
<description>Set corresponding switch</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HMCA</name>
<description>Set corresponding switch</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HMCB</name>
<description>Set corresponding switch</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HMRH</name>
<description>Set corresponding switch</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_HS_N_SEL</name>
<description>HSCMP Neg input switch Waveform selection</description>
<addressOffset>0x284</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x77110000</resetMask>
<fields>
<field>
<name>SW_HCCC</name>
<description>Set corresponding switch</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HCCD</name>
<description>Set corresponding switch</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HCRH</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[26:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HCRL</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[30:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_SHIELD_SEL</name>
<description>Shielding switches Waveform selection</description>
<addressOffset>0x288</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x117777</resetMask>
<fields>
<field>
<name>SW_HCAV</name>
<description>N/A</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HCAG</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HCBV</name>
<description>N/A</description>
<bitRange>[10:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HCBG</name>
<description>Select waveform for corresponding switch, using csd_shield as base</description>
<bitRange>[14:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HCCV</name>
<description>Set corresponding switch</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_HCCG</name>
<description>Set corresponding switch
If the ADC is enabled then this switch is directly controlled by the ADC sequencer.</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_AMUXBUF_SEL</name>
<description>Amuxbuffer switches Waveform selection</description>
<addressOffset>0x290</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x11171110</resetMask>
<fields>
<field>
<name>SW_IRBY</name>
<description>Set corresponding switch</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_IRLB</name>
<description>Set corresponding switch</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_ICA</name>
<description>Set corresponding switch</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_ICB</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_IRLI</name>
<description>Set corresponding switch</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_IRH</name>
<description>Set corresponding switch</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_IRL</name>
<description>Set corresponding switch</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_BYP_SEL</name>
<description>AMUXBUS bypass switches Waveform selection</description>
<addressOffset>0x294</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x111000</resetMask>
<fields>
<field>
<name>SW_BYA</name>
<description>Set corresponding switch</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_BYB</name>
<description>Set corresponding switch</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_CBCC</name>
<description>Set corresponding switch
If the ADC is enabled then this switch is directly controlled by the ADC sequencer.</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_CMP_P_SEL</name>
<description>CSDCMP Pos Switch Waveform selection</description>
<addressOffset>0x2A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1111777</resetMask>
<fields>
<field>
<name>SW_SFPM</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_SFPT</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_SFPS</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[10:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_SFMA</name>
<description>Set corresponding switch</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_SFMB</name>
<description>Set corresponding switch</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_SFCA</name>
<description>Set corresponding switch</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_SFCB</name>
<description>Set corresponding switch</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_CMP_N_SEL</name>
<description>CSDCMP Neg Switch Waveform selection</description>
<addressOffset>0x2A4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x77000000</resetMask>
<fields>
<field>
<name>SW_SCRH</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[26:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_SCRL</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[30:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_REFGEN_SEL</name>
<description>Reference Generator Switch Waveform selection</description>
<addressOffset>0x2A8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x11110011</resetMask>
<fields>
<field>
<name>SW_IAIB</name>
<description>Set corresponding switch</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_IBCB</name>
<description>Set corresponding switch</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_SGMB</name>
<description>Set corresponding switch</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_SGRP</name>
<description>Set corresponding switch</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_SGRE</name>
<description>Set corresponding switch</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_SGR</name>
<description>Set corresponding switch</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_FW_MOD_SEL</name>
<description>Full Wave Cmod Switch Waveform selection</description>
<addressOffset>0x2B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x11170701</resetMask>
<fields>
<field>
<name>SW_F1PM</name>
<description>Set corresponding switch</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_F1MA</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[10:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_F1CA</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_C1CC</name>
<description>Set corresponding switch</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_C1CD</name>
<description>Set corresponding switch</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_C1F1</name>
<description>Set corresponding switch</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_FW_TANK_SEL</name>
<description>Full Wave Csh_tank Switch Waveform selection</description>
<addressOffset>0x2B4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x11177710</resetMask>
<fields>
<field>
<name>SW_F2PT</name>
<description>Set corresponding switch</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_F2MA</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[10:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_F2CA</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[14:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_F2CB</name>
<description>Select waveform for corresponding switch</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_C2CC</name>
<description>Set corresponding switch</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_C2CD</name>
<description>Set corresponding switch</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SW_C2F2</name>
<description>Set corresponding switch</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SW_DSI_SEL</name>
<description>DSI output switch control Waveform selection</description>
<addressOffset>0x2C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DSI_CSH_TANK</name>
<description>Select waveform for dsi_csh_tank output signal
0: static open
1: static closed
2: phi1
3: phi2
4: phi1 &amp; HSCMP
5: phi2 &amp; HSCMP
6: HSCMP // ignores phi1/2
7: !sense // = phi1 but ignores OVERLAP_PHI1
8: phi1_delay // phi1 delayed with shield delay
9: phi2_delay // phi2 delayed with shield delay
10: !phi1
11: !phi2
12: !(phi1 &amp; HSCMP)
13: !(phi2 &amp; HSCMP)
14: !HSCMP // ignores phi1/2
15: sense // = phi2 but ignores OVERLAP_PHI2</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_CMOD</name>
<description>Select waveform for dsi_cmod output signal</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IO_SEL</name>
<description>IO output control Waveform selection</description>
<addressOffset>0x2D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF0FF</resetMask>
<fields>
<field>
<name>CSD_TX_OUT</name>
<description>Select waveform for csd_tx_out output signal</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CSD_TX_OUT_EN</name>
<description>Select waveform for csd_tx_out_en output signal</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CSD_TX_AMUXB_EN</name>
<description>Select waveform for csd_tx_amuxb_en output signal</description>
<bitRange>[15:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CSD_TX_N_OUT</name>
<description>Select waveform for csd_tx_n_out output signal</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CSD_TX_N_OUT_EN</name>
<description>Select waveform for csd_tx_n_out_en output signal</description>
<bitRange>[23:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CSD_TX_N_AMUXA_EN</name>
<description>Select waveform for csd_tx_n_amuxa_en output signal</description>
<bitRange>[27:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_TIME</name>
<description>Sequencer Timing</description>
<addressOffset>0x300</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>AZ_TIME</name>
<description>Define Auto-Zero time in csd_sense cycles -1.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_INIT_CNT</name>
<description>Sequencer Initial conversion and sample counts</description>
<addressOffset>0x310</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONV_CNT</name>
<description>Number of conversion per Initialization sample, if set to 0 the Sample_init state will be skipped.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SEQ_NORM_CNT</name>
<description>Sequencer Normal conversion and sample counts</description>
<addressOffset>0x314</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONV_CNT</name>
<description>Number of conversion per sample, if set to 0 the Sample_norm state will be skipped.
Sample window size = SEQ_NORM_CNT.CONV_CNT * (SENSE_PERIOD.SENSE_DIV+1).
Note for CSDv1 Sample window size = PERIOD</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADC_CTL</name>
<description>ADC Control</description>
<addressOffset>0x320</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x300FF</resetMask>
<fields>
<field>
<name>ADC_TIME</name>
<description>ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&amp;2, or as the aperture to capture the input voltage on Cref1&amp;2</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADC_MODE</name>
<description>Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>No ADC measurement</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VREF_CNT</name>
<description>Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>VREF_BY2_CNT</name>
<description>Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>VIN_CNT</name>
<description>Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SEQ_START</name>
<description>Sequencer start</description>
<addressOffset>0x340</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x31B</resetMask>
<fields>
<field>
<name>START</name>
<description>Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode).</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SEQ_MODE</name>
<description>0 = regular CSD scan + optional ADC
1 = coarse initialization, the Sequencer will go to the INIT_COARSE state.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ABORT</name>
<description>When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_START_EN</name>
<description>When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AZ0_SKIP</name>
<description>When set the AutoZero_0 state will be skipped</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AZ1_SKIP</name>
<description>When set the AutoZero_1 state will be skipped</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IDACA</name>
<description>IDACA Configuration</description>
<addressOffset>0x400</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3EF0FFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>N/A</description>
<bitRange>[6:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>POL_DYN</name>
<description>N/A</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>STATIC</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DYNAMIC</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POLARITY</name>
<description>N/A</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>VSSA_SRC</name>
<description>Normal: sensor switching between Vssio and Cmod. For non-CSD application, IDAC1 will source current.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VDDA_SNK</name>
<description>Inverted: sensor switch between Vddio and Cmod. For non-CSD application, IDAC1 will sink current.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SENSE</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SENSE_INV</name>
<description>N/A</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BAL_MODE</name>
<description>N/A</description>
<bitRange>[11:10]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FULL</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PHI1</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>PHI2</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>PHI1_2</name>
<description>N/A</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEG1_MODE</name>
<description>N/A</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>GP_STATIC</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GP</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CSD_STATIC</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CSD</name>
<description>N/A</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEG2_MODE</name>
<description>N/A</description>
<bitRange>[19:18]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>GP_STATIC</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GP</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CSD_STATIC</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CSD</name>
<description>N/A</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSI_CTRL_EN</name>
<description>N/A</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RANGE</name>
<description>N/A</description>
<bitRange>[23:22]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>IDAC_LO</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IDAC_MED</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>IDAC_HI</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEG1_EN</name>
<description>N/A</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LEG2_EN</name>
<description>N/A</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IDACB</name>
<description>IDACB Configuration</description>
<addressOffset>0x500</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7EF0FFF</resetMask>
<fields>
<field>
<name>VAL</name>
<description>N/A</description>
<bitRange>[6:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>POL_DYN</name>
<description>N/A</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>STATIC</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DYNAMIC</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POLARITY</name>
<description>N/A</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>VSSA_SRC</name>
<description>Normal: sensor switching between Vssio and Cmod. For non-CSD application, IDAC1 will source current.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VDDA_SNK</name>
<description>Inverted: sensor switch between Vddio and Cmod. For non-CSD application, IDAC1 will sink current.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SENSE</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SENSE_INV</name>
<description>N/A</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BAL_MODE</name>
<description>N/A</description>
<bitRange>[11:10]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FULL</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PHI1</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>PHI2</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>PHI1_2</name>
<description>N/A</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEG1_MODE</name>
<description>N/A</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>GP_STATIC</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GP</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CSD_STATIC</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CSD</name>
<description>N/A</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEG2_MODE</name>
<description>N/A</description>
<bitRange>[19:18]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>GP_STATIC</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GP</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CSD_STATIC</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CSD</name>
<description>N/A</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSI_CTRL_EN</name>
<description>N/A</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RANGE</name>
<description>N/A</description>
<bitRange>[23:22]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>IDAC_LO</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IDAC_MED</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>IDAC_HI</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEG1_EN</name>
<description>N/A</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LEG2_EN</name>
<description>N/A</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LEG3_EN</name>
<description>N/A</description>
<bitRange>[26:26]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TCPWM0</name>
<description>Timer/Counter/PWM</description>
<headerStructName>TCPWM</headerStructName>
<baseAddress>0x40380000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<description>TCPWM control register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER_ENABLED</name>
<description>Counter enables for counters 0 up to CNT_NR-1.
'0': counter disabled.
'1': counter enabled.
Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes:
- the associated counter triggers in the CMD register are set to '0'.
- the counter's interrupt cause fields in counter's INTR register.
- the counter's status fields in counter's STATUS register..
- the counter's trigger outputs ('tr_overflow', 'tr_underflow' and 'tr_compare_match').
- the counter's line outputs ('line_out' and 'line_compl_out').
In multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTRL_CLR</name>
<description>TCPWM control clear register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER_ENABLED</name>
<description>Alias of CTRL that only allows disabling of counters. A write access:
'0': Does nothing.
'1': Clears respective COUNTER_ENABLED field.
A read access returns CTRL.COUNTER_ENABLED.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTRL_SET</name>
<description>TCPWM control set register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER_ENABLED</name>
<description>Alias of CTRL that only allows enabling of counters. A write access:
'0': Does nothing.
'1': Sets respective COUNTER_ENABLED field.
A read access returns CTRL.COUNTER_ENABLED.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMD_CAPTURE</name>
<description>TCPWM capture command register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER_CAPTURE</name>
<description>Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMD_RELOAD</name>
<description>TCPWM reload command register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER_RELOAD</name>
<description>Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMD_STOP</name>
<description>TCPWM stop command register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER_STOP</name>
<description>Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMD_START</name>
<description>TCPWM start command register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER_START</name>
<description>Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_CAUSE</name>
<description>TCPWM Counter interrupt cause register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER_INT</name>
<description>Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<cluster>
<dim>24</dim>
<dimIncrement>64</dimIncrement>
<name>CNT[%s]</name>
<description>Timer/Counter/PWM Counter Module</description>
<addressOffset>0x00000100</addressOffset>
<register>
<name>CTRL</name>
<description>Counter control register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x737FF0F</resetMask>
<fields>
<field>
<name>AUTO_RELOAD_CC</name>
<description>Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes.
Timer mode:
'0': never switch.
'1': switch on a compare match event.
PWM, PWM_DT, PWM_PR modes:
'0: never switch.
'1': switch on a terminal count event with an actively pending switch event.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AUTO_RELOAD_PERIOD</name>
<description>Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes.
'0': never switch.
'1': switch on a terminal count event with and actively pending switch event.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PWM_SYNC_KILL</name>
<description>Specifies asynchronous/synchronous kill behavior:
'1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE.
'0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET.
This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PWM_STOP_ON_KILL</name>
<description>Specifies whether the counter stops on a kill events:
'0': kill event does NOT stop counter.
'1': kill event stops counter.
This field has a function in PWM, PWM_DT and PWM_PR modes only.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>GENERIC</name>
<description>Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DIVBY1</name>
<description>Divide by 1 (other-than-PWM_DT mode)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY2</name>
<description>Divide by 2 (other-than-PWM_DT mode)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY4</name>
<description>Divide by 4 (other-than-PWM_DT mode)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY8</name>
<description>Divide by 8 (other-than-PWM_DT mode)</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY16</name>
<description>Divide by 16 (other-than-PWM_DT mode)</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY32</name>
<description>Divide by 32 (other-than-PWM_DT mode)</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY64</name>
<description>Divide by 64 (other-than-PWM_DT mode)</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY128</name>
<description>Divide by 128 (other-than-PWM_DT mode)</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UP_DOWN_MODE</name>
<description>Determines counter direction.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>COUNT_UP</name>
<description>Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNT_DOWN</name>
<description>Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNT_UPDN1</name>
<description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>COUNT_UPDN2</name>
<description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ONE_SHOT</name>
<description>When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>QUADRATURE_MODE</name>
<description>In QUAD mode selects quadrature encoding mode (X1/X2/X4).
In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].</description>
<bitRange>[21:20]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>X1</name>
<description>X1 encoding (QUAD mode)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>X2</name>
<description>X2 encoding (QUAD mode)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>X4</name>
<description>X4 encoding (QUAD mode)</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Counter mode.</description>
<bitRange>[26:24]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>TIMER</name>
<description>Timer mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CAPTURE</name>
<description>Capture mode</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>QUAD</name>
<description>Quadrature encoding mode</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>Pulse width modulation (PWM) mode</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM_DT</name>
<description>PWM with deadtime insertion mode</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM_PR</name>
<description>Pseudo random pulse width modulation</description>
<value>6</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Counter status register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x8000FF01</resetMask>
<fields>
<field>
<name>DOWN</name>
<description>When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>GENERIC</name>
<description>Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.</description>
<bitRange>[15:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RUNNING</name>
<description>When '0', the counter is NOT running. When '1', the counter is running.</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>COUNTER</name>
<description>Counter count register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER</name>
<description>16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CC</name>
<description>Counter compare/capture register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CC</name>
<description>In CAPTURE mode, captures the counter value. In other modes, compared to counter value.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CC_BUFF</name>
<description>Counter buffered compare/capture register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CC</name>
<description>Additional buffer for counter CC register.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PERIOD</name>
<description>Counter period register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PERIOD</name>
<description>Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PERIOD_BUFF</name>
<description>Counter buffered period register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PERIOD</name>
<description>Additional buffer for counter PERIOD register.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TR_CTRL0</name>
<description>Counter trigger control register 0</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFFFFF</resetMask>
<fields>
<field>
<name>CAPTURE_SEL</name>
<description>Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>COUNT_SEL</name>
<description>Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RELOAD_SEL</name>
<description>Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STOP_SEL</name>
<description>Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.</description>
<bitRange>[15:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>START_SEL</name>
<description>Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TR_CTRL1</name>
<description>Counter trigger control register 1</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3FF</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>CAPTURE_EDGE</name>
<description>A capture event will copy the counter value into the CC register.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RISING_EDGE</name>
<description>Rising edge. Any rising edge generates an event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGE</name>
<description>Falling edge. Any falling edge generates an event.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH_EDGES</name>
<description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_EDGE_DET</name>
<description>No edge detection, use trigger as is.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COUNT_EDGE</name>
<description>A counter event will increase or decrease the counter by '1'.</description>
<bitRange>[3:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RISING_EDGE</name>
<description>Rising edge. Any rising edge generates an event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGE</name>
<description>Falling edge. Any falling edge generates an event.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH_EDGES</name>
<description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_EDGE_DET</name>
<description>No edge detection, use trigger as is.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RELOAD_EDGE</name>
<description>A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.</description>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RISING_EDGE</name>
<description>Rising edge. Any rising edge generates an event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGE</name>
<description>Falling edge. Any falling edge generates an event.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH_EDGES</name>
<description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_EDGE_DET</name>
<description>No edge detection, use trigger as is.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOP_EDGE</name>
<description>A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.</description>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RISING_EDGE</name>
<description>Rising edge. Any rising edge generates an event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGE</name>
<description>Falling edge. Any falling edge generates an event.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH_EDGES</name>
<description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_EDGE_DET</name>
<description>No edge detection, use trigger as is.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START_EDGE</name>
<description>A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RISING_EDGE</name>
<description>Rising edge. Any rising edge generates an event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGE</name>
<description>Falling edge. Any falling edge generates an event.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH_EDGES</name>
<description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_EDGE_DET</name>
<description>No edge detection, use trigger as is.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TR_CTRL2</name>
<description>Counter trigger control register 2</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3F</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>CC_MATCH_MODE</name>
<description>Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation.
To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Set to '1'</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Set to '0'</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERT</name>
<description>Invert</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No Change</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVERFLOW_MODE</name>
<description>Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.</description>
<bitRange>[3:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Set to '1'</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Set to '0'</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERT</name>
<description>Invert</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No Change</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UNDERFLOW_MODE</name>
<description>Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.</description>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Set to '1'</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR</name>
<description>Set to '0'</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>INVERT</name>
<description>Invert</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>No Change</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Interrupt request register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>TC</name>
<description>Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CC_MATCH</name>
<description>Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt set request register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>TC</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CC_MATCH</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt mask register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>TC</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CC_MATCH</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt masked request register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>TC</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CC_MATCH</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral derivedFrom="TCPWM0">
<name>TCPWM1</name>
<baseAddress>0x40390000</baseAddress>
</peripheral>
<peripheral>
<name>LCD0</name>
<description>LCD Controller Block</description>
<headerStructName>LCD</headerStructName>
<baseAddress>0x403B0000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ID</name>
<description>ID &amp; Revision</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x1F0F0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ID</name>
<description>the ID of LCD controller peripheral is 0xF0F0</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>REVISION</name>
<description>the version number is 0x0001</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DIVIDER</name>
<description>LCD Divider Register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SUBFR_DIV</name>
<description>Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DEAD_DIV</name>
<description>Length of the dead time period in cycles. When set to zero, no dead time period exists.</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<description>LCD Configuration Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000F7F</resetMask>
<fields>
<field>
<name>LS_EN</name>
<description>Low speed (LS) generator enable
1: enable
0: disable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HS_EN</name>
<description>High speed (HS) generator enable
1: enable
0: disable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LCD_MODE</name>
<description>HS/LS Mode selection</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LS</name>
<description>Select Low Speed (32kHz) Generator (Works in Active, Sleep and DeepSleep power modes).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HS</name>
<description>Select High Speed (system clock) Generator (Works in Active and Sleep power modes only).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TYPE</name>
<description>LCD driving waveform type configuration.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>TYPE_A</name>
<description>Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TYPE_B</name>
<description>Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OP_MODE</name>
<description>Driving mode configuration</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>PWM</name>
<description>PWM Mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CORRELATION</name>
<description>Digital Correlation Mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BIAS</name>
<description>PWM bias selection</description>
<bitRange>[6:5]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>HALF</name>
<description>1/2 Bias</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THIRD</name>
<description>1/3 Bias</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FOURTH</name>
<description>1/4 Bias (not supported by LS generator)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>FIFTH</name>
<description>1/5 Bias (not supported by LS generator)</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>COM_NUM</name>
<description>The number of COM connections minus 2. So:
0: 2 COM's
1: 3 COM's
...
13: 15 COM's
14: 16 COM's
15: undefined</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LS_EN_STAT</name>
<description>LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0.
The following procedure should be followed to disable the LS generator:
1. If LS_EN=0 we are done. Exit the procedure.
2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet.
3. Set LS_EN=0.
4. Wait until LS_EN_STAT=0.</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>DATA0[%s]</name>
<description>LCD Pin Data Registers</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb).</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>DATA1[%s]</name>
<description>LCD Pin Data Registers</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb).</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>DATA2[%s]</name>
<description>LCD Pin Data Registers</description>
<addressOffset>0x300</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb).</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>DATA3[%s]</name>
<description>LCD Pin Data Registers</description>
<addressOffset>0x400</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb).</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>BLE</name>
<description>Bluetooth Low Energy Subsystem</description>
<baseAddress>0x403C0000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>131072</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<name>RCB</name>
<description>Radio Control Bus (RCB) controller</description>
<addressOffset>0x00000000</addressOffset>
<register>
<name>CTRL</name>
<description>RCB control register.</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xF80000</resetValue>
<resetMask>0x80FFFF3E</resetMask>
<fields>
<field>
<name>TX_CLK_EDGE</name>
<description>N/A</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_CLK_EDGE</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_CLK_SRC</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCLK_CONTINUOUS</name>
<description>N/A</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SSEL_POLARITY</name>
<description>N/A</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LEAD</name>
<description>N/A</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LAG</name>
<description>N/A</description>
<bitRange>[11:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIV_ENABLED</name>
<description>N/A</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIV</name>
<description>N/A</description>
<bitRange>[18:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADDR_WIDTH</name>
<description>N/A</description>
<bitRange>[22:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_WIDTH</name>
<description>N/A</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>N/A</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>RCB status register.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>BUS_BUSY</name>
<description>RCB bus is busy. The bus is considered busy ('1') during an ongoing transaction.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TX_CTRL</name>
<description>Transmitter control register.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x21</resetValue>
<resetMask>0x7F</resetMask>
<fields>
<field>
<name>MSB_FIRST</name>
<description>Least significant bit first ('0') or most significant bit first ('1').
This field also affects the Address field
When MSB_FIRST = 1, then [15:0] is data and [(ADDR_WIDTH+15):16] is used for address
When MSB_FIRST = 0, then [15:0] is for data. No address field</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FIFO_RECONFIG</name>
<description>Setting this bit, clears the FIFO and resets the pointer</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_ENTRIES</name>
<description>This field determines the depth of the TX_FIFO. Allowed legal values are 8 and 16 only</description>
<bitRange>[6:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TX_FIFO_CTRL</name>
<description>Transmitter FIFO control register.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1001F</resetMask>
<fields>
<field>
<name>TX_TRIGGER_LEVEL</name>
<description>Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event is generated.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLEAR</name>
<description>When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TX_FIFO_STATUS</name>
<description>Transmitter FIFO status register.</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xF0F801F</resetMask>
<fields>
<field>
<name>USED</name>
<description>Amount of enties in the transmitter FIFO. The value of this field ranges from 0 to 16</description>
<bitRange>[4:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SR_VALID</name>
<description>Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is tranmitted next (when the protocol state machine is not transmitting a data frame).</description>
<bitRange>[15:15]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RD_PTR</name>
<description>FIFO read pointer: FIFO location from which a data frame is read by the hardware.</description>
<bitRange>[19:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WR_PTR</name>
<description>FIFO write pointer: FIFO location at which a new data frame is written.</description>
<bitRange>[27:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TX_FIFO_WR</name>
<description>Transmitter FIFO write register.</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation.
A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'.</description>
<bitRange>[31:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>RX_CTRL</name>
<description>Receiver control register.</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>MSB_FIRST</name>
<description>Least significant bit first ('0') or most significant bit first ('1').
This field also affects the Address field
When MSB_FIRST = 1, then [15:0] is data and [(ADDR_WIDTH+15):16] is used for address
When MSB_FIRST = 0, then [15:0] is for data. No address field</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_CTRL</name>
<description>Receiver FIFO control register.</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1000F</resetMask>
<fields>
<field>
<name>TRIGGER_LEVEL</name>
<description>Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event is generated.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLEAR</name>
<description>When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_STATUS</name>
<description>Receiver FIFO status register.</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xF0F801F</resetMask>
<fields>
<field>
<name>USED</name>
<description>Amount of enties in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR.</description>
<bitRange>[4:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SR_VALID</name>
<description>Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame).</description>
<bitRange>[15:15]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RD_PTR</name>
<description>FIFO read pointer: FIFO location from which a data frame is read.</description>
<bitRange>[19:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WR_PTR</name>
<description>FIFO write pointer: FIFO location at which a new data frame is written by the hardware.</description>
<bitRange>[27:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_RD</name>
<description>Receiver FIFO read register.</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>N/A</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_RD_SILENT</name>
<description>Receiver FIFO read register.</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation.
A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Master interrupt request register.</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x600</resetValue>
<resetMask>0x1F1F01</resetMask>
<fields>
<field>
<name>RCB_DONE</name>
<description>N/A</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_TRIGGER</name>
<description>N/A</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_NOT_FULL</name>
<description>N/A</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_EMPTY</name>
<description>N/A</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_OVERFLOW</name>
<description>N/A</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_UNDERFLOW</name>
<description>Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'.
Only used in FIFO mode.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_TRIGGER</name>
<description>N/A</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_NOT_EMPTY</name>
<description>N/A</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_FULL</name>
<description>N/A</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_OVERFLOW</name>
<description>N/A</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_UNDERFLOW</name>
<description>N/A</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Master interrupt set request register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x600</resetValue>
<resetMask>0x1F1F01</resetMask>
<fields>
<field>
<name>RCB_DONE</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_TRIGGER</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_NOT_FULL</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_EMPTY</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_OVERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_UNDERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_TRIGGER</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_NOT_EMPTY</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_FULL</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_OVERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_UNDERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Master interrupt mask register.</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F1F01</resetMask>
<fields>
<field>
<name>RCB_DONE</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_TRIGGER</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_NOT_FULL</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_EMPTY</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_OVERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_FIFO_UNDERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_TRIGGER</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_NOT_EMPTY</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_FULL</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_OVERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_UNDERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Master interrupt masked request register</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F1F01</resetMask>
<fields>
<field>
<name>RCB_DONE</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_FIFO_TRIGGER</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_FIFO_NOT_FULL</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[9:9]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_FIFO_EMPTY</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[10:10]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_FIFO_OVERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[11:11]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_FIFO_UNDERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[12:12]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_FIFO_TRIGGER</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_FIFO_NOT_EMPTY</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[17:17]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_FIFO_FULL</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[18:18]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_FIFO_OVERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[19:19]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_FIFO_UNDERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[20:20]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<cluster>
<name>RCBLL</name>
<description>Radio Control Bus (RCB) &amp; Link Layer controller</description>
<addressOffset>0x00000100</addressOffset>
<register>
<name>CTRL</name>
<description>RCB LL control register.</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>RCBLL_CTRL</name>
<description>N/A</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RCBLL_CPU_REQ</name>
<description>N/A</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CPU_SINGLE_WRITE</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CPU_SINGLE_READ</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALLOW_CPU_ACCESS_TX_RX</name>
<description>N/A</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE_RADIO_BOD</name>
<description>N/A</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Master interrupt request register.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xD</resetMask>
<fields>
<field>
<name>RCB_LL_DONE</name>
<description>RCB_LL is done and the access is given back to CPU</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SINGLE_WRITE_DONE</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SINGLE_READ_DONE</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Master interrupt set request register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xD</resetMask>
<fields>
<field>
<name>RCB_LL_DONE</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SINGLE_WRITE_DONE</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SINGLE_READ_DONE</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Master interrupt mask register.</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xD</resetMask>
<fields>
<field>
<name>RCB_LL_DONE</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SINGLE_WRITE_DONE</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SINGLE_READ_DONE</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Master interrupt masked request register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xD</resetMask>
<fields>
<field>
<name>RCB_LL_DONE</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SINGLE_WRITE_DONE</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SINGLE_READ_DONE</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RADIO_REG1_ADDR</name>
<description>Address of Register#1 in Radio (MDON)</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1E02</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>REG_ADDR</name>
<description>N/A</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RADIO_REG2_ADDR</name>
<description>Address of Register#2 in Radio (RSSI)</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA03</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>REG_ADDR</name>
<description>N/A</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RADIO_REG3_ADDR</name>
<description>Address of Register#3 in Radio (ACCL)</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x824</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>REG_ADDR</name>
<description>N/A</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RADIO_REG4_ADDR</name>
<description>Address of Register#4 in Radio (ACCH)</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x823</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>REG_ADDR</name>
<description>N/A</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RADIO_REG5_ADDR</name>
<description>Address of Register#5 in Radio (RSSI ENERGY)</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA03</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>REG_ADDR</name>
<description>N/A</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CPU_WRITE_REG</name>
<description>N/A</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADDR</name>
<description>N/A</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WRITE_DATA</name>
<description>N/A</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CPU_READ_REG</name>
<description>N/A</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADDR</name>
<description>N/A</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>READ_DATA</name>
<description>N/A</description>
<bitRange>[31:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</cluster>
</cluster>
<cluster>
<name>BLELL</name>
<description>Bluetooth Low Energy Link Layer</description>
<addressOffset>0x00001000</addressOffset>
<register>
<name>COMMAND_REGISTER</name>
<description>Instruction Register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>COMMAND</name>
<description>N/A</description>
<bitRange>[7:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>EVENT_INTR</name>
<description>Event(Interrupt) status and Clear register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ADV_INTR</name>
<description>Advertiser interrupt. If bit is set to 1, it indicates an event occurred in the advertising procedure. The source of the event needs to be read from the ADV_INTR register.
This bit is cleared, when firmware clears ALL interrupts by writing to the ADV_INTR register.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SCAN_INTR</name>
<description>Scanner interrupt. If bit is set to 1, it indicates an event occurred in the scanning procedure. The source of the event needs to be read from the SCAN_INTR register.
This bit is cleared, when firmware clears ALL interrupts by writing to the SCAN_INTR register.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INIT_INTR</name>
<description>Initiator interrupt. If bit is set to 1, it indicates an event occurred in the initiating procedure. The source of the event needs to be read from the INIT_INTR register.
This bit is cleared, when firmware clears ALL interrupts by writing to the INIT_INTR register.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CONN_INTR</name>
<description>Connection interrupt. If bit is set to 1, it indicates an event occurred in the connection operation. This interrupt is aggregation of interrupts for all the connections. The source of the event for the specific connection, needs to be read from the CONN_INTR register specific to the connection. This bit is cleared, when firmware clears ALL interrupts by writing to the CONN_INTR register.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SM_INTR</name>
<description>Read: Sleep-mode-exit interrupt. This bit is set, when link layer hardware exits from sleep mode.
Write: Clear sleep-mode-exit interrupt. Write to the register with this bit set to 1, clears the interrupt source.
This interrupt is deprecated and should not be used.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSM_INTR</name>
<description>Read: Deep sleep mode exit interrupt. This bit is set, when link layer hardware exits from deep sleep mode.
Write: Clear deep sleep mode exit interrupt. Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENC_INTR</name>
<description>Encryption module interrupt.
This interrupt id deprecated and should not be used</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RSSI_RX_DONE_INTR</name>
<description>RSSI RX done interrupt.</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>EVENT_ENABLE</name>
<description>Event indications enable.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ADV_INT_EN</name>
<description>Advertiser interrupt enable.
1 - enable advertiser procedure to interrupt the firmware.
0 - disable advertiser procedure interrupt to firmware.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCN_INT_EN</name>
<description>Scanner interrupt enable.
1 - enable scan procedure to interrupt the firmware.
0 - disable scan procedure interrupt to firmware.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_INT_EN</name>
<description>Initiator interrupt enable.
1 - enable initiator procedure to interrupt the firmware.
0 - disable initiator procedure interrupt to firmware.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_INT_EN</name>
<description>Connection interrupt enable.
1 - enable connection procedure to interrupt the firmware.
0 - disable connection procedure interrupt to firmware.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SM_INT_EN</name>
<description>Sleep-mode-exit interrupt enable.
1 - enable sleep mode exit event to interrupt the firmware.
0 - disable sleep mode exit interrupt to firmware.
This interrupt is deprecated and should not be used.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSM_INT_EN</name>
<description>Deep Sleep-mode-exit interrupt enable.
1 - enable deep sleep mode exit event to interrupt the firmware.
0 - disable deep sleep mode exit interrupt to firmware.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENC_INT_EN</name>
<description>Encryption module interrupt enable.
1 - Enable encryption module interrupt to firmware.
0 - disable encryption module interrupt to firmware.
This interrupt is deprecated and should not be used</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSSI_RX_DONE_INT_EN</name>
<description>RSSI Rx interrupt enable.
1 - Enable RSSI Rx done interrupt to firmware.
0 - Disable RSSI Rx done interrupt to firmware.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADV_PARAMS</name>
<description>Advertising parameters register.</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xE0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TX_ADDR</name>
<description>Device own address type.
1 - Address type is random.
0 - Address type is public.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_TYPE</name>
<description>The Advertising type is used to determine the packet type that is used for advertising when advertising is enabled.
0x0 - Connectable undirected advertising. (adv_ind)
0x1 - Connectable directed advertising (adv_direct_ind).
0x2 - Discoverable undirected advertising (adv_discover_ind)
0x3 - Non connectable undirected advertising (adv_nonconn_ind).</description>
<bitRange>[2:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_FILT_POLICY</name>
<description>Advertising filter policy. The set of devices that the advertising procedure uses for device filtering is called the White List.
0x0 - Allow scan request from any device, allow connect request from any device.
0x1 - Allow scan request from devices in white list only, allow connect request from any device.
0x2 - Allow scan request from any device, allow connect request from devices in white list only.
0x3 - Allow scan request from devices in white list only, allow connect request from devices in white list only.</description>
<bitRange>[4:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_CHANNEL_MAP</name>
<description>Advertising channel map indicates the advertising channels used for advertising. By setting the bit, corresponding channel is enabled for use. Atleast one channel bit should be set.
7 - enable channel 39.
6 - enable channel 38.
5 - enable channel 37.</description>
<bitRange>[7:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_ADDR</name>
<description>Peer addresses type. This is the Direct_Address_type field programmed, only if ADV_DIRECT_IND type is sent.
1 - Rx addr type is random.
0 - Rx addr type is public</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_SEC_ADDR</name>
<description>Peer secondary addresses type. This is the Direct_Address_type field programmed, only if ADV_DIRECT_IND type is sent. This address type corresponds to the PEER_SERC_ADDR register. Valid only if PRIV_1_2_ADV is set.
1 - Rx secondary addr type is random.
0 - Rx secondary addr type is public</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_LOW_DUTY_CYCLE</name>
<description>This bit field is used to specify to the Controller the Low Duty Cycle connectable directed advertising variant being used.
1 - Low Duty Cycle Connectable Directed Advertising.
0 - High Duty Cycle Connectable Directed Advertising.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INITA_RPA_CHECK</name>
<description>This bit field is used to specify the Advertiser behavior on receiving the same INITA in the connect_req as in the ADV_DIRECT_IND packet it sent. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.
0 - Accept the connect_req packet
1 - Reject the connect_req packet</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_ADDR_PRIV</name>
<description>Device own address type subtype when Address type is random. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.
1 - Random Address type is private.
0 - Random Address type is static.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_RCV_IA_IN_PRIV</name>
<description>Advertiser behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.
1 - Accept packets with peer identity address not in the Resolving list in privacy mode
0 - Reject packets with peer identity address not in the Resolving list in privacy mode</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_RPT_PEER_NRPA_ADDR_IN_PRIV</name>
<description>Advertiser behavior when a peer Non Resolvable Private Address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set. This is applicable when whitelist is disabled.
1 - Only report the packets with peer NRPA address in privacy mode
0 - Respond to packets with peer NRPA address in privacy mode</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RCV_TX_ADDR</name>
<description>Transmit address field of the received packet extracted from the receive packet. This field is used by firmware to report peer_addr_type parameter in the connection complete event.</description>
<bitRange>[15:15]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ADV_INTERVAL_TIMEOUT</name>
<description>Advertising interval register.</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0x7FFF</resetMask>
<fields>
<field>
<name>ADV_INTERVAL</name>
<description>Range: 0x0020 to 0x4000 (For ADV_IND)
0x00A0 to 0x4000 (For ADV_SCAN_IND and NONCONN_IND)
Invalid for ADV_DIRECT_IND
Time = N * 0.625 msec
Time Range: 20 ms to 10.24 sec.
For directed advertising, firmware programs the default value of 1.28 seconds.
In MMMS mode, this register is used as ADV_NI_TIMER when the ADV_NI_VALID is set by firmware</description>
<bitRange>[14:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADV_INTR</name>
<description>Advertising interrupt status and Clear register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FFF</resetMask>
<fields>
<field>
<name>ADV_STRT_INTR</name>
<description>If this bit is set it indicates a new advertising event started after interval expiry.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_CLOSE_INTR</name>
<description>If this bit is set it indicates current advertising event is closed.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_TX_INTR</name>
<description>If this bit is set it indicates ADV packet is transmitted.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_RSP_TX_INTR</name>
<description>If this bit is set it indicates scan response packet transmitted in response to previous scan request packet received.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_REQ_RX_INTR</name>
<description>If this bit is set it indicates scan request packet received.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_REQ_RX_INTR</name>
<description>If this bit is set it indicates connect request packet is received.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLV_CONNECTED</name>
<description>If this bit is set it indicates that connection is created as slave.
Write to the register with this bit set to 1, clears the interrupt source.
Note: On a slave connection creation, the link layer cannot enter deepsleep mode in the same slot . It can enter deepsleep mode only in the subsequent slots.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_TIMEOUT</name>
<description>If this bit is set it indicates that the directed advertising event has timed out after 1.28 seconds. Applicable in adv_direct_ind advertising.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_ON</name>
<description>Advertiser procedure is ON in hardware. Indicates that advertiser procedure is ON in hardware.
1 - ON
0 - OFF</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SLV_CONN_PEER_RPA_UNMCH_INTR</name>
<description>If this bit is set it indicates that connection is created as slave, but the peer device Resolvable Private Address is not resolved/ ID or NRPA are not matched yet. If the address is not resolved prior to connection establishment, the connection will be terminated.
Write to the register with this bit set to 1, clears the interrupt source.
This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_REQ_RX_PEER_RPA_UNMCH_INTR</name>
<description>If this bit is set it indicates scan request packet received, but the peer device Resolvable Private Address is not resolved/ ID or NRPA are not matched yet.
Write to the register with this bit set to 1, clears the interrupt source.
This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_ADDR_MATCH_PRIV_MISMATCH_INTR</name>
<description>If this bit is set it indicates that an Identity address is received from a Scanner and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the Scanner
Write to the register with this bit set to 1, clears the interrupt source.
This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR</name>
<description>If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator
Write to the register with this bit set to 1, clears the interrupt source.
This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADV_NEXT_INSTANT</name>
<description>Advertising next instant.</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ADV_NEXT_INSTANT</name>
<description>Shows the next start of advertising event with reference to the internal reference clock.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SCAN_INTERVAL</name>
<description>Scan Interval Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SCAN_INTERVAL</name>
<description>Scan interval register. Interval between two consecutive scanning events. Firmware sets the scanning interval value to this register before issuing start scan command.
Range: 0x0004 to 0x4000
Default: 0x0010 (10 ms)
Time = N * 0.625 msec
Time Range: 2.5 msec to 10.24 sec.
In MMMS mode, this register is used as SCAN_NI_TIMER when the SCAN_NI_VALID is set by firmware</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SCAN_WINDOW</name>
<description>Scan window Register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SCAN_WINDOW</name>
<description>Duration of scan in a scanning event, which should be less than or equal to scan interval value. Firmware sets the scan window value to this register before issuing start scan command.
Range: 0x0004 to 0x4000
Default: 0x0010 (10 ms)
Time = N * 0.625 msec
Time Range: 2.5 msec to 10.24 sec.
(To prevent ADV RX - SCAN REQ TX - SCAN RSP RX spilling over across the scan window, when not in continuous scan, the scan window must be 2 slots less that the scan interval.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SCAN_PARAM</name>
<description>Scanning parameters register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>TX_ADDR</name>
<description>Device's own address type.
1 - addr type is random.
0 - addr type is public.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_TYPE</name>
<description>0x00 - passive scanning.(default)
0x01 - active scanning.
0x10 - RFU
0x11 - RFU</description>
<bitRange>[2:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_FILT_POLICY</name>
<description>The scanner filter policy determines how the scanner processes advertising packets.
0x00 - Accept advertising packets from any device.
0x01 - Accept advertising packets from only devices in the whitelist.
In the above 2 policies, the directed advertising packets which are not addressed to this device are ignored.
0x10 - Accept all undirected advertising packets and directed advertising packet addressed to this device.
0x11 - Accept undirected advertising packets from devices in the whitelist and directed advertising packet addressed to this device
In the above 2 policies, the directed advertising packets where the initiator address is a resolvable private address are accepted. The above 2 policies are extended scanner filter policies.</description>
<bitRange>[4:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DUP_FILT_EN</name>
<description>Filter duplicate packets.
1- Duplicate filtering enabled.
0- Duplicate filtering not enabled.
This field is derived from the LE_set_scan_enable command.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DUP_FILT_CHK_ADV_DIR</name>
<description>This bit field is used to specify the Scanner duplicate filter behavior for ADV_DIRECT_IND packet when duplicate DUP_FILT_EN is set. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.
0 - Do not filter ADV_DIRECT_IND duplicate packets.
1 - Filter ADV_DIRECT_IND duplicate packets</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_RSP_ADVA_CHECK</name>
<description>This bit field is used to specify the Scanner behavior with respect to ADVA while receiving a SCAN_RSP packet. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.
0 - The ADVA in SCAN_RSP packets are not verified
1 - The ADVA in SCAN_RSP packets are verified against ADVA received in ADV packet . If it fails, then abort the packet.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_RCV_IA_IN_PRIV</name>
<description>Scanner behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.
1 - Accept packets with peer identity address not in the Resolving list in privacy mode
0 - Reject packets with peer identity address not in the Resolving list in privacy mode</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV</name>
<description>Scanner behavior when a peer Non Resolvable Private Address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. This is applicable when whitelist is disabled.
1 - Only report packets with peer NRPA address in privacy mode
0 - Respond packets with peer NRPA address in privacy mode</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SCAN_INTR</name>
<description>Scan interrupt status and Clear register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7FF</resetMask>
<fields>
<field>
<name>SCAN_STRT_INTR</name>
<description>If this bit is set it indicates scan window is opened.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_CLOSE_INTR</name>
<description>If this bit is set it indicates scan window is closed.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_TX_INTR</name>
<description>If this bit is set it indicates scan request packet is transmitted.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_RX_INTR</name>
<description>If this bit is set it indicates ADV packet received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO.
Write to the register with this bit set to 1, clears the interrupt source.
This interrupt is generated while active/passive scanning upon receiving adv packets.
Note: Any ADV RX interrupt received after issuing SCAN_STOP command must be ignored and the ADVCH FIFO flushed.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_RSP_RX_INTR</name>
<description>If this bit is set it indicates SCAN_RSP packet is received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO.
Write to the register with this bit set to 1, clears the interrupt source.
NOTE: This interrupt is generated while active scanning upon receiving scan response packet.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_RX_PEER_RPA_UNMCH_INTR</name>
<description>If this bit is set it indicates ADV packet received but the peer device Address is not match yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.
Write to the register with this bit set to 1, clears the interrupt source.
This interrupt is generated while active/passive scanning upon receiving adv packets.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_RX_SELF_RPA_UNMCH_INTR</name>
<description>If this bit is set it indicates ADV_DIRECT packet received but the self device Resolvable Private Address is not resolved yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.
Write to the register with this bit set to 1, clears the interrupt source.
This interrupt is generated while active/passive scanning upon receiving adv_direct packets.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCANA_TX_ADDR_NOT_SET_INTR</name>
<description>If this bit is set it indicates that a valid ScanA RPA to be transmitted in SCAN_REQ packet in response to an ADV packet is not present in the resolving list
Write to the register with this bit set to 1, clears the interrupt source.
This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_ON</name>
<description>Scan procedure status.
1 - scan procedure is active.
0 - scan procedure is not active.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PEER_ADDR_MATCH_PRIV_MISMATCH_INTR</name>
<description>If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator
Write to the register with this bit set to 1, clears the interrupt source.
This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SELF_ADDR_MATCH_PRIV_MISMATCH_INTR</name>
<description>If this bit is set it indicates that the self Identity address is received from an initiator and matches, but self IRK is set and hence a corresponding RPA is expected from the initiator
Write to the register with this bit set to 1, clears the interrupt source.
This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SCAN_NEXT_INSTANT</name>
<description>Advertising next instant.</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>NEXT_SCAN_INSTANT</name>
<description>Shows the instant with respect to internal reference clock of resolution 625 us at which next scanning event begins.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INIT_INTERVAL</name>
<description>Initiator Interval Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>INIT_SCAN_INTERVAL</name>
<description>Initiator interval register. Firmware sets the initiator's scanning interval value to this regis-ter before issuing create connection command. Interval between two consecutive scanning events.
Range: 0x0004 to 0x4000
Time = N * 0.625 msec
Time Range: 2.5 msec to 10.24 sec.
In MMMS mode, this register is used as INIT_NI_TIMER when the INIT_NI_VALID is set by firmware</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INIT_WINDOW</name>
<description>Initiator window Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>INIT_SCAN_WINDOW</name>
<description>Duration of scan in a scanning event, which should be less than or equal to scan interval value. Firmware sets the scan window value to this register before issuing create connection command.
Range: 0x0004 to 0x4000
Time = N * 0.625 msec
Time Range: 2.5 msec to 10.24 sec.
In MMMS mode, this register is used as INIT_NI_TIMER when the INIT_NI_VALID is set by firmware</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INIT_PARAM</name>
<description>Initiator parameters register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1B</resetMask>
<fields>
<field>
<name>TX_ADDR</name>
<description>Device' own address type.
1 - addr type is random.
0 - addr type is public.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_ADDR__RX_TX_ADDR</name>
<description>Peer address type.
The rx_addr field is updated by the receiver with the address type of the received connectable advertising packet.
1 - addr type is random.
0 - addr type is public.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_FILT_POLICY</name>
<description>The Initiator_Filter_Policy is used to determine whether the White List is used or not.
0 - White list is not used to determine which advertiser to connect to. Instead the Peer_Address_Type and Peer Address fields are used to specify the address type and address of the advertising device to connect to.
1 - White list is used to determine the advertising device to connect to.
Peer_Address_Type and Peer_Address fields are ignored when whitelist is used.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_RCV_IA_IN_PRIV</name>
<description>Init behavior when a peer Identity address is received in privacy mode. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.
1 - Accept packets with peer identity address not in the Resolving list in privacy mode
0 - Reject packets with peer identity address not in the Resolving list in privacy mode &amp; HW_RSLV_LIST_FULL is not set</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INIT_INTR</name>
<description>Scan interrupt status and Clear register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F7</resetMask>
<fields>
<field>
<name>INIT_INTERVAL_EXPIRE_INTR</name>
<description>If this bit is set it indicates initiator scan window has started.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_CLOSE_WINDOW_INR</name>
<description>If this bit is set it indicates initiator scan window has finished.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_TX_START_INTR</name>
<description>If this bit is set it indicates initiator packet (CONREQ) transmission has started.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MASTER_CONN_CREATED</name>
<description>If this bit is set it indicates connection is created as master.
Write to the register with this bit set to 1, clears the interrupt source.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_RX_SELF_ADDR_UNMCH_INTR</name>
<description>If this bit is set it indicates ADV_DIRECT packet received but the self device Resolvable Private Address is not resolved yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.
Write to the register with this bit set to 1, clears the interrupt source.
This interrupt is generated while active/passive scanning upon receiving adv packets.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_RX_PEER_ADDR_UNMCH_INTR</name>
<description>If this bit is set it indicates ADV packet received but the peer device Address is not matched yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.
Write to the register with this bit set to 1, clears the interrupt source.
This interrupt is generated while active/passive scanning upon receiving adv packets.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INITA_TX_ADDR_NOT_SET_INTR</name>
<description>If this bit is set it indicates that a valid INITA RPA to be transmitted in CONN_REQ packet in response to an ADV packet is not present in the resolving list
Write to the register with this bit set to 1, clears the interrupt source.
This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR</name>
<description>If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator
Write to the register with this bit set to 1, clears the interrupt source.
This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR</name>
<description>If this bit is set it indicates that
- an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator
- or an RPA is received from an initiator and matches an entry in the resolving list, but peer IRK is not set and hence a corresponding Identity address is expected from the initiator
Write to the register with this bit set to 1, clears the interrupt source.
This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INIT_NEXT_INSTANT</name>
<description>Initiator next instant.</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>INIT_NEXT_INSTANT</name>
<description>Shows the instant with respect to internal reference clock of resolution 625 us at which next initiator scanning event begins.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DEVICE_RAND_ADDR_L</name>
<description>Lower 16 bit random address of the device.</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DEVICE_RAND_ADDR_L</name>
<description>Lower 16 bit of 48-bit random address of the device.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DEVICE_RAND_ADDR_M</name>
<description>Middle 16 bit random address of the device.</description>
<addressOffset>0x5C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DEVICE_RAND_ADDR_M</name>
<description>Middle 16 bit of 48-bit random address of the device.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DEVICE_RAND_ADDR_H</name>
<description>Higher 16 bit random address of the device.</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DEVICE_RAND_ADDR_H</name>
<description>Higher 16 bit of 48-bit random address of the device.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PEER_ADDR_L</name>
<description>Lower 16 bit address of the peer device.</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PEER_ADDR_L</name>
<description>Lower 16 bit of 48-bit address of the peer device.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PEER_ADDR_M</name>
<description>Middle 16 bit address of the peer device.</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PEER_ADDR_M</name>
<description>Middle 16 bit of 48-bit address of the peer device.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PEER_ADDR_H</name>
<description>Higher 16 bit address of the peer device.</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PEER_ADDR_H</name>
<description>Higher 16 bit of 48-bit address of the peer device.
The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware.
While doing directed Advertising, the firmware writes the peer address of the device specified by the Di-rect_Address parameter of the LE_Set_Advertising_Parameters command.
In non MMMS mode, While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures.
In non MMMS mode, While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created.
When a connection is created as a slave, the firmware can read this register to get the address of the peer de-vice to which connection is created.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WL_ADDR_TYPE</name>
<description>whitelist address type</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WL_ADDR_TYPE</name>
<description>8 address type bits corresponding to the device address stored.
1 - Address type is random.
0 - Address type is public.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WL_ENABLE</name>
<description>whitelist valid entry bit</description>
<addressOffset>0x7C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WL_ENABLE</name>
<description>Stores the valid entry bit corresponding to each of the eight device address stored in the whitelist.
1 - White list entry is Valid
0 - White list entry is Invalid</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TRANSMIT_WINDOW_OFFSET</name>
<description>Transmit window offset</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TX_WINDOW_OFFSET</name>
<description>This is used to determine the first anchor point for the master transmission, from the time of connection creation.
Range: This shall be a multiple of 1.25 ms in the range of 0 ms to connInterval value.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TRANSMIT_WINDOW_SIZE</name>
<description>Transmit window size</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>TX_WINDOW_SIZE</name>
<description>window_size along with the window_offset is used to calculate the first connection point anchor point for the master.
This shall be a multiple of 1.25 ms in the range of 1.25 ms to the lesser of 10 ms and (connInterval - 1.25 ms).
Values range from 0 to 10 ms.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATA_CHANNELS_L0</name>
<description>Data channel map 0 (lower word)</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA_CHANNELS_L0</name>
<description>This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices.
'1' indicates the corresponding data channel is used and '0' indicates the channel is unused.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATA_CHANNELS_M0</name>
<description>Data channel map 0 (middle word)</description>
<addressOffset>0x8C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA_CHANNELS_M0</name>
<description>This register field indicates which of the data channels are in use. This stores the information for the middle 16 (32:16) data channel indices.
'1' indicates the corresponding data channel is used and '0' indicates the channel is unused.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATA_CHANNELS_H0</name>
<description>Data channel map 0 (upper word)</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>DATA_CHANNELS_H0</name>
<description>This register field indicates which of the data channels are in use. This stores the information for the upper 5 (36:32) data channel indices.
'1' indicates the corresponding data channel is used and '0' indicates the channel is unused.
Note: The Data channel map 0 and data channel map 1 are two sets of channel maps stored, common for all the connections. At any given time, only two maps can be maintained and the connections will use one of the two sets as indicated by the channel map index field in the CE_CNFG_STS registers specific to the link. Firmware must also manage to update this field along with the map.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATA_CHANNELS_L1</name>
<description>Data channel map 1 (lower word)</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA_CHANNELS_L1</name>
<description>This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices.
'1' indicates the corresponding data channel is used and '0' indicates the channel is unused.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATA_CHANNELS_M1</name>
<description>Data channel map 1 (middle word)</description>
<addressOffset>0x9C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA_CHANNELS_M1</name>
<description>This register field indicates which of the data channels are in use. This stores the information for the middle 16 (32:16) data channel indices.
'1' indicates the corresponding data channel is used and '0' indicates the channel is unused.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATA_CHANNELS_H1</name>
<description>Data channel map 1 (upper word)</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>DATA_CHANNELS_H1</name>
<description>This register field indicates which of the data channels are in use. This stores the information for the upper 5 data channel indices.
'1' indicates the corresponding data channel is used and '0' indicates the channel is unused.
Note: The Data channel map 0 and data channel map 1 are two sets of channel maps stored, common for all the connections. At any given time, only two maps can be maintained and the connections will use one of the two sets as indicated by the channel map index field in the CE_CNFG_STS registers specific to the link. Firmware must also manage to update this field along with the map.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_INTR</name>
<description>Connection interrupt status and Clear register</description>
<addressOffset>0xA8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_CLOSED</name>
<description>If this bit is set it indicates that the link is disconnected.
If this bit is written with 1, it clears the connection updated interrupt.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_ESTB</name>
<description>If this bit is set it indicates that the connection has been established. The bit is also set when a connection update procedure is complet-ed, at the start of the first anchor point with the updated parameters.
If this bit is written with 1, it clears the connection established interrupt.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MAP_UPDT_DONE</name>
<description>If this bit is set it indicates that the channel map update is completed at the instant specified by the firmware.
If this bit is written with 1, it clears the map update done interrupt.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>START_CE</name>
<description>If this bit is set it indicates that the connection event started interrupt has happened.
If this bit is written with 1, it clears the connection event started interrupt.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLOSE_CE</name>
<description>If this bit is set it indicates that the connection event closed interrupt has happened.
If this bit is written with 1, it clears the connection event closed interrupt.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CE_TX_ACK</name>
<description>If this bit is set it indicates that the connection event transmission acknowledgement is received for the previous non-empty packet transmitted.
If this bit is written with 1, it clears the ce transmission acknowledgement interrupt.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CE_RX</name>
<description>If this bit is set it indicates that a packet is received in the connection event.
If this bit is written with 1, it clears the connection event received interrupt.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CON_UPDT_DONE</name>
<description>This bit is set when the last connection event with previous connec-tion parameters is reached. The bit is set immediately after the re-ceive operation at the anchor point of the last connection event.
If this bit is written with 1, it clears the connection updated interrupt.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DISCON_STATUS</name>
<description>Reason for disconnect - indicates the reason the link is disconnected by hardware.
001 - connection failed to be established
010 - supervision timeout
011 - kill connection by host
100 - kill connection after ACK transmitted
101 - PDU response timer expired</description>
<bitRange>[10:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_PDU_STATUS</name>
<description>Status of PDU received. This information is valid along with receive interrupt.
xx1 - Bad Packet (packet with CRC error)
000 - empty PDU
010 - new data (non-empty) PDU
110 - Duplicate Packet</description>
<bitRange>[13:11]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PING_TIMER_EXPIRD_INTR</name>
<description>If this is set, it indicates that ping timer has expired.
If this bit is written with 1, it clears the interrupt.</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PING_NEARLY_EXPIRD_INTR</name>
<description>If this is set, it indicates that ping timer has nearly expired.
If this bit is written with 1, it clears the interrupt.</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_STATUS</name>
<description>Connection channel status</description>
<addressOffset>0xAC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xF000</resetMask>
<fields>
<field>
<name>RECEIVE_PACKET_COUNT</name>
<description>This field stores the count for the number of receive packets in the receive FIFO that are still not ready by firmware.
The counter value is incremented by hardware for every good packet it stores in the FIFO.
After firmware reads a packet, it decrements the counter by issuing the PACKET_RECEIVED command from the commander.</description>
<bitRange>[15:12]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CONN_INDEX</name>
<description>Connection Index register</description>
<addressOffset>0xB0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_INDEX</name>
<description>This field is used to index the multiple connections existing. Range is 0 to maximum number of connections supported.
For a single connection device, conn_index is 0.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WAKEUP_CONFIG</name>
<description>Wakeup configuration</description>
<addressOffset>0xB8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFCFF</resetMask>
<fields>
<field>
<name>OSC_STARTUP_DELAY</name>
<description>Oscillator stabilization/startup delay. This is in X.Y for-mat where X is in terms of number of BT slots (625 us) and Y is in terms of number of clock periods of 16KHz clock input, required for RF oscillator to stabilize the clock output to the controller on its output pin, after oscillator is turned ON. In this period the clock is as-sumed to be unstable, and so the controller does not turn on the clock to internal logic till this period is over. This means, the wake up from deep sleep mode must account for this delay before the wakeup instant.
Osc_startup_delay[7:5] is number of slots(625us)
Osc_startup_delay[4:0 is number of clock periods of 16KHz clock
(Warning: Min. value of Osc_startup_delay [4:0] sup-ported is 1 and Max. value is 9. Therefore programma-ble range is 1 to 9)</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSM_OFFSET_TO_WAKEUP_INSTANT</name>
<description>Number of 'slots' before the wake up instant before which the hardware needs to exit from deep sleep mode. The slot is of 0.625ms period. This is a onetime configuration field, which is used every time hardware does an auto-wakeup before the next wakeup instant.</description>
<bitRange>[15:10]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WAKEUP_CONTROL</name>
<description>Wakeup control</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WAKEUP_INSTANT</name>
<description>Instant, with reference to the internal 16-bit clock reference, at which the hardware must wakeup from deep sleep mode. This is calculated by firmware based on the next closest instant where a controller operation is required (like advertiser/scanner). Firmware reads the next instant of the procedures in the corresponding *_NEXT_INSTANT registers. This value is used only when hardware auto wakeup from deep sleep mode is enabled in the clock control register.
Note: it is recommended to program wakeup_instant such a way that the actual instant to wakeup shall be at least two counts (two slots of 625 us) ahead of reference clock when entering DSM. The actual instant to wakeup is 'wakeup_instant - dsm_offset_to_wakeup_instant - osc_startup_delay, and it shall be greater than 'reference clock + 2'</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLOCK_CONFIG</name>
<description>Clock control</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80</resetValue>
<resetMask>0xF7FF</resetMask>
<fields>
<field>
<name>ADV_CLK_GATE_EN</name>
<description>Advertiser block clock gate enable. 1 - enable, 0 - disable.
Enables gating of clock to the advertiser module (llh_adv) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_CLK_GATE_EN</name>
<description>Scan block clock gate enable. 1 - enable, 0 - disable.
Enables gating of clock to the scanner module (llh_scan) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_CLK_GATE_EN</name>
<description>Initiator block clock gate enable. 1 - enable, 0 - disable.
Enables gating of clock to the initiator module (llh_init). If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock to the module is always turned ON.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_CLK_GATE_EN</name>
<description>Connection block clock gate enable. 1 - enable, 0 - disable.
Enables gating of clock to the connection module (llh_connch_top) in hardware. If 1, the sleep mode logic can control the clock gate to shutdown/wakeup the clock to the engine. If 0, the logic has no control and clock to the module is always turned ON.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CORECLK_GATE_EN</name>
<description>Core clock gate enable. 1 - enable, 0 - disable.
Enables gating of clock to the llh_core module in hard-ware. If 1, the sleep mode/deep sleep mode logic can control the clock gate to shutdown/wakeup the clock to the module. If 0, the logic has no control and clock is always turned ON.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SYSCLK_GATE_EN</name>
<description>Sysclk gate enable. 1- enable, 0 - disable.
Enables clock gating of system clock input to the link layer. If 1, it enables the DSM logic to control the clock gate for system clock input from pin. If 0, the DSM logic has no control and the system clock is always ON.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PHY_CLK_GATE_EN</name>
<description>Digital PHY clock enable. 1- enable, 0-disable.
Enable the Digital PHY to shutdown the clock. When 1, it indicates that controller has an upcoming activity so PHY clock must be turned ON. When 0, it indicates inactivity in the controller.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LLH_IDLE</name>
<description>Indicates if hardware is doing any transmit/receive operation. This information is used by firmware to decide to program the hardware into deep sleep mode.
1 - LL hardware is idle.
0 - LL hardware is busy. In this case LL hardware will not enter deep sleep mode, even if firmware gives an enter DSM command. (In this situation hardware generates dsm exit interrupt to inform firmware that DSM entry was not successful).</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>LPO_CLK_FREQ_SEL</name>
<description>Clock frequency select. 0 - 32KHz, 1 - 32.768KHz.
Base frequency of the sleep_clk input used for generat-ing the internal reference clock of approximate 16Khz frequency.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LPO_SEL_EXTERNAL</name>
<description>Select external sleep clock. 1 - External clock, 0 - inter-nal generated clock.
The field is used to select either the low power clock in-put on sleep_clk input pin(of frequency 16.384KHz) di-rectly to run the DSM logic or to use the internal gener-ated reference clock(of 16KHz) for the same.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SM_AUTO_WKUP_EN</name>
<description>Enable sleep mode auto wakeup enable. 1- enable, 0 - disable.
Enables hardware to automatically wakeup from sleep mode at the instant = wakeup_instant - sm_offset_to_wakeup_instant. The wakeup_insant is the field in the wakeup control register described earlier. The sm_offset_to_wakeup_instant value is the field described in the wakeup configuration register.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SM_INTR_EN</name>
<description>Enable SM exit interrupt. 1 - enable, 0 - disable.
Enables hardware to generate an interrupt while exiting sleep mode - irrespective of whether it is initiated by hardware or firmware. The interrupt is captured and stored till it gets cleared. Disabling this bit mask the sleep mode exit event from hardware &amp; firmware.
This feature is not available. FW should never set this bit</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DEEP_SLEEP_AUTO_WKUP_DISABLE</name>
<description>Disable Auto Wakeup in DEEP_SLEEP mode.
1 - Disable Auto Wakeup
0 - Auto Wakeup enabled</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLEEP_MODE_EN</name>
<description>Enable sleep mode. 1 - enable, 0 - disable.
Enables hardware to control sleep mode operation.
This feature is not available. FW should never set this bit</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DEEP_SLEEP_MODE_EN</name>
<description>Enable deep sleep mode. 1 - enable, 0 - disable.
Enables hardware logic related to deep sleep mode to control the deep sleep mode operation. If disabled, the related logic is not executed and hardware cannot enter deep sleep mode.</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TIM_COUNTER_L</name>
<description>Reference Clock</description>
<addressOffset>0xC8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TIM_REF_CLOCK</name>
<description>16-bit internal reference clock. The clock is a free run-ning clock, incremented by a 0.625ms periodic pulse. It is used as a reference clock to derive all the timing required as per protocol.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>WAKEUP_CONFIG_EXTD</name>
<description>Wakeup configuration extended</description>
<addressOffset>0xCC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>DSM_LF_OFFSET</name>
<description>Number of 'LF slots' before the wake up instant before which the hardware needs to exit from deep sleep mode. The LF slot is of 62.5us period. This is a onetime configuration field, which is used every time hardware does an auto-wakeup before the next wakeup instant. This is in addition to the LF slots calculated by HW window widening logic.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>POC_REG__TIM_CONTROL</name>
<description>BLE Time Control</description>
<addressOffset>0xD8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF8</resetMask>
<fields>
<field>
<name>BB_CLK_FREQ_MINUS_1</name>
<description>LLH clock configuration. The clock frequency of the clock input to this design is configured in this register. This is used to derive a 1MHz clock.</description>
<bitRange>[7:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>START_SLOT_OFFSET</name>
<description>LLH clock configuration. The start of slot signal is offset by this value. If value is 0, the start of slot signal is generated at the 625us. The offset value is in terms of us.</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADV_TX_DATA_FIFO</name>
<description>Advertising data transmit FIFO. Access ADVCH_TX_FIFO.</description>
<addressOffset>0xE0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ADV_TX_DATA</name>
<description>IO mapped FIFO of depth 16 (2 byte wide), to store ADV data of maximum length 31 bytes for transmitting. Firmware writes consecutive words by writing to the same address location.
Note: ADV_TX_DATA_FIFO and ADV_SCN_RSP_TX_FIFO shares same physical FIFO of depth 32. 16 locations for each FIFO are allocated.
Reading this location resets the FIFO pointer.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADV_SCN_RSP_TX_FIFO</name>
<description>Advertising scan response data transmit FIFO. Access ADVCH_TX_FIFO.</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SCAN_RSP_DATA</name>
<description>IO mapped FIFO of depth 16 (2 byte wide), to store scan response data of maximum length 31 bytes for transmitting. Firmware writes consecutive words by writing to the same location.
Note: ADV_TX_DATA_FIFO and ADV_SCN_RSP_TX_FIFO shares same physical FIFO of depth 32. 16 locations for each FIFO are allocated.
Reading this location resets the FIFO pointer.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INIT_SCN_ADV_RX_FIFO</name>
<description>advertising scan response data receive data FIFO. Access ADVRX_FIFO.</description>
<addressOffset>0xF8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ADV_SCAN_RSP_RX_DATA</name>
<description>IO mapped FIFO of depth 64, to store ADV and SCAN_RSP header and payload received by the scanner. The RSSI value at the time of reception of this packet is also stored. Firmware reads from the same address to read out consecutive words of data.
Note: The 16 bit header is first loaded to the advertise channel data receive FIFO followed by the payload data and then 16 bit RSSI.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CONN_INTERVAL</name>
<description>Connection Interval</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONNECTION_INTERVAL</name>
<description>The value configured in this register determines the spacing be-tween the connection events.
This shall be a multiple of 1.25 ms in the range of 7.5 ms to 4.0 s.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SUP_TIMEOUT</name>
<description>Supervision timeout</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SUPERVISION_TIMEOUT</name>
<description>This field defines the maximum time between two received Data packet PDUs before the connection is considered lost.
This shall be a multiple of 10 ms in the range of 100 ms to 32.0 s and it shall be larger than (1+connSlaveLatency)*connInterval.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLAVE_LATENCY</name>
<description>Slave Latency</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SLAVE_LATENCY</name>
<description>The value configured in this field defines the number of consecutive connection events that the slave device is not required to listen for master.
The value of connSlaveLatency should not cause a Supervision Timeout.
This shall be an integer in the range of 0 to ((connSupervision Timeout/connInterval)-1). connSlaveLatency shall also be less than 500.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CE_LENGTH</name>
<description>Connection event length</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONNECTION_EVENT_LENGTH</name>
<description>This field defines the length of Connection event. This value is derived from the CE length HCI parameters received from the host. This determines the number of master transmit slots in a connection event, subject to either of the MD bits being set. If both MD bits are set to 0, this has no effect. Units: 625us
Note:
The connection event length as specified by the CE_LENGTH shall not exceed CONN_INTERVAL - 1.25 ms.
The CE-length parameter, according to the Bluetooth specification, is the length of the connection event.
Take an example to illustrate this scenario:
Assume a connection with interval = 100ms. that the application has put allowed 20ms of CE-length.
Here, the CE-length can be upto 100ms (100ms - 150us to be exact).
If the connection is maintained for 5 minutes, there could be 10*60*5 = 3000 connection-intervals.
The CE-length need not be maintained constant during all the 3000 connection events.
Here are the typical cases that determine the value of CE-length:
(1) No data packets exchanged. we are just maintaining time and frequency synchronization. In this case, only a packet pair will be exchanged every connection interval. Here, CE-length = 1.
(2) Average of 10 packets to be sent per connection event.
We can pump data in multiple ways here:
2.1: Send data at uniform rate : In this case, the CE-length will be enough to accommodate 10 packets, which will take about 7ms. As this is less than application enforced limit of 20ms, we can comfortably push all the 10 data packets in this connection interval. So data will be pumped to the other BT device at the same rate as is received from my application.
2.2: Can send data in bursts. Assume that we accumulate data for 1 second and pump out at the end of 1 second(this is not done by our Bluetooth stack, the application needs to buffer the data). So, at 10th connection interval, we have 100 packets accumulated. We are now ready to pump this data. 100 packets take about 70 ms. This is above the application enforced 20ms. So, the hardware can pump data that can fill up 20ms. The remaining data will be deferred to the next connection interval.
So, in this case, you would see a CE-length spread over time like this (Per connection interval):
0,0,0,0,0,0,0,0,0,0, 20,20,20,10,0,0,0,0,0,0, 20,20,20,10,0,0,0,0,0,0, 20,20,20,10,0,0,0,0,0,0,
and so on.
(3) We are receiving data at the same rate as in (2). This case is to honor data sent by the other BT-device by giving it more time in the current connection interval.
In (2) and (3) you will see non-empty packets either transmitted or received. We can also utilize the CE-length for different reasons:
(4) A transaction is in progress, and we are expecting a response packet very soon. In this case, we may be exchanging only empty packets now, and in the next few packet-pairs.
In this case, you will the CE-length to be large, and a non-empty packet may not be exchanged in all the slots.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDU_ACCESS_ADDR_L_REGISTER</name>
<description>Access address (lower)</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PDU_ACCESS_ADDRESS_LOWER_BITS</name>
<description>This field defines the lower 16 bits of the access address for each Link layer connection between any two devices.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDU_ACCESS_ADDR_H_REGISTER</name>
<description>Access address (upper)</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PDU_ACCESS_ADDRESS_HIGHER_BITS</name>
<description>This field defines the higher 16 bits of the access address for each Link layer connection between any two devices.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_CE_INSTANT</name>
<description>Connection event instant</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CE_INSTANT</name>
<description>This is the value of the free running Connection Event counter when the new parameters of 'connection update' and/or 'Channel map update' will be effective.
Range : 0x0000 to 0xFFFF</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CE_CNFG_STS_REGISTER</name>
<description>connection configuration &amp; status register</description>
<addressOffset>0x11C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF5FF</resetMask>
<fields>
<field>
<name>DATA_LIST_INDEX_LAST_ACK_INDEX</name>
<description>Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded.
The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4.
Hardware will start the next data transmission from the index indicated by this field.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_LIST_HEAD_UP</name>
<description>Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause.
The bit must be toggled every time the firmware needs to indicate the start/resume. This requires a read modify write operation.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPARE</name>
<description>This bit is unused</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MD</name>
<description>MD bit set to '1' indicates device has more data to be sent.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MAP_INDEX__CURR_INDEX</name>
<description>Written by firmware to select the map index to be used by hardware for this connection.
1 - use channel map register set 1.
0 - use channel map register set 0.
When firmware reads this field, it returns the current map index being used in hardware.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PAUSE_DATA</name>
<description>Pause data.
1 - pause data,
0 - do not pause.
The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared.
But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_ACTIVE</name>
<description>This bit is '1' whenever the connection is active.</description>
<bitRange>[10:10]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CURRENT_PDU_INDEX</name>
<description>The index of the transmit packet buffer that is currently in transmission/waiting for transmission.</description>
<bitRange>[15:12]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>NEXT_CE_INSTANT</name>
<description>Next connection event instant</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>NEXT_CE_INSTANT</name>
<description>16-bit internal reference clock value at which the next connection event will occur on a connection. The connection index register must be programmed with index of the connection, before reading the register.
The reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0xFFFF.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CONN_CE_COUNTER</name>
<description>connection event counter</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONNECTION_EVENT_COUNTER</name>
<description>This is the free running counter, connEventCounter as defined by Bluetooth spec.
Firmware will read the instantaneous Event counter from this register, during connection update and channel map update procedure. Firmware will use this value to calculate the instant from which the new parameters (for connection update and channel map update) will be effective.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DATA_LIST_SENT_UPDATE__STATUS</name>
<description>data list sent update and status</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x8F</resetMask>
<fields>
<field>
<name>LIST_INDEX__TX_SENT_3_0</name>
<description>Write:Indicates the buffer index for which the SENT bit is being updated by firmware.
The default number of buffers in the IP is 4. The index range is 0-3.
Read: Reads TX_SENT[3:0].
The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are
1 - queued
0 - no packet / packet ack received by hardware
Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement.
NOTE:
The SENT status bit and ACK status bit have to be taken together to understand the meaning of packet status. The table below describes how the two bits are sequentially updated by either hardware/firmware to complete one data transmission.
SENT ACK Description
0 0 Buffer is empty. No packet is queued in the buffer
1 0 Packet is queued by firmware.
1 1 Packet is transmitted by hardware. Hardware is waiting for acknowledgement.
0 1 Hardware has received ACK. Firmware has not yet processed the ACK.
0 0 Firmware has processed the ack. The buffer is again empty.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_CLEAR</name>
<description>Write: Used to set the SENT bit in hardware for the selected packet buffer.
1 - packet queued
When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted.
The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device.
Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified.</description>
<bitRange>[7:7]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>DATA_LIST_ACK_UPDATE__STATUS</name>
<description>data list ack update and status</description>
<addressOffset>0x12C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x8F</resetMask>
<fields>
<field>
<name>LIST_INDEX__TX_ACK_3_0</name>
<description>Write: Indicates the buffer index for which the ACK bit is being updated by firmware.
The default number of buffers in the IP is 5. The index range is 0-4.
Read: Reads TX_ACK[3:0]
If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement.
Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware.
Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware.
NOTE:
The SENT status bit and ACK status bit have to be taken together to understand the meaning of packet status. The table below describes how the two bits are sequentially updated by either hardware/firmware to complete one data transmission.
SENT ACK Description
0 0 Buffer is empty. No packet is queued in the buffer
1 0 Packet is queued by firmware.
1 1 Packet is transmitted by hardware. Hardware is waiting for acknowledgement.
0 1 Hardware has received ACK. Firmware has not yet processed the ACK.
0 0 Firmware has processed the ack. The buffer is again empty.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_CLEAR</name>
<description>Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware.
Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware.
For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0.
This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on.
The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet.</description>
<bitRange>[7:7]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CE_CNFG_STS_REGISTER_EXT</name>
<description>connection configuration &amp; status register</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F0F</resetMask>
<fields>
<field>
<name>TX_2M</name>
<description>transmittion on 2M</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_2M</name>
<description>receiving on 2M</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SN</name>
<description>Sequence number for next scheduled connection index</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NESN</name>
<description>Next Sequence number for next scheduled connection index</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LAST_UNMAPPED_CHANNEL</name>
<description>Last unmapped channel for next scheduled connection index</description>
<bitRange>[13:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_EXT_INTR</name>
<description>Connection extended interrupt status and Clear register</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>DATARATE_UPDATE</name>
<description>If this bit is set it indicates that the data rate is updated
If this bit is written with 1, it clears the interrupt status bit</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EARLY_INTR</name>
<description>For master this bit is set on start_ce
For Slave this bit is set on slave_timer_adj</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>GEN_TIMER_INTR</name>
<description>If this bit is set it indicates that the generic timer (PDU response timer reconfigured in MMMS mode) has expired
If this bit is written with 1, it clears the interrupt status bit</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_EXT_INTR_MASK</name>
<description>Connection Extended Interrupt mask</description>
<addressOffset>0x138</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>DATARATE_UPDATE</name>
<description>If this bit is set connection data rate update interrupt is enabled.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EARLY_INTR</name>
<description>If this bit is set connection early interrupt is enabled.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>GEN_TIMER_INTR</name>
<description>Generic timer (PDU response timer reconfigured in MMMS mode) expiry interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>5</dim>
<dimIncrement>4</dimIncrement>
<name>DATA_MEM_DESCRIPTOR[%s]</name>
<description>Data buffer descriptor 0 to 4</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>LLID</name>
<description>N/A</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_LENGTH</name>
<description>This field indicates the length of the data packet. Bits [9:7] are valid only if DLE is set.
Range 0x00 to 0xFF.</description>
<bitRange>[9:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WINDOW_WIDEN_INTVL</name>
<description>Window widen for interval</description>
<addressOffset>0x160</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>WINDOW_WIDEN_INTVL</name>
<description>This value defines the increased listening time for the slave.
The window widening shall be smaller than ((connInterval/2)-T_IFS us)
This value is calculated by firmware based on the drift, the connec-tion interval value. The value is the unit widening value for one con-nection interval duration. In case of slave latency, this value is accu-mulated till the next anchor point at which the slave will listen.</description>
<bitRange>[11:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WINDOW_WIDEN_WINOFF</name>
<description>Window widen for offset</description>
<addressOffset>0x164</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>WINDOW_WIDEN_WINOFF</name>
<description>This field stores the additional number of microseconds the slave must extend its listening window to listen for a master packet. This value is calculated based on the window offset value. This is used at connection setup directly. During connection setup, this value is added with window_widen_intvl register value to calculate the win-dow widening size.</description>
<bitRange>[11:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LE_RF_TEST_MODE</name>
<description>Direct Test Mode control</description>
<addressOffset>0x170</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xA3FF</resetMask>
<fields>
<field>
<name>TEST_FREQUENCY</name>
<description>N = (F - 2402) / 2
Range: 0x00 - 0x27. Frequency Range : 2402 MHz to 2480 MHz</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DTM_STATUS__DTM_CONT_RXEN</name>
<description>This bit is overloaded.
The read operation returns the staus of the DTM
1 - DTM test ON
0 - DTM test OFF
The write operation contrls the DTM RX mode
0: DTM run at normal DTMRX burst mode
1: DTM run at continuous RX DTM mode</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PKT_PAYLOAD</name>
<description>N/A</description>
<bitRange>[9:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DTM_CONT_TXEN</name>
<description>0: DTM run at normal DTMTX burst mode
1: DTM run at continuous TX DTM mode</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DTM_DATA_2MBPS</name>
<description>0: DTM run at 1M bps data rate
1: DTM run at 2M bps data rate</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DTM_RX_PKT_COUNT</name>
<description>Direct Test Mode receive packet count</description>
<addressOffset>0x174</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RX_PACKET_COUNT</name>
<description>Number of packets received in receive test mode.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LE_RF_TEST_MODE_EXT</name>
<description>Direct Test Mode control</description>
<addressOffset>0x178</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DTM_PACKET_LENGTH</name>
<description>DTM TX packet length.
Bits [7:6] are accessible onle when DLE is enabled</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TXRX_HOP</name>
<description>Channel Address register</description>
<addressOffset>0x188</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x7F7F</resetMask>
<fields>
<field>
<name>HOP_CH_TX</name>
<description>Transmit channel index. Channel index on which previous packet is transmitted.</description>
<bitRange>[6:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>HOP_CH_RX</name>
<description>Receive channel index. Channel index on which previous packet is received.</description>
<bitRange>[14:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TX_RX_ON_DELAY</name>
<description>Transmit/Receive data delay</description>
<addressOffset>0x190</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RXON_DELAY</name>
<description>Receive delay - Delay from start of receive to expected first bit of receive packet at the controller. Used to control the turn on time of radio to optimize on power. The delay is in resolution of 1 microsecond.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TXON_DELAY</name>
<description>Transmit delay - Delay from start of transmit to transmission of first bit on air. It is used to control the T_IFS. The delay is in resolution of 1 microsecond.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADV_ACCADDR_L</name>
<description>ADV packet access code low word</description>
<addressOffset>0x1A8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xBED6</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ADV_ACCADDR_L</name>
<description>Lower 16 bit of ADV packet access code</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADV_ACCADDR_H</name>
<description>ADV packet access code high word</description>
<addressOffset>0x1AC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8E89</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ADV_ACCADDR_H</name>
<description>higher 16 bit of ADV packet access code</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADV_CH_TX_POWER_LVL_LS</name>
<description>Advertising channel transmit power setting</description>
<addressOffset>0x1B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ADV_TRANSMIT_POWER_LVL_LS</name>
<description>When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1, this field represents the Advertising channel transmit power setting Least Significant 16 bits.
When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 0, the LS 4 bits represents the Advertising channel transmit power code 4 bits.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADV_CH_TX_POWER_LVL_MS</name>
<description>Advertising channel transmit power setting extension</description>
<addressOffset>0x1B4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>ADV_TRANSMIT_POWER_LVL_MS</name>
<description>Advertising channel transmit power setting Most Significant 2 bits.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_CH_TX_POWER_LVL_LS</name>
<description>Connection channel transmit power setting</description>
<addressOffset>0x1B8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONNCH_TRANSMIT_POWER_LVL_LS</name>
<description>When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1, this field represents the Connection channel transmit power setting Least Significant 16 bits.
When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 0, the LS 4 bits represents the Connection channel transmit power code 4 bits.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_CH_TX_POWER_LVL_MS</name>
<description>Connection channel transmit power setting extension</description>
<addressOffset>0x1BC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>CONNCH_TRANSMIT_POWER_LVL_MS</name>
<description>Connection channel transmit power setting Most Significant 2 bits.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DEV_PUB_ADDR_L</name>
<description>Device public address lower register</description>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3412</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DEV_PUB_ADDR_L</name>
<description>Lower 16 bit of 48-bit public address of the device.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DEV_PUB_ADDR_M</name>
<description>Device public address middle register</description>
<addressOffset>0x1C4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x56</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DEV_PUB_ADDR_M</name>
<description>Middle 16 bit of 48-bit public address of the device.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DEV_PUB_ADDR_H</name>
<description>Device public address higher register</description>
<addressOffset>0x1C8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DEV_PUB_ADDR_H</name>
<description>Higher 16 bit of 48-bit public address of the device.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OFFSET_TO_FIRST_INSTANT</name>
<description>Offset to first instant</description>
<addressOffset>0x1D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x6</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>OFFSET_TO_FIRST_EVENT</name>
<description>The offset w.r.t the internal reference clock at which instant the first event occurs.
This register will give flexibility to the firmware to position the con-nection at a desired point with respect to the internal free running clock. It is optional to be updated by firmware. This is not updated in the current firmware.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADV_CONFIG</name>
<description>Advertiser configuration register</description>
<addressOffset>0x1D4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20FF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ADV_STRT_EN</name>
<description>Enable advertising event start interrupt.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_CLS_EN</name>
<description>Enable advertising event stop interrupt.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_TX_EN</name>
<description>Enable adv packet transmitted interrupt.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCN_RSP_TX_EN</name>
<description>Enable scan response packet transmitted interrupt.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_SCN_REQ_RX_EN</name>
<description>Enable scan request packet received interrupt.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_CONN_REQ_RX_EN</name>
<description>Enable connect request packet received interrupt.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLV_CONNECTED_EN</name>
<description>Enable slave connected interrupt.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_TIMEOUT_EN</name>
<description>Enable adv_timeout interrupt. Applicable in adv_direct_ind advertising.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_RAND_DISABLE</name>
<description>Disable randomization of adv interval. When disabled, interval is same as programmed in adv_interval register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_SCN_PEER_RPA_UNMCH_EN</name>
<description>Enable scan request packet received with peer device address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_ADV are set.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_CONN_PEER_RPA_UNMCH_EN</name>
<description>Enable connect request packet received with peer device address unmatched interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_PKT_INTERVAL</name>
<description>Time between the beginning of two consecutive advertising PDU's.
Time = N * 0.625 msec
Time Range: &lt;=10msec.</description>
<bitRange>[15:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SCAN_CONFIG</name>
<description>Scan configuration register</description>
<addressOffset>0x1D8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xE01F</resetValue>
<resetMask>0xE9FF</resetMask>
<fields>
<field>
<name>SCN_STRT_EN</name>
<description>Enable scan event start interrupt.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCN_CLOSE_EN</name>
<description>Enable scan event close interrupt.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCN_TX_EN</name>
<description>Enable scan request packet transmitted interrupt.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_RX_EN</name>
<description>Enable adv packet received interrupt .</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCN_RSP_RX_EN</name>
<description>Enable scan_rsp packet received interrupt .</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN</name>
<description>Enable ADV peer address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_SCAN are set.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN</name>
<description>Enable ADV self address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_1_2 and PRIV_1_2_SCAN are set.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCANA_TX_ADDR_NOT_SET_INTR_EN</name>
<description>Enable SCANA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN</name>
<description>This bit controls the SCAN engine behavior when an self address match occurs but a privacy mismatch occurs
0 - The packet is aborted
1 - The packet is received and reported to the Link Layer firmware
This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BACKOFF_ENABLE</name>
<description>Enable random backoff feature in scanner.
1 - enable
0 - disable</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_CHANNEL_MAP</name>
<description>Advertising channels that are enabled for scanning operation.
Bit 15: setting 1 - enables channel 39 for use.
Bit 14: setting 1 - enables channel 38 for use.
Bit 13: setting 1 - enables channel 37 for use.</description>
<bitRange>[15:13]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INIT_CONFIG</name>
<description>Initiator configuration register</description>
<addressOffset>0x1DC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xE0F7</resetMask>
<fields>
<field>
<name>INIT_STRT_EN</name>
<description>Enable Initiator event start interrupt.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_CLOSE_EN</name>
<description>Enable Initiator event close interrupt.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_REQ_TX_EN</name>
<description>Enables connection request packet transmission start interrupt.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_CREATED</name>
<description>Enable master connection created interrupt</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN</name>
<description>Enable ADV self address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN</name>
<description>Enable ADV peer address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INITA_TX_ADDR_NOT_SET_INTR_EN</name>
<description>Enable INITA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_CHANNEL_MAP</name>
<description>Advertising channels that are enabled for initiator scanning operation.
Bit 15: setting 1 - enables channel 39 for use.
Bit 14: setting 1 - enables channel 38 for use.
Bit 13: setting 1 - enables channel 37 for use.</description>
<bitRange>[15:13]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_CONFIG</name>
<description>Connection configuration register</description>
<addressOffset>0x1E0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xE11F</resetValue>
<resetMask>0xF9FF</resetMask>
<fields>
<field>
<name>RX_PKT_LIMIT</name>
<description>Defines a limit for the number of Rx packets that can be re-ceived by the LLH. Default maximum value is 0xF.Minimum value shall be '1' or no packet will be stored in the Rx FIFO.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_INTR_THRESHOLD</name>
<description>This register field allows setting a threshold for the packet received interrupt to the firmware.
For example if the value programmed is
0x2 - then HW will generate interrupt only on receiving the second packet.
In any case if the received number of packets in a conn event is less than the threshold or there are still packets (less than threshold) pending in the Rx FIFO, HW will generate the interrupt at the ce_close.
Min value possible is 1. Max value depends on the Rx FIFO capacity.</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MD_BIT_CLEAR</name>
<description>This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and soft-ware logic combined'.
1 - MD bit is exclusively controlled by software, ie based on status of CE_CNFG_STS_REGISTER[6] - md bit.
0 - MD Bit in the transmitted pdu is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the md bit in CE_CNFG_STS_REGISTER[6] and either of the following conditions is true,
a) If there are packets queued for transmission.
b) If there is an acknowledgement awaited from the remote side for the packet transmitted.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSM_SLOT_VARIANCE</name>
<description>This bit configures the DSM slot counting mode.
0 - The DSM slot count variance with respect to actual time is less than 1 slot
1 - The DSM slot count variance with respect to actual time is more than 1 slot &amp;less that 2 slots</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLV_MD_CONFIG</name>
<description>This bit is set to configure the MD bit control when IUT is in slave role.
1 - MD bit will be decided on packet pending status
0 - MD bit will be decided on packet queued in next buffer status
This bit has effect only when 'CONN_CONFIG.md_bit_ctr' bit is not set .</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EXTEND_CU_TX_WIN</name>
<description>This bit is used to enable/disable extending the additional rx window on slave side during connection update in event of packet miss at the update instant.
1 - Enable
0 - Disable</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MASK_SUTO_AT_UPDT</name>
<description>This bit is used to enable/disable masking of internal hardware supervision timeout trigger when switching from old connection parameters to new parameters.
1 - Enable
0 - Disable</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_REQ_1SLOT_EARLY</name>
<description>This bit is used to enable extension of the Conn Request to arbiter to 1 slot early. When enabled the request length is 2 slots.
1 - Enable
0 - Disable</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_PARAM1</name>
<description>Connection parameter 1</description>
<addressOffset>0x1E8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SCA_PARAM</name>
<description>Sleep Clock Accuracy</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HOP_INCREMENT_PARAM</name>
<description>Hop increment for connection channel.</description>
<bitRange>[7:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRC_INIT_L</name>
<description>This field defines the lower byte (7:0) of the CRC initialization vector.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_PARAM2</name>
<description>Connection parameter 2</description>
<addressOffset>0x1EC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CRC_INIT_H</name>
<description>This field defines the upper two bytes (23:8) of the CRC initialization vector.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_INTR_MASK</name>
<description>Connection Interrupt mask</description>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2000</resetValue>
<resetMask>0xE3FF</resetMask>
<fields>
<field>
<name>CONN_CL_INT_EN</name>
<description>If this bit is set connection closed interrupt is enabled.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_ESTB_INT_EN</name>
<description>If this bit is set connection establishment interrupt is enabled.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MAP_UPDT_INT_EN</name>
<description>If this bit is set, channel map update interrupt is enabled.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>START_CE_INT_EN</name>
<description>If this bit is set connection event start interrupt is enabled</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLOSE_CE_INT_EN</name>
<description>If this bit is set connection event closed interrupt is enabled.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CE_TX_ACK_INT_EN</name>
<description>If this bit is set transmission acknowledgement interrupt is enabled:
This interrupt is generated to indicate to the firmware that a non-empty packet transmitted is successfully acknowledged by the remote device.
For negative acknowledgements from remote device, this interrupt indication is not generated.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CE_RX_INT_EN</name>
<description>If this bit is set interrupt is enabled for reception of packet in a connection event.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_UPDATE_INTR_EN</name>
<description>If this bit is set connection update interrupt is enabled.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_GOOD_PDU_INT_EN</name>
<description>If this bit is set packet receive good pdu interrupt is enabled. Effective only when bit 6 is set.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_BAD_PDU_INT_EN</name>
<description>If this bit is set packet receive bad pdu interrupt is enabled. Effective only when bit 6 is set.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CE_CLOSE_NULL_RX_INT_EN</name>
<description>If this but us set, the RX interrupt is triggerred for an end of connection event with a null packet</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PING_TIMER_EXPIRD_INTR</name>
<description>If this bit is set ping timer expired interrupt is enabled.</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PING_NEARLY_EXPIRD_INTR</name>
<description>If this bit is set ping timer nearly expired interrupt is enabled</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLAVE_TIMING_CONTROL</name>
<description>slave timing control</description>
<addressOffset>0x1F4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xBE96</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SLAVE_TIME_SET_VAL</name>
<description>Programmable adjust value to the clock counter when slave is connected</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLAVE_TIME_ADJ_VAL</name>
<description>Timing adjust value. The internal micro second counter is adjusted to this value whenever slave receives a good access address match at connection anchor point. This will ensure the slave gets synchronized to master timing.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RECEIVE_TRIG_CTRL</name>
<description>Receive trigger control</description>
<addressOffset>0x1F8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF3F</resetMask>
<fields>
<field>
<name>ACC_TRIGGER_THRESHOLD</name>
<description>Access address match threshold value. Number of bits of ac-cess address that should match with the expected access ad-dress to trigger an access code match.
Max value : 32 (for 32-bit access address)
Lower values may be programmed for bad radios or channels but care must be taken to ensure there are no 'false' matches due to reduced number of bits required to match.</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACC_TRIGGER_TIMEOUT</name>
<description>If access address match does not occur then within this time from the start of receive operation, the receive operation times out and stops. An internal counter value of 1usec resolution is continuously compared with the value programmed.
Max value :0xFF</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LL_DBG_1</name>
<description>LL debug register 1</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>CONN_RX_WR_PTR</name>
<description>Connection receive FIFO write pointer</description>
<bitRange>[9:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LL_DBG_2</name>
<description>LL debug register 2</description>
<addressOffset>0x204</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>CONN_RX_RD_PTR</name>
<description>Connection receive FIFO read pointer</description>
<bitRange>[9:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LL_DBG_3</name>
<description>LL debug register 3</description>
<addressOffset>0x208</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>CONN_RX_WR_PTR_STORE</name>
<description>Connection receive FIFO stored write pointer for pointer restore</description>
<bitRange>[9:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LL_DBG_4</name>
<description>LL debug register 4</description>
<addressOffset>0x20C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x7FF</resetMask>
<fields>
<field>
<name>CONNECTION_FSM_STATE</name>
<description>Connection FSM state</description>
<bitRange>[3:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SLAVE_LATENCY_FSM_STATE</name>
<description>Slave Latency FSM state</description>
<bitRange>[5:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ADVERTISER_FSM_STATE</name>
<description>Advertiser FSM state</description>
<bitRange>[10:6]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LL_DBG_5</name>
<description>LL debug register 5</description>
<addressOffset>0x210</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>INIT_FSM_STATE</name>
<description>Initiator FSM state</description>
<bitRange>[4:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SCAN_FSM_STATE</name>
<description>Scanner FSM state</description>
<bitRange>[9:5]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LL_DBG_6</name>
<description>LL debug register 6</description>
<addressOffset>0x214</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FFF</resetMask>
<fields>
<field>
<name>ADV_TX_WR_PTR</name>
<description>Advertiser Transmit FIFO write pointer</description>
<bitRange>[3:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SCAN_RSP_TX_WR_PTR</name>
<description>Scan Response Transmit FIFO write pointer</description>
<bitRange>[7:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ADV_TX_RD_PTR</name>
<description>Advertiser/ Scan Response FIFO read pointer</description>
<bitRange>[13:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LL_DBG_7</name>
<description>LL debug register 7</description>
<addressOffset>0x218</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FFF</resetMask>
<fields>
<field>
<name>ADV_RX_WR_PTR</name>
<description>Advertiser Receive FIFO write pointer</description>
<bitRange>[6:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ADV_RX_RD_PTR</name>
<description>Advertiser Receive FIFO read pointer</description>
<bitRange>[13:7]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LL_DBG_8</name>
<description>LL debug register 8</description>
<addressOffset>0x21C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FFF</resetMask>
<fields>
<field>
<name>ADV_RX_WR_PTR_STORE</name>
<description>Advertiser Receive FIFO stored write pointer for pointer restore</description>
<bitRange>[6:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WLF_PTR</name>
<description>Whitelist FIFO pointer</description>
<bitRange>[13:7]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LL_DBG_9</name>
<description>LL debug register 9</description>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x10</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WINDOW_WIDEN</name>
<description>Window Widening value in us. The reset value of this register is 0x0000. After reset de-assertion, at the first clock cycle, the value 0x0010 is assigned to the register.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LL_DBG_10</name>
<description>LL debug register 10</description>
<addressOffset>0x224</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>RF_CHANNEL_NUM</name>
<description>Active channel number</description>
<bitRange>[5:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PEER_ADDR_INIT_L</name>
<description>Lower 16 bit address of the peer device for INIT.</description>
<addressOffset>0x230</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PEER_ADDR_L</name>
<description>Lower 16 bit of 48-bit address of the peer device. This is used only in MMMS mode
The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware.
While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures.
While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PEER_ADDR_INIT_M</name>
<description>Middle 16 bit address of the peer device for INIT.</description>
<addressOffset>0x234</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PEER_ADDR_M</name>
<description>Middle 16 bit of 48-bit address of the peer device. This is used only in MMMS mode
The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware.
While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures.
While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PEER_ADDR_INIT_H</name>
<description>Higher 16 bit address of the peer device for INIT.</description>
<addressOffset>0x238</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PEER_ADDR_H</name>
<description>Higher 16 bit of 48-bit address of the peer device. This is used only in MMMS mode
The peer address registers are used for multiple purposes. The register is written by firmware to provide the peer address to be used for a hardware procedure. When firmware reads the register, it reads back peer address values updated by hardware.
While device is configured as an initiator without white list filtering, the peer address specified in the peer_address field of the create connection command is programmed into this register, which is used by hard-ware procedures.
While device is configured as an initiator and white list is enabled, firmware can read this register to get the address of the peer device from which connectable ADV packet was received and to which the connection is created.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PEER_SEC_ADDR_ADV_L</name>
<description>Lower 16 bits of the secondary address of the peer device for ADV_DIR.</description>
<addressOffset>0x23C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PEER_SEC_ADDR_L</name>
<description>Lower 16 bit of 48-bit secondary address of the peer device for ADV_DIR.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PEER_SEC_ADDR_ADV_M</name>
<description>Middle 16 bits of the secondary address of the peer device for ADV_DIR.</description>
<addressOffset>0x240</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PEER_SEC_ADDR_M</name>
<description>Middle 16 bit of 48-bit secondary address of the peer device for ADV_DIR.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PEER_SEC_ADDR_ADV_H</name>
<description>Higher 16 bits of the secondary address of the peer device for ADV_DIR.</description>
<addressOffset>0x244</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PEER_SEC_ADDR_H</name>
<description>Higher 16 bit of 48-bit secondary address of the peer device for ADV_DIR.
While doing directed Advertising in device privacy mode, if the peer device has shared its IRK, then the peer device RPA is written into the PEER_ADDR registers and the peer device identity address is written into this register. If the peer device has not shared its IRK, then the peer identity address is written into the PEER_ADDR registers and this register must be cleared.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INIT_WINDOW_TIMER_CTRL</name>
<description>Initiator Window NI timer control</description>
<addressOffset>0x248</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INIT_WINDOW_OFFSET_SEL</name>
<description>Controls the INIT Window offset source
1 - Pick INIT Window Offset from HW calculated INIT_WINDOW_OFFSET
0 - Pick INIT Window Offset from FW loaded register</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_CONFIG_EXT</name>
<description>Connection extended configuration register</description>
<addressOffset>0x24C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA000</resetValue>
<resetMask>0xFF7F</resetMask>
<fields>
<field>
<name>CONN_REQ_2SLOT_EARLY</name>
<description>This bit is used to enable extension of the Conn Request to arbiter to 2 slot early. When enabled the request length is 3 slots, irrespective of the status of CONN_REQ_1SLOT_EARLY bit.
1 - Enable
0 - Disable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_REQ_3SLOT_EARLY</name>
<description>This bit is used to enable extension of the Conn Request to arbiter to 3 slot early. When enabled the request length is 4 slots, irrespective of the status of CONN_REQ_1SLOT_EARLY &amp; CONN_REQ_2SLOT_EARLY bits.
1 - Enable
0 - Disable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FW_PKT_RCV_CONN_INDEX</name>
<description>Connection Index for which the FW generates Packet Received Command. In MMMS mode, FW should write this field before giving PKT_RECEIVE_COMMAND to HW.</description>
<bitRange>[6:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MMMS_RX_PKT_LIMIT</name>
<description>Receive Packet Limit for MMMS mode. This is the RX_FIFO Limit and applies to all connections together</description>
<bitRange>[13:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DEBUG_CE_EXPIRE</name>
<description>MMMS CE expire control bit</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MT_PDU_CE_EXPIRE</name>
<description>MMMS empty PDU CE expire handling control bit</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DPLL_CONFIG</name>
<description>DPLL &amp; CY Correlator configuration register</description>
<addressOffset>0x258</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DPLL_CORREL_CONFIG</name>
<description>If MXD_IF_OPTION is 0:
Not used
If CY_CORREL_EN is 1:
[11:0] CY correl Access address compare mask for LSB 12 bits. Ideal value is 0xFFF
[15:12] CY correl maximum number of allowed mismatched bits in access address. Ideal value is 0x0.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INIT_NI_VAL</name>
<description>Initiator Window NI instant</description>
<addressOffset>0x260</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>INIT_NI_VAL</name>
<description>Initiator window Next Instant value used for spacing Master connections in time, to minimize connection contention. This value is in 625us slots.
The read value corresponds to the hardware updated Interval value</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INIT_WINDOW_OFFSET</name>
<description>Initiator Window offset captured at conn request</description>
<addressOffset>0x264</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>INIT_WINDOW_NI</name>
<description>Initiator Window offset captured at conn request. This value is in 1.25ms slots</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INIT_WINDOW_NI_ANCHOR_PT</name>
<description>Initiator Window NI anchor point captured at conn request</description>
<addressOffset>0x268</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>INIT_INT_OFF_CAPT</name>
<description>Initiator interval offset captured at conn request. The value indicates the master connection anchor point. This value is in 625us slots</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CONN_UPDATE_NEW_INTERVAL</name>
<description>Connection update new interval</description>
<addressOffset>0x3A4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_UPDT_INTERVAL</name>
<description>This register will have the new connection interval that the hardware will use after the connection update instant. Before the instant, the connection interval in the register CONN_INTERVAL will be used by hardware.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_UPDATE_NEW_LATENCY</name>
<description>Connection update new latency</description>
<addressOffset>0x3A8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_UPDT_SLV_LATENCY</name>
<description>This register will have the new slave latency parameter that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SLAVE_LATENCY will be used by hardware.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_UPDATE_NEW_SUP_TO</name>
<description>Connection update new supervision timeout</description>
<addressOffset>0x3AC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_UPDT_SUP_TO</name>
<description>This register will have the new supervision timeout that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SUP_TIMEOUT will be used by hardware.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_UPDATE_NEW_SL_INTERVAL</name>
<description>Connection update new Slave Latency X Conn interval Value</description>
<addressOffset>0x3B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SL_CONN_INTERVAL_VAL</name>
<description>This register will have the new Slave Latency * Conn Interval value that the hardware will use after the connection update instant. Before the instant, the connection interval in the register SL_CONN_INTERVAL will be used by hardware.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD0</name>
<description>Connection request address word 0</description>
<addressOffset>0x3C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ACCESS_ADDR_LOWER</name>
<description>This field defines the lower 16 bits of the access address that is to be sent in the connect request packet of the initiator.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD1</name>
<description>Connection request address word 1</description>
<addressOffset>0x3C4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ACCESS_ADDR_UPPER</name>
<description>This field defines the upper16 bits of the access address that is to be sent in the connect request packet of the initiator.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD2</name>
<description>Connection request address word 2</description>
<addressOffset>0x3C8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TX_WINDOW_SIZE_VAL</name>
<description>window_size along with the window_offset is used to calculate the first connection point anchor point for the master.
This shall be a multiple of 1.25 ms in the range of 1.25 ms to the lesser of 10 ms and (connInterval - 1.25 ms).
Values range from 0 to 10 ms.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRC_INIT_LOWER</name>
<description>This field defines the lower byte [7:0] of the CRC initialization value.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD3</name>
<description>Connection request address word 3</description>
<addressOffset>0x3CC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CRC_INIT_UPPER</name>
<description>This field defines the upper byte [23:8] of the CRC initialization value that is to be sent in the connect request packet of the initiator.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD4</name>
<description>Connection request address word 4</description>
<addressOffset>0x3D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TX_WINDOW_OFFSET</name>
<description>This is used to determine the anchor point for the master transmission.
Range: This shall be a multiple of 1.25 ms in the range of 0 ms to connInterval value.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD5</name>
<description>Connection request address word 5</description>
<addressOffset>0x3D4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONNECTION_INTERVAL_VAL</name>
<description>The value configured in this register determines the spacing between the connection events.
This shall be a multiple of 1.25 ms in the range of 7.5 ms to 4.0 s.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD6</name>
<description>Connection request address word 6</description>
<addressOffset>0x3D8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SLAVE_LATENCY_VAL</name>
<description>The value configured in this field defines the number of consecutive connection events that the slave device is not required to listen for master. The value of connSlaveLatency should not cause a Supervision Timeout. This shall be an integer in the range of 0 to ((connSupervision Timeout/connInterval)-1). connSlaveLatency shall also be less than 500.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD7</name>
<description>Connection request address word 7</description>
<addressOffset>0x3DC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SUPERVISION_TIMEOUT_VAL</name>
<description>This field defines the maximum time between two received Data packet PDUs before the connection is considered lost.
This shall be a multiple of 10 ms in the range of 100 ms to 32.0 s and it shall be larger than (1+connSlaveLatency)*connInterval.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD8</name>
<description>Connection request address word 8</description>
<addressOffset>0x3E0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA_CHANNELS_LOWER</name>
<description>This register field indicates which of the data channels are in use. This stores the information for the lower 16 (15:0) data channel indices.
1' indicates the corresponding data channel is used and '0' indicates the channel is unused.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD9</name>
<description>Connection request address word 9</description>
<addressOffset>0x3E4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA_CHANNELS_MID</name>
<description>This register field indicates which of the data channels are in use. This stores the information for the middle 16 (31:16) data channel indices.
'1' indicates the corresponding data channel is used and '0' indicates the channel is unused.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD10</name>
<description>Connection request address word 10</description>
<addressOffset>0x3E8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>DATA_CHANNELS_UPPER</name>
<description>This register field indicates which of the data channels are in use. This stores the information for the upper 5 (36:32) data channel indices.
'1' indicates the corresponding data channel is used and '0' indicates the channel is unused.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_REQ_WORD11</name>
<description>Connection request address word 11</description>
<addressOffset>0x3EC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>HOP_INCREMENT_2</name>
<description>This field is used for the data channel selection process.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCA_2</name>
<description>This field defines the sleep clock accuracies given in ppm.</description>
<bitRange>[7:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDU_RESP_TIMER</name>
<description>PDU response timer/Generic Timer (MMMS mode)</description>
<addressOffset>0xA04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PDU_RESP_TIME_VAL</name>
<description>Non MMMS mode: This register is loaded with the count value to monitor the time to get a response for a PDU from peer device.
Firmware starts the timer by issuing the command, RESP_TIMER_ON, after it has queued a PDU for transmission, that requires a response.
If a response is received, firmware stops and clears the timer by issuing the command RESP_TIMER_OFF.
If this timer expires, it results in hardware closing the connection and triggering a conn_closed interrupt.
The discon_status field in the Connection status register is set with the appropriate reason.
Units : Milliseconds.
Resolution : 1.25 ms
MMMS mode: This register is loaded with a count value, which when matched by the internal timer, triggers the GEN_TIMER_INTR. This is recommended to be used as a one shot timer and not as a periodic timer.
Firmware starts the timer by loading the expiry time and issuing the command, RESP_TIMER_ON.
Once the timer expiry is triggered with the interrupt GEN_TIMER_INTR, the firmware stops the timer by issuing the command RESP_TIMER_OFF.
Resolution : 625 us</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NEXT_RESP_TIMER_EXP</name>
<description>Next response timeout instant</description>
<addressOffset>0xA08</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>NEXT_RESPONSE_INSTANT</name>
<description>This field defines the clock instant at which the next PDU response timeout event will occur on a connection.
This is with reference to the 16-bit internal reference clock.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>NEXT_SUP_TO</name>
<description>Next supervision timeout instant</description>
<addressOffset>0xA0C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>NEXT_TIMEOUT_INSTANT</name>
<description>This field defines the clock instant at which the next connection supervision timeout event will occur on a connection
This is with reference to the 16-bit internal reference clock.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LLH_FEATURE_CONFIG</name>
<description>Feature enable</description>
<addressOffset>0xA10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x6</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>QUICK_TRANSMIT</name>
<description>Quick transmit feature in slave latency is enabled by setting this bit.
When slave latency is enabled, this feature enables the slave to transmit in the immediate connection interval, in case required, instead of waiting till the end of slave latency</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SL_DSM_EN</name>
<description>Enable/Disable Slave Latency Period DSM.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>US_COUNTER_OFFSET_ADJ</name>
<description>Enable/Disable the connection US counter offset adjust. For non-MMMS mode, this bit must be tied to 1.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WIN_MIN_STEP_SIZE</name>
<description>Window minimum step size</description>
<addressOffset>0xA14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2064</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>STEPDN</name>
<description>After receiving 2 consecutive good packets the reference window is gradually decremented by step down size until it reaches window minimum. The unit is in microseconds</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STEPUP</name>
<description>If packets are missed, the reference window is gradually increased by step up size, until it receives 2 consecutive good packets. The unit is in microseconds</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WINDOW_MIN_FW</name>
<description>Minimum window interval value programmed by firmware. While the slave receive window is decremented, the windows_min_fw sets the lowest value of the window widen value to ensure packets are not missed. The unit is in microseconds.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLV_WIN_ADJ</name>
<description>Slave window adjustment</description>
<addressOffset>0xA18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0x7FF</resetMask>
<fields>
<field>
<name>SLV_WIN_ADJ</name>
<description>Window Adjust value. This value is added to the calculated slave window widening value to be used as final window widen value.</description>
<bitRange>[10:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SL_CONN_INTERVAL</name>
<description>Slave Latency X Conn Interval Value</description>
<addressOffset>0xA1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SL_CONN_INTERVAL_VAL</name>
<description>This field defines the (SL*CI) product for the ongoing connection. This value is used in calculation of next connection instant during slave latency.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LE_PING_TIMER_ADDR</name>
<description>LE Ping connection timer address</description>
<addressOffset>0xA20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_PING_TIMER_ADDR</name>
<description>The register used to configure the LE Au-thenticated payload Timeout (LE APTO) which is the Maximum amount of time specified between packets authenticated by a MIC.
This value of ping timer is in the order of 10ms, valid range 0x1 ~ 0xFFFF</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LE_PING_TIMER_OFFSET</name>
<description>LE Ping connection timer offset</description>
<addressOffset>0xA24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_PING_TIMER_OFFSET</name>
<description>The value of ping timer nearly expired offset in the order of 10ms, valid range 0x0 ~ 0xFFFF. This is the time period after which the ping timer nearly expired interrupt is generated.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LE_PING_TIMER_NEXT_EXP</name>
<description>LE Ping timer next expiry instant</description>
<addressOffset>0xA28</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_PING_TIMER_NEXT_EXP</name>
<description>The value of ping timer next expiry instant in the terms of native clock value (least 16 bit value of the 17 bit ping counter).
This together with CONN_PING_TIMER_NEXT_EXP_WRAP will provide the correct status of ping timer duration.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LE_PING_TIMER_WRAP_COUNT</name>
<description>LE Ping Timer wrap count</description>
<addressOffset>0xA2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_SEC_CURRENT_WRAP</name>
<description>This register holds the current position of the Ping timer.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TX_EN_EXT_DELAY</name>
<description>Transmit enable extension delay</description>
<addressOffset>0xE00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1345</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>TXEN_EXT_DELAY</name>
<description>Transmit enable extension delay. This is to extend the active state (high) of rif_tx_en signal after the last bit is sent out from LLH. The unit is in microsecond and the supported range is 00 - 31 us.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RXEN_EXT_DELAY</name>
<description>receiver enable extension delay. This is to extend the active state (high) of dbus_rx_en signal after the last bit is received from demod. The unit is in microsecond and the supported range is 00 - 31 us.</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DEMOD_2M_COMP_DLY</name>
<description>2Mbps demod delay delta compare to 1Mbps demod delay. This data is 2's comp data.</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MOD_2M_COMP_DLY</name>
<description>2Mbps modulation delay delta compare to 1Mbps demod delay. This data is 2's comp data.</description>
<bitRange>[15:12]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TX_RX_SYNTH_DELAY</name>
<description>Transmit/Receive enable delay</description>
<addressOffset>0xE04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RX_EN_DELAY</name>
<description>The delay used to assert rif_rx_en, Rx_tRamp micro-seconds, ahead of first bit of the expected rx_data, which can be used to turn on the Radio receiver.
The value to be programmed to the Rx_en_delay [7:0] = rx_on_delay - Rx_tRamp
rx_on_delay[7:0] = TX_RX_ON_DELAY[7:0])
Rx_tRamp = Radio receiver rampup time</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_EN_DELAY</name>
<description>The delay used to assert rif_tx_en exactly Tx_tRamp micro-seconds ahead of the first bit of the tx_data, which can be used to turn on the Radio transmitter.
The value to be programmed to the Tx_en_delay [7:0] = tx_on_delay - Tx_tRamp
tx_on_delay[7:0] = TX_RX_ON_DELAY[15:8])
Tx_tRamp = Radio transmitter ramp_up</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EXT_PA_LNA_DLY_CNFG</name>
<description>External TX PA and RX LNA delay configuration</description>
<addressOffset>0xE08</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>LNA_CTL_DELAY</name>
<description>The delay used to assert LNA_CTL, LNA_tRamp micro-seconds, ahead of first bit of the expected rx_data, which can be used to turn on the external Low Noise Amplifier.
The value to be programmed to the lna_ctl_delay [7:0] = rx_on_delay - LNA_tRamp
rx_on_delay[7:0] = TX_RX_ON_DELAY[7:0])
LNA_tRamp = External Low Noise Amplifier startup time</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PA_CTL_DELAY</name>
<description>The delay used to assert PA_CTL exactly PA_tRamp micro-seconds ahead of the first bit of the tx_data, which can be used to turn on the external power amplifier.
The value to be programmed to the pa_ctl_delay [7:0] = tx_on_delay - PA_tRamp
tx_on_delay[7:0] = TX_RX_ON_DELAY[15:8])
PA_tRamp = External Power Amplifier ramp time</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LL_CONFIG</name>
<description>Link Layer additional configuration</description>
<addressOffset>0xE10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4C00</resetValue>
<resetMask>0x7FEF</resetMask>
<fields>
<field>
<name>RSSI_SEL</name>
<description>Controls the RSSI reads. When this bit is 1, the bit RSSI_INTR_SEL is don't care.
0 - RSSI read is initiated after the the packet is received
1 - RSSI read is completed before the packet is received.
When RCB Interface is operating 4Mhz are lower this bit should be set to 1'b0.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_RX_CTRL_SEL</name>
<description>Controls the mode of issueing TX_EN &amp; RX_EN to the Radio
1 - TX_EN and RX_EN are issued through direct pins
0 - TX_EN and RX_EN are issued through RCB writes</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TIFS_ENABLE</name>
<description>Setting this bit enables the tx 1MHz pulse to match the received bpktctl from CYBLERD55. This will result is reduced TIFS variation</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TIMER_LF_SLOT_ENABLE</name>
<description>Controls the wakeup timer configuration
1 - Wakeup time is compensated with the LF_OFFSET
0 - Wakeup time is not compensated with the LF_OFFSET as in legacy mode</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSSI_INTR_SEL</name>
<description>Controls the engine interrupt generation based on RSSI reads. This is valid only if RSSI_SEL is 0.
0 - Receive interrupts are triggerred after the RSSI read is complete
1 - Receive interrupts are triggerred after the last bit of CRC</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSSI_EARLY_CNFG</name>
<description>Controls the early RSSI reads. This is applicable only when RSSI_SEL is 1.
1 - RSSI read is initiated during the first CRC byte reception.
0 - RSSI read is initiated during the third CRC byte reception.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_RX_PIN_DLY</name>
<description>Controls the delay from DBUS_TX, DBUS_RX assertion to the assertion on the pins. This is applicable only when TX_RX_CTRL_SEL is set.
0 - The pin assertion is delayed by 4 cycles.
1 - The pin assertion is delayed by 8 cycles.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_PA_PWR_LVL_TYPE</name>
<description>Controls the TX power level format given to the CYBLERD55 chip.
0 - The power level given to CYBLERD55 is in 4 bit code format from ADV_CH_TX_POWER for advertising channel and DTM packets &amp; from CONN_CH_TX_POWER for connection channel packets. The power level setting is decoded and given to the PA.
1 - The power level given to CYBLERD55 is in 18 bit power level setting format from {ADV_CH_TX_POWER_LVL_MS, ADV_CH_TX_POWER_LVL_LS} channel and DTM packets &amp; from {CONN_CH_TX_POWER_LVL_MS, CONN_CH_TX_POWER_LVL_LS} for connection channel packets. This setting is directly given to the PA.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSSI_ENERGY_RD</name>
<description>Controls the RSSI reads.
0 - Channel Energy read is not initiated if no packet is received during a receive cycle
1 - Channel Energy read is initiated at the end of the receive cycle if no packet is received</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSSI_EACH_PKT</name>
<description>Controls the RSSI reads.
0 - RSSI read is not initiated for zero length and aborted packets
1 - RSSI read is initiated for zero length and aborted packets</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FORCE_TRIG_RCB_UPDATE</name>
<description>Controls the RCB update to radio on TX/RX enable. Applicable only when TX_RX_CTRL_SEL is 1'b1
0 - RCB update is triggerred only when the fields change on rising edge of TX/RX enable
1 - RCB update is force triggerred on rising edge of TX/RX enable
If TX_RX_CTRL_SEL is 1'b1 and ENABLE_RADIO_BOD is 1'b1, this bit needs to be set to 1'b1</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CHECK_DUP_CONN</name>
<description>Controls the duplicate connection checkin ADV and INIT
0 - Does not check if the peer is already connection before a new connection is created
1 - Checks if the peer is already connection before a new connection is created and aborts a duplicate connection creation</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MULTI_ENGINE_LPM</name>
<description>Controls the LPM entry condition
0 - Legacy mode LPM entry check
1 - MMMS mode LPM entry check</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_DIR_DEVICE_PRIV_EN</name>
<description>Controls the ADV behavior while advertising ADV_DIR and only device privacy is set. When the ADV is transmitting INITA RPA, the bahavior when an Identity address in received from the Initiator in the CONN_REQ is given below
0 - Abort the CONN_REQ and continue with advertisement
1 - Check the address against PEER_SEC_ADDR_ADV and create connection on a match.</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LL_CONTROL</name>
<description>LL Backward compatibility</description>
<addressOffset>0xF00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>PRIV_1_2</name>
<description>Enables Privacy 1.2 Feature.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DLE</name>
<description>Enables Data Length extension feature in DTM, connection and encryption modules.
This bit should always be set to 1'b1. 1'b0 is not supported.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WL_READ_AS_MEM</name>
<description>The Whilelist read logic is controlled using this bit.
0 - The reads to the whitelist address range is treated as FIFO reads and the pointers are reset by issueing the RESET_READ_PTR command.
1 - The reads to the whitelist address range is treated an memory reads. Any whilelist entry can be read.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL</name>
<description>Controls the ADVCH FIFO flushing when PRIV_1_2 is enabled.
0 - Flushes all ADV &amp; INIT packets, as in non privacy 1.2 mode, except those with unresolved peer or self RPA.
1 - Does not flush any CRC good packets</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HW_RSLV_LIST_FULL</name>
<description>This bit indicates that the resolving list in the hardware is full and the list is extended in the FW. This will affect the behavior of address resolution.
0 - The resolving list in the hardware is not fully filled. When Whitelist is disabled and a peer identity address not in the resolving list is received, the packet is responded to by the hardware.
1 - The resolving list in the hardware is fully filled. All address comparisons must be extended to the Firmware list as well, Any match in the Firmware list should be followed by copying the matching entry into the hardware resolving list.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV</name>
<description>This bit controls the ADV engine behavior when an initiator address match occurs but a privacy mismatch occurs
0 - The packet is aborted
1 - The packet is received and reported to the Link Layer firmware</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV</name>
<description>This bit controls the ADV engine behavior when a scanner address match occurs but a privacy mismatch occurs
0 - The packet is aborted
1 - The packet is received and reported to the Link Layer firmware</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN</name>
<description>This bit controls the SCAN engine behavior when an peer address match occurs but a privacy mismatch occurs
0 - The packet is aborted
1 - The packet is received and reported to the Link Layer firmware</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI</name>
<description>This bit controls the INIT engine behavior when an peer address match occurs but a privacy mismatch occurs
0 - The packet is aborted
1 - The packet is received and reported to the Link Layer firmware</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI</name>
<description>This bit controls the INIT engine behavior when a self address match occurs but a privacy mismatch occurs
0 - The packet is aborted
1 - The packet is received and reported to the Link Layer firmware</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIV_1_2_ADV</name>
<description>Enables Privacy 1.2 for ADV engine</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIV_1_2_SCAN</name>
<description>Enables Privacy 1.2 for SCAN engine</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRIV_1_2_INIT</name>
<description>Enables Privacy 1.2 for INIT engine</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EN_CONN_RX_EN_MOD</name>
<description>This bit controls the Connection RX enable modification mode when SLV_CONN_PEER_RPA_NOT_RSLVD is set.
1'b0 - The Connection RX enable is unmodified
1'b1 - The Connection RX enable is during the Peer INIT RPA unresolved state is modified, until it is resolved.</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLV_CONN_PEER_RPA_NOT_RSLVD</name>
<description>This bit is asserted when SLV_CONN_PEER_RPA_UNMCH_INTR is set. The device does not enter into Connection established state until this bit is cleared after the RPA is resoved by the firmware. If the firmware is not able to resolve the RPA within the supervision timeout, the device aborts the connection establishement and this bit is cleared by the hardware.
This bit is valid only if PRIV_1_2 is set.</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADVCH_FIFO_FLUSH</name>
<description>When set, flushes the ADVCH FIFO. The bit is auto cleared.
Note that this should be used only when the FIFO is not read by the firmware. If firmware has started reading the FIFO, then the FIFO must be emptied exclusively by firmware reads</description>
<bitRange>[15:15]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>DEV_PA_ADDR_L</name>
<description>Device Resolvable/Non-Resolvable Private address lower register</description>
<addressOffset>0xF04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3412</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DEV_PA_ADDR_L</name>
<description>Lower 16 bit of 48-bit Random Private address of the device.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DEV_PA_ADDR_M</name>
<description>Device Resolvable/Non-Resolvable Private address middle register</description>
<addressOffset>0xF08</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x56</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DEV_PA_ADDR_M</name>
<description>Middle 16 bit of 48-bit Random Private address of the device.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DEV_PA_ADDR_H</name>
<description>Device Resolvable/Non-Resolvable Private address higher register</description>
<addressOffset>0xF0C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DEV_PA_ADDR_H</name>
<description>Higher 16 bit of 48-bit Random Private address of the device.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>4</dimIncrement>
<name>RSLV_LIST_ENABLE[%s]</name>
<description>Resolving list entry control bit</description>
<addressOffset>0xF10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7FF</resetMask>
<fields>
<field>
<name>VALID_ENTRY</name>
<description>Indicates if the index is valid</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PEER_ADDR_IRK_SET</name>
<description>Indicates if the listed peer device has shared its IRK.
0 - Identity address in a received packet is accepted. If a valid peer device RPA is available in the list, then the RPA in a received packet is accepted.
1 - Only the peer device RPA, if available in the list, in a received packet is accepted. An Identity address in the received packet is reported as a privacy mismatch.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SELF_ADDR_IRK_SET_RX</name>
<description>Indicates if the local IRK has been shared with the listed peer device
0 - Self Identity address in a received packet is accepted. If a valid self RPA is available in the list, then the RPA in a received packet is accepted.
1 - Only the self device RPA, if available in the list, in a received packet is accepted. A Self Identity address in the received packet is reported as a privacy mismatch.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WHITELISTED_PEER</name>
<description>Indicates if the listed peer device is in the whitelist</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PEER_ADDR_TYPE</name>
<description>Indicates the address type of the listed peer device</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PEER_ADDR_RPA_VAL</name>
<description>Indicates that the peer device RPA in the list is valid</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SELF_ADDR_RXD_RPA_VAL</name>
<description>Indicates that the received self RPA in the list is valid</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SELF_ADDR_TX_RPA_VAL</name>
<description>Indicates that the self RPA in the list to be transmitted is valid</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SELF_ADDR_INIT_RPA_SEL</name>
<description>When Initiator whitelist is disabled, this bit indicates the specific device to from which ADV packets will be accepted.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SELF_ADDR_TYPE_TX</name>
<description>Indicates the TX addr type to be used for SCANA and INITA
0 - Self Identity address is used in SCANA/INITA in SCAN_REQ/CONN_REQ packets
1 - Self RPA address provided in RSLV_LIST_TX_INIT_RPA field in the resolving list with the associated valid bit in SELF_ADDR_TX_RPA_VAL above is used in SCANA/INITA in SCAN_REQ/CONN_REQ packets</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENTRY_CONNECTED</name>
<description>Indicates if the entry is already in connection with our device</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WL_CONNECTION_STATUS</name>
<description>whitelist valid entry bit</description>
<addressOffset>0xFA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WL_ENTRY_CONNECTED</name>
<description>Stores the connection status of each of the sixteen device address stored in the whitelist.
1 - White list entry is already in a connection
0 - White list entry is not in a connection</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_RXMEM_BASE_ADDR_DLE</name>
<description>DLE Connection RX memory base address</description>
<addressOffset>0x1800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CONN_RX_MEM_BASE_ADDR_DLE</name>
<description>Data from Rx memory are read as 32-bit wide data. This memory is valid only if DLE is set.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_TXMEM_BASE_ADDR_DLE</name>
<description>DLE Connection TX memory base address</description>
<addressOffset>0x2800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CONN_TX_MEM_BASE_ADDR_DLE</name>
<description>Data to Tx memory are written as 32-bit wide data. This memory is valid only if DLE is set.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_1_PARAM_MEM_BASE_ADDR</name>
<description>Connection Parameter memory base address for connection 1</description>
<addressOffset>0x12800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_1_PARAM</name>
<description>N/A</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_2_PARAM_MEM_BASE_ADDR</name>
<description>Connection Parameter memory base address for connection 2</description>
<addressOffset>0x12880</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_2_PARAM</name>
<description>N/A</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_3_PARAM_MEM_BASE_ADDR</name>
<description>Connection Parameter memory base address for connection 3</description>
<addressOffset>0x12900</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_3_PARAM</name>
<description>N/A</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_4_PARAM_MEM_BASE_ADDR</name>
<description>Connection Parameter memory base address for connection 4</description>
<addressOffset>0x12980</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_4_PARAM</name>
<description>N/A</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NI_TIMER</name>
<description>Next Instant Timer</description>
<addressOffset>0x14000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>NI_TIMER</name>
<description>BT Slot at which the next connection has to be serviced, granularity is 625us. The NI timer has to be programmed 1.25ms before the connection event</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>US_OFFSET</name>
<description>Micro-second Offset</description>
<addressOffset>0x14004</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>US_OFFSET_SLOT_BOUNDARY</name>
<description>Micro Second Offset from the Slot Bounday at which the connection programmed in NEXT_CONN has to be serviced. This register along with NI_TIMER has to be programmed 1.25ms before the connection event. The granularity is 1us</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NEXT_CONN</name>
<description>Next Connection</description>
<addressOffset>0x14008</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7F</resetMask>
<fields>
<field>
<name>NEXT_CONN_INDEX</name>
<description>Connection Index to be serviced. Allowed values are 0,1,2,3.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NEXT_CONN_TYPE</name>
<description>Connection type
1 - Master Connection
0 - Slave Connection</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NI_VALID</name>
<description>Flag indication if programmed NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the connection of if NI_TIMER is pointing to past value</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NI_ABORT</name>
<description>Abort next scheduled connection</description>
<addressOffset>0x1400C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>NI_ABORT</name>
<description>Setting this bit clears the schedule NI</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ABORT_ACK</name>
<description>This bit will set if the scheduled NI is aborted</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_NI_STATUS</name>
<description>Connection NI Status</description>
<addressOffset>0x14020</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFF</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_NI</name>
<description>HW updates this register with the next Connection Instant for current serviced connection, granularity is 625us. The reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0xFFFF.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>NEXT_SUP_TO_STATUS</name>
<description>Next Supervision timeout Status</description>
<addressOffset>0x14024</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>NEXT_SUP_TO</name>
<description>HW updates this register for the SuperVision timeout next instant, granularity is 625us</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MMMS_CONN_STATUS</name>
<description>Connection Status</description>
<addressOffset>0x14028</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CURR_CONN_INDEX</name>
<description>Connection Index that was serviced. Legal values are 0,1,2,3.</description>
<bitRange>[4:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CURR_CONN_TYPE</name>
<description>Connection type
1 - Master Connection
0 - Slave Connection</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SN_CURR</name>
<description>Sequence Number of Packets exchanged</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NESN_CURR</name>
<description>Next Sequence Number</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>LAST_UNMAPPED_CHANNEL</name>
<description>Last Unmapped Channel</description>
<bitRange>[13:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PKT_MISS</name>
<description>1 - Packet Missed
0 - Connection exchanged packets</description>
<bitRange>[14:14]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ANCHOR_PT_STATE</name>
<description>Anchor Point State
0 - Anchor point missed
1 - Anchor point established</description>
<bitRange>[15:15]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BT_SLOT_CAPT_STATUS</name>
<description>BT Slot Captured Status</description>
<addressOffset>0x1402C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>BT_SLOT</name>
<description>During slave connection event, HW updates this register with the captured BT_SLOT at anchor point, granularity is 625us</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>US_CAPT_STATUS</name>
<description>Micro-second Capture Status</description>
<addressOffset>0x14030</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>US_CAPT</name>
<description>During slave connection event, HW updates this register with the captured microsecond at anchor point, granularity is 1us</description>
<bitRange>[9:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>US_OFFSET_STATUS</name>
<description>Micro-second Offset Status</description>
<addressOffset>0x14034</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xD5</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>US_OFFSET</name>
<description>During slave connection event, HW updates this register with the calculated us_offset at anchor point, granularity is 1us. The reset value is 0x0000. After reset deassertion, then the very next clock, the value assigned to the registers is 0x00D5.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ACCU_WINDOW_WIDEN_STATUS</name>
<description>Accumulated Window Widen Status</description>
<addressOffset>0x14038</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>ACCU_WINDOW_WIDEN</name>
<description>Accumulated Window Widen Value. HW updates this register at the close of slave connection event</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>EARLY_INTR_STATUS</name>
<description>Status when early interrupt is raised</description>
<addressOffset>0x1403C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CONN_INDEX_FOR_EARLY_INTR</name>
<description>Connection Index for which early interrupt is raised</description>
<bitRange>[4:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CONN_TYPE_FOR_EARLY_INTR</name>
<description>Connection type for which early interrupt is raised.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>US_FOR_EARLY_INTR</name>
<description>US offset when early interrupt is raised</description>
<bitRange>[15:6]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MMMS_CONFIG</name>
<description>Multi-Master Multi-Slave Config</description>
<addressOffset>0x14040</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7FF</resetMask>
<fields>
<field>
<name>MMMS_ENABLE</name>
<description>Configuration bit to enable MMMS functionality</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DISABLE_CONN_REQ_PARAM_IN_MEM</name>
<description>If set to 1'b1 and MMMS enabled, then the parameters received in connection request are not stored in CONN_REQ_PARAM memory. By default this bit is 1'b0 and the connection request parameters are stored in connection memory.
This bit is intended as a fail-safe. Should not be changed dynamically during runtime</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DISABLE_CONN_PARAM_MEM_WR</name>
<description>By default on end_ce, the connection parameters memory is loaded with the updated connection parameters. Setting this bit prevent's this update.
This bit is intended as a fail-safe. Should not be changed dynamically during runtime</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CONN_PARAM_FROM_REG</name>
<description>By default the parameters for the connection are picked up from the connection parameters memory. Setting this bit disables this and the parameters are picked up from registers
0 - HW loads the parameters from connection memory
1 - Firmware should program the paramters for the connection event
This bit is intended as a fail-safe. Should not be changed dynamically during runtime</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADV_CONN_INDEX</name>
<description>This field specifies the connection index for which ADV is enabled</description>
<bitRange>[8:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CE_LEN_IMMEDIATE_EXPIRE</name>
<description>Enable for CE length immediate expiry</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_RX_FIFO_PTR</name>
<description>Setting this bit resets the receive FIFO pointers</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>US_COUNTER</name>
<description>Running US of the current BT Slot</description>
<addressOffset>0x14044</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>US_COUNTER</name>
<description>Current value of the US Counter</description>
<bitRange>[9:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>US_CAPT_PREV</name>
<description>Previous captured US of the BT Slot</description>
<addressOffset>0x14048</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>US_CAPT_LOAD</name>
<description>HW uses this register to load the us_offset from connection parameter memory. This can be used by firmware as a fail safe option if the HW load from memory is disabled. In alll other conditions firmware should not use this register.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EARLY_INTR_NI</name>
<description>NI at early interrupt</description>
<addressOffset>0x1404C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>EARLY_INTR_NI</name>
<description>Connection Next instant when the early interrupt is triggered</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MMMS_MASTER_CREATE_BT_CAPT</name>
<description>BT slot capture for master connection creation</description>
<addressOffset>0x14080</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>BT_SLOT</name>
<description>This register captures the BT_SLOT when master connection is created, granularity is 625us</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MMMS_SLAVE_CREATE_BT_CAPT</name>
<description>BT slot capture for slave connection creation</description>
<addressOffset>0x14084</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>US_CAPT</name>
<description>This register captures the BT_SLOT when slave connection is created, granularity is 625us</description>
<bitRange>[9:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MMMS_SLAVE_CREATE_US_CAPT</name>
<description>Micro second capture for slave connection creation</description>
<addressOffset>0x14088</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>US_OFFSET_SLAVE_CREATED</name>
<description>This register captures the us when slave connection is created, granularity is 1us</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>4</dimIncrement>
<name>MMMS_DATA_MEM_DESCRIPTOR[%s]</name>
<description>Data buffer descriptor 0 to 15</description>
<addressOffset>0x14100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>LLID_C1</name>
<description>N/A</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_LENGTH_C1</name>
<description>This field indicates the length of the data packet. Bits [9:7] are valid only if DLE is set.
Range 0x00 to 0xFF.</description>
<bitRange>[9:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_1_DATA_LIST_SENT</name>
<description>data list sent update and status for connection 1</description>
<addressOffset>0x14200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF8F</resetMask>
<fields>
<field>
<name>LIST_INDEX__TX_SENT_3_0_C1</name>
<description>Write:Indicates the buffer index for which the SENT bit is being updated by firmware.
The default number of buffers in the IP is 5. The index range is 0-3.
Read: Reads TX_SENT[3:0].
The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are
1 - queued
0 - no packet / packet ack received by hardware
Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_CLEAR_C1</name>
<description>Write: Used to set the SENT bit in hardware for the selected packet buffer.
1 - packet queued
When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted.
The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device.
Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified.</description>
<bitRange>[7:7]</bitRange>
<access>write-only</access>
</field>
<field>
<name>BUFFER_NUM_TX_SENT_3_0_C1</name>
<description>Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_1_DATA_LIST_ACK</name>
<description>data list ack update and status for connection 1</description>
<addressOffset>0x14204</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x8F</resetMask>
<fields>
<field>
<name>LIST_INDEX__TX_ACK_3_0_C1</name>
<description>Write: Indicates the buffer index for which the ACK bit is being updated by firmware.
The default number of buffers in the IP is 5. The index range is 0-3.
Read: Reads TX_ACK[3:0]
If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement.
Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware.
Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_CLEAR_C1</name>
<description>Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware.
Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware.
For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0.
This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on.
The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet.</description>
<bitRange>[7:7]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CONN_1_CE_DATA_LIST_CFG</name>
<description>Connection specific pause resume for connection 1</description>
<addressOffset>0x14208</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA_LIST_INDEX_LAST_ACK_INDEX_C1</name>
<description>Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded.
The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4.
Hardware will start the next data transmission from the index indicated by this field.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_LIST_HEAD_UP_C1</name>
<description>Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause.
The bit must be set every time the firmware needs to indicate the start/resume.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLV_MD_CONFIG_C1</name>
<description>This bit is set to configure the MD bit control when the design is in slave mode.
1 - MD bit will be decided on packet pending status
0 - MD bit will be decided on packet queued in next buffer status
This bit has valid only when MD_BIT_CLEAR bit is not set</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MD_C1</name>
<description>MD bit set to '1' indicates device has more data to be sent.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MD_BIT_CLEAR_C1</name>
<description>This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined'
1 - MD bit is exclusively controlled by software, based on status of bit [6].
0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true,
a) If there are packets queued for transmission.
b) If there is an acknowledgement awaited from the remote side for the packet transmitted.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PAUSE_DATA_C1</name>
<description>Pause data.
1 - pause data,
0 - do not pause.
The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared.
But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>KILL_CONN</name>
<description>Kills the connection immediately when the connection event is active</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>KILL_CONN_AFTER_TX</name>
<description>Kills the connection when the connection event is active and a TX is completed</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EMPTYPDU_SENT</name>
<description>This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CURRENT_PDU_INDEX_C1</name>
<description>The index of the transmit packet buffer that is currently in transmission/waiting for transmission.</description>
<bitRange>[15:12]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CONN_2_DATA_LIST_SENT</name>
<description>data list sent update and status for connection 2</description>
<addressOffset>0x14210</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF8F</resetMask>
<fields>
<field>
<name>LIST_INDEX__TX_SENT_3_0_C1</name>
<description>Write:Indicates the buffer index for which the SENT bit is being updated by firmware.
The default number of buffers in the IP is 5. The index range is 0-3.
Read: Reads TX_SENT[3:0].
The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are
1 - queued
0 - no packet / packet ack received by hardware
Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_CLEAR_C1</name>
<description>Write: Used to set the SENT bit in hardware for the selected packet buffer.
1 - packet queued
When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted.
The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device.
Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified.</description>
<bitRange>[7:7]</bitRange>
<access>write-only</access>
</field>
<field>
<name>BUFFER_NUM_TX_SENT_3_0_C1</name>
<description>Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_2_DATA_LIST_ACK</name>
<description>data list ack update and status for connection 2</description>
<addressOffset>0x14214</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x8F</resetMask>
<fields>
<field>
<name>LIST_INDEX__TX_ACK_3_0_C1</name>
<description>Write: Indicates the buffer index for which the ACK bit is being updated by firmware.
The default number of buffers in the IP is 5. The index range is 0-3.
Read: Reads TX_ACK[3:0]
If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement.
Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware.
Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_CLEAR_C1</name>
<description>Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware.
Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware.
For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0.
This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on.
The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet.</description>
<bitRange>[7:7]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CONN_2_CE_DATA_LIST_CFG</name>
<description>Connection specific pause resume for connection 2</description>
<addressOffset>0x14218</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA_LIST_INDEX_LAST_ACK_INDEX_C1</name>
<description>Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded.
The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4.
Hardware will start the next data transmission from the index indicated by this field.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_LIST_HEAD_UP_C1</name>
<description>Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause.
The bit must be set every time the firmware needs to indicate the start/resume.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLV_MD_CONFIG_C1</name>
<description>This bit is set to configure the MD bit control when the design is in slave mode.
1 - MD bit will be decided on packet pending status
0 - MD bit will be decided on packet queued in next buffer status
This bit has valid only when MD_BIT_CLEAR bit is not set</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MD_C1</name>
<description>MD bit set to '1' indicates device has more data to be sent.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MD_BIT_CLEAR_C1</name>
<description>This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined'
1 - MD bit is exclusively controlled by software, based on status of bit [6].
0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true,
a) If there are packets queued for transmission.
b) If there is an acknowledgement awaited from the remote side for the packet transmitted.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PAUSE_DATA_C1</name>
<description>Pause data.
1 - pause data,
0 - do not pause.
The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared.
But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>KILL_CONN</name>
<description>Kills the connection immediately when the connection event is active</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>KILL_CONN_AFTER_TX</name>
<description>Kills the connection when the connection event is active and a TX is completed</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EMPTYPDU_SENT</name>
<description>This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CURRENT_PDU_INDEX_C1</name>
<description>The index of the transmit packet buffer that is currently in transmission/waiting for transmission.</description>
<bitRange>[15:12]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CONN_3_DATA_LIST_SENT</name>
<description>data list sent update and status for connection 3</description>
<addressOffset>0x14220</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF8F</resetMask>
<fields>
<field>
<name>LIST_INDEX__TX_SENT_3_0_C1</name>
<description>Write:Indicates the buffer index for which the SENT bit is being updated by firmware.
The default number of buffers in the IP is 5. The index range is 0-3.
Read: Reads TX_SENT[3:0].
The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are
1 - queued
0 - no packet / packet ack received by hardware
Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_CLEAR_C1</name>
<description>Write: Used to set the SENT bit in hardware for the selected packet buffer.
1 - packet queued
When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted.
The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device.
Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified.</description>
<bitRange>[7:7]</bitRange>
<access>write-only</access>
</field>
<field>
<name>BUFFER_NUM_TX_SENT_3_0_C1</name>
<description>Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_3_DATA_LIST_ACK</name>
<description>data list ack update and status for connection 3</description>
<addressOffset>0x14224</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x8F</resetMask>
<fields>
<field>
<name>LIST_INDEX__TX_ACK_3_0_C1</name>
<description>Write: Indicates the buffer index for which the ACK bit is being updated by firmware.
The default number of buffers in the IP is 5. The index range is 0-3.
Read: Reads TX_ACK[3:0]
If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement.
Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware.
Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_CLEAR_C1</name>
<description>Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware.
Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware.
For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0.
This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on.
The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet.</description>
<bitRange>[7:7]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CONN_3_CE_DATA_LIST_CFG</name>
<description>Connection specific pause resume for connection 3</description>
<addressOffset>0x14228</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA_LIST_INDEX_LAST_ACK_INDEX_C1</name>
<description>Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded.
The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4.
Hardware will start the next data transmission from the index indicated by this field.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_LIST_HEAD_UP_C1</name>
<description>Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause.
The bit must be set every time the firmware needs to indicate the start/resume.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLV_MD_CONFIG_C1</name>
<description>This bit is set to configure the MD bit control when the design is in slave mode.
1 - MD bit will be decided on packet pending status
0 - MD bit will be decided on packet queued in next buffer status
This bit has valid only when MD_BIT_CLEAR bit is not set</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MD_C1</name>
<description>MD bit set to '1' indicates device has more data to be sent.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MD_BIT_CLEAR_C1</name>
<description>This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined'
1 - MD bit is exclusively controlled by software, based on status of bit [6].
0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true,
a) If there are packets queued for transmission.
b) If there is an acknowledgement awaited from the remote side for the packet transmitted.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PAUSE_DATA_C1</name>
<description>Pause data.
1 - pause data,
0 - do not pause.
The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared.
But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>KILL_CONN</name>
<description>Kills the connection immediately when the connection event is active</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>KILL_CONN_AFTER_TX</name>
<description>Kills the connection when the connection event is active and a TX is completed</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EMPTYPDU_SENT</name>
<description>This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CURRENT_PDU_INDEX_C1</name>
<description>The index of the transmit packet buffer that is currently in transmission/waiting for transmission.</description>
<bitRange>[15:12]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CONN_4_DATA_LIST_SENT</name>
<description>data list sent update and status for connection 4</description>
<addressOffset>0x14230</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF8F</resetMask>
<fields>
<field>
<name>LIST_INDEX__TX_SENT_3_0_C1</name>
<description>Write:Indicates the buffer index for which the SENT bit is being updated by firmware.
The default number of buffers in the IP is 5. The index range is 0-3.
Read: Reads TX_SENT[3:0].
The bits in this field indicate the status of the SENT bit in the hard-ware for each packet buffer. The bit values are
1 - queued
0 - no packet / packet ack received by hardware
Example1: If the read value is : 0x03, then packets in buffer 0 and buffer 1 are in the queue to be transmitted. All the other FIFOs are empty or hardware has cleared them after receiving acknowledgement.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_CLEAR_C1</name>
<description>Write: Used to set the SENT bit in hardware for the selected packet buffer.
1 - packet queued
When firmware has a packet to send, firmware first loads the next available packet buffer. Then the hardware SENT bit is set by writing 1 to this bit field along with the list_index field that identified the buffer index. This indicates that a packet has been queued in the data buffer for sending. This packet is now ready to be transmitted.
The SENT bit in hardware is cleared by hardware only when it has received an acknowledgement from the remote device.
Firmware typically does not clear the bit. However, It only clears the bit on its own if it needs to 'flush' a packet from the buffer, without waiting to receive acknowledgement from the remote device, firmware clears BIT7 along with the list_index specified.</description>
<bitRange>[7:7]</bitRange>
<access>write-only</access>
</field>
<field>
<name>BUFFER_NUM_TX_SENT_3_0_C1</name>
<description>Write: Indicates the buffer number for which SENT bit is updated by firmware. This is the mapping of the list index to the physical transmit buffer. The total number of transmit buffers is 16, can be shared with up to 8 connections</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_4_DATA_LIST_ACK</name>
<description>data list ack update and status for connection 4</description>
<addressOffset>0x14234</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x8F</resetMask>
<fields>
<field>
<name>LIST_INDEX__TX_ACK_3_0_C1</name>
<description>Write: Indicates the buffer index for which the ACK bit is being updated by firmware.
The default number of buffers in the IP is 5. The index range is 0-3.
Read: Reads TX_ACK[3:0]
If a particular bit is set, then the packet in the selected buffer has been transmitted (at least once) by the hardware and hardware is waiting for acknowledgement.
Example1 : If the read value is : 0x03, then packets in FIFO-0 and FIFO-1 are acknowledged by the remote device. These acknowledgements are pending to be processed by firmware.
Example2 : If the read value is : 0x02, then packet FIFO-1 is acknowledged by the remote device. This acknowledgement is pending to be processed by firmware.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_CLEAR_C1</name>
<description>Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that the acknowledgement for the transmit packet has been received and processed by firmware.
Firmware clears the ACK bit in the hardware by writing in this register only after the acknowledgement is processed successfully by firmware.
For clearing ack for a packet transmitted in fifo-index : '3', firm-ware will write '3' in the 'list-index' field and set this bit (BIT7) to 0.
This is the indication that the corresponding packet buffer identi-fied by List-Index is cleared of previous transmission and can be re-used for another packet from now on.
The ACK bit in hardware is set by hardware when it has success-fully transmitted a packet.</description>
<bitRange>[7:7]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CONN_4_CE_DATA_LIST_CFG</name>
<description>Connection specific pause resume for connection 4</description>
<addressOffset>0x14238</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA_LIST_INDEX_LAST_ACK_INDEX_C1</name>
<description>Data list index for start/resume. This field must be valid along with data_list_head_up and indicate the transmit packet buffer index at which the data is loaded.
The default number of buffers in the IP is 5,but may be customized for a customer. The buffers are in-dexed 0 to 4.
Hardware will start the next data transmission from the index indicated by this field.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_LIST_HEAD_UP_C1</name>
<description>Update the first packet buffer index ready for transmis-sion to start/resume data transfer after a pause.
The bit must be set every time the firmware needs to indicate the start/resume.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLV_MD_CONFIG_C1</name>
<description>This bit is set to configure the MD bit control when the design is in slave mode.
1 - MD bit will be decided on packet pending status
0 - MD bit will be decided on packet queued in next buffer status
This bit has valid only when MD_BIT_CLEAR bit is not set</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MD_C1</name>
<description>MD bit set to '1' indicates device has more data to be sent.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MD_BIT_CLEAR_C1</name>
<description>This register field indicates whether the MD (More Data) bit needs to be controlled by 'software' or, 'hardware and software logic combined'
1 - MD bit is exclusively controlled by software, based on status of bit [6].
0 - MD Bit in the transmitted PDU is controlled by software and hardware logic. MD bit is set in transmitted packet, only if the software has set the MD in bit [6] and either of the following conditions is true,
a) If there are packets queued for transmission.
b) If there is an acknowledgement awaited from the remote side for the packet transmitted.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PAUSE_DATA_C1</name>
<description>Pause data.
1 - pause data,
0 - do not pause.
The current_pdu_index in hardware does not move to next in-dex until pause_data is cleared.
But if the SENT bit is set for the current_pdu_index as which pause is set, data will be sent out</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>KILL_CONN</name>
<description>Kills the connection immediately when the connection event is active</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>KILL_CONN_AFTER_TX</name>
<description>Kills the connection when the connection event is active and a TX is completed</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EMPTYPDU_SENT</name>
<description>This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cleared by HW</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CURRENT_PDU_INDEX_C1</name>
<description>The index of the transmit packet buffer that is currently in transmission/waiting for transmission.</description>
<bitRange>[15:12]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MMMS_ADVCH_NI_ENABLE</name>
<description>Enable bits for ADV_NI, SCAN_NI and INIT_NI</description>
<addressOffset>0x14400</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>ADV_NI_ENABLE</name>
<description>This bit is used to enable the Advertisement NI timer and is valid when MMMS_ENABLE=1.
0 - ADV_NI timer is disabled
1 - ADV_NI timer is enabled
In this mode, the adv engine next instant is scheduled by firmware</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_NI_ENABLE</name>
<description>This bit is used to enable the SCAN NI timer and is valid when MMMS_ENABLE=1.
0 - SCAN_NI timer is disabled
1 - SCAN_NI timer is enabled
In this mode, the scan engine next instant is scheduled by firmware</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_NI_ENABLE</name>
<description>This bit is used to enable the INIT NI timer and is valid when MMMS_ENABLE=1.
0 - INIT_NI timer is disabled
1 - INIT_NI timer is enabled
In this mode, the init engine next instant is scheduled by firmware</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MMMS_ADVCH_NI_VALID</name>
<description>Next instant valid for ADV, SCAN, INIT</description>
<addressOffset>0x14404</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>ADV_NI_VALID</name>
<description>This bit indicates if the programmed advertisement NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the advertisment event
0 - ADV_NI timer is not valid
1 - ADV_NI timer is valid</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCAN_NI_VALID</name>
<description>This bit indicates if the programmed scan NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the scanner event
0 - SCAN_NI timer is not valid
1 - SCAN_NI timer is valid</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INIT_NI_VALID</name>
<description>This bit indicates if the programmed initiator NI_TIMER is valid. FW sets this bit to indicate that the NI_TIMER is programmed. HW clears this bit on servicing the initiator event
0 - INIT_NI timer is not valid
1 - INIT_NI timer is valid</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MMMS_ADVCH_NI_ABORT</name>
<description>Abort the next instant of ADV, SCAN, INIT</description>
<addressOffset>0x14408</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>ADVCH_NI_ABORT</name>
<description>FW can use this bit to clear an unserviced NI_VALID for Advertisement or scanner or initiator. HW will clear NI_VALID for ADV/SCAN/INIT if the event has not yet started</description>
<bitRange>[0:0]</bitRange>
<access>write-only</access>
</field>
<field>
<name>ADVCH_ABORT_STATUS</name>
<description>The link layer hardware logic will set this bit when the NI_TIMER is aborted. Firmware to clear this by writing 1'b1 to this register bit</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_PARAM_NEXT_SUP_TO</name>
<description>Register to configure the supervision timeout for next scheduled connection</description>
<addressOffset>0x14410</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>NEXT_SUP_TO_LOAD</name>
<description>HW uses this register to load the Supervision timeout Next instant from the connection memory. This can be used by firmware as a failsafe option when the hardware load is disabled. In all other conditions, this register should not be updated by firmware.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CONN_PARAM_ACC_WIN_WIDEN</name>
<description>Register to configure Accumulated window widening for next scheduled connection</description>
<addressOffset>0x14414</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>ACC_WINDOW_WIDEN</name>
<description>HW uses this register to load the accumulated window windeing value from the connection memory. This can be used by firmware as a failsafe option when the hardware load is disabled. In all other conditions, this register should not be updated by firmware.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HW_LOAD_OFFSET</name>
<description>Register to configure offset from connection anchor point at which connection parameter memory should be read</description>
<addressOffset>0x14420</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x4</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>LOAD_OFFSET</name>
<description>Load Offset in us before connection event at which the connection parameters are loaded from memory, granularity is in 1us</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADV_RAND</name>
<description>Random number generated by Hardware for ADV NI calculation</description>
<addressOffset>0x14424</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x7</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>ADV_RAND</name>
<description>Random ADV delay, to be used for ADV next instant calculation. The granularity is in BT slot</description>
<bitRange>[3:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MMMS_RX_PKT_CNTR</name>
<description>Packet Counter of packets in RX FIFO in MMMS mode</description>
<addressOffset>0x14428</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>MMMS_RX_PKT_CNT</name>
<description>Count of all packets in the RX FIFO in MMMS mode</description>
<bitRange>[5:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>CONN_RX_PKT_CNTR[%s]</name>
<description>Packet Counter for Individual connection index</description>
<addressOffset>0x14430</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>RX_PKT_CNT</name>
<description>Number of packets received for the connection. Incremented when the packet is received during the connection event and decremented when firmware has processed the packet. The register field FW_PKT_RCV_CONN_INDEX should be programmed before firmware issues the packet received command</description>
<bitRange>[5:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>WHITELIST_BASE_ADDR</name>
<description>Whitelist base address</description>
<addressOffset>0x14800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>WL_BASE_ADDR</name>
<description>Device address values written to white list memory are written as 16-bit wide address.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RSLV_LIST_PEER_IDNTT_BASE_ADDR</name>
<description>Resolving list base address for storing Peer Identity address</description>
<addressOffset>0x148C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RSLV_LIST_PEER_IDNTT_BASE_ADDR</name>
<description>Device address values written to the list are written as 16-bit wide address.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RSLV_LIST_PEER_RPA_BASE_ADDR</name>
<description>Resolving list base address for storing resolved Peer RPA address</description>
<addressOffset>0x14980</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RSLV_LIST_PEER_RPA_BASE_ADDR</name>
<description>Device address values written to the list are written as 16-bit wide address.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR</name>
<description>Resolving list base address for storing Resolved received INITA RPA</description>
<addressOffset>0x14A40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR</name>
<description>Device address values written to the list are written as 16-bit wide address.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RSLV_LIST_TX_INIT_RPA_BASE_ADDR</name>
<description>Resolving list base address for storing generated TX INITA RPA</description>
<addressOffset>0x14B00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RSLV_LIST_TX_INIT_RPA_BASE_ADDR</name>
<description>Device address values written to the list are written as 16-bit wide address.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
<cluster>
<name>BLESS</name>
<description>Bluetooth Low Energy Subsystem Miscellaneous</description>
<addressOffset>0x0001F000</addressOffset>
<register>
<name>DDFT_CONFIG</name>
<description>BLESS DDFT configuration register</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F1F03</resetMask>
<fields>
<field>
<name>DDFT_ENABLE</name>
<description>Enables the DDFT output from BLESS
1: DDFT is enabled
0: DDFT is disabled</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLERD_DDFT_EN</name>
<description>Enables the DDFT inputs from CYBLERD55 chip
1: DDFT inputs are enabled
0: DDFT inputs are disabled</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DDFT_MUX_CFG1</name>
<description>dbg_mux_pin1 selection, combine with BLERD and BLESS
5'h00 blerd_ddft_out[0]
5'h01 rcb_tx_fifo_empty
5'h02 hv_ldo_lv_detect_raw
5'h03 dbus_rx_en
5'h04 1'b0
5'h05 clk_switch_to_sysclk
5'h06 ll_clk_en_sync
5'h07 dsm_entry_stat
5'h08 proc_tx_en
5'h09 rssi_read_start
5'h0A tx_2mbps
5'h0B rcb_bus_busy
5'h0C hv_ldo_en_mt (act_stdbyb)
5'h0D ll_eco_clk_en
5'h0E blerd_reset_assert
5'h0F hv_ldo_byp_n
5'h10 hv_ldo_lv_detect_mt
5'h11 enable_ldo
5'h12 enable_ldo_dly
5'h13 bless_rcb_le_out
5'h14 bless_rcb_clk_out
5'h15 bless_dig_ldo_on_out
5'h16 bless_act_ldo_en_out
5'h17 bless_clk_en_out
5'h18 bless_buck_en_out
5'h19 bless_ret_switch_hv_out
5'h1A efuse_rw_out
5'h1B efuse_avdd_out
5'h1C efuse_config_efuse_mode
5'h1D bless_dbus_tx_en_pad
5'h1E bless_bpktctl_rd
5'h1F 1'b0</description>
<bitRange>[12:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DDFT_MUX_CFG2</name>
<description>dbg_mux_pin2 selection, combine with BLERD and BLESS
5'h00 blerd_ddft_out[1]
5'h01 rcb_rx_fifo_empty
5'h02 ll_decode_rxdata
5'h03 dbus_tx_en
5'h04 fw_clk_en
5'h05 interrupt_ll_n
5'h06 llh_st_sm
5'h07 llh_st_dsm
5'h08 proc_rx_en
5'h09 rssi_rx_done
5'h0A rx_2mbps
5'h0B rcb_ll_ctrl
5'h0C hv_ldo_byp_n
5'h0D reset_deassert
5'h0E rcb_intr
5'h0F rcb_ll_intr
5'h10 hv_ldo_en_mt (act_stdbyb)
5'h11 hv_ldo_lv_detect_raw
5'h12 bless_rcb_data_in
5'h13 bless_xtal_en_out
5'h14 bless_isolate_n_out
5'h15 bless_reset_n_out
5'h16 bless_ret_ldo_ol_hv_out
5'h17 bless_txd_rxd_out
5'h18 tx_rx_ctrl_sel
5'h19 bless_bpktctl_cy
5'h1A efuse_cs_out
5'h1B efuse_pgm_out
5'h1C efuse_sclk_out
5'h1D hv_ldo_lv_detect_mt
5'h1E enable_ldo
5'h1F enable_ldo_dly</description>
<bitRange>[20:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>XTAL_CLK_DIV_CONFIG</name>
<description>Crystal clock divider configuration register</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>SYSCLK_DIV</name>
<description>System clock pre-divider value. The 24 MHz crystal clock is divided to generate the system clock.
0: NO_DIV: SYSCLK= XTALCLK/1
1: DIV_BY_2: SYSCLK= XTALCLK/2
2: DIV_BY_4: SYSCLK= XTALCLK/4
3: DIV_BY_8: SYSCLK= XTALCLK/8</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LLCLK_DIV</name>
<description>Link Layer clock pre-divider value. The 24 MHz crystal clock is divided to generate the Link Layer clock.
0: NO_DIV: LLCLK= XTALCLK/1
1: DIV_BY_2: LLCLK= XTALCLK/2
2: DIV_BY_4: LLCLK= XTALCLK/4
3: DIV_BY_8: LLCLK= XTALCLK/8</description>
<bitRange>[3:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_STAT</name>
<description>Link Layer interrupt status register</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>DSM_ENTERED_INTR</name>
<description>On a firmware request to LL to enter into state machine, working on LF clock, LL transitions into Deep Sleep Mode and asserts this interrupt. The interrupt can be cleared by writing one into this location.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSM_EXITED_INTR</name>
<description>On a firmware request to LL to exit from Deep Sleep Mode, working on LF clock, LL transitions from Deep Sleep Mode and asserts this interrupt when the Deep Sleep clock gater is turned ON. The interrupt can be cleared by writing one into this location.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RCBLL_DONE_INTR</name>
<description>RCB transaction Complete</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BLERD_ACTIVE_INTR</name>
<description>CYBLERD55 is in active mode. RF is active</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RCB_INTR</name>
<description>RCB controller Interrupt - Refer to RCB_INTR_STAT register</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>LL_INTR</name>
<description>LL controller interrupt - Refer to EVENT_INTR register</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>GPIO_INTR</name>
<description>GPIO interrupt</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EFUSE_INTR</name>
<description>This bit when set by efuse controller logic when the efuse read/write is completed</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>XTAL_ON_INTR</name>
<description>enabled crystal stable signal rising edge interrupt. The interrupt can be cleared by writing one into this location.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENC_INTR</name>
<description>Encryption Interrupt Triggered</description>
<bitRange>[9:9]</bitRange>
<access>read-only</access>
</field>
<field>
<name>HVLDO_LV_DETECT_POS</name>
<description>This interrupt is set on HVLDO LV Detector Rise edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLDO_LV_DETECT_NEG</name>
<description>This interrupt is set on HVLDO LV Detector Fall edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Link Layer interrupt mask register</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FFF</resetMask>
<fields>
<field>
<name>DSM_EXIT</name>
<description>When the Link Layer is in Deep Sleep Mode, firmware can set this bit to wake the Link Layer.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSM_ENTERED_INTR_MASK</name>
<description>Masks the DSM Entered Interrupt, when disabled.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSM_EXITED_INTR_MASK</name>
<description>Masks the DSM Exited Interrupt, when disabled.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>XTAL_ON_INTR_MASK</name>
<description>Masks the Crystal Stable Interrupt, when disabled.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RCBLL_INTR_MASK</name>
<description>Mask for RCBLL interrupt</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLERD_ACTIVE_INTR_MASK</name>
<description>Mask for CYBLERD55 Active Interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RCB_INTR_MASK</name>
<description>Mask for RCB interrupt</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LL_INTR_MASK</name>
<description>Mask for LL interrupt</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>GPIO_INTR_MASK</name>
<description>Mask for GPIO interrupt</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EFUSE_INTR_MASK</name>
<description>This bit enables the efuse interrupt to firmware</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENC_INTR_MASK</name>
<description>Mask for Encryption interrupt</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLDO_LV_DETECT_POS_MASK</name>
<description>Mask for HVLDO LV Detector Rise edge interrupt</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLDO_LV_DETECT_NEG_MASK</name>
<description>Mask for HVLDO LV Detector Fall edge interrupt</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LL_CLK_EN</name>
<description>Link Layer primary clock enable</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x26</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>CLK_EN</name>
<description>Set this bit 1 to enable the clock to Link Layer.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CY_CORREL_EN</name>
<description>If MXD_IF option is 1, this bit needs to be set to enable configuring the correlator through BLELL.DPLL_CONFIG register</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MXD_IF_OPTION</name>
<description>1: MXD IF option 0: CYBLERD55 correlates Access Code
0: MXD IF option 1: LL correlates Access Code</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SEL_RCB_CLK</name>
<description>0: AHB clock (clk_sys) is used as the clock for RCB access
1: LL clock (clk_eco) is used as the clock for RCB access</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLESS_RESET</name>
<description>0: No Soft Reset
1: Initiate Soft Reset
Setting this bit will reset entire BLESS_VER3</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DPSLP_HWRCB_EN</name>
<description>Controls the DPSLP entry and exit writes to RD and controls the active domain reset and clock.
1 - LL HW controls the RD active domain reset and clock.
0 - The RD active domain reset and clock. Must be controlled by the FW</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LF_CLK_CTRL</name>
<description>BLESS LF clock control and BLESS revision ID indicator</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40000000</resetValue>
<resetMask>0xE0000003</resetMask>
<fields>
<field>
<name>DISABLE_LF_CLK</name>
<description>When set to 1, gates the LF clock input to the Link Layer. Ths is done for extended DSM mode where the DSM state machine needs to be forzen to prevent a default auto exit.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE_ENC_CLK</name>
<description>This bit is used to enable the clock to the encryption engine
0 - Disable the clock to ENC engine
1 - Enable the clock to ENC engine</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>M0S8BLESS_REV_ID</name>
<description>Indicates the m0s8bless IP revision.</description>
<bitRange>[31:29]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>EXT_PA_LNA_CTRL</name>
<description>External TX PA and RX LNA control</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3E</resetMask>
<fields>
<field>
<name>ENABLE_EXT_PA_LNA</name>
<description>When set to 1, enables the external PA &amp; LNA</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CHIP_EN_POL</name>
<description>Controls the polarity of the chip enable control signal
0 - High enable, low disable
1 - Low enable, High disable</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PA_CTRL_POL</name>
<description>Controls the polarity of the PA control signal
0 - High enable, low disable
1 - Low enable, High disable</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LNA_CTRL_POL</name>
<description>Controls the polarity of the LNA control signal
0 - High enable, low disable
1 - Low enable, High disable</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT_EN_DRIVE_VAL</name>
<description>Configures the drive value on the output enables of PA, LNA and CHI_EN signals
0 - drive 0 on the output enable signals
1 - drive 1 on the output enable signals</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LL_PKT_RSSI_CH_ENERGY</name>
<description>Link Layer Last Received packet RSSI/Channel energy and channel number</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x7FFFFF</resetMask>
<fields>
<field>
<name>RSSI</name>
<description>This field captures the RSSI of the packet when a packet reception is complete or gives the Channel energy when a Receive cycle is over without packet reception.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_CHANNEL</name>
<description>This field indicates the last channel for which the RSSI is captured</description>
<bitRange>[21:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PKT_RSSI_OR_CH_ENERGY</name>
<description>This field indicates if the captured RSSI is for a received packet or is the channel energy</description>
<bitRange>[22:22]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BT_CLOCK_CAPT</name>
<description>BT clock captured on an LL DSM exit</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>BT_CLOCK</name>
<description>This field captures the LF BT clock captured on an LL DSM exit. This register is valid only when MT_STATUS.LL_CLK_STATE is set. This value may be used to manage the low power entry.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MT_CFG</name>
<description>MT Configuration Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8100000</resetValue>
<resetMask>0xFFFFFFF</resetMask>
<fields>
<field>
<name>ENABLE_BLERD</name>
<description>This register bit needs to be set to enable CYBLERD55
1'b1 - CYBLERD55 enabled
1'b0 - CYBLERD55 disabled
On power up this bit needs to be set to make CYBLERD55 active.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DEEPSLEEP_EXIT_CFG</name>
<description>This register bit indicates the source for PSoC DeepSleep exit to BLESS
1'b0 - act_power_good from SRSS indicates PSoC DeepSleep exit
1'b1 - MT_CFG.DEEPSLEEP_EXITED indicates PSoC DeepSleep exit</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DEEPSLEEP_EXITED</name>
<description>This register bit is used by FW to indicate that PSoC is out of DeepSleep
1'b0 - PSoC in DeepSleep
1'b1 - PSoC out of DeepSleep
This bit is cleared by HW on exit from DPSLP</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_LDO_NOT_BUCK</name>
<description>This register bit specifies whether the Active LDO or BUCK in CYBLERD55 is used in active mode</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE_HVLDO_BYPASS</name>
<description>This register should be set to override the HW generated signal to HVLDO. When set HVLDO_BYPASS is driven to the IP</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLDO_BYPASS</name>
<description>Override value for HVLDO BYPASS
1'b0: bypass the HVLDO
1'b1: Do not bypass the HVLDO</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE_ACT_REGULATOR</name>
<description>This register should be set to override the HW generated signal to enable ACTIVE_LDO/BUCK. When set ACT_REGULATOR_EN is driven to CYBLERD55</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_REGULATOR_EN</name>
<description>Override value for ACT_LDO_EN/BUCK_EN</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE_DIG_REGULATOR</name>
<description>This register should be set to override the HW generated signal to Digital regulator of CYBLERD55. When set DIG_REGULATOR_EN is driven to CYBLERD55</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIG_REGULATOR_EN</name>
<description>Override value for digital regulator of CYBLERD55</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE_RET_SWITCH</name>
<description>This register should be set to override the HW generated signal to the retention switch of CYBLERD55. When set OVERRIDE_RET_SWITCH is driven to the IP</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RET_SWITCH</name>
<description>Override value for RET_SWITCH</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE_ISOLATE</name>
<description>This register should be set to override the HW generated isolation signal to CYBLERD55. When set ISOLATE_N is driven to the IP</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ISOLATE_N</name>
<description>Override value for isolation to CYBLERD55</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE_LL_CLK_EN</name>
<description>This register should be set to override the HW generated ECO Clock gate. When set LL_CLK_EN is used to gate the clock</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LL_CLK_EN</name>
<description>Override value for LL Clock gate</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE_HVLDO_EN</name>
<description>This register should be set to override the HW generated enable to HVLSO. When set HVLDO_EN is used.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLDO_EN</name>
<description>Overrie value for HVLDO enable
1'b1: switch to Active LDO
1'b0: switch to standby LDO</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DPSLP_ECO_ON</name>
<description>This bit when set indicates that ECO clock should be kept on even in BLESS DPSLP. This bit must be toggled only when the Link Layer is active.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE_RESET_N</name>
<description>This register should be set to override the HW generated reset to CYBLERD55. When set RESET_N is used.</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESET_N</name>
<description>Overrie value for CYBLERD55 RESET_N</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE_XTAL_EN</name>
<description>This register should be set to override the HW generated XTAL_EN to CYBLERD55. When set XTAL_EN is used.</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>XTAL_EN</name>
<description>Overrie value for CYBLERD55 XTAL_EN</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE_CLK_EN</name>
<description>This register should be set to override the HW generated CLK_EN to CYBLERD55. When set CLK_EN is used.</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLERD_CLK_EN</name>
<description>Overrie value for CYBLERD55 CLK_EN</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE_RET_LDO_OL</name>
<description>This register should be set to override the HW generated RET_LDO_OL_HV to CYBLERD55. When set CLK_EN is used.</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RET_LDO_OL</name>
<description>Overrie value for CYBLERD55 RET_LDO_OL_HV</description>
<bitRange>[26:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLDO_POR_HV</name>
<description>Reset for HVLDO
1'b1 - HVLDO Disabled
1'b0 - HVLDO Enabled</description>
<bitRange>[27:27]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MT_DELAY_CFG</name>
<description>MT Delay configuration for state transitions</description>
<addressOffset>0xA4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HVLDO_STARTUP_DELAY</name>
<description>This register specifies the startup delay for the HVLDO interms of number of LF Clock cycles. FW has to program this register based on the selected LF clock frequency</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ISOLATE_DEASSERT_DELAY</name>
<description>This register specifies the time from switching the CYBLERD55 logic to Active regulator to removal of ISOLATE_N</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_TO_SWITCH_DELAY</name>
<description>This register specifies the time from assertion of ISOLATE_N to switching the CYBLERD55 logic to Retention LDO</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HVLDO_DISABLE_DELAY</name>
<description>This register specifies the time from disabling XTAL to switching of the HVLDO.</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MT_DELAY_CFG2</name>
<description>MT Delay configuration for state transitions</description>
<addressOffset>0xA8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OSC_STARTUP_DELAY_LF</name>
<description>This register specifies the time for OSC Startup. After this delay, clock is enabled to the link layer. Clock is enabled after OSC_STARTUP_DELAY + 1 LF clock cycles. If PSoC was in DPSLP when XTAL is enabled, then the wakeup delay will be OSC_STARTUP_DELAY + 1 + PSoC Wakeup time. Minimum value to be programmed in 1. This is equivalent to Link Layer register WAKEUP_CONFIG.OSC_STARTUP_DELAY, but is specified in LF cycles</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSM_OFFSET_TO_WAKEUP_INSTANT_LF</name>
<description>This register specifies the pre-processing time required in Link Layer. This is esentially the time from CLK_EN (ungating clock in CYBLERD55) to the time when logic in CYBLERD55 is switched to Active mode Regulator.The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. This is equivalent to Link Layer register WAKEUP_CONFIG.DSM_OFFSET_TO_WAKEUP_INSTANT_LF, but is specified in LF cycles.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_STARTUP_DELAY</name>
<description>This register specifes the Active Regulator startup time in CYBLERD55. The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. The digital LDO will be turned on after this time elapses</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIG_LDO_STARTUP_DELAY</name>
<description>This register specifes the Digital LDO startup time in CYBLERD55.The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency. The logic in CYBLERD55 is switched to Active mode Regulator after this (ACT_STARTUP_DELAY + DIG_LDO_STARTUP_DELAY)</description>
<bitRange>[31:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MT_DELAY_CFG3</name>
<description>MT Delay configuration for state transitions</description>
<addressOffset>0xAC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>XTAL_DISABLE_DELAY</name>
<description>This register specifies the time from switching of logic to Retention LDO in CYBLERD55 to XTAL Disable. This should include the post processing time
The delay is in terms of LF Clock cycles. FW has to program this register based on the selected LF clock frequency.
At the minimum XTAL_DISABLE_DELAY should be the sum of DIG_LDO_DISABLE_DELAY and the powerdown time of ACTIVE_LDO</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIG_LDO_DISABLE_DELAY</name>
<description>This field holds the delay from the time of diabling Digital LDO to the time at which ACTIVE regulator is disabled</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VDDR_STABLE_DELAY</name>
<description>This field holds the delay after HVLDO Startup to VDDR Stable. Refer to memo AKK-410</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MT_VIO_CTRL</name>
<description>MT Configuration Register to control VIO switches</description>
<addressOffset>0xB0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>SRSS_SWITCH_EN</name>
<description>Enable to turn on HVLDO (One leg)
1'b0 - Switch is turned off
1'b1 - Switch is turned on</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SRSS_SWITCH_EN_DLY</name>
<description>Enable to turn on HVLDO (All legs). This must be enabled 64us after enabling SRSS_SWITCH_EN
1'b0 - Switch is turned off
1'b1 - Switch is turned on</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MT_STATUS</name>
<description>MT Status Register</description>
<addressOffset>0xB4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>BLESS_STATE</name>
<description>1'b0 - BLESS in DPSLP state
1'b1 - BLESS in ACTIVE state</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MT_CURR_STATE</name>
<description>This register reflects the current state of the MT FSM
4'h0 - IDLE
4'h1 - BLERD_DEEPSLEEP
4'h2 - HVLDO_STARTUP
4'h3 - WAIT_CLK
4'h4 - BLERD_IDLE
4'h5 - SWITCH_EN
4'h6 - ACTIVE
4'h7 - ISOLATE
4'h8 - WAIT_IDLE
4'h9 - XTAL_DISABLE
4'hA - HVLDO_DISABLE</description>
<bitRange>[4:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>HVLDO_STARTUP_CURR_STATE</name>
<description>This register reflects the current state of the HVLDO Startup FSM
3'h0 - HVLDO_OFF
3'h1 - HVLDO_WAIT
3'h2 - HVLDO_SAMPLE
3'h3 - HVLDO_ENABLED
3'h4 - HVLDO_SET_BYPASS</description>
<bitRange>[7:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>LL_CLK_STATE</name>
<description>This bit indicates when the Link Layer registers are accessible upon a DSM exit. This bit should not be used after a DSM entry command has been issued.
1'b0 - Link Layer clock is not available
1'b1 - Link Layer clock is active</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PWR_CTRL_SM_ST</name>
<description>Link Layer Power Control FSM Status Register</description>
<addressOffset>0xB8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>PWR_CTRL_SM_CURR_STATE</name>
<description>This register reflects the current state of the LL Power Control FSM
4'h0 - IDLE
4'h1 - SLEEP
4'h2 - DEEP_SLEEP
4'h4 - WAIT_OSC_STABLE
4'h5 - INTR_GEN
4'h6 - ACTIVE
4'h7 - REQ_RF_OFF</description>
<bitRange>[3:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HVLDO_CTRL</name>
<description>HVLDO Configuration register</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x8000005F</resetMask>
<fields>
<field>
<name>ADFT_EN</name>
<description>ADFT enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADFT_CTRL</name>
<description>ADFT select</description>
<bitRange>[4:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREF_EXT_EN</name>
<description>Vref ext input enable.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STATUS</name>
<description>hvldo LV detect status</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MISC_EN_CTRL</name>
<description>Radio Buck and Active regulator enable control</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>BUCK_EN_CTRL</name>
<description>Buck enable control. This must be programmed before enabling the Radio.
1'b1 - Buck enable output to radio is tied to 0
1'b0 - Buck enable output to radio is controlled from Mode transition FSM</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_REG_EN_CTRL</name>
<description>Active regulator enable control. This must be programmed before enabling the Radio.
1'b0 - Active regulator enable output to radio is tied to 0
1'b1 - Active regulator enable output to radio is controlled from Mode transition FSM</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LPM_DRIFT_EN</name>
<description>Controls the LPM drift calculation.
1 - Enables the LPM drift mod
0 - Disables the LPM drift mod</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LPM_DRIFT_MULTI</name>
<description>Controls the LPM drift multi level compensation.
1 - Enables the LPM drift multi comp
0 - Disables the LPM drift multi comp</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LPM_ENTRY_CTRL_MODE</name>
<description>Controls the LPM entry control mode
1 - LPM can be entered in the same slot as the previous LPM exit
0 - LPM must not be entered in the same slot or the subsequent slot as the last LPM exit</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EFUSE_CONFIG</name>
<description>EFUSE mode configuration register</description>
<addressOffset>0xD0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>EFUSE_MODE</name>
<description>This register enables the efuse mode in m0s8bless_ver3</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EFUSE_READ</name>
<description>This bit when set by firmware enables the read from EFUSE macro. It is cleared when the efuse read is completed</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EFUSE_WRITE</name>
<description>This bit when set by firmware enables the write to EFUSE macro. It is cleared when the efuse write is completed</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EFUSE_TIM_CTRL1</name>
<description>EFUSE timing control register (common for Program and Read modes)</description>
<addressOffset>0xD4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x111201C0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCLK_HIGH</name>
<description>Decides the duration of TPGM (in Program mode) or TCKHP (in Read mode)
TPGM: Burning Time
TCKHP : SCLK high Period</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCLK_LOW</name>
<description>Duration of SCLK LOW (TCLKP_R) or TCKLP_P</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CS_SCLK_SETUP_TIME</name>
<description>This register specifies the setup time between CS and SCLK (TSR_CLK)</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CS_SCLK_HOLD_TIME</name>
<description>This register specifies the hold time between CS and SCLK
(THR_CLK)</description>
<bitRange>[23:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RW_CS_SETUP_TIME</name>
<description>This field decides setup time between RW &amp; CS (TSR_RW: in read mode) or RW &amp; AVDD (TSP_RW: in Program mode).
TSR_RW: RW to CS setup time into Read mode
TSP_RW: RW to AVDD setup time into program mode</description>
<bitRange>[27:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RW_CS_HOLD_TIME</name>
<description>This field decides hold time between RW &amp; CS (THR_RW: in read mode) or RW &amp; AVDD (THP_RW: in Program mode).
THR_RW: RW to CS hold time out of Read mode
THP_RW: RW to AVDD hold time out of program mode</description>
<bitRange>[31:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EFUSE_TIM_CTRL2</name>
<description>EFUSE timing control Register (for Read)</description>
<addressOffset>0xD8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x102</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>DATA_SAMPLE_TIME</name>
<description>This register specifies the time for data sampling from SCLK HIGH
(TCKDQ_H)</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DOUT_CS_HOLD_TIME</name>
<description>Wait time
DOUT to CS hold time out of read mode (TDQH)</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EFUSE_TIM_CTRL3</name>
<description>EFUSE timing control Register (for Program)</description>
<addressOffset>0xDC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3A3A11</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>PGM_SCLK_SETUP_TIME</name>
<description>PGM to SCLK setup time (TS_PGM)
PGM_SCLK_SETUP_TIME &lt;CS_SCLK_SETUP_TIME</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PGM_SCLK_HOLD_TIME</name>
<description>PGM to SCLK hold time (TH_PGM)</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AVDD_CS_SETUP_TIME</name>
<description>AVDD to CS setup time into program mode (TSP_AVDD_CS)</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AVDD_CS_HOLD_TIME</name>
<description>AVDD to CS hold time out of program mode (THP_AVDD_CS)</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EFUSE_RDATA_L</name>
<description>EFUSE Lower read data</description>
<addressOffset>0xE0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>This register has the read value from the Efuse macro, fuse bits[31:0]</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>EFUSE_RDATA_H</name>
<description>EFUSE higher read data</description>
<addressOffset>0xE4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>This register has the read value from the Efuse macro, fuse bits[63:32]</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>EFUSE_WDATA_L</name>
<description>EFUSE lower write word</description>
<addressOffset>0xE8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>This register has the write value to the Efuse macro, fuse bits[31:0]</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EFUSE_WDATA_H</name>
<description>EFUSE higher write word</description>
<addressOffset>0xEC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>This register has the write value to the Efuse macro, fuse bits[63:32]</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIV_BY_625_CFG</name>
<description>Divide by 625 for FW Use</description>
<addressOffset>0xF0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF02</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description>This bit enables the divider for use by FW
1'b0 - divider used by LL
1'b1 - divider can be used by FW
This divider can only be used in MMMS mode. Do not enable for legacy operation</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIVIDEND</name>
<description>This field holds the dividend</description>
<bitRange>[23:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIV_BY_625_STS</name>
<description>Output of divide by 625 divider</description>
<addressOffset>0xF4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x100</resetValue>
<resetMask>0x3FF3F</resetMask>
<fields>
<field>
<name>QUOTIENT</name>
<description>Quotient value from the divider. Available 1 cycle after dividend is programmed.</description>
<bitRange>[5:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>REMAINDER</name>
<description>Remainder value from the divider. Available 1 cycle after dividend is programmed.</description>
<bitRange>[17:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PACKET_COUNTER0</name>
<description>Packet counter 0</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PACKET_COUNTER_LOWER</name>
<description>Lower 32-bits of the packet counter value passed as part of Nonce for the packet to be encrypted.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PACKET_COUNTER2</name>
<description>Packet counter 2</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>PACKET_COUNTER_UPPER</name>
<description>Upper 8 bits of the packet counter value passed as part of Nonce for the packet to be encrypted.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IV_MASTER0</name>
<description>Master Initialization Vector 0</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IV_MASTER</name>
<description>This is the IVm field, which contains the master's portion of the initialization vector.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IV_SLAVE0</name>
<description>Slave Initialization Vector 0</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IV_SLAVE</name>
<description>This is the IVs field, which contains the slave's portion of the initialization vector.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>ENC_KEY[%s]</name>
<description>Encryption Key register 0-3</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENC_KEY</name>
<description>The encryption key / session key which is used in ECB encryption, CCM encryption and CCM decryption.</description>
<bitRange>[31:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>MIC_IN0</name>
<description>MIC input register</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MIC_IN</name>
<description>This is the MIC field used for CCM decryption.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MIC_OUT0</name>
<description>MIC output register</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MIC_OUT</name>
<description>This is the MIC generated during CCM encryption.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ENC_PARAMS</name>
<description>Encryption Parameter register</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>DATA_PDU_HEADER</name>
<description>LLID of the packet.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PAYLOAD_LENGTH_LSB</name>
<description>Length of the input data.</description>
<bitRange>[6:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIRECTION</name>
<description>The directionBit shall be set to '1' for Data Channel PDUs sent by the master and set to '0' for Data Channel PDUs sent by the slave.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PAYLOAD_LENGTH_LSB_EXT</name>
<description>3 Most significant bits of the LS byte of the length of the input data. Valid only when DLE is enabled.
When DLE is enabled total ENC payload length = {PAYLOAD_LENGTH_LSB_EXT, PAYLOAD_LENGTH_LSB}</description>
<bitRange>[10:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MEM_LATENCY_HIDE</name>
<description>Controls the encryption memory access mode. Valid only when DLE is enabled.
0 - The AES is idle while memory fetch/store in progress.
1- The AES is pipelined while memory fetch/store in progress.</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ENC_CONFIG</name>
<description>Encryption Configuration</description>
<addressOffset>0x12C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FFFF07</resetMask>
<fields>
<field>
<name>START_PROC</name>
<description>1 Start the AES processing</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ECB_CCM</name>
<description>0 - CCM
1 - ECB</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DEC_ENC</name>
<description>Decryption/Encryption
0 - Encrypt
1 - Decrypt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PAYLOAD_LENGTH_MSB</name>
<description>MS byte of the length of the input data when B0 needs to be completely configurable. Valid only when AES_B0_DATA_OVERRIDE is enabled.
When AES_B0_DATA_OVERRIDE is enabled total ENC payload length = {PAYLOAD_LENGTH_MSB, PAYLOAD_LENGTH_MSB, PAYLOAD_LENGTH}</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>B0_FLAGS</name>
<description>LS byte of the input data when B0 needs to be completely configurable. Valid only when AES_B0_DATA_OVERRIDE is enabled.</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AES_B0_DATA_OVERRIDE</name>
<description>Configuration to use B0 DATA provided by FW for CCM computation</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ENC_INTR_EN</name>
<description>Encryption Interrupt enable</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>AUTH_PASS_INTR_EN</name>
<description>Authentication interrupt enable
0 - Disable
1 - Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ECB_PROC_INTR_EN</name>
<description>ECB processed interrupt enable
0 - Disable
1 - Enable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CCM_PROC_INTR_EN</name>
<description>CCM processed interupt enable
0 - Disable
1 - Enable</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ENC_INTR</name>
<description>Encryption Interrupt status and clear register</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>AUTH_PASS_INTR</name>
<description>Authentication interrupt.
0x1- indicates MIC matched
0x0 -indicated MIC mismatched
Writing 1 to this register clears the interrupt.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ECB_PROC_INTR</name>
<description>ECB processed interrupt.
Writing 1 to this register clears the interrupt.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CCM_PROC_INTR</name>
<description>CCM processed interrupt.
Writing 1 to this register clears the interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IN_DATA_CLEAR</name>
<description>Clears the input data. Used for Zero padding of encryption for less than block sized data.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>B1_DATA_REG[%s]</name>
<description>Programmable B1 Data register (0-3)</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>B1_DATA</name>
<description>Programmable B1 Data register</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ENC_MEM_BASE_ADDR</name>
<description>Encryption memory base address</description>
<addressOffset>0x150</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENC_MEM</name>
<description>Data values written to Enc memory are written as 16-bit wide data. This memory is valid only if DLE is set.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TRIM_LDO_0</name>
<description>LDO Trim register 0</description>
<addressOffset>0xF00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x58</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ACT_LDO_VREG</name>
<description>To trim the regulated voltage in steps of 25mV typically</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ACT_LDO_ITAIL</name>
<description>To trim the bias currents for all the active mode blocks</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TRIM_LDO_1</name>
<description>LDO Trim register 1</description>
<addressOffset>0xF04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>ACT_REF_BGR</name>
<description>To trim active regulator reference voltage</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SB_BGRES</name>
<description>To trim standby regulator reference voltage</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TRIM_LDO_2</name>
<description>LDO Trim register 2</description>
<addressOffset>0xF08</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x60</resetValue>
<resetMask>0x7F</resetMask>
<fields>
<field>
<name>SB_BMULT_RES</name>
<description>To trim standby regulator beta-multiplier current</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SB_BMULT_NBIAS</name>
<description>To trim standby regulator beta-multiplier current</description>
<bitRange>[6:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TRIM_LDO_3</name>
<description>LDO Trim register 3</description>
<addressOffset>0xF0C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10</resetValue>
<resetMask>0x7F</resetMask>
<fields>
<field>
<name>LVDET</name>
<description>To trim the trip points of the LV-Detect block</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLOPE_SB_BMULT</name>
<description>To trim standby regulator beta-multiplier temp-co slope</description>
<bitRange>[6:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>TRIM_MXD[%s]</name>
<description>MXD die Trim registers</description>
<addressOffset>0xF10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MXD_TRIM_BITS</name>
<description>MXD trim bits</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TRIM_LDO_4</name>
<description>LDO Trim register 4</description>
<addressOffset>0xF30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>T_LDO</name>
<description>To debug post layout or post silicon</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TRIM_LDO_5</name>
<description>LDO Trim register 5</description>
<addressOffset>0xF34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RSVD</name>
<description>N/A</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>USBFS0</name>
<description>USB Host and Device Controller</description>
<headerStructName>USBFS</headerStructName>
<baseAddress>0x403F0000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<name>USBDEV</name>
<description>USB Device</description>
<addressOffset>0x00000000</addressOffset>
<register>
<dim>8</dim>
<dimIncrement>4</dimIncrement>
<name>EP0_DR[%s]</name>
<description>Control End point EP0 Data Register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA_BYTE</name>
<description>This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CR0</name>
<description>USB control 0 Register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DEVICE_ADDRESS</name>
<description>These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.
If USB bus reset is detected, these bits are initialized. Refer to CDT#293217.</description>
<bitRange>[6:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>USB_ENABLE</name>
<description>This bit enables the device to respond to USB traffic.
If USB bus reset is detected, this bit is cleared.
Note:
When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps. Refer to CDT#293217.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<description>USB control 1 Register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>REG_ENABLE</name>
<description>This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE_LOCK</name>
<description>This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUS_ACTIVITY</name>
<description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High
value until firmware clears it.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSVD_3</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP_INT_EN</name>
<description>USB SIE Data Endpoints Interrupt Enable Register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EP1_INTR_EN</name>
<description>Enables interrupt for EP1</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2_INTR_EN</name>
<description>Enables interrupt for EP2</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP3_INTR_EN</name>
<description>Enables interrupt for EP3</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP4_INTR_EN</name>
<description>Enables interrupt for EP4</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP5_INTR_EN</name>
<description>Enables interrupt for EP5</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP6_INTR_EN</name>
<description>Enables interrupt for EP6</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP7_INTR_EN</name>
<description>Enables interrupt for EP7</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP8_INTR_EN</name>
<description>Enables interrupt for EP8</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP_INT_SR</name>
<description>USB SIE Data Endpoint Interrupt Status</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EP1_INTR</name>
<description>Interrupt status for EP1</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2_INTR</name>
<description>Interrupt status for EP2</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP3_INTR</name>
<description>Interrupt status for EP3</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP4_INTR</name>
<description>Interrupt status for EP4</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP5_INTR</name>
<description>Interrupt status for EP5</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP6_INTR</name>
<description>Interrupt status for EP6</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP7_INTR</name>
<description>Interrupt status for EP7</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP8_INTR</name>
<description>Interrupt status for EP8</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP1_CNT0</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC7</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DATA_ERROR</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_VALID</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP1_CNT1</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP1_CR0</name>
<description>Non-control endpoint's control Register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept
IN: NAK
OUT: NAK</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept
IN: STALL
OUT: STALL</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Stall</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: NAK</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Accept data</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore
IN: NAK
OUT: Ignore</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACKED_NO</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACKED_YES</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USBIO_CR0</name>
<description>USBIO Control 0 Register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xE0</resetMask>
<fields>
<field>
<name>RD</name>
<description>Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device.
If D+=D- (SE0), this value is undefined.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DIFF_LOW</name>
<description>D+ &lt; D- (K state)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIFF_HIGH</name>
<description>D+ &gt; D- (J state)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TD</name>
<description>Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DIFF_K</name>
<description>Force USB K state (D+ is low D- is high).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIFF_J</name>
<description>Force USB J state (D+ is high D- is low).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSE0</name>
<description>Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TEN</name>
<description>USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually
transmitting is to force a resume state on the bus.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USBIO_CR2</name>
<description>USBIO control 2 Register</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RSVD_5_0</name>
<description>N/A</description>
<bitRange>[5:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TEST_PKT</name>
<description>This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSVD_7</name>
<description>N/A</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USBIO_CR1</name>
<description>USBIO control 1 Register</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20</resetValue>
<resetMask>0x20</resetMask>
<fields>
<field>
<name>DMO</name>
<description>This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit.
This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0.
This bit is valid if USB Device.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DPO</name>
<description>This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit.
This bit displays the output value of D+ pin when USB transmits SE0 or data.
This bit is valid if USB Device.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RSVD_2</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IOMODE</name>
<description>This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DYN_RECONFIG</name>
<description>USB Dynamic reconfiguration register</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>DYN_CONFIG_EN</name>
<description>This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP.
Use 0 for EP1, 1 for EP2, etc.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DYN_RECONFIG_EPNO</name>
<description>These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1.</description>
<bitRange>[3:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DYN_RECONFIG_RDY_STS</name>
<description>This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration.</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SOF0</name>
<description>Start Of Frame Register</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FRAME_NUMBER</name>
<description>It has the lower 8 bits [7:0] of the SOF frame number.</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SOF1</name>
<description>Start Of Frame Register</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>FRAME_NUMBER_MSB</name>
<description>It has the upper 3 bits [10:8] of the SOF frame number.</description>
<bitRange>[2:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP2_CNT0</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC7</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DATA_ERROR</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_VALID</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP2_CNT1</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP2_CR0</name>
<description>Non-control endpoint's control Register</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept
IN: NAK
OUT: NAK</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept
IN: STALL
OUT: STALL</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Stall</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: NAK</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Accept data</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore
IN: NAK
OUT: Ignore</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACKED_NO</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACKED_YES</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OSCLK_DR0</name>
<description>Oscillator lock data register 0</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>ADDER</name>
<description>These bits return the lower 8 bits of the oscillator locking circuits adder output.</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OSCLK_DR1</name>
<description>Oscillator lock data register 1</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>ADDER_MSB</name>
<description>These bits return the upper 7 bits of the oscillator locking circuits adder output.</description>
<bitRange>[6:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>EP0_CR</name>
<description>Endpoint0 control Register</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept
IN: NAK
OUT: NAK</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept
IN: STALL
OUT: STALL</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Stall</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: NAK</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Accept data</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore
IN: NAK
OUT: Ignore</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACKED_NO</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACKED_YES</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUT_RCVD</name>
<description>When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IN_RCVD</name>
<description>When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SETUP_RCVD</name>
<description>When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EP0_CNT</name>
<description>Endpoint0 count Register</description>
<addressOffset>0xA4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xCF</resetMask>
<fields>
<field>
<name>BYTE_COUNT</name>
<description>These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DATA_ERROR</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_VALID</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP3_CNT0</name>
<description>Non-control endpoint count register</description>
<addressOffset>0xB0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC7</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DATA_ERROR</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_VALID</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP3_CNT1</name>
<description>Non-control endpoint count register</description>
<addressOffset>0xB4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP3_CR0</name>
<description>Non-control endpoint's control Register</description>
<addressOffset>0xB8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept
IN: NAK
OUT: NAK</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept
IN: STALL
OUT: STALL</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Stall</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: NAK</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Accept data</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore
IN: NAK
OUT: Ignore</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACKED_NO</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACKED_YES</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP4_CNT0</name>
<description>Non-control endpoint count register</description>
<addressOffset>0xF0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC7</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DATA_ERROR</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_VALID</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP4_CNT1</name>
<description>Non-control endpoint count register</description>
<addressOffset>0xF4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP4_CR0</name>
<description>Non-control endpoint's control Register</description>
<addressOffset>0xF8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept
IN: NAK
OUT: NAK</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept
IN: STALL
OUT: STALL</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Stall</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: NAK</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Accept data</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore
IN: NAK
OUT: Ignore</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACKED_NO</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACKED_YES</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP5_CNT0</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC7</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DATA_ERROR</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_VALID</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP5_CNT1</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP5_CR0</name>
<description>Non-control endpoint's control Register</description>
<addressOffset>0x138</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept
IN: NAK
OUT: NAK</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept
IN: STALL
OUT: STALL</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Stall</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: NAK</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Accept data</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore
IN: NAK
OUT: Ignore</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACKED_NO</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACKED_YES</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP6_CNT0</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x170</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC7</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DATA_ERROR</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_VALID</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP6_CNT1</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x174</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP6_CR0</name>
<description>Non-control endpoint's control Register</description>
<addressOffset>0x178</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept
IN: NAK
OUT: NAK</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept
IN: STALL
OUT: STALL</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Stall</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: NAK</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Accept data</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore
IN: NAK
OUT: Ignore</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACKED_NO</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACKED_YES</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP7_CNT0</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x1B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC7</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DATA_ERROR</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_VALID</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP7_CNT1</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x1B4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP7_CR0</name>
<description>Non-control endpoint's control Register</description>
<addressOffset>0x1B8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept
IN: NAK
OUT: NAK</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept
IN: STALL
OUT: STALL</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Stall</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: NAK</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Accept data</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore
IN: NAK
OUT: Ignore</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACKED_NO</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACKED_YES</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP8_CNT0</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC7</resetMask>
<fields>
<field>
<name>DATA_COUNT_MSB</name>
<description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_VALID</name>
<description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DATA_ERROR</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_VALID</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DATA_TOGGLE</name>
<description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP8_CNT1</name>
<description>Non-control endpoint count register</description>
<addressOffset>0x1F4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA_COUNT</name>
<description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SIE_EP8_CR0</name>
<description>Non-control endpoint's control Register</description>
<addressOffset>0x1F8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>MODE</name>
<description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Ignore all USB traffic to this endpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_INOUT</name>
<description>SETUP: Accept
IN: NAK
OUT: NAK</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_OUT_ONLY</name>
<description>SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL_INOUT</name>
<description>SETUP: Accept
IN: STALL
OUT: STALL</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STATUS_IN_ONLY</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Stall</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: NAK</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT</name>
<description>SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_OUT_STATUS_IN</name>
<description>SETUP: Accept
IN: Respond with 0B data
OUT: Accept data</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK_IN</name>
<description>SETUP: Ignore
IN: NAK
OUT: Ignore</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN</name>
<description>SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ACK_IN_STATUS_OUT</name>
<description>SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKED_TXN</name>
<description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACKED_NO</name>
<description>No ACK'd transactions since bit was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACKED_YES</name>
<description>Indicates a transaction ended with an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NAK_INT_EN</name>
<description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_IN_TXN</name>
<description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP1_CFG</name>
<description>Endpoint Configuration Register *1</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CRC_NORMAL</name>
<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRC_BYPASS</name>
<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET_PTR</name>
<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RESET_KRYPTON</name>
<description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET_NORMAL</name>
<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ARB_EP1_INT_EN</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x204</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant Enable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow Enable</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow Enable</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt Enable</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP1_SR</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x208</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x2F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL</name>
<description>IN Endpoint Local Buffer Full Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT</name>
<description>Endpoint DMA Grant Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER</name>
<description>Endpoint Buffer Overflow Interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER</name>
<description>Endpoint Buffer Underflow Interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN</name>
<description>Endpoint DMA Terminated Interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_WA</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x210</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WA</name>
<description>Write Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_WA_MSB</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x214</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>WA_MSB</name>
<description>Write Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_RA</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x218</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RA</name>
<description>Read Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_RA_MSB</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x21C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>RA_MSB</name>
<description>Read Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_DR</name>
<description>Endpoint Data Register</description>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BUF_SIZE</name>
<description>Dedicated Endpoint Buffer Size Register *1</description>
<addressOffset>0x230</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IN_BUF</name>
<description>Buffer size for IN Endpoints.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT_BUF</name>
<description>Buffer size for OUT Endpoints.</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EP_ACTIVE</name>
<description>Endpoint Active Indication Register *1</description>
<addressOffset>0x238</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EP1_ACT</name>
<description>Indicates that Endpoint is currently active.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2_ACT</name>
<description>Indicates that Endpoint is currently active.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP3_ACT</name>
<description>Indicates that Endpoint is currently active.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP4_ACT</name>
<description>Indicates that Endpoint is currently active.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP5_ACT</name>
<description>Indicates that Endpoint is currently active.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP6_ACT</name>
<description>Indicates that Endpoint is currently active.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP7_ACT</name>
<description>Indicates that Endpoint is currently active.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP8_ACT</name>
<description>Indicates that Endpoint is currently active.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EP_TYPE</name>
<description>Endpoint Type (IN/OUT) Indication *1</description>
<addressOffset>0x23C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EP1_TYP</name>
<description>Endpoint Type Indication.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>EP_IN</name>
<description>IN outpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EP_OUT</name>
<description>OUT outpoint</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EP2_TYP</name>
<description>Endpoint Type Indication.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>EP_IN</name>
<description>IN outpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EP_OUT</name>
<description>OUT outpoint</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EP3_TYP</name>
<description>Endpoint Type Indication.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>EP_IN</name>
<description>IN outpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EP_OUT</name>
<description>OUT outpoint</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EP4_TYP</name>
<description>Endpoint Type Indication.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>EP_IN</name>
<description>IN outpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EP_OUT</name>
<description>OUT outpoint</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EP5_TYP</name>
<description>Endpoint Type Indication.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>EP_IN</name>
<description>IN outpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EP_OUT</name>
<description>OUT outpoint</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EP6_TYP</name>
<description>Endpoint Type Indication.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>EP_IN</name>
<description>IN outpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EP_OUT</name>
<description>OUT outpoint</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EP7_TYP</name>
<description>Endpoint Type Indication.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>EP_IN</name>
<description>IN outpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EP_OUT</name>
<description>OUT outpoint</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EP8_TYP</name>
<description>Endpoint Type Indication.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>EP_IN</name>
<description>IN outpoint</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EP_OUT</name>
<description>OUT outpoint</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ARB_EP2_CFG</name>
<description>Endpoint Configuration Register *1</description>
<addressOffset>0x240</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CRC_NORMAL</name>
<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRC_BYPASS</name>
<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET_PTR</name>
<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RESET_KRYPTON</name>
<description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET_NORMAL</name>
<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ARB_EP2_INT_EN</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x244</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant Enable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow Enable</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow Enable</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt Enable</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP2_SR</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x248</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x2F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL</name>
<description>IN Endpoint Local Buffer Full Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT</name>
<description>Endpoint DMA Grant Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER</name>
<description>Endpoint Buffer Overflow Interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER</name>
<description>Endpoint Buffer Underflow Interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN</name>
<description>Endpoint DMA Terminated Interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_WA</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x250</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WA</name>
<description>Write Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_WA_MSB</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x254</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>WA_MSB</name>
<description>Write Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_RA</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x258</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RA</name>
<description>Read Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_RA_MSB</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x25C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>RA_MSB</name>
<description>Read Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_DR</name>
<description>Endpoint Data Register</description>
<addressOffset>0x260</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_CFG</name>
<description>Arbiter Configuration Register *1</description>
<addressOffset>0x270</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF0</resetMask>
<fields>
<field>
<name>AUTO_MEM</name>
<description>Enables Auto Memory Configuration. Manual memory configuration by default.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_CFG</name>
<description>DMA Access Configuration.</description>
<bitRange>[6:5]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DMA_NONE</name>
<description>No DMA</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA_MANUAL</name>
<description>Manual DMA</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA_AUTO</name>
<description>Auto DMA</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CFG_CMP</name>
<description>Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_CLK_EN</name>
<description>USB Block Clock Enable Register</description>
<addressOffset>0x274</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>CSR_CLK_EN</name>
<description>Clock Enable for Core Logic clocked by AHB bus clock</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_INT_EN</name>
<description>Arbiter Interrupt Enable *1</description>
<addressOffset>0x278</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EP1_INTR_EN</name>
<description>Enables interrupt for EP1</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2_INTR_EN</name>
<description>Enables interrupt for EP2</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP3_INTR_EN</name>
<description>Enables interrupt for EP3</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP4_INTR_EN</name>
<description>Enables interrupt for EP4</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP5_INTR_EN</name>
<description>Enables interrupt for EP5</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP6_INTR_EN</name>
<description>Enables interrupt for EP6</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP7_INTR_EN</name>
<description>Enables interrupt for EP7</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP8_INTR_EN</name>
<description>Enables interrupt for EP8</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_INT_SR</name>
<description>Arbiter Interrupt Status *1</description>
<addressOffset>0x27C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EP1_INTR</name>
<description>Interrupt status for EP1</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2_INTR</name>
<description>Interrupt status for EP2</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP3_INTR</name>
<description>Interrupt status for EP3</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP4_INTR</name>
<description>Interrupt status for EP4</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP5_INTR</name>
<description>Interrupt status for EP5</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP6_INTR</name>
<description>Interrupt status for EP6</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP7_INTR</name>
<description>Interrupt status for EP7</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP8_INTR</name>
<description>Interrupt status for EP8</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP3_CFG</name>
<description>Endpoint Configuration Register *1</description>
<addressOffset>0x280</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CRC_NORMAL</name>
<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRC_BYPASS</name>
<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET_PTR</name>
<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RESET_KRYPTON</name>
<description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET_NORMAL</name>
<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ARB_EP3_INT_EN</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x284</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant Enable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow Enable</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow Enable</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt Enable</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP3_SR</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x288</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x2F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL</name>
<description>IN Endpoint Local Buffer Full Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT</name>
<description>Endpoint DMA Grant Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER</name>
<description>Endpoint Buffer Overflow Interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER</name>
<description>Endpoint Buffer Underflow Interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN</name>
<description>Endpoint DMA Terminated Interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_WA</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x290</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WA</name>
<description>Write Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_WA_MSB</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x294</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>WA_MSB</name>
<description>Write Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_RA</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x298</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RA</name>
<description>Read Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_RA_MSB</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x29C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>RA_MSB</name>
<description>Read Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_DR</name>
<description>Endpoint Data Register</description>
<addressOffset>0x2A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CWA</name>
<description>Common Area Write Address *1</description>
<addressOffset>0x2B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CWA</name>
<description>Write Address for Common Area</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CWA_MSB</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x2B4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>CWA_MSB</name>
<description>Write Address for Common Area</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP4_CFG</name>
<description>Endpoint Configuration Register *1</description>
<addressOffset>0x2C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CRC_NORMAL</name>
<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRC_BYPASS</name>
<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET_PTR</name>
<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RESET_KRYPTON</name>
<description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET_NORMAL</name>
<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ARB_EP4_INT_EN</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x2C4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant Enable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow Enable</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow Enable</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt Enable</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP4_SR</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x2C8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x2F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL</name>
<description>IN Endpoint Local Buffer Full Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT</name>
<description>Endpoint DMA Grant Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER</name>
<description>Endpoint Buffer Overflow Interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER</name>
<description>Endpoint Buffer Underflow Interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN</name>
<description>Endpoint DMA Terminated Interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_WA</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x2D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WA</name>
<description>Write Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_WA_MSB</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x2D4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>WA_MSB</name>
<description>Write Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_RA</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x2D8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RA</name>
<description>Read Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_RA_MSB</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x2DC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>RA_MSB</name>
<description>Read Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_DR</name>
<description>Endpoint Data Register</description>
<addressOffset>0x2E0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DMA_THRES</name>
<description>DMA Burst / Threshold Configuration</description>
<addressOffset>0x2F0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DMA_THS</name>
<description>DMA Threshold count</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DMA_THRES_MSB</name>
<description>DMA Burst / Threshold Configuration</description>
<addressOffset>0x2F4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>DMA_THS_MSB</name>
<description>DMA Threshold count</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP5_CFG</name>
<description>Endpoint Configuration Register *1</description>
<addressOffset>0x300</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CRC_NORMAL</name>
<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRC_BYPASS</name>
<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET_PTR</name>
<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RESET_KRYPTON</name>
<description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET_NORMAL</name>
<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ARB_EP5_INT_EN</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x304</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant Enable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow Enable</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow Enable</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt Enable</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP5_SR</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x308</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x2F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL</name>
<description>IN Endpoint Local Buffer Full Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT</name>
<description>Endpoint DMA Grant Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER</name>
<description>Endpoint Buffer Overflow Interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER</name>
<description>Endpoint Buffer Underflow Interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN</name>
<description>Endpoint DMA Terminated Interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW5_WA</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x310</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WA</name>
<description>Write Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW5_WA_MSB</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x314</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>WA_MSB</name>
<description>Write Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW5_RA</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x318</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RA</name>
<description>Read Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW5_RA_MSB</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x31C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>RA_MSB</name>
<description>Read Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW5_DR</name>
<description>Endpoint Data Register</description>
<addressOffset>0x320</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BUS_RST_CNT</name>
<description>Bus Reset Count Register</description>
<addressOffset>0x330</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>BUS_RST_CNT</name>
<description>Bus Reset Count Length</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP6_CFG</name>
<description>Endpoint Configuration Register *1</description>
<addressOffset>0x340</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CRC_NORMAL</name>
<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRC_BYPASS</name>
<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET_PTR</name>
<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RESET_KRYPTON</name>
<description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET_NORMAL</name>
<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ARB_EP6_INT_EN</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x344</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant Enable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow Enable</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow Enable</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt Enable</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP6_SR</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x348</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x2F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL</name>
<description>IN Endpoint Local Buffer Full Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT</name>
<description>Endpoint DMA Grant Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER</name>
<description>Endpoint Buffer Overflow Interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER</name>
<description>Endpoint Buffer Underflow Interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN</name>
<description>Endpoint DMA Terminated Interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW6_WA</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x350</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WA</name>
<description>Write Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW6_WA_MSB</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x354</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>WA_MSB</name>
<description>Write Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW6_RA</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x358</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RA</name>
<description>Read Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW6_RA_MSB</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x35C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>RA_MSB</name>
<description>Read Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW6_DR</name>
<description>Endpoint Data Register</description>
<addressOffset>0x360</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP7_CFG</name>
<description>Endpoint Configuration Register *1</description>
<addressOffset>0x380</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CRC_NORMAL</name>
<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRC_BYPASS</name>
<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET_PTR</name>
<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RESET_KRYPTON</name>
<description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET_NORMAL</name>
<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ARB_EP7_INT_EN</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x384</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant Enable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow Enable</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow Enable</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt Enable</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP7_SR</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x388</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x2F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL</name>
<description>IN Endpoint Local Buffer Full Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT</name>
<description>Endpoint DMA Grant Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER</name>
<description>Endpoint Buffer Overflow Interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER</name>
<description>Endpoint Buffer Underflow Interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN</name>
<description>Endpoint DMA Terminated Interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW7_WA</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x390</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WA</name>
<description>Write Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW7_WA_MSB</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x394</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>WA_MSB</name>
<description>Write Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW7_RA</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x398</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RA</name>
<description>Read Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW7_RA_MSB</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x39C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>RA_MSB</name>
<description>Read Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW7_DR</name>
<description>Endpoint Data Register</description>
<addressOffset>0x3A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP8_CFG</name>
<description>Endpoint Configuration Register *1</description>
<addressOffset>0x3C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>IN_DATA_RDY</name>
<description>Indication that Endpoint Packet Data is Ready in Main memory</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_REQ</name>
<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRC_BYPASS</name>
<description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CRC_NORMAL</name>
<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRC_BYPASS</name>
<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET_PTR</name>
<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RESET_KRYPTON</name>
<description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET_NORMAL</name>
<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ARB_EP8_INT_EN</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x3C4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL_EN</name>
<description>IN Endpoint Local Buffer Full Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT_EN</name>
<description>Endpoint DMA Grant Enable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER_EN</name>
<description>Endpoint Buffer Overflow Enable</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER_EN</name>
<description>Endpoint Buffer Underflow Enable</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ERR_INT_EN</name>
<description>Endpoint Error in Transaction Interrupt Enable</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN_EN</name>
<description>Endpoint DMA Terminated Enable</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_EP8_SR</name>
<description>Endpoint Interrupt Enable Register *1</description>
<addressOffset>0x3C8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x2F</resetMask>
<fields>
<field>
<name>IN_BUF_FULL</name>
<description>IN Endpoint Local Buffer Full Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_GNT</name>
<description>Endpoint DMA Grant Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_OVER</name>
<description>Endpoint Buffer Overflow Interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUF_UNDER</name>
<description>Endpoint Buffer Underflow Interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMA_TERMIN</name>
<description>Endpoint DMA Terminated Interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW8_WA</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x3D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>WA</name>
<description>Write Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW8_WA_MSB</name>
<description>Endpoint Write Address value *1</description>
<addressOffset>0x3D4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>WA_MSB</name>
<description>Write Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW8_RA</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x3D8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RA</name>
<description>Read Address for EP</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW8_RA_MSB</name>
<description>Endpoint Read Address value *1</description>
<addressOffset>0x3DC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>RA_MSB</name>
<description>Read Address for EP</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW8_DR</name>
<description>Endpoint Data Register</description>
<addressOffset>0x3E0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>512</dim>
<dimIncrement>4</dimIncrement>
<name>MEM_DATA[%s]</name>
<description>DATA</description>
<addressOffset>0x400</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SOF16</name>
<description>Start Of Frame Register</description>
<addressOffset>0x1060</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x7FF</resetMask>
<fields>
<field>
<name>FRAME_NUMBER16</name>
<description>The frame number (11b)</description>
<bitRange>[10:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OSCLK_DR16</name>
<description>Oscillator lock data register</description>
<addressOffset>0x1080</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>ADDER16</name>
<description>These bits return the oscillator locking circuits adder output.</description>
<bitRange>[14:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_WA16</name>
<description>Endpoint Write Address value</description>
<addressOffset>0x1210</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>WA16</name>
<description>Write Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_RA16</name>
<description>Endpoint Read Address value</description>
<addressOffset>0x1218</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>RA16</name>
<description>Read Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW1_DR16</name>
<description>Endpoint Data Register</description>
<addressOffset>0x1220</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR16</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_WA16</name>
<description>Endpoint Write Address value</description>
<addressOffset>0x1250</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>WA16</name>
<description>Write Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_RA16</name>
<description>Endpoint Read Address value</description>
<addressOffset>0x1258</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>RA16</name>
<description>Read Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW2_DR16</name>
<description>Endpoint Data Register</description>
<addressOffset>0x1260</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR16</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_WA16</name>
<description>Endpoint Write Address value</description>
<addressOffset>0x1290</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>WA16</name>
<description>Write Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_RA16</name>
<description>Endpoint Read Address value</description>
<addressOffset>0x1298</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>RA16</name>
<description>Read Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW3_DR16</name>
<description>Endpoint Data Register</description>
<addressOffset>0x12A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR16</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CWA16</name>
<description>Common Area Write Address</description>
<addressOffset>0x12B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>CWA16</name>
<description>Write Address for Common Area</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_WA16</name>
<description>Endpoint Write Address value</description>
<addressOffset>0x12D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>WA16</name>
<description>Write Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_RA16</name>
<description>Endpoint Read Address value</description>
<addressOffset>0x12D8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>RA16</name>
<description>Read Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW4_DR16</name>
<description>Endpoint Data Register</description>
<addressOffset>0x12E0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR16</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DMA_THRES16</name>
<description>DMA Burst / Threshold Configuration</description>
<addressOffset>0x12F0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>DMA_THS16</name>
<description>DMA Threshold count</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW5_WA16</name>
<description>Endpoint Write Address value</description>
<addressOffset>0x1310</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>WA16</name>
<description>Write Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW5_RA16</name>
<description>Endpoint Read Address value</description>
<addressOffset>0x1318</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>RA16</name>
<description>Read Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW5_DR16</name>
<description>Endpoint Data Register</description>
<addressOffset>0x1320</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR16</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW6_WA16</name>
<description>Endpoint Write Address value</description>
<addressOffset>0x1350</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>WA16</name>
<description>Write Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW6_RA16</name>
<description>Endpoint Read Address value</description>
<addressOffset>0x1358</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>RA16</name>
<description>Read Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW6_DR16</name>
<description>Endpoint Data Register</description>
<addressOffset>0x1360</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR16</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW7_WA16</name>
<description>Endpoint Write Address value</description>
<addressOffset>0x1390</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>WA16</name>
<description>Write Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW7_RA16</name>
<description>Endpoint Read Address value</description>
<addressOffset>0x1398</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>RA16</name>
<description>Read Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW7_DR16</name>
<description>Endpoint Data Register</description>
<addressOffset>0x13A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR16</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW8_WA16</name>
<description>Endpoint Write Address value</description>
<addressOffset>0x13D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>WA16</name>
<description>Write Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW8_RA16</name>
<description>Endpoint Read Address value</description>
<addressOffset>0x13D8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>RA16</name>
<description>Read Address for EP</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ARB_RW8_DR16</name>
<description>Endpoint Data Register</description>
<addressOffset>0x13E0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DR16</name>
<description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
<cluster>
<name>USBLPM</name>
<description>USB Device LPM and PHY Test</description>
<addressOffset>0x00002000</addressOffset>
<register>
<name>POWER_CTL</name>
<description>Power Control Register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x303F0004</resetMask>
<fields>
<field>
<name>SUSPEND</name>
<description>Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep).
Note:
- This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DP_UP_EN</name>
<description>Enables the pull up on the DP.
'0' : Disable.
'1' : Enable.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DP_BIG</name>
<description>Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO.
'0' : The resister value is from 900 to1575Opull up on the DP.
'1' : The resister value is from 1425 to 3090Opull up on the DP</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DP_DOWN_EN</name>
<description>Enables the ~15k pull down on the DP.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DM_UP_EN</name>
<description>Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO.
'0' : Disable.
'1' : Enable.</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DM_BIG</name>
<description>Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO.
'0' : The resister value is from 900 to1575Opull up on the DM.
'1' : The resister value is from 1425 to 3090Opull up on the DM</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DM_DOWN_EN</name>
<description>Enables the ~15k pull down on the DP.</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE_DPO</name>
<description>Enables the single ended receiver on D+.</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE_DMO</name>
<description>Enables the signle ended receiver on D-.</description>
<bitRange>[29:29]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USBIO_CTL</name>
<description>USB IO Control Register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>DM_P</name>
<description>The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Mode 0: Output buffer off (high Z). Input buffer off.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT</name>
<description>Mode 1: Output buffer off (high Z). Input buffer on.
Other values, not supported.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DM_M</name>
<description>The GPIO Drive Mode for DM IO pad.</description>
<bitRange>[5:3]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FLOW_CTL</name>
<description>Flow Control Register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EP1_ERR_RESP</name>
<description>End Point 1 error response
0: do nothing (backward compatibility mode)
1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2_ERR_RESP</name>
<description>End Point 2 error response</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP3_ERR_RESP</name>
<description>End Point 3 error response</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP4_ERR_RESP</name>
<description>End Point 4 error response</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP5_ERR_RESP</name>
<description>End Point 5 error response</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP6_ERR_RESP</name>
<description>End Point 6 error response</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP7_ERR_RESP</name>
<description>End Point 7 error response</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP8_ERR_RESP</name>
<description>End Point 8 error response</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LPM_CTL</name>
<description>LPM Control Register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x17</resetMask>
<fields>
<field>
<name>LPM_EN</name>
<description>LPM enable
0: Disabled, LPM token will not get a response (backward compatibility mode)
1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK)
A STALL will be sent if the bLinkState is not 0001b
A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LPM_ACK_RESP</name>
<description>LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request
0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode
1: a LPM token will get an ACK response and the device will go to the requested low power mode</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NYET_EN</name>
<description>Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0).
0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token.
1: a LPM token will get a NYET response</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SUB_RESP</name>
<description>Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LPM_STAT</name>
<description>LPM Status register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>LPM_BESL</name>
<description>Best Effort Service Latency
This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor.</description>
<bitRange>[3:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>LPM_REMOTEWAKE</name>
<description>0: Device is prohibited from initiating a remote wake
1: Device is allow to wake the host</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_SIE</name>
<description>USB SOF, BUS RESET and EP0 Interrupt Status</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>SOF_INTR</name>
<description>Interrupt status for USB SOF</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUS_RESET_INTR</name>
<description>Interrupt status for BUS RESET</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP0_INTR</name>
<description>Interrupt status for EP0</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LPM_INTR</name>
<description>Interrupt status for LPM (Link Power Management, L1 entry)</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESUME_INTR</name>
<description>Interrupt status for Resume</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SIE_SET</name>
<description>USB SOF, BUS RESET and EP0 Interrupt Set</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>SOF_INTR_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUS_RESET_INTR_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP0_INTR_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LPM_INTR_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESUME_INTR_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SIE_MASK</name>
<description>USB SOF, BUS RESET and EP0 Interrupt Mask</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>SOF_INTR_MASK</name>
<description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BUS_RESET_INTR_MASK</name>
<description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP0_INTR_MASK</name>
<description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LPM_INTR_MASK</name>
<description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESUME_INTR_MASK</name>
<description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SIE_MASKED</name>
<description>USB SOF, BUS RESET and EP0 Interrupt Masked</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>SOF_INTR_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BUS_RESET_INTR_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP0_INTR_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>LPM_INTR_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RESUME_INTR_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_LVL_SEL</name>
<description>Select interrupt level for each interrupt source</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFC3FF</resetMask>
<fields>
<field>
<name>SOF_LVL_SEL</name>
<description>USB SOF Interrupt level select</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>HI</name>
<description>High priority interrupt</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MED</name>
<description>Medium priority interrupt</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>LO</name>
<description>Low priority interrupt</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>illegal</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUS_RESET_LVL_SEL</name>
<description>BUS RESET Interrupt level select</description>
<bitRange>[3:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP0_LVL_SEL</name>
<description>EP0 Interrupt level select</description>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LPM_LVL_SEL</name>
<description>LPM Interrupt level select</description>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RESUME_LVL_SEL</name>
<description>Resume Interrupt level select</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ARB_EP_LVL_SEL</name>
<description>Arbiter Endpoint Interrupt level select</description>
<bitRange>[15:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP1_LVL_SEL</name>
<description>EP1 Interrupt level select</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2_LVL_SEL</name>
<description>EP2 Interrupt level select</description>
<bitRange>[19:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP3_LVL_SEL</name>
<description>EP3 Interrupt level select</description>
<bitRange>[21:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP4_LVL_SEL</name>
<description>EP4 Interrupt level select</description>
<bitRange>[23:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP5_LVL_SEL</name>
<description>EP5 Interrupt level select</description>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP6_LVL_SEL</name>
<description>EP6 Interrupt level select</description>
<bitRange>[27:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP7_LVL_SEL</name>
<description>EP7 Interrupt level select</description>
<bitRange>[29:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP8_LVL_SEL</name>
<description>EP8 Interrupt level select</description>
<bitRange>[31:30]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_CAUSE_HI</name>
<description>High priority interrupt Cause register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF9F</resetMask>
<fields>
<field>
<name>SOF_INTR</name>
<description>USB SOF Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BUS_RESET_INTR</name>
<description>BUS RESET Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP0_INTR</name>
<description>EP0 Interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>LPM_INTR</name>
<description>LPM Interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RESUME_INTR</name>
<description>Resume Interrupt</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ARB_EP_INTR</name>
<description>Arbiter Endpoint Interrupt</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP1_INTR</name>
<description>EP1 Interrupt</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2_INTR</name>
<description>EP2 Interrupt</description>
<bitRange>[9:9]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP3_INTR</name>
<description>EP3 Interrupt</description>
<bitRange>[10:10]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP4_INTR</name>
<description>EP4 Interrupt</description>
<bitRange>[11:11]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP5_INTR</name>
<description>EP5 Interrupt</description>
<bitRange>[12:12]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP6_INTR</name>
<description>EP6 Interrupt</description>
<bitRange>[13:13]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP7_INTR</name>
<description>EP7 Interrupt</description>
<bitRange>[14:14]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP8_INTR</name>
<description>EP8 Interrupt</description>
<bitRange>[15:15]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_CAUSE_MED</name>
<description>Medium priority interrupt Cause register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF9F</resetMask>
<fields>
<field>
<name>SOF_INTR</name>
<description>USB SOF Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BUS_RESET_INTR</name>
<description>BUS RESET Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP0_INTR</name>
<description>EP0 Interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>LPM_INTR</name>
<description>LPM Interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RESUME_INTR</name>
<description>Resume Interrupt</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ARB_EP_INTR</name>
<description>Arbiter Endpoint Interrupt</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP1_INTR</name>
<description>EP1 Interrupt</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2_INTR</name>
<description>EP2 Interrupt</description>
<bitRange>[9:9]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP3_INTR</name>
<description>EP3 Interrupt</description>
<bitRange>[10:10]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP4_INTR</name>
<description>EP4 Interrupt</description>
<bitRange>[11:11]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP5_INTR</name>
<description>EP5 Interrupt</description>
<bitRange>[12:12]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP6_INTR</name>
<description>EP6 Interrupt</description>
<bitRange>[13:13]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP7_INTR</name>
<description>EP7 Interrupt</description>
<bitRange>[14:14]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP8_INTR</name>
<description>EP8 Interrupt</description>
<bitRange>[15:15]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_CAUSE_LO</name>
<description>Low priority interrupt Cause register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF9F</resetMask>
<fields>
<field>
<name>SOF_INTR</name>
<description>USB SOF Interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BUS_RESET_INTR</name>
<description>BUS RESET Interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP0_INTR</name>
<description>EP0 Interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>LPM_INTR</name>
<description>LPM Interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RESUME_INTR</name>
<description>Resume Interrupt</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>ARB_EP_INTR</name>
<description>Arbiter Endpoint Interrupt</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP1_INTR</name>
<description>EP1 Interrupt</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2_INTR</name>
<description>EP2 Interrupt</description>
<bitRange>[9:9]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP3_INTR</name>
<description>EP3 Interrupt</description>
<bitRange>[10:10]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP4_INTR</name>
<description>EP4 Interrupt</description>
<bitRange>[11:11]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP5_INTR</name>
<description>EP5 Interrupt</description>
<bitRange>[12:12]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP6_INTR</name>
<description>EP6 Interrupt</description>
<bitRange>[13:13]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP7_INTR</name>
<description>EP7 Interrupt</description>
<bitRange>[14:14]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP8_INTR</name>
<description>EP8 Interrupt</description>
<bitRange>[15:15]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DFT_CTL</name>
<description>DFT control</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>DDFT_OUT_SEL</name>
<description>DDFT output select signal</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Nothing connected, output 0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DP_SE</name>
<description>Single Ended output of DP</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DM_SE</name>
<description>Single Ended output of DM</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TXOE</name>
<description>Output Enable</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>RCV_DF</name>
<description>Differential Receiver output</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>GPIO_DP_OUT</name>
<description>GPIO output of DP</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>GPIO_DM_OUT</name>
<description>GPIO output of DM</description>
<value>6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DDFT_IN_SEL</name>
<description>DDFT input select signal</description>
<bitRange>[4:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Nothing connected, output 0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GPIO_DP_IN</name>
<description>GPIO input of DP</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>GPIO_DM_IN</name>
<description>GPIO input of DM</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</cluster>
<cluster>
<name>USBHOST</name>
<description>USB Host Controller</description>
<addressOffset>0x00004000</addressOffset>
<register>
<name>HOST_CTL0</name>
<description>Host Control 0 Register.</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000001</resetMask>
<fields>
<field>
<name>HOST</name>
<description>This bit selects an operating mode of this IP.
'0' : USB Device
'1' : USB Host
Notes:
- The operation mode does not transition to the required one immediately after it was changed using this bit. Read this bit to check that the operation mode has changed.
- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'..
- Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'.
* The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'.
* The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'.
* The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLE</name>
<description>This bit enables the operation of this IP.
'0' : Disable USB Host
'1' : Enable USB Host
Note:
- This bit doesn' affect the USB Device.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_CTL1</name>
<description>Host Control 1 Register.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x83</resetValue>
<resetMask>0x83</resetMask>
<fields>
<field>
<name>CLKSEL</name>
<description>This bit selects the operating clock of USB Host.
'0' : Low-speed clock
'1' : Full-speed clock
Notes:
- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.
- This bit must always be set to '1' in the USB Device mode.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>USTP</name>
<description>This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit.
'0' : Normal mode.
'1' : Stops the clock for the USB Host operating unit.
Notes:
- If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped.
- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RST</name>
<description>This bit resets this IP.
'0' : Releases the reset for USB Host.
'1' : Resets USB Host.
Notes:
- This bit is initialized if ENABLE bit of the Host Control 0 Register changes from '1' to '0'.
- If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_CTL2</name>
<description>Host Control 2 Register.</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>RETRY</name>
<description>If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed during the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER).
* : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1'
'0' : Doesn't retry token sending.
'1' : Retries token sending
Note:
- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CANCEL</name>
<description>When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST).
'0' : Continues a token.
'1' : Cancels a token.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SOFSTEP</name>
<description>If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent.
If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'.
'0' : An interrupt occurred due to the HOST_HFCOMP setting.
'1' : An interrupt occurred.
Notes:
- If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ALIVE</name>
<description>This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is effective when the CLKSEL bit of the Host Conrtol 1 Register (HOST_CTL1) is '0'. If the CLKSEL bit is '1', SOF is output regardless of the setting of the ALIVE bit.
'0' : SOF output.
'1' : SE0 output (Keep alive)</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSVD_4</name>
<description>N/A</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSVD_5</name>
<description>N/A</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TTEST</name>
<description>Timer Test. Set this bits to '00'.</description>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_ERR</name>
<description>Host Error Status Register.</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>HS</name>
<description>These flags indicate the status of a handshake packet to be sent or received.
These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN).
These bits are updated when sending or receiving has been ended.
HS bits change values '11' under the following condition. However, if HS bits are written except the following conditions, the values are ignored.
- HS bits indicate values except '11' and write the value '11' to HS bits.
Note:
This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACK</name>
<description>Acknowledge Packet</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NAK</name>
<description>Non-Acknowledge Packet</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STALL</name>
<description>Stall Packet</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NULL</name>
<description>Null Packet</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STUFF</name>
<description>If this bit is set to '1', it means that a bit stuffing error is detected. When this bit is '0', it means that no stuffing error is detected. If a stuffing error is detected, bit5 (Timeout) of this register is also set to '1'. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : No stuffing error.
'1' : Stuffing error occurs.
Note:
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TGERR</name>
<description>If this bit is set to '1', it means that the data of this bit does not match the value of the received toggle data. When this bit is '0', it means that no toggle error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : No toggle error.
'1' : Toggle error occurs.
Note:
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRC</name>
<description>If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no CRC error is detected. If a CRC error is detected, bit5 (Timeout) of this register is also set to '1'. When this bit is '0', it means that no CRC error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : No CRC error.
'1' : CRC error occurs.
Note:
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TOUT</name>
<description>If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected. When this bit is '0', it means that no error occurs. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : No timeout.
'1' : Timeout occurs.
Note:
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RERR</name>
<description>When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (Timeout) of this register is also set to '1'. When this bit is '0', it means that no error occurs. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : No receive error.
'1' : Maximum packet receive error.
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LSTSOF</name>
<description>If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that no lost SOF error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : Sends SOF.
'1' : SOF sending error.
Note:
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_STATUS</name>
<description>Host Status Register.</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC2</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>CSTAT</name>
<description>When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected.
'0' : Device is disconnected.
'1' : Device is connected.
Notes:
- This bit is initialized if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'.
- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TMODE</name>
<description>If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'.
'0' : Low-speed.
'1' : Full-speed.
Notes:
- This bit is initialized if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SUSP</name>
<description>If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, the suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
Set to '1' : Suspend.
Set '0' while this bit is '1' : Resume.
Others : Holds the status.
Notes:
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
- If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
- Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running).
- If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SOFBUSY</name>
<description>When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored.
'0' : The SOF timer is stopped.
'1' : The SOF timer is active.
Notes:
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
- The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>URST</name>
<description>When this bit is set to '1', the USB bus is reset. This bit continues set to '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', no processing is performed.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSVD_5</name>
<description>N/A</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RSTBUSY</name>
<description>This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'.
If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'.
'0' : USB Host isn't being reset.
'1' : USB Host is being reset.
Notes:
- If this bit is '1', the token must't be executed.
- This bit isn't set to '0' or '1' immediately evne if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'.</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CLKSEL_ST</name>
<description>This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'.
'0' : Low speed
'1' : Full speed
Note:
- If this bit is different from the CLKSEL bit, The execution of the token and bus reset must be waited until the match.
- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>HOST_ST</name>
<description>This bit shows whether it is USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'.
'0' : USB Device
'1' : USB Host
Notes:
- If this bit is different from the CLKSEL bit, The execution of the token must be waited until the match.
- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HOST_FCOMP</name>
<description>Host SOF Interrupt Frame Compare Register</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>FRAMECOMP</name>
<description>These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token.
If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'.
Note:
- This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_RTIMER</name>
<description>Host Retry Timer Setup Register</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FFFF</resetMask>
<fields>
<field>
<name>RTIMER</name>
<description>These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing is ended.
If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped.</description>
<bitRange>[17:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_ADDR</name>
<description>Host Address Register</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7F</resetMask>
<fields>
<field>
<name>ADDRESS</name>
<description>These bits are used to specify a token address.
Note:
- This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[6:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_EOF</name>
<description>Host EOF Setup Register</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FFF</resetMask>
<fields>
<field>
<name>EOF</name>
<description>These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time.
Setting example: MAXPKT = 64 bytes, full-speed mode
(Token_length + packet_length + header + CRC)*7/6 + Turn_around_time
=(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit
Therefore, set 0x2C9.
Note:
- This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[13:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_FRAME</name>
<description>Host Frame Setup Register</description>
<addressOffset>0x11C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7FF</resetMask>
<fields>
<field>
<name>FRAME</name>
<description>These bits are used to specify a frame number of SOF.
Notes:
- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
- Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN).
- This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process.</description>
<bitRange>[10:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_TOKEN</name>
<description>Host Token Endpoint Register</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x17F</resetMask>
<fields>
<field>
<name>ENDPT</name>
<description>These bits are used to specify an endpoint to send or receive data to or from the device.
Note:
- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TKNEN</name>
<description>These bits send a token according to the settings. After operation has been ended, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
The settings of the TGGL and ENDPT bits are ignored when sending a SOF token.
Notes:
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
- The PRE packet isn't supported.
- Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1'
- Change the USB to the USB Host before writing data to this bit.
- When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit.
- Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt.
- Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token.
1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'.
2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'.
3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'.</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NONE</name>
<description>Sends no data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SETUP</name>
<description>Sends SETUP token.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>IN</name>
<description>Sends IN token.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>OUT</name>
<description>Sends OUT token.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>SOF</name>
<description>Sends SOF token.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_IN</name>
<description>Sends Isochronous IN.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>ISO_OUT</name>
<description>Sends Isochronous OUT.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>RSV</name>
<description>N/A</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TGGL</name>
<description>This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs.
'0' : DATA0
'1' : DATA1
Notes:
- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
- Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_EP1_CTL</name>
<description>Host Endpoint 1 Control Register</description>
<addressOffset>0x400</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8100</resetValue>
<resetMask>0x9DFF</resetMask>
<fields>
<field>
<name>PKS1</name>
<description>This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100.
- If automatic buffer transfer mode (DMEA='1') is used, this Endpoint must not set from 0 to 2.</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NULLE</name>
<description>When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer.
'0' : Releases the NULL automatic transfer mode.
'1' : Sets the NULL automatic transfer mode.
Note :
- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMAE</name>
<description>This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred.
'0' : Releases the automatic buffer transfer mode.
'1' : Sets the automatic buffer transfer mode.
Note :
- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR).</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIR</name>
<description>This bit specifies the transfer direction the Endpoint support.
'0' : IN Endpoint.
'1' : OUT Endpoint
Note:
- This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BFINI</name>
<description>This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit.
'0' : Clears the initialization.
'1' : Initializes the send/receive buffer
Note :
- The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits.</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_EP1_STATUS</name>
<description>Host Endpoint 1 Status Register</description>
<addressOffset>0x404</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x60000</resetValue>
<resetMask>0x70000</resetMask>
<fields>
<field>
<name>SIZE1</name>
<description>These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished.
The indication range is from 0x000 to 0x100.
Note :
- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect.</description>
<bitRange>[8:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>VAL_DATA</name>
<description>This bit shows that there is valid data in the EP1 buffer.
'0' : Invalid data in the buffer
'1' : Valid data in the buffer</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INI_ST</name>
<description>This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'.
'0' : Release of the initialization
'1' : Initialization
Note:
- This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'.</description>
<bitRange>[17:17]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RSVD_18</name>
<description>N/A</description>
<bitRange>[18:18]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HOST_EP1_RW1_DR</name>
<description>Host Endpoint 1 Data 1-Byte Register</description>
<addressOffset>0x408</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BFDT8</name>
<description>Data Register for EP1. The 1-Byte data is valid.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_EP1_RW2_DR</name>
<description>Host Endpoint 1 Data 2-Byte Register</description>
<addressOffset>0x40C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>BFDT16</name>
<description>Data Register for EP1. The 2-Byte data is valid.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_EP2_CTL</name>
<description>Host Endpoint 2 Control Register</description>
<addressOffset>0x500</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x8040</resetValue>
<resetMask>0x9C7F</resetMask>
<fields>
<field>
<name>PKS2</name>
<description>This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40.
- If automatic buffer transfer mode (DMEA='1') is used, this Endpoint must not set from 0 to 2.</description>
<bitRange>[6:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NULLE</name>
<description>When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer.
'0' : Releases the NULL automatic transfer mode.
'1' : Sets the NULL automatic transfer mode.
Note :
- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DMAE</name>
<description>This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred.
'0' : Releases the automatic buffer transfer mode.
'1' : Sets the automatic buffer transfer mode.
Note :
- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR).</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIR</name>
<description>This bit specifies the transfer direction the Endpoint support.
'0' : IN Endpoint.
'1' : OUT Endpoint
Note:
- This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BFINI</name>
<description>This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit.
'0' : Clears the initialization.
'1' : Initializes the send/receive buffer
Note :
- The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits.</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_EP2_STATUS</name>
<description>Host Endpoint 2 Status Register</description>
<addressOffset>0x504</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x60000</resetValue>
<resetMask>0x70000</resetMask>
<fields>
<field>
<name>SIZE2</name>
<description>These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished.
The indication range is from 0x000 to 0x40.
Note :
- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect.</description>
<bitRange>[6:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>VAL_DATA</name>
<description>This bit shows that there is valid data in the EP2 buffer.
'0' : Invalid data in the buffer
'1' : Valid data in the buffer</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INI_ST</name>
<description>This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'.
'0' : Release of the initialization
'1' : Initialization
Note:
- This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'.</description>
<bitRange>[17:17]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RSVD_18</name>
<description>N/A</description>
<bitRange>[18:18]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HOST_EP2_RW1_DR</name>
<description>Host Endpoint 2 Data 1-Byte Register</description>
<addressOffset>0x508</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>BFDT8</name>
<description>Data Register for EP2. The 1-Byte data is valid.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_EP2_RW2_DR</name>
<description>Host Endpoint 2 Data 2-Byte Register</description>
<addressOffset>0x50C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>BFDT16</name>
<description>Data Register for EP2. The 2-Byte data is valid.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_LVL1_SEL</name>
<description>Host Interrupt Level 1 Selection Register</description>
<addressOffset>0x800</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SOFIRQ_SEL</name>
<description>These bits assign SOFIRQ interrupt flag to any interrupt signals.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>HI</name>
<description>High priority interrupt</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MED</name>
<description>Medium priority interrupt</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>LO</name>
<description>Low priority interrupt</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>illegal</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIRQ_SEL</name>
<description>These bits assign DIRQ interrupt flag to any interrupt signals.</description>
<bitRange>[3:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CNNIRQ_SEL</name>
<description>These bits assign CNNIRQ interrupt flag to any interrupt signals.</description>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMPIRQ_SEL</name>
<description>These bits assign URIRQ interrupt flag to any interrupt signals.</description>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>URIRQ_SEL</name>
<description>These bits assign URIRQ interrupt flag to any interrupt signals.</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RWKIRQ_SEL</name>
<description>These bits assign RWKIRQ interrupt flag to any interrupt signals.</description>
<bitRange>[11:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSVD_13_12</name>
<description>N/A</description>
<bitRange>[13:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TCAN_SEL</name>
<description>These bits assign TCAN interrupt flag to any interrupt signals.</description>
<bitRange>[15:14]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_LVL2_SEL</name>
<description>Host Interrupt Level 2 Selection Register</description>
<addressOffset>0x804</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF0</resetMask>
<fields>
<field>
<name>EP1_DRQ_SEL</name>
<description>These bits assign EP1_DRQ interrupt flag to any interrupt signals.</description>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>HI</name>
<description>High priority interrupt</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MED</name>
<description>Medium priority interrupt</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>LO</name>
<description>Low priority interrupt</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>illegal</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EP1_SPK_SEL</name>
<description>These bits assign EP1_SPK interrupt flag to any interrupt signals.</description>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2_DRQ_SEL</name>
<description>These bits assign EP2_DRQ interrupt flag to any interrupt signals.</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2_SPK_SEL</name>
<description>These bits assign EP2_SPK interrupt flag to any interrupt signals.</description>
<bitRange>[11:10]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_USBHOST_CAUSE_HI</name>
<description>Interrupt USB Host Cause High Register</description>
<addressOffset>0x900</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOFIRQ_INT</name>
<description>SOFIRQ interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DIRQ_INT</name>
<description>DIRQ interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CNNIRQ_INT</name>
<description>CNNIRQ interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CMPIRQ_INT</name>
<description>CMPIRQ interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>URIRQ_INT</name>
<description>URIRQ interrupt</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RWKIRQ_INT</name>
<description>RWKIRQ interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RSVD_6</name>
<description>N/A</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TCAN_INT</name>
<description>TCAN interrupt</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_USBHOST_CAUSE_MED</name>
<description>Interrupt USB Host Cause Medium Register</description>
<addressOffset>0x904</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOFIRQ_INT</name>
<description>SOFIRQ interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DIRQ_INT</name>
<description>DIRQ interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CNNIRQ_INT</name>
<description>CNNIRQ interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CMPIRQ_INT</name>
<description>CMPIRQ interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>URIRQ_INT</name>
<description>URIRQ interrupt</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RWKIRQ_INT</name>
<description>RWKIRQ interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RSVD_6</name>
<description>N/A</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TCAN_INT</name>
<description>TCAN interrupt</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_USBHOST_CAUSE_LO</name>
<description>Interrupt USB Host Cause Low Register</description>
<addressOffset>0x908</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOFIRQ_INT</name>
<description>SOFIRQ interrupt</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DIRQ_INT</name>
<description>DIRQ interrupt</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CNNIRQ_INT</name>
<description>CNNIRQ interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CMPIRQ_INT</name>
<description>CMPIRQ interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>URIRQ_INT</name>
<description>URIRQ interrupt</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RWKIRQ_INT</name>
<description>RWKIRQ interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RSVD_6</name>
<description>N/A</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TCAN_INT</name>
<description>TCAN interrupt</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_HOST_EP_CAUSE_HI</name>
<description>Interrupt USB Host Endpoint Cause High Register</description>
<addressOffset>0x920</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3C</resetMask>
<fields>
<field>
<name>EP1DRQ_INT</name>
<description>EP1DRQ interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP1SPK_INT</name>
<description>EP1SPK interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2DRQ_INT</name>
<description>EP2DRQ interrupt</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2SPK_INT</name>
<description>EP2SPK interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_HOST_EP_CAUSE_MED</name>
<description>Interrupt USB Host Endpoint Cause Medium Register</description>
<addressOffset>0x924</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3C</resetMask>
<fields>
<field>
<name>EP1DRQ_INT</name>
<description>EP1DRQ interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP1SPK_INT</name>
<description>EP1SPK interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2DRQ_INT</name>
<description>EP2DRQ interrupt</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2SPK_INT</name>
<description>EP2SPK interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_HOST_EP_CAUSE_LO</name>
<description>Interrupt USB Host Endpoint Cause Low Register</description>
<addressOffset>0x928</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3C</resetMask>
<fields>
<field>
<name>EP1DRQ_INT</name>
<description>EP1DRQ interrupt</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP1SPK_INT</name>
<description>EP1SPK interrupt</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2DRQ_INT</name>
<description>EP2DRQ interrupt</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2SPK_INT</name>
<description>EP2SPK interrupt</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_USBHOST</name>
<description>Interrupt USB Host Register</description>
<addressOffset>0x940</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOFIRQ</name>
<description>If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : Does not issue an interrupt request by starting a SOF token.
'1' : Issues an interrupt request by starting a SOF token.
Note :
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIRQ</name>
<description>If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : Issues no interrupt request by detecting a device disconnection.
'1' : Issues an interrupt request by detecting a device disconnection.
Note :
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CNNIRQ</name>
<description>If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : Issues no interrupt request by detecting a device connection.
'1' : Issues an interrupt request by detecting a device connection.
Note :
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMPIRQ</name>
<description>If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : Issues no interrupt request by token completion.
'1' : Issues an interrupt request by token completion.
Note :
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
- This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'.
- Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token.
1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'.
2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'.
3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>URIRQ</name>
<description>If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : Issues no interrupt request by USB bus resetting.
'1' : Issues an interrupt request by USB bus resetting.
Note :
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RWKIRQ</name>
<description>If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : Issues no interrupt request by restart.
'1' : Issues an interrupt request by restart.
Note :
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSVD_6</name>
<description>N/A</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TCAN</name>
<description>If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
'0' : Does not cancel token sending.
'1' : Cancels token sending.
Note :
- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_USBHOST_SET</name>
<description>Interrupt USB Host Set Register</description>
<addressOffset>0x944</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOFIRQS</name>
<description>This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIRQS</name>
<description>This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CNNIRQS</name>
<description>This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMPIRQS</name>
<description>This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>URIRQS</name>
<description>This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RWKIRQS</name>
<description>This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSVD_6</name>
<description>BCNFTEST interrupt. This bit is test bit</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TCANS</name>
<description>This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_USBHOST_MASK</name>
<description>Interrupt USB Host Mask Register</description>
<addressOffset>0x948</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOFIRQM</name>
<description>This bit masks the interrupt by SOF flag.
'0' : Disables
'1' : Enables</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIRQM</name>
<description>This bit masks the interrupt by DIRQ flag.
'0' : Disables
'1' : Enables</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CNNIRQM</name>
<description>This bit masks the interrupt by CNNIRQ flag.
'0' : Disables
'1' : Enables</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMPIRQM</name>
<description>This bit masks the interrupt by CMPIRQ flag.
'0' : Disables
'1' : Enables</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>URIRQM</name>
<description>This bit masks the interrupt by URIRQ flag.
'0' : Disables
'1' : Enables</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RWKIRQM</name>
<description>This bit masks the interrupt by RWKIRQ flag.
'0' : Disables
'1' : Enables</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RSVD_6</name>
<description>N/A</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TCANM</name>
<description>This bit masks the interrupt by TCAN flag.
'0' : Disables
'1' : Enables</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_USBHOST_MASKED</name>
<description>Interrupt USB Host Masked Register</description>
<addressOffset>0x94C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>SOFIRQED</name>
<description>This bit indicates the interrupt by SOF flag.
'0' : Doesn't request the interrupt by SOF
'1' : Request the interrupt by SOF</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DIRQED</name>
<description>This bit indicates the interrupt by DIRQ flag.
'0' : Doesn't request the interrupt by DIRQ
'1' : Request the interrupt by DIRQ</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CNNIRQED</name>
<description>This bit indicates the interrupt by CNNIRQ flag.
'0' : Doesn't request the interrupt by CNNIRQ
'1' : Request the interrupt by CNNIRQ</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CMPIRQED</name>
<description>This bit indicates the interrupt by CMPIRQ flag.
'0' : Doesn't request the interrupt by CMPIRQ
'1' : Request the interrupt by CMPIRQ</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>URIRQED</name>
<description>This bit indicates the interrupt by URIRQ flag.
'0' : Doesn't request the interrupt by URIRQ
'1' : Request the interrupt by URIRQ</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RWKIRQED</name>
<description>This bit indicates the interrupt by RWKIRQ flag.
'0' : Doesn't request the interrupt by RWKIRQ
'1' : Request the interrupt by RWKIRQ</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RSVD_6</name>
<description>N/A</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TCANED</name>
<description>This bit indicates the interrupt by TCAN flag.
'0' : Doesn't request the interrupt by TCAN
'1' : Request the interrupt by TCAN</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_HOST_EP</name>
<description>Interrupt USB Host Endpoint Register</description>
<addressOffset>0xA00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3C</resetMask>
<fields>
<field>
<name>EP1DRQ</name>
<description>This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'.
'0' : Clears the interrupt cause
'1' : Packet transfer normally ended
Note :
- If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP1SPK</name>
<description>This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'.
'0' : Received data size satisfies the maximum packet size
'1' : Received data size does not satisfy the maximum packet size
Note :
- The SPK bit is not set during data transfer in the OUT direction.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2DRQ</name>
<description>This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'.
'0' : Clears the interrupt cause
'1' : Packet transfer normally ended
Note :
- If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2SPK</name>
<description>This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'.
'0' : Received data size satisfies the maximum packet size
'1' : Received data size does not satisfy the maximum packet size
Note :
- The SPK bit is not set during data transfer in the OUT direction.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_HOST_EP_SET</name>
<description>Interrupt USB Host Endpoint Set Register</description>
<addressOffset>0xA04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3C</resetMask>
<fields>
<field>
<name>EP1DRQS</name>
<description>This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
Note:
If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP1SPKS</name>
<description>This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored.
Note:
If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2DRQS</name>
<description>This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
Note:
If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2SPKS</name>
<description>This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored.
Note:
If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_HOST_EP_MASK</name>
<description>Interrupt USB Host Endpoint Mask Register</description>
<addressOffset>0xA08</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3C</resetMask>
<fields>
<field>
<name>EP1DRQM</name>
<description>This bit masks the interrupt by EP1DRQ flag.
'0' : Disables
'1' : Enables</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP1SPKM</name>
<description>This bit masks the interrupt by EP1SPK flag.
'0' : Disables
'1' : Enables</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2DRQM</name>
<description>This bit masks the interrupt by EP2DRQ flag.
'0' : Disables
'1' : Enables</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EP2SPKM</name>
<description>This bit masks the interrupt by EP2SPK flag.
'0' : Disables
'1' : Enables</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_HOST_EP_MASKED</name>
<description>Interrupt USB Host Endpoint Masked Register</description>
<addressOffset>0xA0C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3C</resetMask>
<fields>
<field>
<name>EP1DRQED</name>
<description>This bit indicates the interrupt by EP1DRQ flag.
'0' : Doesn't request the interrupt by EP1DRQ
'1' : Request the interrupt by EP1DRQ</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP1SPKED</name>
<description>This bit indicates the interrupt by EP1SPK flag.
'0' : Doesn't request the interrupt by EP1SPK
'1' : Request the interrupt by EP1SPK</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2DRQED</name>
<description>This bit indicates the interrupt by EP2DRQ flag.
'0' : Doesn't request the interrupt by EP2DRQ
'1' : Request the interrupt by EP2DRQ</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EP2SPKED</name>
<description>This bit indicates the interrupt by EP2SPK flag.
'0' : Doesn't request the interrupt by EP2SPK
'1' : Request the interrupt by EP2SPK</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HOST_DMA_ENBL</name>
<description>Host DMA Enable Register</description>
<addressOffset>0xB00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC</resetMask>
<fields>
<field>
<name>DM_EP1DRQE</name>
<description>This bit enables DMA Request by EP1DRQ.
'0' : Disable
'1' : Enable</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DM_EP2DRQE</name>
<description>This bit enables DMA Request by EP2DRQ.
'0' : Disable
'1' : Enable</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_EP1_BLK</name>
<description>Host Endpoint 1 Block Register</description>
<addressOffset>0xB20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF0000</resetMask>
<fields>
<field>
<name>BLK_NUM</name>
<description>Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decrement when DMAE='1'.
- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1')</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_EP2_BLK</name>
<description>Host Endpoint 2 Block Register</description>
<addressOffset>0xB30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF0000</resetMask>
<fields>
<field>
<name>BLK_NUM</name>
<description>Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decrement when DMAE='1'.
- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1')</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>SMIF0</name>
<description>Serial Memory Interface</description>
<headerStructName>SMIF</headerStructName>
<baseAddress>0x40420000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTL</name>
<description>Control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3000</resetValue>
<resetMask>0x81073001</resetMask>
<fields>
<field>
<name>XIP_MODE</name>
<description>Mode of operation.
Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>MMIO_MODE</name>
<description>'0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>XIP_MODE</name>
<description>1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLOCK_IF_RX_SEL</name>
<description>Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'.
'0': 'spi_clk_out' (internal clock)
'1': !'spi_clk_out' (internal clock)
'2': 'spi_clk_in' (feedback clock)
'3': !'spi_clk_in' (feedback clock)
Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'.</description>
<bitRange>[13:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DESELECT_DELAY</name>
<description>Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers:
'0': 1 interface clock cycle.
'1': 2 interface clock cycles.
'2': 3 interface clock cycles.
'3': 4 interface clock cycles.
'4': 5 interface clock cycles.
'5': 6 interface clock cycles.
'6': 7 interface clock cycles.
'7': 8 interface clock cycles.
During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive.</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLOCK</name>
<description>Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE.
This field is not used for test controller accesses.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>BUS_ERROR</name>
<description>0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WAIT_STATES</name>
<description>1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENABLED</name>
<description>IP enable:
'0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors.
'1': Enabled.
Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Status</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000000</resetMask>
<fields>
<field>
<name>BUSY</name>
<description>Cache, cryptography, XIP, device interface or any other logic busy in the IP:
'0': not busy
'1': busy
When BUSY is '0', the IP can be safely disabled without:
- the potential loss of transient write data.
- the potential risk of aborting an inflight SPI device interface transfer.
When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed.</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TX_CMD_FIFO_STATUS</name>
<description>Transmitter command FIFO status</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>USED3</name>
<description>Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4].</description>
<bitRange>[2:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TX_CMD_FIFO_WR</name>
<description>Transmitter command FIFO write</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFF</resetMask>
<fields>
<field>
<name>DATA20</name>
<description>Command data. The higher two bits DATA[19:18] specify the specific command
'0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format.
- DATA[17:16] specifies the width of the data transfer:
- '0': 1 bit/cycle (single data transfer).
- '1': 2 bits/cycle (dual data transfer).
- '2': 4 bits/cycle (quad data transfer).
- '3': 8 bits/cycle (octal data transfer).
- DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer.
- DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode.
- '0': device deselected
- '1': device selected
- DATA[7:0] specifies the transmitted Byte.
'1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers.
- DATA[17:16] specifies the width of the transfer.
- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO.
'2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers.
- DATA[17:16] specifies the width of the transfer.
- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO.
'3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command.
- DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven.</description>
<bitRange>[19:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>TX_DATA_FIFO_CTL</name>
<description>Transmitter data FIFO control</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>TRIGGER_LEVEL</name>
<description>Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE):
- Trigger is active when TX_DATA_FIFO_STATUS.USED &lt;= TRIGGER_LEVEL.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TX_DATA_FIFO_STATUS</name>
<description>Transmitter data FIFO status</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>USED4</name>
<description>Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8].</description>
<bitRange>[3:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TX_DATA_FIFO_WR1</name>
<description>Transmitter data FIFO write</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>TX data (written to TX data FIFO).</description>
<bitRange>[7:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>TX_DATA_FIFO_WR2</name>
<description>Transmitter data FIFO write</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>TX data (written to TX data FIFO, first byte).</description>
<bitRange>[7:0]</bitRange>
<access>write-only</access>
</field>
<field>
<name>DATA1</name>
<description>TX data (written to TX data FIFO, second byte).</description>
<bitRange>[15:8]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>TX_DATA_FIFO_WR4</name>
<description>Transmitter data FIFO write</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>TX data (written to TX data FIFO, first byte).</description>
<bitRange>[7:0]</bitRange>
<access>write-only</access>
</field>
<field>
<name>DATA1</name>
<description>TX data (written to TX data FIFO, second byte).</description>
<bitRange>[15:8]</bitRange>
<access>write-only</access>
</field>
<field>
<name>DATA2</name>
<description>TX data (written to TX data FIFO, third byte).</description>
<bitRange>[23:16]</bitRange>
<access>write-only</access>
</field>
<field>
<name>DATA3</name>
<description>TX data (written to TX data FIFO, fourth byte).</description>
<bitRange>[31:24]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>RX_DATA_FIFO_CTL</name>
<description>Receiver data FIFO control</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>TRIGGER_LEVEL</name>
<description>Determines when RX data FIFI 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE):
- Trigger is active when RX_DATA_FIFO_STATUS.USED &gt; TRIGGER_LEVEL.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RX_DATA_FIFO_STATUS</name>
<description>Receiver data FIFO status</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>USED4</name>
<description>Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8].</description>
<bitRange>[3:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_DATA_FIFO_RD1</name>
<description>Receiver data FIFO read</description>
<addressOffset>0xD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>RX data (read from RX data FIFO).</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_DATA_FIFO_RD2</name>
<description>Receiver data FIFO read</description>
<addressOffset>0xD4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>RX data (read from RX data FIFO, first byte).</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DATA1</name>
<description>RX data (read from RX data FIFO, second byte).</description>
<bitRange>[15:8]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_DATA_FIFO_RD4</name>
<description>Receiver data FIFO read</description>
<addressOffset>0xD8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>RX data (read from RX data FIFO, first byte).</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DATA1</name>
<description>RX data (read from RX data FIFO, second byte).</description>
<bitRange>[15:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DATA2</name>
<description>RX data (read from RX data FIFO, third byte).</description>
<bitRange>[23:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DATA3</name>
<description>RX data (read from RX data FIFO, fourth byte).</description>
<bitRange>[31:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_DATA_FIFO_RD1_SILENT</name>
<description>Receiver data FIFO silent read</description>
<addressOffset>0xE0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>RX data (read from RX data FIFO).</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SLOW_CA_CTL</name>
<description>Slow cache control</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<resetMask>0xC3030000</resetMask>
<fields>
<field>
<name>WAY</name>
<description>this is for debug purpose only, and should be hidden to customers in technical document</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_ADDR</name>
<description>this is for debug purpose only, and should be hidden to customers in technical document</description>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PREF_EN</name>
<description>N/A</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>N/A</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLOW_CA_CMD</name>
<description>Slow cache command</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INV</name>
<description>Cache invalidation. SW writes a '1' to clear the cache. The cache's LRU structure is also reset to its default state.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FAST_CA_CTL</name>
<description>Fast cache control</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<resetMask>0xC3030000</resetMask>
<fields>
<field>
<name>WAY</name>
<description>this is for debug purpose only, and should be hidden to customers in technical document</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SET_ADDR</name>
<description>this is for debug purpose only, and should be hidden to customers in technical document</description>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PREF_EN</name>
<description>N/A</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>N/A</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FAST_CA_CMD</name>
<description>Fast cache command</description>
<addressOffset>0x188</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>INV</name>
<description>See SLOW_CA_CMD.INV.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_CMD</name>
<description>Cryptography Command</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>START</name>
<description>SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3.
The operation takes roughly 13 clk_hf clock cycles.
Note: An operation can only be started in MMIO_MODE.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_INPUT0</name>
<description>Cryptography input 0</description>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>INPUT</name>
<description>Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_INPUT1</name>
<description>Cryptography input 1</description>
<addressOffset>0x224</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>INPUT</name>
<description>Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_INPUT2</name>
<description>Cryptography input 2</description>
<addressOffset>0x228</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>INPUT</name>
<description>Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_INPUT3</name>
<description>Cryptography input 3</description>
<addressOffset>0x22C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>INPUT</name>
<description>Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_KEY0</name>
<description>Cryptography key 0</description>
<addressOffset>0x240</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_KEY1</name>
<description>Cryptography key 1</description>
<addressOffset>0x244</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_KEY2</name>
<description>Cryptography key 2</description>
<addressOffset>0x248</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_KEY3</name>
<description>Cryptography key 3</description>
<addressOffset>0x24C</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_OUTPUT0</name>
<description>Cryptography output 0</description>
<addressOffset>0x260</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>OUTPUT</name>
<description>Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_OUTPUT1</name>
<description>Cryptography output 1</description>
<addressOffset>0x264</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>OUTPUT</name>
<description>Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_OUTPUT2</name>
<description>Cryptography output 2</description>
<addressOffset>0x268</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>OUTPUT</name>
<description>Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRYPTO_OUTPUT3</name>
<description>Cryptography output 3</description>
<addressOffset>0x26C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>OUTPUT</name>
<description>Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0].</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Interrupt register</description>
<addressOffset>0x7C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>TR_TX_REQ</name>
<description>Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TR_RX_REQ</name>
<description>Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>XIP_ALIGNMENT_ERROR</name>
<description>Activated in XIP mode, if:
- The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2.
- The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes.
Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_CMD_FIFO_OVERFLOW</name>
<description>Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_DATA_FIFO_OVERFLOW</name>
<description>Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_DATA_FIFO_UNDERFLOW</name>
<description>Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt set register</description>
<addressOffset>0x7C4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>TR_TX_REQ</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TR_RX_REQ</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>XIP_ALIGNMENT_ERROR</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_CMD_FIFO_OVERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_DATA_FIFO_OVERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_DATA_FIFO_UNDERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt mask register</description>
<addressOffset>0x7C8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>TR_TX_REQ</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TR_RX_REQ</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>XIP_ALIGNMENT_ERROR</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_CMD_FIFO_OVERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_DATA_FIFO_OVERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_DATA_FIFO_UNDERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt masked register</description>
<addressOffset>0x7CC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>TR_TX_REQ</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TR_RX_REQ</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>XIP_ALIGNMENT_ERROR</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_CMD_FIFO_OVERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_DATA_FIFO_OVERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_DATA_FIFO_UNDERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<cluster>
<dim>4</dim>
<dimIncrement>128</dimIncrement>
<name>DEVICE[%s]</name>
<description>Device (only used in XIP mode)</description>
<addressOffset>0x00000800</addressOffset>
<register>
<name>CTL</name>
<description>Control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80030101</resetMask>
<fields>
<field>
<name>WR_EN</name>
<description>Write enable:
'0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error.
'1': write transfers are allowed to this device.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CRYPTO_EN</name>
<description>Cryptography on read/write accesses:
'0': disabled.
'1': enabled.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DATA_SEL</name>
<description>Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7):
'0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode.
'1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes.
'2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device.
'3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Device enable:
'0': Disabled.
'1': Enabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADDR</name>
<description>Device region base address</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>ADDR</name>
<description>Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m.
In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index.
The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24].</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MASK</name>
<description>Device region mask</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>MASK</name>
<description>Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] &amp; MASK[31:8]) == ADDR.ADDR[31:8].
The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff.
Note: a transfer request that is not in any device region results in an AHB-Lite bus error.</description>
<bitRange>[31:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADDR_CTL</name>
<description>Address control</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x103</resetMask>
<fields>
<field>
<name>SIZE2</name>
<description>Specifies the size of the XIP device address in Bytes:
'0': 1 Byte address.
'1': 2 Byte address.
'2': 3 Byte address.
'3': 4 Byte address.
The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DIV2</name>
<description>Specifies if the AHB-Lite bus transfer address is divided by 2 or not:
'0': No divide by 2.
'1': Divide by 2.
This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RD_CMD_CTL</name>
<description>Read command control</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x800300FF</resetMask>
<fields>
<field>
<name>CODE</name>
<description>Command byte code.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WIDTH</name>
<description>Width of data transfer:
'0': 1 bit/cycle (single data transfer).
'1': 2 bits/cycle (dual data transfer).
'2': 4 bits/cycle (quad data transfer).
'3': 8 bits/cycle (octal data transfer).</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRESENT</name>
<description>Presence of command field:
'0': not present
'1': present</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RD_ADDR_CTL</name>
<description>Read address control</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x30000</resetMask>
<fields>
<field>
<name>WIDTH</name>
<description>Width of transfer.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RD_MODE_CTL</name>
<description>Read mode control</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x800300FF</resetMask>
<fields>
<field>
<name>CODE</name>
<description>Mode byte code.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WIDTH</name>
<description>Width of transfer.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRESENT</name>
<description>Presence of mode field:
'0': not present
'1': present</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RD_DUMMY_CTL</name>
<description>Read dummy control</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x8000001F</resetMask>
<fields>
<field>
<name>SIZE5</name>
<description>Number of dummy cycles (minus 1):
'0': 1 cycles
...
'31': 32 cycles.
Note: this field specifies dummy cycles, not dummy Bytes!</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRESENT</name>
<description>Presence of dummy cycles:
'0': not present
'1': present</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RD_DATA_CTL</name>
<description>Read data control</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x30000</resetMask>
<fields>
<field>
<name>WIDTH</name>
<description>Width of transfer.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WR_CMD_CTL</name>
<description>Write command control</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x800300FF</resetMask>
<fields>
<field>
<name>CODE</name>
<description>Command byte code.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WIDTH</name>
<description>Width of transfer.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRESENT</name>
<description>Presence of command field:
'0': not present
'1': present</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WR_ADDR_CTL</name>
<description>Write address control</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x30000</resetMask>
<fields>
<field>
<name>WIDTH</name>
<description>Width of transfer.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WR_MODE_CTL</name>
<description>Write mode control</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x800300FF</resetMask>
<fields>
<field>
<name>CODE</name>
<description>Mode byte code.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WIDTH</name>
<description>Width of transfer.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRESENT</name>
<description>Presence of mode field:
'0': not present
'1': present</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WR_DUMMY_CTL</name>
<description>Write dummy control</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x8000001F</resetMask>
<fields>
<field>
<name>SIZE5</name>
<description>Number of dummy cycles (minus 1):
'0': 1 cycles
...
'31': 32 cycles.</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PRESENT</name>
<description>Presence of dummy cycles:
'0': not present
'1': present</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WR_DATA_CTL</name>
<description>Write data control</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x30000</resetMask>
<fields>
<field>
<name>WIDTH</name>
<description>Width of transfer.</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<peripheral>
<name>SCB0</name>
<description>Serial Communications Block (SPI/UART/I2C)</description>
<headerStructName>SCB</headerStructName>
<baseAddress>0x40610000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<description>Generic control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x300000F</resetValue>
<resetMask>0x83031F0F</resetMask>
<fields>
<field>
<name>OVS</name>
<description>N/A</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EC_AM_MODE</name>
<description>This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)
'0': Internally clocked mode
'1': Externally clocked mode
In internally clocked mode, the serial interface protocols run off the SCB clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface.
The clocking for the rest of the logic is determined by CTRL.EC_OP_MODE.
Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported.
In UART mode this field should be '0'.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EC_OP_MODE</name>
<description>This field specifies the clocking for the SCB block
'0': Internally clocked mode
'1': externally clocked mode
In internally clocked mode, the serial interface protocols run off the SCB clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface.
Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate).
In UART mode this field should be '0'.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_MODE</name>
<description>Non EZ mode ('0') or EZ mode ('1').
In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames not seperated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of 32 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first.
In UART mode this field should be '0'.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BYTE_MODE</name>
<description>N/A</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CMD_RESP_MODE</name>
<description>N/A</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ADDR_ACCEPT</name>
<description>Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0').
In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when this bit is '1' for both I2C read and write transfers.
In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLOCK</name>
<description>Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide, this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, CPU read operations return 0xffff:ffff and CPU write operations are ignored. Colliding accesses are registered as interrupt causes: INTR_TX.BLOCKED and INTR_RX.BLOCKED.</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>N/A</description>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>I2C</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>UART</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENABLED</name>
<description>SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:
- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL registers. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable.
- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality.
- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information.
- Program CTRL register to enable SCB, select the specific operation mode and oversampling factor.
When this block is enabled, no control information should be changed. Changes should be made AFTER disabling this block, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the block is re-enabled. Note that disabling the block will cause re-initialization of the design and associated state is lost (e.g. FIFO content).</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Generic status</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>EC_BUSY</name>
<description>Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CMD_RESP_CTRL</name>
<description>Command/response control</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1FF01FF</resetMask>
<fields>
<field>
<name>BASE_RD_ADDR</name>
<description>I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers.</description>
<bitRange>[8:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BASE_WR_ADDR</name>
<description>I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers.</description>
<bitRange>[24:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMD_RESP_STATUS</name>
<description>Command/response status</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>CURR_RD_ADDR</name>
<description>I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address).
The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR).
This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e. when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
<bitRange>[8:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CURR_WR_ADDR</name>
<description>I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address).
The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR).
This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
<bitRange>[24:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CMD_RESP_EC_BUS_BUSY</name>
<description>Indicates whether there is an ongoing bus transfer to the IP.
'0': no ongoing bus transfer.
'1': ongoing bus transfer.
For SPI, the field is '1' when slave mode is selected.
For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match.</description>
<bitRange>[30:30]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CMD_RESP_EC_BUSY</name>
<description>N/A</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SPI_CTRL</name>
<description>SPI control</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3000000</resetValue>
<resetMask>0x8F010F3F</resetMask>
<fields>
<field>
<name>SSEL_CONTINUOUS</name>
<description>Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field.
When continuous transfers are enabled individual data frame transfers are not necessarily seperated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection.
When continuous transfers are not enabled individual data frame transfers are always seperated by slave deselection: independent of the availability of TX FIFO data frames, data frames are sent out with slave deselection.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SELECT_PRECEDE</name>
<description>Only used in SPI Texas Instruments' submode.
When '1', the data frame start indication is a pulse on the Slave SELECT line that precedes the transfer of the first data frame bit.
When '0', the data frame start indication is a pulse on the Slave SELECT line that coincides with the transfer of the first data frame bit.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CPHA</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CPOL</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LATE_MISO_SAMPLE</name>
<description>Changes the SCLK edge on which MISO is captured. Only used in master mode.
When '0', the default applies (
for Motorola as determined by CPOL and CPHA,
for Texas Instruments on the falling edge of SCLK and
for National Semiconductors on the rising edge of SCLK).
When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCLK_CONTINUOUS</name>
<description>N/A</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SSEL_POLARITY0</name>
<description>N/A</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SSEL_POLARITY1</name>
<description>N/A</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SSEL_POLARITY2</name>
<description>N/A</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SSEL_POLARITY3</name>
<description>N/A</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LOOPBACK</name>
<description>Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode.
'0': No local loopback
'1': the SPI master MISO line is connected to the SPI master MOSI line. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>N/A</description>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SPI_MOTOROLA</name>
<description>SPI Motorola submode. In master mode, when not transmitting data (Slave SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), Slave SELECT is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI_TI</name>
<description>SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), Slave SELECT is inactive; i.e. no pulse is generated.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI_NS</name>
<description>SPI National Semiconducturs submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), Slave SELECT is inactive.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSEL</name>
<description>Selects one of the four incoming/outgoing SPI slave select signals:
- 0: Slave 0, SSEL[0].
- 1: Slave 1, SSEL[1].
- 2: Slave 2, SSEL[2].
- 3: Slave 3, SSEL[3].
SCB block should be disabled when changes are made to this field.</description>
<bitRange>[27:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MASTER_MODE</name>
<description>N/A</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_STATUS</name>
<description>SPI status</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>BUS_BUSY</name>
<description>SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SPI_EC_BUSY</name>
<description>Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CURR_EZ_ADDR</name>
<description>SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design.</description>
<bitRange>[15:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BASE_EZ_ADDR</name>
<description>SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design.</description>
<bitRange>[23:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UART_CTRL</name>
<description>UART control</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x3000000</resetValue>
<resetMask>0x3010000</resetMask>
<fields>
<field>
<name>LOOPBACK</name>
<description>Local loopback control (does NOT affect the information on the pins).
0: Loopback is not enabled
1: UART_TX is connected to UART_RX. UART_RTS is connected to UART_CTS.
This allows a SCB UART transmitter to communicate with its receiver counterpart.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>N/A</description>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>UART_STD</name>
<description>N/A</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UART_SMARTCARD</name>
<description>N/A</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>UART_IRDA</name>
<description>Infrared Data Association (IrDA) submode. Return to Zero modulation scheme. In this mode, the oversampling factor should be 16, that is OVS should be set to 15.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART_TX_CTRL</name>
<description>UART transmitter control</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2</resetValue>
<resetMask>0x137</resetMask>
<fields>
<field>
<name>STOP_BITS</name>
<description>Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PARITY</name>
<description>Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PARITY_ENABLED</name>
<description>Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RETRY_ON_NACK</name>
<description>When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UART_RX_CTRL</name>
<description>UART receiver control</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA0002</resetValue>
<resetMask>0xF3777</resetMask>
<fields>
<field>
<name>STOP_BITS</name>
<description>N/A</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PARITY</name>
<description>N/A</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PARITY_ENABLED</name>
<description>N/A</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>POLARITY</name>
<description>Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DROP_ON_PARITY_ERROR</name>
<description>Behaviour when a parity check fails.
When '0', received data is sent to the RX FIFO.
When '1', received data is dropped and lost.
Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field).</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DROP_ON_FRAME_ERROR</name>
<description>Behaviour when an error is detected in a start or stop period.
When '0', received data is sent to the RX FIFO.
When '1', received data is dropped and lost.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MP_MODE</name>
<description>N/A</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LIN_MODE</name>
<description>Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SKIP_START</name>
<description>N/A</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BREAK_WIDTH</name>
<description>N/A</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UART_RX_STATUS</name>
<description>UART receiver status</description>
<addressOffset>0x4C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>BR_COUNTER</name>
<description>Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'.</description>
<bitRange>[11:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UART_FLOW_CTRL</name>
<description>UART flow control</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x30100FF</resetMask>
<fields>
<field>
<name>TRIGGER_LEVEL</name>
<description>Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to '0', flow control is effectively disabled (may be useful for debug purposes).</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RTS_POLARITY</name>
<description>Polarity of the RTS output signal:
'0': RTS is active low;
'1': RTS is active high;
During SCB reset (Hibernate system power mode), RTS output signal is '1'. This represents an inactive state assuming an active low polarity.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTS_POLARITY</name>
<description>Polarity of the CTS input signal
'0': CTS is active low ;
'1': CTS is active high;</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTS_ENABLED</name>
<description>Enable use of CTS input signal by the UART transmitter:
'0': Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register.
'1': Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register.
If UART_CTRL.LOOPBACK is '1', the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes are indicated by RTS_POLARITY and CTS_POLARITY).</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2C_CTRL</name>
<description>I2C control</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFB88</resetValue>
<resetMask>0xC001FBFF</resetMask>
<fields>
<field>
<name>HIGH_PHASE_OVS</name>
<description>Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering.
The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the SCB clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be &gt;= 6 SCB clock cycles and &lt;= 16 SCB clock cycles. Without input signal median filtering, the IF high time should be &gt;= 5 SCB clock cycles and &lt;= 16 SCB clock cycles.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LOW_PHASE_OVS</name>
<description>Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering.
The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the SCB clock wrt. the regular (no stretching) interface (IF) low time to guarantee functionally correct behavior. With input signal median filtering, the IF low time should be &gt;= 8 SCB clock cycles and &lt;= 16 IP clock cycles. Without input signal median filtering, the IF low time should be &gt;= 7 SCB clock cycles and &lt;= 16 SCB clock cycles.</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>M_READY_DATA_ACK</name>
<description>N/A</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>M_NOT_READY_DATA_NACK</name>
<description>N/A</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>S_GENERAL_IGNORE</name>
<description>N/A</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>S_READY_ADDR_ACK</name>
<description>N/A</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>S_READY_DATA_ACK</name>
<description>N/A</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>S_NOT_READY_ADDR_NACK</name>
<description>This field is used during an address match or general call address in internally clocked mode
Only used when:
- EC_AM_MODE is '0', EC_OP_MODE is '0', S_GENERAL_IGNORE is '0] and non EZ mode.
Functionality is as follows:
- 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full.
- 0: clock stretching is performed (till the receiver FIFO is no longer full).
For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode):
- EC_AM is '1' and EC_OP is '0'.
- EC_AM is '1' and general call address match.
- EC_AM is '1' and non EZ mode.
Functionality is as follows:
- 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities:
1). the SCB clock is available (in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK.
2).SCB clock is not present (in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode).
- 0: clock stretching is performed (till the SCB clock is available). The logic will handle the ongoing transfer as soon as the clock is enabled.</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>S_NOT_READY_DATA_NACK</name>
<description>Only used when:
- non EZ mode
Functionality is as follows:
- 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full.
- 0: clock stretching is performed (till the receiver FIFO is no longer full).</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
<field>
<name>LOOPBACK</name>
<description>Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode.
When '0', no loopback
When '1', loopback is enabled internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SLAVE_MODE</name>
<description>N/A</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MASTER_MODE</name>
<description>N/A</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2C_STATUS</name>
<description>I2C status</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x31</resetMask>
<fields>
<field>
<name>BUS_BUSY</name>
<description>I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If SCB block is disabled, BUS_BUSY is '0'. After enabling the block, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period).
For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions).
For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions).</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_EC_BUSY</name>
<description>N/A</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>S_READ</name>
<description>N/A</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>M_READ</name>
<description>N/A</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CURR_EZ_ADDR</name>
<description>N/A</description>
<bitRange>[15:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BASE_EZ_ADDR</name>
<description>N/A</description>
<bitRange>[23:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>I2C_M_CMD</name>
<description>I2C master command</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1F</resetMask>
<fields>
<field>
<name>M_START</name>
<description>When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>M_START_ON_IDLE</name>
<description>When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>M_ACK</name>
<description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>M_NACK</name>
<description>When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>M_STOP</name>
<description>When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'.
I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2C_S_CMD</name>
<description>I2C slave command</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>S_ACK</name>
<description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode).</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>S_NACK</name>
<description>When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2C_CFG</name>
<description>I2C configuration</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x2A1013</resetValue>
<resetMask>0x303F1313</resetMask>
<fields>
<field>
<name>SDA_IN_FILT_TRIM</name>
<description>Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SDA_IN_FILT_SEL</name>
<description>Enable for 50ns glitch filter on SDA input
'0': 0 ns.
'1: 50 ns (filter enabled).</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCL_IN_FILT_TRIM</name>
<description>Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCL_IN_FILT_SEL</name>
<description>Enable for 50ns glitch filter on SCL input
'0': 0 ns.
'1: 50 ns (filter enabled).</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SDA_OUT_FILT0_TRIM</name>
<description>Trim settings for the 50ns delay filter on SDA output used to gurantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required</description>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SDA_OUT_FILT1_TRIM</name>
<description>Trim settings for the 50ns delay filter on SDA output used to gurantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required</description>
<bitRange>[19:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SDA_OUT_FILT2_TRIM</name>
<description>Trim settings for the 50ns delay filter on SDA output used to gurantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required</description>
<bitRange>[21:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SDA_OUT_FILT_SEL</name>
<description>Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter
'0': 0 ns.
'1': 50 ns (filter 0 enabled).
'2': 100 ns (filters 0 and 1 enabled).
'3': 150 ns (filters 0, 1 and 2 enabled).</description>
<bitRange>[29:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DDFT_CTRL</name>
<description>Digital DfT control</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x770011</resetMask>
<fields>
<field>
<name>DDFT_IN0_SEL</name>
<description>Specifies signal that is connected to 'ddft_in[0]' (digital DfT input signal 0):
'0': not used
'1': used as 'i2c_scl_in' in I2C mode, as 'spi_clk_in' in SPI mode</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DDFT_IN1_SEL</name>
<description>Specifies signal that is connected to 'ddft_in[1]' (digital DfT input signal 0):
'0': not used
'1': used as 'i2c_sda_in' in I2C mode, as 'spi_mosi_in' in SPI mode</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DDFT_OUT0_SEL</name>
<description>Specifies signal that is connected to 'ddft_out[0]' (digital DfT output signal 0):
In I2C mode (CTRL.MODE=0),
'0': Constant '0'.
'1': 'ec_busy_pp'.
'2': 'rst_i2c_start_stop_n'.
'3': 'rst_i2c_start_stop_n'.
'4': 'i2c_scl_in_qual'.
'5': 'i2c_sda_out_prel'.
'6'-'7': Undefined.
in SPI mode (CTRL.MODE=1),
'0': Constant '0'.
'1': 'rst_spi_n'
'2': 'rst_spi_stop_n'
'3'-'7': Undefined.</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DDFT_OUT1_SEL</name>
<description>Specifies signal that is connected to 'ddft_out[1]' (digital DfT output signal 1):
In I2C mode (CTRL.MODE=0),
'0': Constant '0'.
'1': 'clk_ff_sram'.
'2': 'rst_i2c_n'.
'3': 'rst_i2c_stop_n'.
'4': 'i2c_sda_in_qual'.
'5': 'i2c_sda_out'.
'6': 'event_i2c_ec_wake_up_ddft' from I2CS_IC
'7': Undefined.
In SPI mode (CTRL.MODE=1),
'0': Constant '0'.
'1': 'spi_start_detect'
'2': 'spi_stop_detect'
'3'-'7': Undefined.</description>
<bitRange>[22:20]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TX_CTRL</name>
<description>Transmitter control</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x107</resetValue>
<resetMask>0x1010F</resetMask>
<fields>
<field>
<name>DATA_WIDTH</name>
<description>Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MSB_FIRST</name>
<description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OPEN_DRAIN</name>
<description>Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'.
'0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'.
'1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1').
The open drain mode is supported for:
- I2C mode, 'i2c_scl' and 'i2c_sda' IO cells.
- UART mode, 'uart_tx' IO cell (SPI slave).
- SPI mode, 'spi_miso' IO cell.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TX_FIFO_CTRL</name>
<description>Transmitter FIFO control</description>
<addressOffset>0x204</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x300FF</resetMask>
<fields>
<field>
<name>TRIGGER_LEVEL</name>
<description>Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event is generated.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLEAR</name>
<description>When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FREEZE</name>
<description>When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer.</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TX_FIFO_STATUS</name>
<description>Transmitter FIFO status</description>
<addressOffset>0x208</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF81FF</resetMask>
<fields>
<field>
<name>USED</name>
<description>Amount of enties in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR.</description>
<bitRange>[8:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SR_VALID</name>
<description>Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is tranmitted next (when the protocol state machine is not transmitting a data frame).</description>
<bitRange>[15:15]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RD_PTR</name>
<description>FIFO read pointer: FIFO location from which a data frame is read by the hardware.</description>
<bitRange>[23:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WR_PTR</name>
<description>FIFO write pointer: FIFO location at which a new data frame is written.</description>
<bitRange>[31:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TX_FIFO_WR</name>
<description>Transmitter FIFO write</description>
<addressOffset>0x240</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used.
A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'.</description>
<bitRange>[15:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>RX_CTRL</name>
<description>Receiver control</description>
<addressOffset>0x300</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x107</resetValue>
<resetMask>0x30F</resetMask>
<fields>
<field>
<name>DATA_WIDTH</name>
<description>Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7.</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MSB_FIRST</name>
<description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MEDIAN</name>
<description>Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptability to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_CTRL</name>
<description>Receiver FIFO control</description>
<addressOffset>0x304</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x300FF</resetMask>
<fields>
<field>
<name>TRIGGER_LEVEL</name>
<description>Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event is generated.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLEAR</name>
<description>When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FREEZE</name>
<description>When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer.</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_STATUS</name>
<description>Receiver FIFO status</description>
<addressOffset>0x308</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF81FF</resetMask>
<fields>
<field>
<name>USED</name>
<description>Amount of enties in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR.</description>
<bitRange>[8:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SR_VALID</name>
<description>Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame).</description>
<bitRange>[15:15]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RD_PTR</name>
<description>FIFO read pointer: FIFO location from which a data frame is read.</description>
<bitRange>[23:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WR_PTR</name>
<description>FIFO write pointer: FIFO location at which a new data frame is written by the hardware.</description>
<bitRange>[31:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_MATCH</name>
<description>Slave address and mask</description>
<addressOffset>0x310</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF00FF</resetMask>
<fields>
<field>
<name>ADDR</name>
<description>N/A</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MASK</name>
<description>Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR &amp; MASK) == ('slave address' &amp; MASK)).</description>
<bitRange>[23:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_RD</name>
<description>Receiver FIFO read</description>
<addressOffset>0x340</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used.
A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.
When this register is read through the debugger, the data frame will not be removed from the FIFO. Similar in operation to RX_FIFO_RD_SILENT</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_RD_SILENT</name>
<description>Receiver FIFO read silent</description>
<addressOffset>0x344</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x0</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used.
A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_CAUSE</name>
<description>Active clocked interrupt signal</description>
<addressOffset>0xE00</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>M</name>
<description>Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>S</name>
<description>Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX</name>
<description>Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX</name>
<description>Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_EC</name>
<description>Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0.</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SPI_EC</name>
<description>Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_I2C_EC</name>
<description>Externally clocked I2C interrupt request</description>
<addressOffset>0xE80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>WAKE_UP</name>
<description>Wake up request. Active on incoming slave request (with address match).
Only used when CTRL.EC_AM_MODE is '1'.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_STOP</name>
<description>STOP detection. Activated on the end of a every transfer (I2C STOP).
Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_WRITE_STOP</name>
<description>STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event.
Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_READ_STOP</name>
<description>STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from.
Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_I2C_EC_MASK</name>
<description>Externally clocked I2C interrupt mask</description>
<addressOffset>0xE88</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>WAKE_UP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_STOP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_WRITE_STOP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_READ_STOP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_I2C_EC_MASKED</name>
<description>Externally clocked I2C interrupt masked</description>
<addressOffset>0xE8C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>WAKE_UP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EZ_STOP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EZ_WRITE_STOP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EZ_READ_STOP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_SPI_EC</name>
<description>Externally clocked SPI interrupt request</description>
<addressOffset>0xEC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>WAKE_UP</name>
<description>Wake up request. Active on incoming slave request when externally clocked selection is '1'.
Only used when CTRL.EC_AM_MODE is '1'.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_STOP</name>
<description>STOP detection. Activated on the end of a every transfer (SPI deselection).
Only available in EZ and CMD_RESP mode and when CTRL.EC_OP_MODE is '1'.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_WRITE_STOP</name>
<description>STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event.
Only used in EZ and CMD_RESP modes and when CTRL.EC_OP_MODE is '1'.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_READ_STOP</name>
<description>STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from.
Only used in EZ and CMD_RESP modes and when CTRL.EC_OP_MODE is '1'.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SPI_EC_MASK</name>
<description>Externally clocked SPI interrupt mask</description>
<addressOffset>0xEC8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>WAKE_UP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_STOP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_WRITE_STOP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EZ_READ_STOP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SPI_EC_MASKED</name>
<description>Externally clocked SPI interrupt masked</description>
<addressOffset>0xECC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>WAKE_UP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EZ_STOP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EZ_WRITE_STOP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EZ_READ_STOP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_M</name>
<description>Master interrupt request</description>
<addressOffset>0xF00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x317</resetMask>
<fields>
<field>
<name>I2C_ARB_LOST</name>
<description>I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_NACK</name>
<description>I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data).</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_ACK</name>
<description>I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data).</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_STOP</name>
<description>I2C master STOP. Set to '1', when the master has transmitted a STOP.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_BUS_ERROR</name>
<description>I2C master bus error (unexpected detection of START or STOP condition).</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_DONE</name>
<description>SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_M_SET</name>
<description>Master interrupt set request</description>
<addressOffset>0xF04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x317</resetMask>
<fields>
<field>
<name>I2C_ARB_LOST</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_NACK</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_ACK</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_STOP</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_BUS_ERROR</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_DONE</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_M_MASK</name>
<description>Master interrupt mask</description>
<addressOffset>0xF08</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x317</resetMask>
<fields>
<field>
<name>I2C_ARB_LOST</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_NACK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_ACK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_STOP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_BUS_ERROR</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_DONE</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_M_MASKED</name>
<description>Master interrupt masked request</description>
<addressOffset>0xF0C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x317</resetMask>
<fields>
<field>
<name>I2C_ARB_LOST</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_NACK</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_ACK</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_STOP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_BUS_ERROR</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SPI_DONE</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[9:9]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_S</name>
<description>Slave interrupt request</description>
<addressOffset>0xF40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>I2C_ARB_LOST</name>
<description>I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine aborts the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_NACK</name>
<description>N/A</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_ACK</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_WRITE_STOP</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_STOP</name>
<description>N/A</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_START</name>
<description>I2C slave START received. Set to '1', when START or REPEATED START event is detected.
In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_ADDR_MATCH</name>
<description>N/A</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_GENERAL</name>
<description>N/A</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_BUS_ERROR</name>
<description>N/A</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_EZ_WRITE_STOP</name>
<description>N/A</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_EZ_STOP</name>
<description>N/A</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_BUS_ERROR</name>
<description>N/A</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_S_SET</name>
<description>Slave interrupt set request</description>
<addressOffset>0xF44</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>I2C_ARB_LOST</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_NACK</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_ACK</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_WRITE_STOP</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_STOP</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_START</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_ADDR_MATCH</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_GENERAL</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_BUS_ERROR</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_EZ_WRITE_STOP</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_EZ_STOP</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_BUS_ERROR</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_S_MASK</name>
<description>Slave interrupt mask</description>
<addressOffset>0xF48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>I2C_ARB_LOST</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_NACK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_ACK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_WRITE_STOP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_STOP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_START</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_ADDR_MATCH</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_GENERAL</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>I2C_BUS_ERROR</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_EZ_WRITE_STOP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_EZ_STOP</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SPI_BUS_ERROR</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_S_MASKED</name>
<description>Slave interrupt masked request</description>
<addressOffset>0xF4C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>I2C_ARB_LOST</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_NACK</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_ACK</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_WRITE_STOP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_STOP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_START</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_ADDR_MATCH</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_GENERAL</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>I2C_BUS_ERROR</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SPI_EZ_WRITE_STOP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[9:9]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SPI_EZ_STOP</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[10:10]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SPI_BUS_ERROR</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[11:11]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_TX</name>
<description>Transmitter interrupt request</description>
<addressOffset>0xF80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7F3</resetMask>
<fields>
<field>
<name>TRIGGER</name>
<description>N/A</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NOT_FULL</name>
<description>N/A</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EMPTY</name>
<description>N/A</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERFLOW</name>
<description>N/A</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UNDERFLOW</name>
<description>Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'.
Only used in FIFO mode.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLOCKED</name>
<description>SW cannot get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UART_NACK</name>
<description>N/A</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UART_DONE</name>
<description>N/A</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UART_ARB_LOST</name>
<description>N/A</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_TX_SET</name>
<description>Transmitter interrupt set request</description>
<addressOffset>0xF84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7F3</resetMask>
<fields>
<field>
<name>TRIGGER</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NOT_FULL</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EMPTY</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UNDERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLOCKED</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UART_NACK</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UART_DONE</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UART_ARB_LOST</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_TX_MASK</name>
<description>Transmitter interrupt mask</description>
<addressOffset>0xF88</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x7F3</resetMask>
<fields>
<field>
<name>TRIGGER</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NOT_FULL</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EMPTY</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UNDERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLOCKED</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UART_NACK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UART_DONE</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UART_ARB_LOST</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_TX_MASKED</name>
<description>Transmitter interrupt masked request</description>
<addressOffset>0xF8C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x7F3</resetMask>
<fields>
<field>
<name>TRIGGER</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NOT_FULL</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>EMPTY</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>OVERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>UNDERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BLOCKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>UART_NACK</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>UART_DONE</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[9:9]</bitRange>
<access>read-only</access>
</field>
<field>
<name>UART_ARB_LOST</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[10:10]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_RX</name>
<description>Receiver interrupt request</description>
<addressOffset>0xFC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFED</resetMask>
<fields>
<field>
<name>TRIGGER</name>
<description>N/A</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NOT_EMPTY</name>
<description>N/A</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FULL</name>
<description>N/A</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERFLOW</name>
<description>N/A</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UNDERFLOW</name>
<description>N/A</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLOCKED</name>
<description>SW cannot get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FRAME_ERROR</name>
<description>N/A</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PARITY_ERROR</name>
<description>N/A</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BAUD_DETECT</name>
<description>N/A</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BREAK_DETECT</name>
<description>N/A</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_RX_SET</name>
<description>Receiver interrupt set request</description>
<addressOffset>0xFC4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFED</resetMask>
<fields>
<field>
<name>TRIGGER</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NOT_EMPTY</name>
<description>Write with '1' to set corresponding bit in interrupt status register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FULL</name>
<description>Write with '1' to set corresponding bit in interrupt status register.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt status register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UNDERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt status register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLOCKED</name>
<description>Write with '1' to set corresponding bit in interrupt status register.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FRAME_ERROR</name>
<description>Write with '1' to set corresponding bit in interrupt status register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PARITY_ERROR</name>
<description>Write with '1' to set corresponding bit in interrupt status register.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BAUD_DETECT</name>
<description>Write with '1' to set corresponding bit in interrupt status register.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BREAK_DETECT</name>
<description>Write with '1' to set corresponding bit in interrupt status register.</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_RX_MASK</name>
<description>Receiver interrupt mask</description>
<addressOffset>0xFC8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFED</resetMask>
<fields>
<field>
<name>TRIGGER</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NOT_EMPTY</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FULL</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UNDERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BLOCKED</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FRAME_ERROR</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PARITY_ERROR</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BAUD_DETECT</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BREAK_DETECT</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_RX_MASKED</name>
<description>Receiver interrupt masked request</description>
<addressOffset>0xFCC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFED</resetMask>
<fields>
<field>
<name>TRIGGER</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>NOT_EMPTY</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>FULL</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>OVERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>UNDERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BLOCKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>FRAME_ERROR</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>PARITY_ERROR</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[9:9]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BAUD_DETECT</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[10:10]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BREAK_DETECT</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[11:11]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SCB0">
<name>SCB1</name>
<baseAddress>0x40620000</baseAddress>
</peripheral>
<peripheral derivedFrom="SCB0">
<name>SCB2</name>
<baseAddress>0x40630000</baseAddress>
</peripheral>
<peripheral derivedFrom="SCB0">
<name>SCB3</name>
<baseAddress>0x40640000</baseAddress>
</peripheral>
<peripheral derivedFrom="SCB0">
<name>SCB4</name>
<baseAddress>0x40650000</baseAddress>
</peripheral>
<peripheral derivedFrom="SCB0">
<name>SCB5</name>
<baseAddress>0x40660000</baseAddress>
</peripheral>
<peripheral derivedFrom="SCB0">
<name>SCB6</name>
<baseAddress>0x40670000</baseAddress>
</peripheral>
<peripheral derivedFrom="SCB0">
<name>SCB7</name>
<baseAddress>0x40680000</baseAddress>
</peripheral>
<peripheral derivedFrom="SCB0">
<name>SCB8</name>
<baseAddress>0x40690000</baseAddress>
</peripheral>
<peripheral>
<name>CTBM0</name>
<description>Continuous Time Block Mini</description>
<headerStructName>CTBM</headerStructName>
<baseAddress>0x41100000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTB_CTRL</name>
<description>global CTB and power control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC0000000</resetMask>
<fields>
<field>
<name>DEEPSLEEP_ON</name>
<description>- 0: CTB IP disabled off during DeepSleep power mode
- 1: CTB IP remains enabled during DeepSleep power mode (if ENABLED=1)</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>- 0: CTB IP disabled (put analog in power down, open all switches)
- 1: CTB IP enabled</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OA_RES0_CTRL</name>
<description>Opamp0 and resistor0 control</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1BFF</resetMask>
<fields>
<field>
<name>OA0_PWR_MODE</name>
<description>Opamp0 power level, assumes Cload=15pF for the (internal only) 1x driver or 50pF for the (external) 10x driver</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Off</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW</name>
<description>Low power mode (IDD: 350uA, GBW: 1MHz for both 1x/10x)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MEDIUM</name>
<description>Medium power mode (IDD: 600uA, GBW: 3MHz for 1x &amp; 2.5MHz for 10x)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>High power mode for highest GBW (IDD: 1500uA, GBW: 8MHz for 1x &amp; 6MHz for 10x)</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD</name>
<description>N/A</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>PS_LOW</name>
<description>Power Saver Low power mode (IDD: ~20uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is disabled)</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>PS_MEDIUM</name>
<description>Power Saver Medium power mode (IDD: ~40uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is enabled)</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>PS_HIGH</name>
<description>Power Saver Medium power mode (IDD: ~60uA with 1uA bias from AREF, GBW: ~200kHz for 1x/10x, offset correcting IDAC is enabled)</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OA0_DRIVE_STR_SEL</name>
<description>Opamp0 output strength select 0=1x, 1=10x
This setting sets specific requirements for OA0_BOOST_EN and OA0_COMP_TRIM</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0_COMP_EN</name>
<description>Opamp0 comparator enable</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0_HYST_EN</name>
<description>Opamp0 hysteresis enable (10mV)</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0_BYPASS_DSI_SYNC</name>
<description>Opamp0 bypass comparator output synchronization for DSI (trigger) output: 0=synchronize (level or pulse), 1=bypass (output async)</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0_DSI_LEVEL</name>
<description>Opamp0 comparator DSI (trigger) out level :
0=pulse, each time an edge is detected (see OA0_COMPINT) a pulse is sent out on DSI
1=level, DSI output is a synchronized version of the comparator output</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0_COMPINT</name>
<description>Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger)</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disabled, no interrupts will be detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edge</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH</name>
<description>Both rising and falling edges</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OA0_PUMP_EN</name>
<description>Opamp0 pump enable</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0_BOOST_EN</name>
<description>Opamp0 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OA_RES1_CTRL</name>
<description>Opamp1 and resistor1 control</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1BFF</resetMask>
<fields>
<field>
<name>OA1_PWR_MODE</name>
<description>Opamp1 power level: see description of OA0_PWR_MODE</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1_DRIVE_STR_SEL</name>
<description>Opamp1 output strength select 0=1x, 1=10x
This setting sets specific requirements for OA1_BOOST_EN and OA1_COMP_TRIM</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1_COMP_EN</name>
<description>Opamp1 comparator enable</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1_HYST_EN</name>
<description>Opamp1 hysteresis enable (10mV)</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1_BYPASS_DSI_SYNC</name>
<description>Opamp1 bypass comparator output synchronization for DSI output: 0=synchronize, 1=bypass</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1_DSI_LEVEL</name>
<description>Opamp1 comparator DSI (trigger) out level :
0=pulse, each time an edge is detected (see OA1_COMPINT) a pulse is sent out on DSI
1=level, DSI output is a synchronized version of the comparator output</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1_COMPINT</name>
<description>Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger)</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLE</name>
<description>Disabled, no interrupts will be detected</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>Rising edge</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Falling edge</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH</name>
<description>Both rising and falling edges</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OA1_PUMP_EN</name>
<description>Opamp1 pump enable</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1_BOOST_EN</name>
<description>Opamp1 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COMP_STAT</name>
<description>Comparator status</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x10001</resetMask>
<fields>
<field>
<name>OA0_COMP</name>
<description>Opamp0 current comparator status</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>OA1_COMP</name>
<description>Opamp1 current comparator status</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Interrupt request register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>COMP0</name>
<description>Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>COMP1</name>
<description>Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt request set register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>COMP0_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>COMP1_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt request mask</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>COMP0_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>COMP1_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt request masked</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>COMP0_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>COMP1_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OA0_SW</name>
<description>Opamp0 switch control</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x24410D</resetMask>
<fields>
<field>
<name>OA0P_A00</name>
<description>Opamp0 positive terminal amuxbusa</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0P_A20</name>
<description>Opamp0 positive terminal P0</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0P_A30</name>
<description>Opamp0 positive terminal ctbbus0</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0M_A11</name>
<description>Opamp0 negative terminal P1</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0M_A81</name>
<description>Opamp0 negative terminal Opamp0 output</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0O_D51</name>
<description>Opamp0 output sarbus0 (ctbbus2 in CTB)</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0O_D81</name>
<description>Opamp0 output switch to short 1x with 10x drive</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OA0_SW_CLEAR</name>
<description>Opamp0 switch control clear</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x24410D</resetMask>
<fields>
<field>
<name>OA0P_A00</name>
<description>see corresponding bit in OA0_SW</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0P_A20</name>
<description>see corresponding bit in OA0_SW</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0P_A30</name>
<description>see corresponding bit in OA0_SW</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0M_A11</name>
<description>see corresponding bit in OA0_SW</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0M_A81</name>
<description>see corresponding bit in OA0_SW</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0O_D51</name>
<description>see corresponding bit in OA0_SW</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA0O_D81</name>
<description>see corresponding bit in OA0_SW</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OA1_SW</name>
<description>Opamp1 switch control</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x2C4193</resetMask>
<fields>
<field>
<name>OA1P_A03</name>
<description>Opamp1 positive terminal amuxbusb</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1P_A13</name>
<description>Opamp1 positive terminal P5</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1P_A43</name>
<description>Opamp1 positive terminal ctbbus1</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1P_A73</name>
<description>Opamp1 positive terminal to vref1</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1M_A22</name>
<description>Opamp1 negative terminal P4</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1M_A82</name>
<description>Opamp1 negative terminal Opamp1 output</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1O_D52</name>
<description>Opamp1 output sarbus0 (ctbbus2 in CTB)</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1O_D62</name>
<description>Opamp1 output sarbus1 (ctbbus3 in CTB)</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1O_D82</name>
<description>Opamp1 output switch to short 1x with 10x drive</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OA1_SW_CLEAR</name>
<description>Opamp1 switch control clear</description>
<addressOffset>0x8C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x2C4193</resetMask>
<fields>
<field>
<name>OA1P_A03</name>
<description>see corresponding bit in OA1_SW</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1P_A13</name>
<description>see corresponding bit in OA1_SW</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1P_A43</name>
<description>see corresponding bit in OA1_SW</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1P_A73</name>
<description>see corresponding bit in OA1_SW</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1M_A22</name>
<description>see corresponding bit in OA1_SW</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1M_A82</name>
<description>see corresponding bit in OA1_SW</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1O_D52</name>
<description>see corresponding bit in OA1_SW</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1O_D62</name>
<description>see corresponding bit in OA1_SW</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OA1O_D82</name>
<description>see corresponding bit in OA1_SW</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTD_SW</name>
<description>CTDAC connection switch control</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF732</resetMask>
<fields>
<field>
<name>CTDD_CRD</name>
<description>CTDAC Reference opamp output to ctdrefdrive</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDS_CRS</name>
<description>ctdrefsense to opamp input</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDS_COR</name>
<description>ctdvout to opamp input</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDO_C6H</name>
<description>P6 pin to Hold capacitor</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDO_COS</name>
<description>ctdvout to Hold capacitor (Sample switch). Note this switch will temporarily be opened for deglitching if CTDAC.DEGLITCH_COS is set</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDH_COB</name>
<description>Drive the CTDAC output with CTBM 1x output during hold mode in Sample and Hold operation</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDH_CHD</name>
<description>Hold capacitor connect</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDH_CA0</name>
<description>Hold capacitor to opamp input</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDH_CIS</name>
<description>Hold capacitor isolation (from all the other switches)</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDH_ILR</name>
<description>Hold capacitor leakage reduction (drive other side of CIS to capacitor voltage)</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTD_SW_CLEAR</name>
<description>CTDAC connection switch control clear</description>
<addressOffset>0xA4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF732</resetMask>
<fields>
<field>
<name>CTDD_CRD</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDS_CRS</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDS_COR</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDO_C6H</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDO_COS</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDH_COB</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDH_CHD</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDH_CA0</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDH_CIS</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDH_ILR</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTB_SW_DS_CTRL</name>
<description>CTB bus switch control</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x80000C00</resetMask>
<fields>
<field>
<name>P2_DS_CTRL23</name>
<description>for P22, D51 (dsi_out[2])</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>P3_DS_CTRL23</name>
<description>for P33, D52, D62 (dsi_out[3])</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTD_COS_DS_CTRL</name>
<description>Hold capacitor Sample switch (COS)</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTB_SW_SQ_CTRL</name>
<description>CTB bus switch Sar Sequencer control</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC00</resetMask>
<fields>
<field>
<name>P2_SQ_CTRL23</name>
<description>for D51</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>P3_SQ_CTRL23</name>
<description>for D52, D62</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTB_SW_STATUS</name>
<description>CTB bus switch control status</description>
<addressOffset>0xC8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xF0000000</resetMask>
<fields>
<field>
<name>OA0O_D51_STAT</name>
<description>see OA0O_D51 bit in OA0_SW</description>
<bitRange>[28:28]</bitRange>
<access>read-only</access>
</field>
<field>
<name>OA1O_D52_STAT</name>
<description>see OA1O_D52 bit in OA1_SW</description>
<bitRange>[29:29]</bitRange>
<access>read-only</access>
</field>
<field>
<name>OA1O_D62_STAT</name>
<description>see OA1O_D62 bit in OA1_SW</description>
<bitRange>[30:30]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CTD_COS_STAT</name>
<description>see COS bit in CTD_SW</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>OA0_OFFSET_TRIM</name>
<description>Opamp0 trim control</description>
<addressOffset>0xF00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>OA0_OFFSET_TRIM</name>
<description>Opamp0 offset trim</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OA0_SLOPE_OFFSET_TRIM</name>
<description>Opamp0 trim control</description>
<addressOffset>0xF04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>OA0_SLOPE_OFFSET_TRIM</name>
<description>Opamp0 slope offset drift trim</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OA0_COMP_TRIM</name>
<description>Opamp0 trim control</description>
<addressOffset>0xF08</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>OA0_COMP_TRIM</name>
<description>Opamp0 Compensation Capacitor Trim.
Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OA1_OFFSET_TRIM</name>
<description>Opamp1 trim control</description>
<addressOffset>0xF0C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>OA1_OFFSET_TRIM</name>
<description>Opamp1 offset trim</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OA1_SLOPE_OFFSET_TRIM</name>
<description>Opamp1 trim control</description>
<addressOffset>0xF10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>OA1_SLOPE_OFFSET_TRIM</name>
<description>Opamp1 slope offset drift trim</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OA1_COMP_TRIM</name>
<description>Opamp1 trim control</description>
<addressOffset>0xF14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>OA1_COMP_TRIM</name>
<description>Opamp1 Compensation Capacitor Trim.
Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CTDAC0</name>
<description>Continuous Time DAC</description>
<headerStructName>CTDAC</headerStructName>
<baseAddress>0x41140000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTDAC_CTRL</name>
<description>Global CTDAC control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFBC0033F</resetMask>
<fields>
<field>
<name>DEGLITCH_CNT</name>
<description>To prevent glitches after VALUE changes from propagating the output switch can be opened for DEGLITCH_CNT+1 clk_peri clock cycles.</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DEGLITCH_CO6</name>
<description>Force CTDAC.CO6 switch open after each VALUE change for the set number of clock cycles.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DEGLITCH_COS</name>
<description>Force CTB.COS switch open after each VALUE change for the set number of clock cycles.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OUT_EN</name>
<description>Output enable, intended to be used during the Hold phase of the Sample and Hold when power cycling :
0: output disabled, the output is either:
- Tri-state (DISABLED_MODE=0)
- or Vssa (DISABLED_MODE=1 &amp;&amp; CTDAC_RANGE=0)
- or Vref (DISABLED_MODE=1 &amp;&amp; CTDAC_RANGE=1)
1: output enabled, CTDAC output drives the programmed VALUE</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDAC_RANGE</name>
<description>By closing the bottom switch in the R2R network the output is lifted by one LSB, effectively adding 1
0: Range is [0, 4095] * Vref / 4096
1: Range is [1, 4096] * Vref / 4096</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDAC_MODE</name>
<description>DAC mode, this determines the Value decoding</description>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>UNSIGNED12</name>
<description>Unsigned 12-bit VDAC, i.e. no value decoding.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VIRT_SIGNED12</name>
<description>Virtual signed 12-bits' VDAC. Value decoding:
add 0x800 to the 12-bit Value (=invert MSB), to convert the lowest signed number 0x800 to the lowest unsigned number 0x000. This is the same as the SAR handles 12-bit 'virtual' signed numbers.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD2</name>
<description>N/A</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RSVD3</name>
<description>N/A</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DISABLED_MODE</name>
<description>Select the output value when the output is disabled (OUT_EN=0) (for risk mitigation)
0: Tri-state CTDAC output when disabled
1: output Vssa or Vref when disabled (see OUT_EN description)</description>
<bitRange>[27:27]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_STROBE_EN</name>
<description>DSI strobe input Enable. This enables CTDAC updates to be further throttled by DSI.
0: Ignore DSI strobe input
1: Only do a CTDAC update if alllowed by the DSI stobe (throttle), see below for level or edge</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_STROBE_LEVEL</name>
<description>Select level or edge detect for DSI strobe
- 0: DSI strobe signal is a pulse input, after a positive edge is detected on the DSI strobe signal the next DAC value update is done on the next CTDAC clock
- 1: DSI strobe signal is a level input, as long as the DSI strobe signal remains high the CTDAC will do a next DAC value update on each CTDAC clock.</description>
<bitRange>[29:29]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DEEPSLEEP_ON</name>
<description>- 0: CTDAC IP disabled off during DeepSleep power mode
- 1: CTDAC IP remains enabled during DeepSleep power mode (if ENABLED=1)</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>0: CTDAC IP disabled (put analog in power down, open all switches)
1: CTDAC IP enabled</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Interrupt request register</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>VDAC_EMPTY</name>
<description>VDAC Interrupt: hardware sets this interrupt when VDAC next value field is empty, i.e. was copied to the current VALUE. Write with '1' to clear bit.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt request set register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>VDAC_EMPTY_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt request mask</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>VDAC_EMPTY_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt request masked</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>VDAC_EMPTY_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CTDAC_SW</name>
<description>CTDAC switch control</description>
<addressOffset>0xB0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x101</resetMask>
<fields>
<field>
<name>CTDD_CVD</name>
<description>VDDA supply to ctdrefdrive</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDO_CO6</name>
<description>ctdvout to P6 pin. Note this switch will temporarily be opened for deglitching if DEGLITCH_CO6 is set</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTDAC_SW_CLEAR</name>
<description>CTDAC switch control clear</description>
<addressOffset>0xB4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x101</resetMask>
<fields>
<field>
<name>CTDD_CVD</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTDO_CO6</name>
<description>see corresponding bit in CTD_SW</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTDAC_VAL</name>
<description>DAC Value</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>VALUE</name>
<description>Value, in CTDAC_MODE 1 this value is decoded</description>
<bitRange>[11:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CTDAC_VAL_NXT</name>
<description>Next DAC value (double buffering)</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFF</resetMask>
<fields>
<field>
<name>VALUE</name>
<description>Next value fpr CTDAC_VAL.VALUE</description>
<bitRange>[11:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SAR</name>
<description>SAR ADC with Sequencer</description>
<baseAddress>0x411D0000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<description>Analog control register.</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10000000</resetValue>
<resetMask>0xFF3FEEF7</resetMask>
<fields>
<field>
<name>PWR_CTRL_VREF</name>
<description>VREF buffer low power mode.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>PWR_100</name>
<description>full power (100 percent) (default), bypass cap, max clk_sar is 18MHz.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PWR_80</name>
<description>80 percent power</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>PWR_60</name>
<description>60 percent power</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>PWR_50</name>
<description>50 percent power</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>PWR_40</name>
<description>40 percent power</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>PWR_30</name>
<description>30 percent power</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>PWR_20</name>
<description>20 percent power</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>PWR_10</name>
<description>10 percent power</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREF_SEL</name>
<description>SARADC internal VREF selection.</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>VREF0</name>
<description>VREF0 from PRB (VREF buffer on)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VREF1</name>
<description>VREF1 from PRB (VREF buffer on)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>VREF2</name>
<description>VREF2 from PRB (VREF buffer on)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>VREF_AROUTE</name>
<description>VREF from AROUTE (VREF buffer on)</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>VBGR</name>
<description>1.024V from BandGap (VREF buffer on)</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>VREF_EXT</name>
<description>External precision Vref direct from a pin (low impedance path).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>VDDA_DIV_2</name>
<description>Vdda/2 (VREF buffer on)</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>VDDA</name>
<description>Vdda.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREF_BYP_CAP_EN</name>
<description>VREF bypass cap enable for when VREF buffer is on</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NEG_SEL</name>
<description>SARADC internal NEG selection for Single ended conversion</description>
<bitRange>[11:9]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>VSSA_KELVIN</name>
<description>NEG input of SARADC is connected to 'vssa_kelvin', gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-before-make cycle on those switches when SWITCH_DISABLE is high.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ART_VSSA</name>
<description>NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>P1</name>
<description>NEG input of SARADC is connected to P1 pin of SARMUX</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>P3</name>
<description>NEG input of SARADC is connected to P3 pin of SARMUX</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>P5</name>
<description>NEG input of SARADC is connected to P5 pin of SARMUX</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>P7</name>
<description>NEG input of SARADC is connected to P7 pin of SARMUX</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>ACORE</name>
<description>NEG input of SARADC is connected to an ACORE in AROUTE</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>VREF</name>
<description>NEG input of SARADC is shorted with VREF input of SARADC.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SAR_HW_CTRL_NEGVREF</name>
<description>Hardware control: 0=only firmware control, 1=hardware control masked by firmware setting for VREF to NEG switch.</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>COMP_DLY</name>
<description>Set the comparator latch delay in accordance with SAR conversion rate</description>
<bitRange>[15:14]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>D2P5</name>
<description>2.5ns delay, use this for 2.5Msps</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>D4</name>
<description>4.0ns delay, use this for 2.0Msps</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>D10</name>
<description>10ns delay, use this for 1.5Msps</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>D12</name>
<description>12ns delay, use this for 1.0Msps or less</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPARE</name>
<description>Spare controls, not yet designated, for late changes done with an ECO</description>
<bitRange>[19:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>BOOSTPUMP_EN</name>
<description>deprecated</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>REFBUF_EN</name>
<description>For normal ADC operation this bit must be set, for all reference choices - internal, external or vdda based reference.
Setting this bit is critical to proper function of switches inside SARREF block.</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>COMP_PWR</name>
<description>Comparator power mode. (Sample rate TBD)</description>
<bitRange>[26:24]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>P100</name>
<description>Power = 100 percent, use this for &gt;2000Ksps</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>P80</name>
<description>Power = 80 percent, use this for 1500-2000Ksps</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>P60</name>
<description>Power = 60 percent, use this for 1000-1500Ksps</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>P50</name>
<description>Power = 50 percent, use this for 500-1000Ksps</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>P40</name>
<description>Power = 40 percent, use this for 250-500Ksps</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>P30</name>
<description>Power = 30 percent, use this for 100-250Ksps</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>P20</name>
<description>Power = 20 percent, use this for 100-250Ksps (TBD!)</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>P10</name>
<description>Power = 10 percent, use this for &lt;100Ksps</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEEPSLEEP_ON</name>
<description>- 0: SARMUX IP disabled off during DeepSleep power mode
- 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1)</description>
<bitRange>[27:27]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_SYNC_CONFIG</name>
<description>- 0: bypass clock domain synchronisation of the DSI config signals.
- 1: synchronize the DSI config signals to peripheral clock domain.</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_MODE</name>
<description>SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)
- 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations
- 1: CHAN_EN, INJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored</description>
<bitRange>[29:29]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SWITCH_DISABLE</name>
<description>Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control)
- 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations
- 1: Switches disabled, SAR sequencer does not enable any switches, it is the responsibility of the firmware or UDBs (through DSI) to set the switches to route the signal to be converted through the SARMUX</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>- 0: SAR IP disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER and INJ_START_EN (if not tailgaiting) on write.
- 1: SAR IP enabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SAMPLE_CTRL</name>
<description>Sample control register.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x80008</resetValue>
<resetMask>0xDFCF01FE</resetMask>
<fields>
<field>
<name>LEFT_ALIGN</name>
<description>Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SINGLE_ENDED_SIGNED</name>
<description>Output data from a single ended conversion as a signed value</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>UNSIGNED</name>
<description>Default: result data is unsigned (zero extended if needed)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SIGNED</name>
<description>result data is signed (sign extended if needed)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIFFERENTIAL_SIGNED</name>
<description>Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NEG_ADDR_EN is set to 1</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>UNSIGNED</name>
<description>result data is unsigned (zero extended if needed)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SIGNED</name>
<description>Default: result data is signed (sign extended if needed)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AVG_CNT</name>
<description>Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be sampled (1&lt;&lt;(AVG_CNT+1)) = [2..256] times.
- In ACCUNDUMP mode (1st order accumulate and dump filter) a channel will be sampled back to back, the average result is calculated and stored and then the next enabled channel is sampled. If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3).
- In INTERLEAVED mode one sample is taken per triggered scan, only in the scan where the final averaging count is reached a valid average is calculated and stored in the RESULT register (by definition the same scan for all the channels that have averaging enabled). In all other scans the RESULT register for averaged channels will have an invalid result and the intermediate accumulated value is stored in the 16-bit WORK register. In this mode make sure that the averaging count is low enough to ensure that the intermediate value does not exceed 16-bits otherwise the MSBs will be lost. So for a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=&lt;3).</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AVG_SHIFT</name>
<description>Averaging shifting: after averaging the result is shifted right to fit in 12 bits.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AVG_MODE</name>
<description>Averaging mode, in DSI mode this bit is ignored and only AccuNDump mode is available.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ACCUNDUMP</name>
<description>Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INTERLEAVED</name>
<description>Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CONTINUOUS</name>
<description>- 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels.
- 1: Continuously scan enabled channels, ignore triggers.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_TRIGGER_EN</name>
<description>- 0: firmware trigger only: disable hardware trigger tr_sar_in.
- 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB).</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_TRIGGER_LEVEL</name>
<description>- 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan.
- 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_SYNC_TRIGGER</name>
<description>- 0: bypass clock domain synchronisation of the trigger signal.
- 1: synchronize the trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain.</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>UAB_SCAN_MODE</name>
<description>Select whether UABs are scheduled or unscheduled. When no UAB is scanned this selection is ignored.</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>UNSCHEDULED</name>
<description>Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for each channel that scans a UAB the SAR will wait for a positive edge on the trigger output of that UAB. Caveat: in this mode the length of SAR scan can be variable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SCHEDULED</name>
<description>Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e. their output is assumed to be valid when sampled by the SAR and the SAR does not wait. In this mode the length of the SAR scan is constant.
This mode requires that the SAR scans strictly periodically, i.e. the SAR has to either run continuously or has to be triggered by a periodic hardware trigger (TCPWM or UDB timer). It also requires that the end of the UAB valid phase is precisely aligned with the end of the SAR sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REPEAT_INVALID</name>
<description>For unscheduled UAB_SCAN_MODE only, do the following if an invalid sample is received:
- 0: use the last known valid sample for that channel and clear the NEWVALUE flag
- 1: repeat the conversions until a valid sample is received (caveat: could be never if the UAB valid window is incorrectly schedule w.r.t. SAR sampling)</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VALID_SEL</name>
<description>Static UAB Valid select
0=UAB0 half 0 Valid output
1=UAB0 half 1 Valid output
2=UAB1 half 0 Valid output
3=UAB1 half 1 Valid output
4=UAB2 half 0 Valid output
5=UAB2 half 1 Valid output
6=UAB3 half 0 Valid output
7=UAB3 half 1 Valid output</description>
<bitRange>[26:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VALID_SEL_EN</name>
<description>Enable static UAB Valid selection (override Hardware)</description>
<bitRange>[27:27]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VALID_IGNORE</name>
<description>Ignore UAB valid signal, including the dynamic/Hardware from AROUTE and the static Valid selection from the VALID_SEL fields above</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TRIGGER_OUT_EN</name>
<description>SAR output trigger enable (used for UAB synchronization). To ensure multiple UABs starting at the same trigger it is recommended to use this bit to temporarily disable the trigger output until all those UABs are set to run (UAB.SRAM_CTRL.RUN=1).</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>EOS_DSI_OUT_EN</name>
<description>Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SAMPLE_TIME01</name>
<description>Sample time specification ST0 and ST1</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x30003</resetValue>
<resetMask>0x3FF03FF</resetMask>
<fields>
<field>
<name>SAMPLE_TIME0</name>
<description>Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2.</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SAMPLE_TIME1</name>
<description>Sample time1</description>
<bitRange>[25:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SAMPLE_TIME23</name>
<description>Sample time specification ST2 and ST3</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x30003</resetValue>
<resetMask>0x3FF03FF</resetMask>
<fields>
<field>
<name>SAMPLE_TIME2</name>
<description>Sample time2</description>
<bitRange>[9:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SAMPLE_TIME3</name>
<description>Sample time3</description>
<bitRange>[25:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RANGE_THRES</name>
<description>Global range detect threshold register.</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RANGE_LOW</name>
<description>Low threshold for range detect.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RANGE_HIGH</name>
<description>High threshold for range detect.</description>
<bitRange>[31:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RANGE_COND</name>
<description>Global range detect mode register.</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC0000000</resetMask>
<fields>
<field>
<name>RANGE_COND</name>
<description>Range condition select.</description>
<bitRange>[31:30]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>BELOW</name>
<description>result &lt; RANGE_LOW</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INSIDE</name>
<description>RANGE_LOW &lt;= result &lt; RANGE_HIGH</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ABOVE</name>
<description>RANGE_HIGH &lt;= result</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTSIDE</name>
<description>result &lt; RANGE_LOW || RANGE_HIGH &lt;= result</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHAN_EN</name>
<description>Enable bits for the channels</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CHAN_EN</name>
<description>Channel enable.
- 0: the corresponding channel is disabled.
- 1: the corresponding channel is enabled, it will be included in the next scan.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>START_CTRL</name>
<description>Start control register (firmware trigger).</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>FW_TRIGGER</name>
<description>When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>4</dimIncrement>
<name>CHAN_CONFIG[%s]</name>
<description>Channel configuration register.</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x81773577</resetMask>
<fields>
<field>
<name>POS_PIN_ADDR</name>
<description>Address of the pin to be sampled by this channel (connected to Vplus)</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>POS_PORT_ADDR</name>
<description>Address of the port that contains the pin to be sampled by this channel (connected to Vplus)</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SARMUX</name>
<description>SARMUX pins.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CTB0</name>
<description>CTB0</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CTB1</name>
<description>CTB1</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CTB2</name>
<description>CTB2</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CTB3</name>
<description>CTB3</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>AROUTE_VIRT2</name>
<description>AROUTE virtual port2 (VPORT2)</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>AROUTE_VIRT1</name>
<description>AROUTE virtual port1 (VPORT1)</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>SARMUX_VIRT</name>
<description>SARMUX virtual port (VPORT0)</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIFFERENTIAL_EN</name>
<description>Differential enable for this channel.
If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins.
- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register.
- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AVG_EN</name>
<description>Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SAMPLE_TIME_SEL</name>
<description>Sample time select: select which of the 4 global sample times to use for this channel</description>
<bitRange>[13:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NEG_PIN_ADDR</name>
<description>Address of the neg pin to be sampled by this channel.</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>NEG_PORT_ADDR</name>
<description>Address of the neg port that contains the pin to be sampled by this channel.</description>
<bitRange>[22:20]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SARMUX</name>
<description>SARMUX pins.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AROUTE_VIRT2</name>
<description>AROUTE virtual port2 (VPORT2)</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>AROUTE_VIRT1</name>
<description>AROUTE virtual port1 (VPORT1)</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>SARMUX_VIRT</name>
<description>SARMUX virtual port (VPORT0)</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NEG_ADDR_EN</name>
<description>1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_OUT_EN</name>
<description>DSI data output enable for this channel.
- 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set.
- 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>4</dimIncrement>
<name>CHAN_WORK[%s]</name>
<description>Channel working data register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x88000000</resetMask>
<fields>
<field>
<name>WORK</name>
<description>SAR conversion working data of the channel. The data is written here right after sampling this channel.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CHAN_WORK_NEWVALUE_MIR</name>
<description>mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register</description>
<bitRange>[27:27]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CHAN_WORK_UPDATED_MIR</name>
<description>mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>4</dimIncrement>
<name>CHAN_RESULT[%s]</name>
<description>Channel result data register</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xE8000000</resetMask>
<fields>
<field>
<name>RESULT</name>
<description>SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CHAN_RESULT_NEWVALUE_MIR</name>
<description>mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register</description>
<bitRange>[27:27]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SATURATE_INTR_MIR</name>
<description>mirror bit of corresponding bit in SAR_SATURATE_INTR register</description>
<bitRange>[29:29]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RANGE_INTR_MIR</name>
<description>mirror bit of corresponding bit in SAR_RANGE_INTR register</description>
<bitRange>[30:30]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CHAN_RESULT_UPDATED_MIR</name>
<description>mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CHAN_WORK_UPDATED</name>
<description>Channel working data register 'updated' bits</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CHAN_WORK_UPDATED</name>
<description>If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CHAN_RESULT_UPDATED</name>
<description>Channel result data register 'updated' bits</description>
<addressOffset>0x204</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CHAN_RESULT_UPDATED</name>
<description>If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CHAN_WORK_NEWVALUE</name>
<description>Channel working data register 'new value' bits</description>
<addressOffset>0x208</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CHAN_WORK_NEWVALUE</name>
<description>If set the corresponding WORK data received a new value, i.e. was already sampled during the current scan and data was valid.
In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid.
In case of averaging this New Value bit is an OR of all the valid bits received by each conversion.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CHAN_RESULT_NEWVALUE</name>
<description>Channel result data register 'new value' bits</description>
<addressOffset>0x20C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>CHAN_RESULT_NEWVALUE</name>
<description>If set the corresponding RESULT data received a new value, i.e. was sampled during the last scan and data was valid.
In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid.
In case of averaging this New Value bit is an OR of all the valid bits received by each conversion.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Interrupt request register.</description>
<addressOffset>0x210</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EOS_INTR</name>
<description>End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERFLOW_INTR</name>
<description>Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware. Write with '1' to clear bit.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FW_COLLISION_INTR</name>
<description>Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIGGER has been completed, i.e. not when the preceeding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_COLLISION_INTR</name>
<description>DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the DSI trigger has been completed, i.e. not when the preceeding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_EOC_INTR</name>
<description>Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used). Write with '1' to clear bit.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_SATURATE_INTR</name>
<description>Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_RANGE_INTR</name>
<description>Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_COLLISION_INTR</name>
<description>Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 &amp;&amp; INJ_TAILGATING==0) while the SAR is BUSY. Raising this interrupt is delayed to when the sampling of the injection channel has been completed, i.e. not when the preceeding scan with which this trigger collided is completed. When this interrupt is set it implies that the injection channel was sampled later than was intended. Write with '1' to clear bit.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt set request register</description>
<addressOffset>0x214</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EOS_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERFLOW_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FW_COLLISION_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_COLLISION_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_EOC_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_SATURATE_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_RANGE_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_COLLISION_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt mask register.</description>
<addressOffset>0x218</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EOS_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>OVERFLOW_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FW_COLLISION_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>DSI_COLLISION_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_EOC_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_SATURATE_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_RANGE_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_COLLISION_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt masked request register</description>
<addressOffset>0x21C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>EOS_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>OVERFLOW_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>FW_COLLISION_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DSI_COLLISION_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_EOC_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_SATURATE_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_RANGE_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_COLLISION_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SATURATE_INTR</name>
<description>Saturate interrupt request register.</description>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SATURATE_INTR</name>
<description>Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SATURATE_INTR_SET</name>
<description>Saturate interrupt set request register</description>
<addressOffset>0x224</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SATURATE_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SATURATE_INTR_MASK</name>
<description>Saturate interrupt mask register.</description>
<addressOffset>0x228</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SATURATE_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SATURATE_INTR_MASKED</name>
<description>Saturate interrupt masked request register</description>
<addressOffset>0x22C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>SATURATE_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RANGE_INTR</name>
<description>Range detect interrupt request register.</description>
<addressOffset>0x230</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RANGE_INTR</name>
<description>Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RANGE_INTR_SET</name>
<description>Range detect interrupt set request register</description>
<addressOffset>0x234</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RANGE_SET</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RANGE_INTR_MASK</name>
<description>Range detect interrupt mask register.</description>
<addressOffset>0x238</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RANGE_MASK</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RANGE_INTR_MASKED</name>
<description>Range interrupt masked request register</description>
<addressOffset>0x23C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF</resetMask>
<fields>
<field>
<name>RANGE_MASKED</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR_CAUSE</name>
<description>Interrupt cause register</description>
<addressOffset>0x240</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xC00000FF</resetMask>
<fields>
<field>
<name>EOS_MASKED_MIR</name>
<description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>OVERFLOW_MASKED_MIR</name>
<description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>FW_COLLISION_MASKED_MIR</name>
<description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>DSI_COLLISION_MASKED_MIR</name>
<description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_EOC_MASKED_MIR</name>
<description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_SATURATE_MASKED_MIR</name>
<description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_RANGE_MASKED_MIR</name>
<description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_COLLISION_MASKED_MIR</name>
<description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SATURATE_MASKED_RED</name>
<description>Reduction OR of all SAR_SATURATION_INTR_MASKED bits</description>
<bitRange>[30:30]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RANGE_MASKED_RED</name>
<description>Reduction OR of all SAR_RANGE_INTR_MASKED bits</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INJ_CHAN_CONFIG</name>
<description>Injection channel configuration register.</description>
<addressOffset>0x280</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC0003577</resetMask>
<fields>
<field>
<name>INJ_PIN_ADDR</name>
<description>Address of the pin to be sampled by this injection channel. If differential is enabled then INJ_PIN_ADDR[0] is ignored and considered to be 0, i.e. INJ_PIN_ADDR points to the even pin of a pin pair.</description>
<bitRange>[2:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_PORT_ADDR</name>
<description>Address of the port that contains the pin to be sampled by this channel.</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SARMUX</name>
<description>SARMUX pins.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CTB0</name>
<description>CTB0</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CTB1</name>
<description>CTB1</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CTB2</name>
<description>CTB2</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CTB3</name>
<description>CTB3</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>AROUTE_VIRT</name>
<description>AROUTE virtual port</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>SARMUX_VIRT</name>
<description>SARMUX virtual port</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INJ_DIFFERENTIAL_EN</name>
<description>Differential enable for this channel.
- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register.
- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (INJ_PIN_ADDR[0] is ignored).</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_AVG_EN</name>
<description>Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_SAMPLE_TIME_SEL</name>
<description>Injection sample time select: select which of the 4 global sample times to use for this channel</description>
<bitRange>[13:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_TAILGATING</name>
<description>Injection channel tailgating.
- 0: no tailgating for this channel, SAR is immediately triggered when the INJ_START_EN bit is set.
- 1: injection channel tailgating. The addressed pin is sampled after the next trigger and after all enabled channels have been scanned.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>INJ_START_EN</name>
<description>Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit also functions as trigger for this channel. Cleared by hardware after this channel has been sampled (i.e. this channel is always one shot even if CONTINUOUS is set). Also cleared if the SAR is disabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INJ_RESULT</name>
<description>Injection channel result register</description>
<addressOffset>0x290</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xF8000000</resetMask>
<fields>
<field>
<name>INJ_RESULT</name>
<description>SAR conversion result of the channel.</description>
<bitRange>[15:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_NEWVALUE</name>
<description>The data in this register received a new value (only relevant for UAB, this bit shows the value of the UAB valid bit)</description>
<bitRange>[27:27]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_COLLISION_INTR_MIR</name>
<description>mirror bit of corresponding bit in SAR_INTR register</description>
<bitRange>[28:28]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_SATURATE_INTR_MIR</name>
<description>mirror bit of corresponding bit in SAR_INTR register</description>
<bitRange>[29:29]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_RANGE_INTR_MIR</name>
<description>mirror bit of corresponding bit in SAR_INTR register</description>
<bitRange>[30:30]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INJ_EOC_INTR_MIR</name>
<description>mirror bit of corresponding bit in SAR_INTR register</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Current status of internal SAR registers (mostly for debug)</description>
<addressOffset>0x2A0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xC000001F</resetMask>
<fields>
<field>
<name>CUR_CHAN</name>
<description>current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY.</description>
<bitRange>[4:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>SW_VREF_NEG</name>
<description>the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL).</description>
<bitRange>[30:30]</bitRange>
<access>read-only</access>
</field>
<field>
<name>BUSY</name>
<description>If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down.</description>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>AVG_STAT</name>
<description>Current averaging status (for debug)</description>
<addressOffset>0x2A4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF8FFFFF</resetMask>
<fields>
<field>
<name>CUR_AVG_ACCU</name>
<description>the current value of the averaging accumulator</description>
<bitRange>[19:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>INTRLV_BUSY</name>
<description>If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging.
This bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR.</description>
<bitRange>[23:23]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CUR_AVG_CNT</name>
<description>the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update.</description>
<bitRange>[31:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MUX_SWITCH0</name>
<description>SARMUX Firmware switch controls</description>
<addressOffset>0x300</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FFFFFFF</resetMask>
<fields>
<field>
<name>MUX_FW_P0_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with '1' to set bit.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P1_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with '1' to set bit.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P2_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with '1' to set bit.</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P3_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with '1' to set bit.</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P4_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with '1' to set bit.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P5_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with '1' to set bit.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P6_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with '1' to set bit.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P7_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with '1' to set bit.</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P0_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with '1' to set bit.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P1_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with '1' to set bit.</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P2_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with '1' to set bit.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P3_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with '1' to set bit.</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P4_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with '1' to set bit.</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P5_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with '1' to set bit.</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P6_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with '1' to set bit.</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P7_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with '1' to set bit.</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_VSSA_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write with '1' to set bit.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_TEMP_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, also powers on the temperature sensor. Write with '1' to set bit.</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_AMUXBUSA_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write with '1' to set bit.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_AMUXBUSB_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write with '1' to set bit.</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_AMUXBUSA_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write with '1' to set bit.</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_AMUXBUSB_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write with '1' to set bit.</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_SARBUS0_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with '1' to set bit.</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_SARBUS1_VPLUS</name>
<description>Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with '1' to set bit.</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_SARBUS0_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write with '1' to set bit.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_SARBUS1_VMINUS</name>
<description>Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write with '1' to set bit.</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P4_COREIO0</name>
<description>Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with '1' to set bit.</description>
<bitRange>[26:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P5_COREIO1</name>
<description>Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with '1' to set bit.</description>
<bitRange>[27:27]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P6_COREIO2</name>
<description>Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with '1' to set bit.</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P7_COREIO3</name>
<description>Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with '1' to set bit.</description>
<bitRange>[29:29]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MUX_SWITCH_CLEAR0</name>
<description>SARMUX Firmware switch control clear</description>
<addressOffset>0x304</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FFFFFFF</resetMask>
<fields>
<field>
<name>MUX_FW_P0_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P1_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P2_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P3_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P4_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P5_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P6_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P7_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P0_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P1_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[9:9]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P2_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P3_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[11:11]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P4_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P5_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P6_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[14:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P7_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[15:15]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_VSSA_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_TEMP_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_AMUXBUSA_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_AMUXBUSB_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_AMUXBUSA_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_AMUXBUSB_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_SARBUS0_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_SARBUS1_VPLUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_SARBUS0_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_SARBUS1_VMINUS</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P4_COREIO0</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[26:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P5_COREIO1</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[27:27]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P6_COREIO2</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_FW_P7_COREIO3</name>
<description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
<bitRange>[29:29]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MUX_SWITCH_DS_CTRL</name>
<description>SARMUX switch DSI control</description>
<addressOffset>0x340</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xCF00FF</resetMask>
<fields>
<field>
<name>MUX_DS_CTRL_P0</name>
<description>for P0 switches</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_P1</name>
<description>for P1 switches</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_P2</name>
<description>for P2 switches</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_P3</name>
<description>for P3 switches</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_P4</name>
<description>for P4 switches</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_P5</name>
<description>for P5 switches</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_P6</name>
<description>for P6 switches</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_P7</name>
<description>for P7 switches</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_VSSA</name>
<description>for vssa switch</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_TEMP</name>
<description>for temp switch</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_AMUXBUSA</name>
<description>for amuxbusa switch</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_AMUXBUSB</name>
<description>for amuxbusb switches</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_SARBUS0</name>
<description>for sarbus0 switch</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_DS_CTRL_SARBUS1</name>
<description>for sarbus1 switch</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MUX_SWITCH_SQ_CTRL</name>
<description>SARMUX switch Sar Sequencer control</description>
<addressOffset>0x344</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xCF00FF</resetMask>
<fields>
<field>
<name>MUX_SQ_CTRL_P0</name>
<description>for P0 switches</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_P1</name>
<description>for P1 switches</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_P2</name>
<description>for P2 switches</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_P3</name>
<description>for P3 switches</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_P4</name>
<description>for P4 switches</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_P5</name>
<description>for P5 switches</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_P6</name>
<description>for P6 switches</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_P7</name>
<description>for P7 switches</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_VSSA</name>
<description>for vssa switch</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_TEMP</name>
<description>for temp switch</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_AMUXBUSA</name>
<description>for amuxbusa switch</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_AMUXBUSB</name>
<description>for amuxbusb switches</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_SARBUS0</name>
<description>for sarbus0 switch</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>MUX_SQ_CTRL_SARBUS1</name>
<description>for sarbus1 switch</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MUX_SWITCH_STATUS</name>
<description>SARMUX switch status</description>
<addressOffset>0x348</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x3FFFFFF</resetMask>
<fields>
<field>
<name>MUX_FW_P0_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P1_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P2_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P3_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P4_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P5_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P6_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P7_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P0_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P1_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[9:9]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P2_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[10:10]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P3_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[11:11]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P4_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[12:12]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P5_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[13:13]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P6_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[14:14]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_P7_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[15:15]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_VSSA_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_TEMP_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[17:17]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_AMUXBUSA_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[18:18]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_AMUXBUSB_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[19:19]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_AMUXBUSA_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[20:20]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_AMUXBUSB_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[21:21]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_SARBUS0_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[22:22]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_SARBUS1_VPLUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[23:23]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_SARBUS0_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[24:24]</bitRange>
<access>read-only</access>
</field>
<field>
<name>MUX_FW_SARBUS1_VMINUS</name>
<description>switch status of corresponding bit in MUX_SWITCH0</description>
<bitRange>[25:25]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ANA_TRIM0</name>
<description>Analog trim register.</description>
<addressOffset>0xF00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>CAP_TRIM</name>
<description>Attenuation cap trimming</description>
<bitRange>[4:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TRIMUNIT</name>
<description>Attenuation cap trimming</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ANA_TRIM1</name>
<description>Analog trim register.</description>
<addressOffset>0xF04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>SAR_REF_BUF_TRIM</name>
<description>SAR Reference buffer trim</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PASS</name>
<description>PASS top-level MMIO (DSABv2, INTR)</description>
<baseAddress>0x411F0000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>65536</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>INTR_CAUSE</name>
<description>Interrupt cause register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>CTB0_INT</name>
<description>CTB0 interrupt pending</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CTB1_INT</name>
<description>CTB1 interrupt pending</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CTB2_INT</name>
<description>CTB2 interrupt pending</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CTB3_INT</name>
<description>CTB3 interrupt pending</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CTDAC0_INT</name>
<description>CTDAC0 interrupt pending</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CTDAC1_INT</name>
<description>CTDAC1 interrupt pending</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CTDAC2_INT</name>
<description>CTDAC2 interrupt pending</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>CTDAC3_INT</name>
<description>CTDAC3 interrupt pending</description>
<bitRange>[7:7]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<cluster>
<name>AREF</name>
<description>AREF configuration</description>
<addressOffset>0x00000E00</addressOffset>
<register>
<name>AREF_CTRL</name>
<description>global AREF control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF039FFFD</resetMask>
<fields>
<field>
<name>AREF_MODE</name>
<description>Control bit to trade off AREF settling and noise performance</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NORMAL</name>
<description>Nominal noise normal startup mode (meets normal mode settling and noise specifications)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST_START</name>
<description>High noise fast startup mode (meets fast mode settling and noise specifications)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AREF_BIAS_SCALE</name>
<description>BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized)
0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times)
1: 250nA ('default' setting to meet bandgap performance (noise/startup) and IDDA specifications)
2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times)
3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times)</description>
<bitRange>[3:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>AREF_RMB</name>
<description>AREF control signals (RMB).
Bit 0: Manual VBG startup circuit enable
0: normal VBG startup circuit operation
1: VBG startup circuit is forced 'always on'
Bit 1: Manual disable of IPTAT2 DAC
0: normal IPTAT2 DAC operation
1: PTAT2 DAC is disabled while VBG startup is active
Bit 2: Manual enable of VBG offset correction DAC
0: normal VBG offset correction DAC operation
1: VBG offset correction DAC is enabled while VBG startup is active</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTB_IPTAT_SCALE</name>
<description>CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers).
0: 1uA
1: 100nA</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CTB_IPTAT_REDIRECT</name>
<description>Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility).
0: Opamp&lt;n&gt;.IPTAT = AREF.IPTAT and Opamp&lt;n&gt;.IZTAT= AREF.IZTAT
1: Opamp&lt;n&gt;.IPTAT = HiZ and Opamp&lt;n&gt;.IZTAT= AREF.IPTAT
*Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp&lt;n&gt;.IZTAT/IPTAT will be HiZ.</description>
<bitRange>[15:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IZTAT_SEL</name>
<description>iztat current select control</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SRSS</name>
<description>Use 250nA IZTAT from SRSS</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCAL</name>
<description>Use locally generated 250nA</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLOCK_PUMP_PERI_SEL</name>
<description>CTBm charge pump clock source select. This field has nothing to do with the AREF.
0: Use the dedicated pump clock from SRSS (default)
1: Use one of the CLK_PERI dividers</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>VREF_SEL</name>
<description>bandgap voltage select control</description>
<bitRange>[21:20]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SRSS</name>
<description>Use 0.8V Vref from SRSS</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCAL</name>
<description>Use locally generated Vref</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTERNAL</name>
<description>Use externally supplied Vref (aref_ext_vref)</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEEPSLEEP_MODE</name>
<description>AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1)</description>
<bitRange>[29:28]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>All blocks 'OFF' in DeepSleep</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IPTAT</name>
<description>IPTAT bias generator 'ON' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>IPTAT_IZTAT</name>
<description>IPTAT bias generator and outputs 'ON' in DeepSleep (used for biasing the CTBm with a PTAT current only in deepsleep)
*Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>IPTAT_IZTAT_VREF</name>
<description>IPTAT, VREF, and IZTAT generators 'ON' in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEEPSLEEP_ON</name>
<description>- 0: AREF IP disabled/off during DeepSleep power mode
- 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1)</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Disable AREF</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</cluster>
<register>
<name>VREF_TRIM0</name>
<description>VREF Trim bits</description>
<addressOffset>0xF00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VREF_ABS_TRIM</name>
<description>N/A</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>VREF_TRIM1</name>
<description>VREF Trim bits</description>
<addressOffset>0xF04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VREF_TEMPCO_TRIM</name>
<description>N/A</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>VREF_TRIM2</name>
<description>VREF Trim bits</description>
<addressOffset>0xF08</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>VREF_CURV_TRIM</name>
<description>N/A</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>VREF_TRIM3</name>
<description>VREF Trim bits</description>
<addressOffset>0xF0C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>VREF_ATTEN_TRIM</name>
<description>Obsolete</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IZTAT_TRIM0</name>
<description>IZTAT Trim bits</description>
<addressOffset>0xF10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IZTAT_ABS_TRIM</name>
<description>N/A</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IZTAT_TRIM1</name>
<description>IZTAT Trim bits</description>
<addressOffset>0xF14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IZTAT_TC_TRIM</name>
<description>IZTAT temperature correction trim (RMB)
0x00 : No IZTAT temperature correction
0xFF : Maximum IZTAT temperature correction
As this is a Risk Mitigation Register, it should be loaded with 0x08.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IPTAT_TRIM0</name>
<description>IPTAT Trim bits</description>
<addressOffset>0xF18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFF</resetMask>
<fields>
<field>
<name>IPTAT_CORE_TRIM</name>
<description>IPTAT trim
0x0 : Minimum IPTAT current (~150nA at room)
0xF : Maximum IPTAT current (~350nA at room)</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>IPTAT_CTBM_TRIM</name>
<description>CTMB PTAT Current Trim
0x0 : Minimum CTMB IPTAT Current (~875nA)
0xF : Maximum CTMB IPTAT Current (~1.1uA)</description>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ICTAT_TRIM0</name>
<description>ICTAT Trim bits</description>
<addressOffset>0xF1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>ICTAT_TRIM</name>
<description>ICTAT trim
0x00 : Minimum ICTAT current (~150nA at room)
0x0F : Maximum ICTAT current (~350nA at room)</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2S0</name>
<description>I2S registers</description>
<headerStructName>I2S</headerStructName>
<baseAddress>0x42A10000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>4096</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTL</name>
<description>Control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xC0000000</resetMask>
<fields>
<field>
<name>TX_ENABLED</name>
<description>Enables the I2S TX component:
'0': Disabled.
'1': Enabled.</description>
<bitRange>[30:30]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_ENABLED</name>
<description>Enables the I2S RX component:
'0': Disabled.
'1': Enabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLOCK_CTL</name>
<description>Clock control</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x13F</resetMask>
<fields>
<field>
<name>CLOCK_DIV</name>
<description>Frequency divisor for generating I2S clock frequency.
The selected clock with CLOCK_SEL is divided by this.
'0': Bypass
'1': 2 x
'2': 3 x
'3': 4 x
...
'62': 63 x
'63': 64 x</description>
<bitRange>[5:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLOCK_SEL</name>
<description>Selects clock to be used by I2S:
'0': Internal clock ('clk_audio_i2s')
'1': External clock ('clk_i2s_if')</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMD</name>
<description>Command</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x10101</resetMask>
<fields>
<field>
<name>TX_START</name>
<description>Transmitter enable:
'0': Disabled.
'1': Enabled.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_PAUSE</name>
<description>Pause enable:
'0': Disabled (TX FIFO data is sent over I2S).
'1': Enabled ('0' data is sent over I2S, instead of TX FIFO data).</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_START</name>
<description>Receiver enable:
'0': Disabled.
'1': Enabled.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TR_CTL</name>
<description>Trigger control</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x10001</resetMask>
<fields>
<field>
<name>TX_REQ_EN</name>
<description>Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission
'0': Disabled.
'1': Enabled.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_REQ_EN</name>
<description>Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception
'0': Disabled.
'1': Enabled.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TX_CTL</name>
<description>Transmitter control</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x440510</resetValue>
<resetMask>0x37737F8</resetMask>
<fields>
<field>
<name>B_CLOCK_INV</name>
<description>Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode.
When set to '1', the serial data will be transmitted 0.5 SCK cycles earlier than when set to '0'.
1) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK falling edge
2) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK rising edge that is 0.5 SCK cycles before the SCK falling edge in 1)
3) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK rising edge
4) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK falling edge that is 0.5 SCK cycles before the SCK rising edge in 3)
(Note that this is only the appearance w.r.t. SCK edge, the actual timing is generated by an internal clock that runs 8x the SCK frequency). The word sync (TX_WS) signal is not affected by this bit setting.
Note: When Master mode, must be '0'.
(Note: This bit is connected to AR38U12.TX_CFG.TX_BCLKINV)</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FALLING_EDGE_TX</name>
<description>SDO transmitted at SCK falling edge when TX_CTL.SCKI_POL=0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGE_TX</name>
<description>SDO transmitted at SCK rising edge when TX_CTL.SCKI_POL=0</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH_NR</name>
<description>Specifies number of channels per frame:
Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes.
(Note: These bits are connected to AR38U12.TX_CFG.TX_CHSET)</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CH_NUM1</name>
<description>1 channel</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM2</name>
<description>2 channels</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM3</name>
<description>3 channels</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM4</name>
<description>4 channels</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM5</name>
<description>5 channels</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM6</name>
<description>6 channels</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM7</name>
<description>7 channels</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM8</name>
<description>8 channels</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MS</name>
<description>Set interface in master or slave mode:
(Note: This bit is connected to AR38U12.TX_CFG.TX_MS)</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SLAVE</name>
<description>Slave</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MASTER</name>
<description>Master</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2S_MODE</name>
<description>Select I2S, left-justified or TDM:
(Note: These bits are connected to AR38U12.TX_CFG.TX_I2S_MODE)</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LEFT_JUSTIFIED</name>
<description>Left Justified</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>I2S</name>
<description>I2S mode</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TDM_A</name>
<description>TDM mode A, the 1st Channel align to WSO
Rising Edge</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TDM_B</name>
<description>TDM mode B, the 1st Channel align to WSO
Rising edge with1 SCK Delay</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WS_PULSE</name>
<description>Set WS pulse width in TDM mode:
(Note: This bit is connected to AR38U12.TX_CFG.TX_WS_PULSE)
Note: When not TDM mode, must be '1'.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SCK_PERIOD</name>
<description>Pulse width is 1 SCK period</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_LENGTH</name>
<description>Pulse width is 1 channel length</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVHDATA</name>
<description>Set overhead value:
'0': Set to '0'
'1': Set to '1'
(Note: This bit is connected to AR38U12.TX_CFG.TX_OVHDATA)</description>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>WD_EN</name>
<description>Set watchdog for 'tx_ws_in':
'0': Disabled.
'1': Enabled.</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CH_LEN</name>
<description>Channel length in number of bits:
Note:
- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5').
- When TDM mode, must be 32-bit length to this field.
(Note: These bits are connected to AR38U12.TX_CFG.TX_CHLEN)</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>BIT_LEN8</name>
<description>8-bit</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN16</name>
<description>16-bit</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN18</name>
<description>18-bit</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN20</name>
<description>20-bit</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN24</name>
<description>24-bit</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN32</name>
<description>32-bit</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WORD_LEN</name>
<description>Word length in number of bits:
Note:
- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5').
- Don't configure this field as beyond Channel length.
(Note: These bits are connected to AR38U12.TX_CFG.TX_IWL)</description>
<bitRange>[22:20]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>BIT_LEN8</name>
<description>8-bit</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN16</name>
<description>16-bit</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN18</name>
<description>18-bit</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN20</name>
<description>20-bit</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN24</name>
<description>24-bit</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN32</name>
<description>32-bit</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCKO_POL</name>
<description>TX master bit clock polarity.
When this bit is 1, the outgoing tx_sck signal is inverted after it has been transmitted from the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting.
'0': When transmitter is in master mode, serial data is transmitted from the falling bit clock edge
'1': When transmitter is in master mode, serial data is transmitted from the rising bit clock edge</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCKI_POL</name>
<description>TX slave bit clock polarity.
When this bit is 1, the incoming tx_sck signal is inverted before it is received by the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. See TX_CTL.B_CLOCK_INV for more details.</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TX_WATCHDOG</name>
<description>Transmitter watchdog</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WD_COUNTER</name>
<description>Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RX_CTL</name>
<description>Receiver control</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x440510</resetValue>
<resetMask>0x3F727F8</resetMask>
<fields>
<field>
<name>B_CLOCK_INV</name>
<description>Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode.
When set to '1', the serial data will be captured 0.5 SCK cycles later than when set to '0'.
1) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK rising edge
2) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK falling edge that is 0.5 SCK cycles after the SCK rising edge in 1)
3) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK falling edge
4) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK rising edge that is 0.5 SCK cycles after the SCK falling edge in 3)
(Note that this is only the appearance w.r.t. SCK edge, the actual capture timing is derived from an internal clock that runs 8x the SCK frequency). The word sync (RX_WS) signal is not affected by this bit setting.
Note: When Slave mode, must be '0'.
(Note: This bit is connected to AR38U12.TX_CFG.RX_BCLKINV)</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>RISING_EDGE_RX</name>
<description>SDI received at SCK rising edge when RX_CTL.SCKO_POL=0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGE_RX</name>
<description>SDI received at SCK falling edge when RX_CTL.SCKO_POL=0</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH_NR</name>
<description>Specifies number of channels per frame:
Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes.
(Note: These bits are connected to AR38U12.RX_CFG.RX_CHSET)</description>
<bitRange>[6:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>CH_NUM1</name>
<description>1 channel</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM2</name>
<description>2 channels</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM3</name>
<description>3 channels</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM4</name>
<description>4 channels</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM5</name>
<description>5 channels</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM6</name>
<description>6 channels</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM7</name>
<description>7 channels</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_NUM8</name>
<description>8 channels</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MS</name>
<description>Set interface in master or slave mode:
(Note: This bit is connected to AR38U12.TX_CFG.RX_MS)</description>
<bitRange>[7:7]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SLAVE</name>
<description>Slave</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MASTER</name>
<description>Master</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2S_MODE</name>
<description>Select I2S, left-justified or TDM:
(Note: These bits are connected to AR38U12.RX_CFG.RX_I2S_MODE)</description>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LEFT_JUSTIFIED</name>
<description>Left Justified</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>I2S</name>
<description>I2S mode</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TDM_A</name>
<description>TDM mode A, the 1st Channel align to WSO
Rising Edge</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TDM_B</name>
<description>TDM mode B, the 1st Channel align to WSO
Rising edge with1 SCK Delay</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WS_PULSE</name>
<description>Set WS pulse width in TDM mode:
(Note: This bit is connected to AR38U12.RX_CFG.RX_WS_PULSE)
Note: When not TDM mode, must be '1'.</description>
<bitRange>[10:10]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>SCK_PERIOD</name>
<description>Pulse width is 1 SCK period</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_LENGTH</name>
<description>Pulse width is 1 channel length</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WD_EN</name>
<description>Set watchdog for 'rx_ws_in'
'0': Disabled.
'1': Enabled.</description>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CH_LEN</name>
<description>Channel length in number of bits:
Note:
- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5').
- When TDM mode, must be 32-bit length to this field.
(Note: These bits are connected to AR38U12.RX_CFG.RX_CHLEN)</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>BIT_LEN8</name>
<description>8-bit</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN16</name>
<description>16-bit</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN18</name>
<description>18-bit</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN20</name>
<description>20-bit</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN24</name>
<description>24-bit</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN32</name>
<description>32-bit</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WORD_LEN</name>
<description>Word length in number of bits:
Note:
- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5').
- Don't configure this field as beyond Channel length.
(Note: These bits are connected to AR38U12.RX_CFG.RX_IWL)</description>
<bitRange>[22:20]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>BIT_LEN8</name>
<description>8-bit</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN16</name>
<description>16-bit</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN18</name>
<description>18-bit</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN20</name>
<description>20-bit</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN24</name>
<description>24-bit</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN32</name>
<description>32-bit</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BIT_EXTENSION</name>
<description>When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set.
'0': Extended by '0'
'1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0')</description>
<bitRange>[23:23]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCKO_POL</name>
<description>RX master bit clock polarity.
When this bit is 1, the outgoing rx_sck signal is inverted after it has been transmitted from the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting.See RX_CTL.B_CLOCK_INV for more details.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SCKI_POL</name>
<description>RX slave bit clock polarity.
When this bit is 1, the incoming rx_sck signal is inverted before it is received by the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting.
'0': When receiver is in slave mode, serial data is sampled on the rising bit clock edge
'1': When receiver is in slave mode, serial data is sampled on the falling bit clock edge</description>
<bitRange>[25:25]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RX_WATCHDOG</name>
<description>Receiver watchdog</description>
<addressOffset>0xA4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WD_COUNTER</name>
<description>Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TX_FIFO_CTL</name>
<description>TX FIFO control</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x300FF</resetMask>
<fields>
<field>
<name>TRIGGER_LEVEL</name>
<description>Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated.</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLEAR</name>
<description>When '1', the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FREEZE</name>
<description>When '1', hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes.</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TX_FIFO_STATUS</name>
<description>TX FIFO status</description>
<addressOffset>0x204</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF01FF</resetMask>
<fields>
<field>
<name>USED</name>
<description>Number of entries in the TX FIFO. The field value is in the range [0, 256].</description>
<bitRange>[8:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RD_PTR</name>
<description>TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes.</description>
<bitRange>[23:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WR_PTR</name>
<description>TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes.</description>
<bitRange>[31:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TX_FIFO_WR</name>
<description>TX FIFO write</description>
<addressOffset>0x208</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data written into the TX FIFO. Behavior is similar to that of a PUSH operation.
Note: Don't access to this register while TX_FIFO_CTL.CLEAR is '1'.</description>
<bitRange>[31:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_CTL</name>
<description>RX FIFO control</description>
<addressOffset>0x300</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x300FF</resetMask>
<fields>
<field>
<name>TRIGGER_LEVEL</name>
<description>Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated.
Note: software can configure up to 253 in I2S mode or Left Justified (RX_CTL.I2S_MODE = '0' or '1'). In TDM mode (RX_CTL.I2S_MODE = '2' or '3'), it can configure up to [256 - (RX_CTL.CH_NR+2)].</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLEAR</name>
<description>When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FREEZE</name>
<description>When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee.</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_STATUS</name>
<description>RX FIFO status</description>
<addressOffset>0x304</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF01FF</resetMask>
<fields>
<field>
<name>USED</name>
<description>Number of entries in the RX FIFO. The field value is in the range [0, 256].</description>
<bitRange>[8:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RD_PTR</name>
<description>RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes.</description>
<bitRange>[23:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WR_PTR</name>
<description>RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes.</description>
<bitRange>[31:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_RD</name>
<description>RX FIFO read</description>
<addressOffset>0x308</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation.
Notes:
- Don't access to this register while RX_FIFO_CTL.CLEAR is '1'.
- Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_RD_SILENT</name>
<description>RX FIFO silent read</description>
<addressOffset>0x30C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes.
Notes:
- Don't access to this register while RX_FIFO_CTL.CLEAR is '1'.
- Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Interrupt register</description>
<addressOffset>0xF00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x16D0173</resetMask>
<fields>
<field>
<name>TX_TRIGGER</name>
<description>Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_NOT_FULL</name>
<description>TX FIFO is not full.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>TX FIFO is empty; i.e. it has 0 entries.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_OVERFLOW</name>
<description>Attempt to write to a full TX FIFO.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_UNDERFLOW</name>
<description>Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_WD</name>
<description>Triggers (sets to '1') when the Tx watchdog event occurs.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_TRIGGER</name>
<description>More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_NOT_EMPTY</name>
<description>RX FIFO is not empty.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FULL</name>
<description>RX FIFO is full.</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_OVERFLOW</name>
<description>Attempt to write to a full RX FIFO.</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_UNDERFLOW</name>
<description>Attempt to read from an empty RX FIFO.</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_WD</name>
<description>Triggers (sets to '1') when the Rx watchdog event occurs.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt set register</description>
<addressOffset>0xF04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x16D0173</resetMask>
<fields>
<field>
<name>TX_TRIGGER</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_NOT_FULL</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_OVERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_UNDERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_WD</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_TRIGGER</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_NOT_EMPTY</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FULL</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_OVERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_UNDERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_WD</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt mask register</description>
<addressOffset>0xF08</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x16D0173</resetMask>
<fields>
<field>
<name>TX_TRIGGER</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_NOT_FULL</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_OVERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_UNDERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>TX_WD</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_TRIGGER</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_NOT_EMPTY</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_FULL</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_OVERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_UNDERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_WD</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt masked register</description>
<addressOffset>0xF0C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x16D0173</resetMask>
<fields>
<field>
<name>TX_TRIGGER</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_NOT_FULL</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_OVERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_UNDERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_WD</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[8:8]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_TRIGGER</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_NOT_EMPTY</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[18:18]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_FULL</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[19:19]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_OVERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[21:21]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_UNDERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[22:22]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_WD</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[24:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PDM0</name>
<description>PDM registers</description>
<headerStructName>PDM</headerStructName>
<baseAddress>0x42A20000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>4096</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTL</name>
<description>Control</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x20808</resetValue>
<resetMask>0x80030F0F</resetMask>
<fields>
<field>
<name>PGA_R</name>
<description>Right channel PGA gain:
+1.5dB/step, -12dB ~ +10.5dB
'0': -12 dB
'1': -10.5 dB
...
'15' +10.5 dB
(Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_R)</description>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>PGA_L</name>
<description>Left channel PGA gain:
+1.5dB/step, -12dB ~ +10.5dB
'0': -12 dB
'1': -10.5 dB
...
'15': +10.5 dB
(Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_L)</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SOFT_MUTE</name>
<description>Soft mute function to mute the volume smoothly
'0': Disabled.
'1': Enabled.
(Note: This bit is connected to AR36U12.PDM_CORE_CFG.SOFT_MUTE)</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>STEP_SEL</name>
<description>Set fine gain step for smooth PGA or Soft-Mute attenuation transition.
'0': 0.13dB
'1': 0.26dB
(Note: This bit is connected to AR36U12.PDM_CORE2_CFG.SEL_STEP)</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ENABLED</name>
<description>Enables the PDM component:
'0': Disabled.
'1': Enabled.</description>
<bitRange>[31:31]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLOCK_CTL</name>
<description>Clock control</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x200310</resetValue>
<resetMask>0x7F0F33</resetMask>
<fields>
<field>
<name>CLK_CLOCK_DIV</name>
<description>PDM CLK (FPDM_CLK) (1st divider):
This configures a frequency of PDM CLK. The configured frequency is used to operate PDM core. I.e. the frequency is input to MCLKQ_CLOCK_DIV register.
Note: configure a frequency of PDM CLK as lower than or equal 50MHz with this divider.</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DIVBY1</name>
<description>Divide by 1</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY2</name>
<description>Divide by 2 (no 50 percent duty cycle)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY3</name>
<description>Divide by 3 (no 50 percent duty cycle)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY4</name>
<description>Divide by 4 (no 50 percent duty cycle)</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCLKQ_CLOCK_DIV</name>
<description>MCLKQ divider (2nd divider)
(Note: These bits are connected to
AR36U12.PDM_CORE2_CFG.DIV_MCLKQ)</description>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DIVBY1</name>
<description>Divide by 1</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY2</name>
<description>Divide by 2 (no 50 percent duty cycle)</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY3</name>
<description>Divide by 3 (no 50 percent duty cycle)</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DIVBY4</name>
<description>Divide by 4 (no 50 percent duty cycle)</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKO_CLOCK_DIV</name>
<description>PDM CKO (FPDM_CKO) clock divider (3rd divider):
FPDM_CKO = MCLKQ / (CKO_CLOCK_DIV + 1)
Note: To configure '0' to this field is prohibited.
(Note: PDM_CKO is configured by MCLKQ_CLOCK_DIV, CLK_CLOCK_DIV and CKO_CLOCK_DIV. )
(Note: These bits are connected to
AR36U12.PDM_CORE_CFG.MCLKDIV)</description>
<bitRange>[11:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>SINC_RATE</name>
<description>SINC Decimation Rate. For details, see the data sheet provided by Archband.
Oversampling Ratio = Decimation Rate = 2 X SINC_RATE
(Note: These bits are connected to AR36U12.PDM_CORE_CFG.SINC_RATE)</description>
<bitRange>[22:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MODE_CTL</name>
<description>Mode control</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1B000103</resetValue>
<resetMask>0x1F070707</resetMask>
<fields>
<field>
<name>PCM_CH_SET</name>
<description>Specifies PCM output channels as mono or stereo:
(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_CHSET)</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Channel disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MONO_L</name>
<description>Mono left channel enable</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MONO_R</name>
<description>Mono right channel enable</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STEREO</name>
<description>Stereo channel enable</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWAP_LR</name>
<description>Input data L/R channel swap:
'1': Right/Left channel recording swap
'0': No Swap
(Note: This bit is connected to AR36U12.PDM_CORE_CFG.LRSWAP)</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>S_CYCLES</name>
<description>Set time step for gain change during PGA or soft mute operation in
number of 1/a sampling rate.
(Note: These bits are connected to AR36U12.PDM_CORE_CFG.S_CYCLES)</description>
<bitRange>[10:8]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>STEP_NUM64</name>
<description>64steps</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>STEP_NUM96</name>
<description>96steps</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STEP_NUM128</name>
<description>128steps</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STEP_NUM160</name>
<description>160steps</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>STEP_NUM192</name>
<description>192steps</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>STEP_NUM256</name>
<description>256steps</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>STEP_NUM384</name>
<description>384steps</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>STEP_NUM512</name>
<description>512steps</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CKO_DELAY</name>
<description>Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of PDM_CKO clock:
(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PDMCKO_DLY)</description>
<bitRange>[18:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ADV3</name>
<description>CLK_IS is 3*PDM_CLK period early</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADV2</name>
<description>CLK_IS is 2*PDM_CLK period early</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADV1</name>
<description>CLK_IS is 1*PDM_CLK period early</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_DELAY</name>
<description>CLK_IS is the same as PDM_CKO</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DLY1</name>
<description>CLK_IS is 1*PDM_CLK period late</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DLY2</name>
<description>CLK_IS is 2*PDM_CLK period late</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DLY3</name>
<description>CLK_IS is 3*PDM_CLK period late</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DLY4</name>
<description>CLK_IS is 4*PDM_CLK period late</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HPF_GAIN</name>
<description>Adjust high pass filter coefficients.
H(Z) = (1 - Z-1 ) / [1 - (1- 2 -HPF_GAIN) Z-1 ]
(Note: These bits are connected to AR36U12.PDM_CORE_CFG.HPGAIN)</description>
<bitRange>[27:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>HPF_EN_N</name>
<description>Enable high pass filter (active low)
'1': Disabled.
'0': Enabled.
(Note: This bit is connected to AR36U12.PDM_CORE_CFG.ADCHPD)</description>
<bitRange>[28:28]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATA_CTL</name>
<description>Data control</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x103</resetMask>
<fields>
<field>
<name>WORD_LEN</name>
<description>PCM Word Length in number of bits:
(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_IWL)</description>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>BIT_LEN16</name>
<description>16-bit</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN18</name>
<description>18-bit</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN20</name>
<description>20-bit</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BIT_LEN24</name>
<description>24-bit</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BIT_EXTENSION</name>
<description>When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set.
'0': Extended by '0'
'1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0')</description>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMD</name>
<description>Command</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x1</resetMask>
<fields>
<field>
<name>STREAM_EN</name>
<description>Enable data streaming flow:
'0': Disabled.
'1': Enabled.
(Note: This bit is connected to AR36U12.PDM_CORE_CFG.PDMA_EN)</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TR_CTL</name>
<description>Trigger control</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x10000</resetMask>
<fields>
<field>
<name>RX_REQ_EN</name>
<description>Trigger output ('tr_pdm_rx_req') enable for requests of DMA transfer
'0': Disabled.
'1': Enabled.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_CTL</name>
<description>RX FIFO control</description>
<addressOffset>0x300</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x300FF</resetMask>
<fields>
<field>
<name>TRIGGER_LEVEL</name>
<description>Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated.
Note: software can configure up to 254 in Mono channel enabled (MODE_CTL.PCM_CH_SET = '1' or '2'), up to 253 in Stereo channel enabled (MODE_CTL.PCM_CH_SET = '3').</description>
<bitRange>[7:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>CLEAR</name>
<description>When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>FREEZE</name>
<description>When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer.This field is used only for debugging purposes.</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_STATUS</name>
<description>RX FIFO status</description>
<addressOffset>0x304</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFF00FF</resetMask>
<fields>
<field>
<name>USED</name>
<description>Number of entries in the RX FIFO. The field value is in the range [0, 255]. When this is zero, the RX FIFO is empty.</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RD_PTR</name>
<description>RX FIFO read pointer: RX FIFO location from which a data frame is read by the host.This field is used only for debugging purposes.</description>
<bitRange>[23:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>WR_PTR</name>
<description>RX FIFO write pointer: RX FIFO location at which a new data frame is written by the hardware.This field is used only for debugging purposes.</description>
<bitRange>[31:24]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_RD</name>
<description>RX FIFO read</description>
<addressOffset>0x308</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data read from the RX FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation.
Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RX_FIFO_RD_SILENT</name>
<description>RX FIFO silent read</description>
<addressOffset>0x30C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes.
Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>Interrupt register</description>
<addressOffset>0xF00</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x650000</resetMask>
<fields>
<field>
<name>RX_TRIGGER</name>
<description>More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_NOT_EMPTY</name>
<description>RX FIFO is not empty.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_OVERFLOW</name>
<description>Attempt to write to a full RX FIFO</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_UNDERFLOW</name>
<description>Attempt to read from an empty RX FIFO</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_SET</name>
<description>Interrupt set register</description>
<addressOffset>0xF04</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x650000</resetMask>
<fields>
<field>
<name>RX_TRIGGER</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_NOT_EMPTY</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_OVERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_UNDERFLOW</name>
<description>Write with '1' to set corresponding bit in interrupt request register.</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASK</name>
<description>Interrupt mask register</description>
<addressOffset>0xF08</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0x650000</resetMask>
<fields>
<field>
<name>RX_TRIGGER</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_NOT_EMPTY</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_OVERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[21:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>RX_UNDERFLOW</name>
<description>Mask bit for corresponding bit in interrupt request register.</description>
<bitRange>[22:22]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>INTR_MASKED</name>
<description>Interrupt masked register</description>
<addressOffset>0xF0C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0x650000</resetMask>
<fields>
<field>
<name>RX_TRIGGER</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_NOT_EMPTY</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[18:18]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_OVERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[21:21]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_UNDERFLOW</name>
<description>Logical and of corresponding request and mask bits.</description>
<bitRange>[22:22]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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