16171 lines
548 KiB
XML
16171 lines
548 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
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<name>M367</name>
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<version>0.1</version>
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<description>TOSHIBA Cortex-M3 MCU</description>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<peripherals>
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<peripheral>
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<name>UDFS</name>
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<description>UDC2 AHB Bridge</description>
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<baseAddress>0x40008000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x24</size>
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<usage>registers</usage>
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</addressBlock>
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<addressBlock>
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<offset>0x24</offset>
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<size>0x18</size>
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<usage>reserved</usage>
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</addressBlock>
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<addressBlock>
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<offset>0x3c</offset>
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<size>0x24</size>
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<usage>registers</usage>
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</addressBlock>
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<addressBlock>
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<offset>0x60</offset>
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<size>0x20</size>
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<usage>reserved</usage>
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</addressBlock>
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<addressBlock>
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<offset>0x80</offset>
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<size>0xc</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>INTSTS</name>
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<description>Interrupt Status Register</description>
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<addressOffset>0x000</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field>
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<name>INT_SETUP</name>
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<description>INT_SETUP</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>INT_STATUS_NAK</name>
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<description>INT_STATUS_NAK</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>INT_STATUS</name>
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<description>INT_STATUS</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>INT_RX_ZERO</name>
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<description>INT_RX_ZERO</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>INT_SOF</name>
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<description>INT_SOF</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>INT_EP0</name>
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<description>INT_EP0</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>INT_EP</name>
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<description>INT_EP</description>
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<bitOffset>6</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>INT_NAK</name>
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<description>INT_NAK</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>INT_SUSPEND_RESUME</name>
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<description>INT_SUSPEND_RESUME</description>
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<bitOffset>8</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_USB_RESET</name>
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<description>INT_USB_RESET</description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_USB_RESET_END</name>
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<description>INT_USB_RESET_END</description>
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<bitOffset>10</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_MW_SET_ADD</name>
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<description>INT_MW_SET_ADD</description>
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<bitOffset>17</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_MW_END_ADD</name>
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<description>INT_MW_END_ADD</description>
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<bitOffset>18</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_MW_TIMEOUT</name>
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<description>INT_MW_TIMEOUT</description>
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<bitOffset>19</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_MW_AHBERR</name>
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<description>INT_MW_AHBERR</description>
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<bitOffset>20</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_MR_END_ADD</name>
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<description>INT_MR_END_ADD</description>
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<bitOffset>21</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_MR_EP_DSET</name>
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<description>INT_MR_EP_DSET</description>
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<bitOffset>22</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_MR_AHBERR</name>
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<description>INT_MR_AHBERR</description>
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<bitOffset>23</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_UDC2_REG_RD</name>
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<description>INT_UDC2_REG_RD</description>
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<bitOffset>24</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_DMAC_REG_RD</name>
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<description>INT_DMAC_REG_RD</description>
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<bitOffset>25</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_POWERDETECT</name>
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<description>INT_POWERDETECT</description>
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<bitOffset>28</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>INT_MW_RERROR</name>
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<description>INT_MW_RERROR</description>
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<bitOffset>29</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>INTENB</name>
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<description>Interrupt Enable Register</description>
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<addressOffset>0x004</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field>
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<name>SUSPEND_RESUME_EN</name>
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<description>SUSPEND_RESUME_EN</description>
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<bitOffset>8</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>RESET_EN</name>
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<description>RESET_EN</description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>RESET_END_EN</name>
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<description>RESET_END_EN</description>
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<bitOffset>10</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>MW_SET_ADD_EN</name>
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<description>MW_SET_ADD_EN</description>
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<bitOffset>17</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>MW_END_ADD_EN</name>
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<description>MW_END_ADD_EN</description>
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<bitOffset>18</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>MW_TIMEOUT_EN</name>
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<description>MW_TIMEOUT_EN</description>
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<bitOffset>19</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>MW_AHBERR_EN</name>
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<description>MW_AHBERR_EN</description>
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<bitOffset>20</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>MR_END_ADD_EN</name>
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<description>MR_END_ADD_EN</description>
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<bitOffset>21</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>MR_EP_DSET_EN</name>
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<description>MR_EP_DSET_EN</description>
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<bitOffset>22</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>MR_AHBERR_EN</name>
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<description>MR_AHBERR_EN</description>
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<bitOffset>23</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>UDC2_REG_RD_EN</name>
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<description>UDC2_REG_RD_EN</description>
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<bitOffset>24</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>DMAC_REG_RD_EN</name>
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<description>DMAC_REG_RD_EN</description>
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<bitOffset>25</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>POWER_DETECT_EN</name>
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<description>POWER_DETECT_EN</description>
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<bitOffset>28</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>MW_RERROR_EN</name>
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<description>MW_RERROR_EN</description>
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<bitOffset>29</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>MWTOUT</name>
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<description>Master Write Timeout Register</description>
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<addressOffset>0x008</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0xffffffff</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field>
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<name>TIMEOUT_EN</name>
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<description>TIMEOUT_EN</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>TIMEOUTSET</name>
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<description>TIMEOUTSET</description>
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<bitOffset>1</bitOffset>
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<bitWidth>31</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>C2STSET</name>
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<description>UDC2 setting</description>
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<addressOffset>0x00C</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000010</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field>
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<name>TX0</name>
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<description>TX0</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>EOPB_ENABLE</name>
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<description>EOPB_ENABLE</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>MSTSET</name>
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<description>DMAC setting</description>
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<addressOffset>0x0010</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field>
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<name>MW_ENABLE</name>
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<description>MW_ENABLE</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>MW_ABORT</name>
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<description>MW_ABORT</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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<field>
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<name>MW_RESET</name>
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<description>MW_RESET</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>MR_ENABLE</name>
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<description>MR_ENABLE</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>MR_ABORT</name>
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<description>MR_ABORT</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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<field>
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<name>MR_RESET</name>
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<description>MR_RESET</description>
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<bitOffset>6</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>M_BURST_TYPE</name>
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<description>M_BURST_TYPE</description>
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<bitOffset>8</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>DMACRDREQ</name>
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<description>DMAC Read request</description>
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<addressOffset>0x0014</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field>
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<name>DMARDADR</name>
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<description>DMARDADR</description>
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<bitOffset>2</bitOffset>
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<bitWidth>6</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>DMARDCLR</name>
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<description>DMARDCLR</description>
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<bitOffset>30</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>DMARDREQ</name>
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<description>DMARDREQ</description>
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<bitOffset>31</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>DMACRDVL</name>
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<description>DMAC Read Value</description>
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<addressOffset>0x0018</addressOffset>
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<size>32</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field>
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<name>DMARDDATA</name>
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<description>DMARDDATA</description>
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<bitOffset>0</bitOffset>
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<bitWidth>32</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>UDC2RDREQ</name>
|
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<description>UDC2 Read Request</description>
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<addressOffset>0x001C</addressOffset>
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<size>32</size>
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<access>read-write</access>
|
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<resetValue>0x00000000</resetValue>
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<resetMask>0xffffffff</resetMask>
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<fields>
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<field>
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<name>UDC2RDADR</name>
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<description>UDC2RDADR</description>
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<bitOffset>2</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-write</access>
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</field>
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<field>
|
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<name>UDC2RDCLR</name>
|
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<description>UDC2RDCLR</description>
|
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<bitOffset>30</bitOffset>
|
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<bitWidth>1</bitWidth>
|
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<access>read-write</access>
|
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</field>
|
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<field>
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<name>UDC2RDREQ</name>
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<description>UDC2RDREQ</description>
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<bitOffset>31</bitOffset>
|
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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</fields>
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</register>
|
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<register>
|
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<name>UDC2RDVL</name>
|
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<description>UDC2 Read Value</description>
|
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<addressOffset>0x0020</addressOffset>
|
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<size>32</size>
|
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<access>read-only</access>
|
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<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UDC2RDATA</name>
|
|
<description>UDC2RDATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARBTSET</name>
|
|
<description>Arbiter Setting</description>
|
|
<addressOffset>0x003C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ABTPRI_R0</name>
|
|
<description>ABTPRI_R0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ABTPRI_R1</name>
|
|
<description>ABTPRI_R1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ABTPRI_W0</name>
|
|
<description>ABTPRI_W0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ABTPRI_W1</name>
|
|
<description>ABTPRI_W1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ABTMOD</name>
|
|
<description>ABTMOD</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ABT_EN</name>
|
|
<description>ABT_EN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MWSADR</name>
|
|
<description>Master Write Start Address</description>
|
|
<addressOffset>0x0040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MWSADR</name>
|
|
<description>MWSADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MWEADR</name>
|
|
<description>Master Write End Address</description>
|
|
<addressOffset>0x0044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MWEADR</name>
|
|
<description>MWEADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MWCADR</name>
|
|
<description>Master Write Current Address</description>
|
|
<addressOffset>0x0048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MWCADR</name>
|
|
<description>MWCADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MWAHBADR</name>
|
|
<description>Master Write AHB Address</description>
|
|
<addressOffset>0x004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MWAHBADR</name>
|
|
<description>MWAHBADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MRSADR</name>
|
|
<description>Master Read Start Address</description>
|
|
<addressOffset>0x0050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MRSADR</name>
|
|
<description>MRSADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MREADR</name>
|
|
<description>Master Read End Address</description>
|
|
<addressOffset>0x0054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MREADR</name>
|
|
<description>MREADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MRCADR</name>
|
|
<description>Master Read Current Address</description>
|
|
<addressOffset>0x0058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MRCADR</name>
|
|
<description>MRCADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MRAHBADR</name>
|
|
<description>Master Read AHB Address</description>
|
|
<addressOffset>0x005C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MRAHBADR</name>
|
|
<description>MRAHBADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWCTL</name>
|
|
<description>Power Detect Control</description>
|
|
<addressOffset>0x0080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000032</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RESET</name>
|
|
<description>USB_RESET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PW_RESETB</name>
|
|
<description>PW_RESETB</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PW_DETECT</name>
|
|
<description>PW_DETECT</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PHY_SUSPEND</name>
|
|
<description>PHY_SUSPEND</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SUSPEND_X</name>
|
|
<description>SUSPEND_X</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PHY_RESETB</name>
|
|
<description>PHY_RESETB</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PHY_REMOTE_WKUP</name>
|
|
<description>PHY_REMOTE_WKUP</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP_EN</name>
|
|
<description>WAKEUP_EN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSTSTS</name>
|
|
<description>Master Status</description>
|
|
<addressOffset>0x0084</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000001c</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MWEPDSET</name>
|
|
<description>MWEPDSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MREPDSET</name>
|
|
<description>MREPDSET</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MWBFEMP</name>
|
|
<description>MWBFEMP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MRBFEMP</name>
|
|
<description>MRBFEMP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MREPEMPTY</name>
|
|
<description>MREPEMPTY</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOUTCNT</name>
|
|
<description>Timeout Count</description>
|
|
<addressOffset>0x0088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xffffffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TMOUTCNT</name>
|
|
<description>TMOUTCNT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UDFS2</name>
|
|
<description>UDC2(USB -Spec2.0 Device contoller)</description>
|
|
<baseAddress>0x40008200</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xc</offset>
|
|
<size>0xa4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xb0</offset>
|
|
<size>0x280</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x330</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ADR</name>
|
|
<description>UDC2 Address State</description>
|
|
<addressOffset>0x0000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEV_ADR</name>
|
|
<description>DEV_ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEFAULT</name>
|
|
<description>DEFAULT</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDRESSED</name>
|
|
<description>ADDRESSED</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CONFIGURED</name>
|
|
<description>CONFIGURED</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SUSPEND</name>
|
|
<description>SUSPEND</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CUR_SPEED</name>
|
|
<description>CUR_SPEED</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP_BI_MODE</name>
|
|
<description>EP_BI_MODE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STAGE_ERR</name>
|
|
<description>STAGE_ERR</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRM</name>
|
|
<description>UDC2 Frame</description>
|
|
<addressOffset>0x0004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>FRAME</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>F_STATUS</name>
|
|
<description>F_STATUS</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CREATE_SOF</name>
|
|
<description>CREATE_SOF</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>UDC2 Command</description>
|
|
<addressOffset>0x000C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COM</name>
|
|
<description>COM</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EP</name>
|
|
<description>EP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX_NULLPKT_EP</name>
|
|
<description>RX_NULLPKT_EP</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INT_TOGGLE</name>
|
|
<description>INT_TOGGLE</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRQ</name>
|
|
<description>UDC2 bRequest-bmRequest Type</description>
|
|
<addressOffset>0x0010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECIPIENT</name>
|
|
<description>RECIPIENT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REQ_TYPE</name>
|
|
<description>REQ_TYPE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REQUESET</name>
|
|
<description>REQUESET</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WVL</name>
|
|
<description>UDC2 wValue</description>
|
|
<addressOffset>0x0014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>VALUE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WIDX</name>
|
|
<description>UDC2 wIndex</description>
|
|
<addressOffset>0x0018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INDEX</name>
|
|
<description>INDEX</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WLGTH</name>
|
|
<description>UDC2 wLength</description>
|
|
<addressOffset>0x001C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LENGTH</name>
|
|
<description>LENGTH</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT</name>
|
|
<description>UDC2 INT</description>
|
|
<addressOffset>0x0020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I_SETUP</name>
|
|
<description>I_SETUP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_STATUS_NAK</name>
|
|
<description>I_STATUS_NAK</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_STATUS</name>
|
|
<description>I_STATUS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_RX_DATA0</name>
|
|
<description>I_RX_DATA0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_SOF</name>
|
|
<description>I_SOF</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP0</name>
|
|
<description>I_EP0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP</name>
|
|
<description>I_EP</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_NAK</name>
|
|
<description>I_NAK</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_SETUP</name>
|
|
<description>M_SETUP</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_STATUS_NAK</name>
|
|
<description>M_STATUS_NAK</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_STATUS</name>
|
|
<description>M_STATUS</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_RX_DATA0</name>
|
|
<description>M_RX_DATA0</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_SOF</name>
|
|
<description>M_SOF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_EP0</name>
|
|
<description>M_EP0</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_EP</name>
|
|
<description>M_EP</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_NAK</name>
|
|
<description>M_NAK</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEP</name>
|
|
<description>UDC2 INT_EP</description>
|
|
<addressOffset>0x0024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I_EP1</name>
|
|
<description>I_EP1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP2</name>
|
|
<description>I_EP2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP3</name>
|
|
<description>I_EP3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP4</name>
|
|
<description>I_EP4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP5</name>
|
|
<description>I_EP5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP6</name>
|
|
<description>I_EP6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP7</name>
|
|
<description>I_EP7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEPMSK</name>
|
|
<description>UDC2 INT_EP_MASK</description>
|
|
<addressOffset>0x0028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M_EP</name>
|
|
<description>M_EP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTRX0</name>
|
|
<description>UDC2 INT RX DATA0</description>
|
|
<addressOffset>0x002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_D0_EP</name>
|
|
<description>RX_D0_EP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP0MSZ</name>
|
|
<description>UDC2 EP0 Max Packet Size</description>
|
|
<addressOffset>0x0030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAX_PKT</name>
|
|
<description>MAX_PKT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>DSET</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_0DATA</name>
|
|
<description>TX_0DATA</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP0STS</name>
|
|
<description>UDC2 EP0 Status</description>
|
|
<addressOffset>0x0034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOGGLE</name>
|
|
<description>TOGGLE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP0_MASK</name>
|
|
<description>EP0_MASK</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP0DSZ</name>
|
|
<description>UDC2 EP0 Data Size</description>
|
|
<addressOffset>0x0038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>SIZE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP0FIFO</name>
|
|
<description>UDC2 EP0 FIFO</description>
|
|
<addressOffset>0x003C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP1MSZ</name>
|
|
<description>UDC2 EP1 Max Packet Size</description>
|
|
<addressOffset>0x0040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAX_PKT</name>
|
|
<description>MAX_PKT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>DSET</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_0DATA</name>
|
|
<description>TX_0DATA</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP1STS</name>
|
|
<description>UDC2 EP1 Status</description>
|
|
<addressOffset>0x0044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUM_MF</name>
|
|
<description>NUM_MF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>T_TYPE</name>
|
|
<description>T_TYPE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE</name>
|
|
<description>DISABLE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOGGLE</name>
|
|
<description>TOGGLE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUS_SEL</name>
|
|
<description>BUS_SEL</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKT_MODE</name>
|
|
<description>PKT_MODE</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP1DSZ</name>
|
|
<description>UDC2 EP1 Data Size</description>
|
|
<addressOffset>0x0048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>SIZE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP1FIFO</name>
|
|
<description>UDC2 EP1 FIFO</description>
|
|
<addressOffset>0x004C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP2MSZ</name>
|
|
<description>UDC2 EP2 Max Packet Size</description>
|
|
<addressOffset>0x0050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAX_PKT</name>
|
|
<description>MAX_PKT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>DSET</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_0DATA</name>
|
|
<description>TX_0DATA</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP2STS</name>
|
|
<description>UDC2 EP2 Status</description>
|
|
<addressOffset>0x0054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUM_MF</name>
|
|
<description>NUM_MF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>T_TYPE</name>
|
|
<description>T_TYPE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE</name>
|
|
<description>DISABLE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOGGLE</name>
|
|
<description>TOGGLE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUS_SEL</name>
|
|
<description>BUS_SEL</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKT_MODE</name>
|
|
<description>PKT_MODE</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP2DSZ</name>
|
|
<description>UDC2 EP2 Data Size</description>
|
|
<addressOffset>0x0058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>SIZE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP2FIFO</name>
|
|
<description>UDC2 EP2 FIFO</description>
|
|
<addressOffset>0x005C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP3MSZ</name>
|
|
<description>UDC3 EP3 Max Packet Size</description>
|
|
<addressOffset>0x0060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAX_PKT</name>
|
|
<description>MAX_PKT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>DSET</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_0DATA</name>
|
|
<description>TX_0DATA</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP3STS</name>
|
|
<description>UDC3 EP3 Status</description>
|
|
<addressOffset>0x0064</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUM_MF</name>
|
|
<description>NUM_MF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>T_TYPE</name>
|
|
<description>T_TYPE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE</name>
|
|
<description>DISABLE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOGGLE</name>
|
|
<description>TOGGLE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUS_SEL</name>
|
|
<description>BUS_SEL</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKT_MODE</name>
|
|
<description>PKT_MODE</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP3DSZ</name>
|
|
<description>UDC3 EP3 Data Size</description>
|
|
<addressOffset>0x0068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>SIZE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP3FIFO</name>
|
|
<description>UDC3 EP3 FIFO</description>
|
|
<addressOffset>0x006C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP4MSZ</name>
|
|
<description>UDC2 EP4 Max Packet Size</description>
|
|
<addressOffset>0x0070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAX_PKT</name>
|
|
<description>MAX_PKT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>DSET</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_0DATA</name>
|
|
<description>TX_0DATA</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP4STS</name>
|
|
<description>UDC2 EP4 Status</description>
|
|
<addressOffset>0x0074</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUM_MF</name>
|
|
<description>NUM_MF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>T_TYPE</name>
|
|
<description>T_TYPE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE</name>
|
|
<description>DISABLE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOGGLE</name>
|
|
<description>TOGGLE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUS_SEL</name>
|
|
<description>BUS_SEL</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKT_MODE</name>
|
|
<description>PKT_MODE</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP4DSZ</name>
|
|
<description>UDC2 EP4 Data Size</description>
|
|
<addressOffset>0x0078</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>SIZE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP4FIFO</name>
|
|
<description>UDC2 EP4 FIFO</description>
|
|
<addressOffset>0x007C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP5MSZ</name>
|
|
<description>UDC2 EP5 Max Packet Size</description>
|
|
<addressOffset>0x0080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAX_PKT</name>
|
|
<description>MAX_PKT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>DSET</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_0DATA</name>
|
|
<description>TX_0DATA</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP5STS</name>
|
|
<description>UDC2 EP5 Status</description>
|
|
<addressOffset>0x0084</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUM_MF</name>
|
|
<description>NUM_MF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>T_TYPE</name>
|
|
<description>T_TYPE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE</name>
|
|
<description>DISABLE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOGGLE</name>
|
|
<description>TOGGLE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUS_SEL</name>
|
|
<description>BUS_SEL</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKT_MODE</name>
|
|
<description>PKT_MODE</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP5DSZ</name>
|
|
<description>UDC2 EP5 Data Size</description>
|
|
<addressOffset>0x0088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>SIZE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP5FIFO</name>
|
|
<description>UDC2 EP5 FIFO</description>
|
|
<addressOffset>0x008C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP6MSZ</name>
|
|
<description>UDC2 EP6 Max Packet Size</description>
|
|
<addressOffset>0x0090</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAX_PKT</name>
|
|
<description>MAX_PKT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>DSET</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_0DATA</name>
|
|
<description>TX_0DATA</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP6STS</name>
|
|
<description>UDC2 EP6 Status</description>
|
|
<addressOffset>0x0094</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUM_MF</name>
|
|
<description>NUM_MF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>T_TYPE</name>
|
|
<description>T_TYPE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE</name>
|
|
<description>DISABLE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOGGLE</name>
|
|
<description>TOGGLE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUS_SEL</name>
|
|
<description>BUS_SEL</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKT_MODE</name>
|
|
<description>PKT_MODE</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP6DSZ</name>
|
|
<description>UDC2 EP6 Data Size</description>
|
|
<addressOffset>0x0098</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>SIZE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP6FIFO</name>
|
|
<description>UDC2 EP6 FIFO</description>
|
|
<addressOffset>0x009C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP7MSZ</name>
|
|
<description>UDC2 EP7 Max Packet Size</description>
|
|
<addressOffset>0x00A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAX_PKT</name>
|
|
<description>MAX_PKT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>DSET</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX_0DATA</name>
|
|
<description>TX_0DATA</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP7STS</name>
|
|
<description>UDC2 EP7 Status</description>
|
|
<addressOffset>0x00A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUM_MF</name>
|
|
<description>NUM_MF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>T_TYPE</name>
|
|
<description>T_TYPE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE</name>
|
|
<description>DISABLE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>STATUS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOGGLE</name>
|
|
<description>TOGGLE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUS_SEL</name>
|
|
<description>BUS_SEL</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKT_MODE</name>
|
|
<description>PKT_MODE</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP7DSZ</name>
|
|
<description>UDC2 EP7 Data Size</description>
|
|
<addressOffset>0x00A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>SIZE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP7FIFO</name>
|
|
<description>UDC2 EP7 FIFO</description>
|
|
<addressOffset>0x00AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTNAK</name>
|
|
<description>UDC2 INT NAK</description>
|
|
<addressOffset>0x0330</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I_EP1</name>
|
|
<description>I_EP1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP2</name>
|
|
<description>I_EP2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP3</name>
|
|
<description>I_EP3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP4</name>
|
|
<description>I_EP4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP5</name>
|
|
<description>I_EP5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP6</name>
|
|
<description>I_EP6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I_EP7</name>
|
|
<description>I_EP7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTNAKMSK</name>
|
|
<description>UDC2 INT NAK MASK</description>
|
|
<addressOffset>0x0334</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M_EP1</name>
|
|
<description>M_EP1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_EP2</name>
|
|
<description>M_EP2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_EP3</name>
|
|
<description>M_EP3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_EP4</name>
|
|
<description>M_EP4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_EP5</name>
|
|
<description>M_EP5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_EP6</name>
|
|
<description>M_EP6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M_EP7</name>
|
|
<description>M_EP7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SSP0</name>
|
|
<description>Synchronous Serial Port</description>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>SSP Control Register 0</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSS</name>
|
|
<description>DSS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRF</name>
|
|
<description>FRF</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SPO</name>
|
|
<description>SPO</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SPH</name>
|
|
<description>SPH</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCR</name>
|
|
<description>SCR</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>SSP Control Register 1</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000f</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LBM</name>
|
|
<description>LBM</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSE</name>
|
|
<description>SSE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MS</name>
|
|
<description>MS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOD</name>
|
|
<description>SOD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>SSP Data Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000ffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>SSP Status Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x0000001f</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>TFE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TNF</name>
|
|
<description>TNF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RNE</name>
|
|
<description>RNE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFF</name>
|
|
<description>RFF</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>BSY</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPSR</name>
|
|
<description>SSP Clock Prescaler Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000ff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CPSDVSR</name>
|
|
<description>CPSDVSR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMSC</name>
|
|
<description>SSP Interrupt Mask Set and Clear Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000f</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORIM</name>
|
|
<description>RORIM</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTIM</name>
|
|
<description>RTIM</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXIM</name>
|
|
<description>RXIM</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXIM</name>
|
|
<description>TXIM</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>SSP Raw Interrupt Status Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0x0000000f</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORRIS</name>
|
|
<description>RORRIS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTRIS</name>
|
|
<description>RTRIS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRIS</name>
|
|
<description>RXRIS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRIS</name>
|
|
<description>TXRIS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>SSP Masked Interrupt Status Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000f</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORMIS</name>
|
|
<description>RORMIS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTMIS</name>
|
|
<description>RTMIS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXMIS</name>
|
|
<description>RXMIS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXMIS</name>
|
|
<description>TXMIS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>SSP Interrupt Clear Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORIC</name>
|
|
<description>RORIC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTIC</name>
|
|
<description>RTIC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACR</name>
|
|
<description>SSP DMA Control Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDMAE</name>
|
|
<description>RXDMAE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAE</name>
|
|
<description>TXDMAE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SSP0">
|
|
<name>SSP1</name>
|
|
<baseAddress>0x40041000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SSP0">
|
|
<name>SSP2</name>
|
|
<baseAddress>0x40042000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART4</name>
|
|
<description>ARM Prime Cell PL011</description>
|
|
<baseAddress>0x40048000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x10</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1c</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x2c</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>Data Register</description>
|
|
<addressOffset>0x0000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>FE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>PE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BE</name>
|
|
<description>BE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>OE</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSR</name>
|
|
<description>Receive Status Register</description>
|
|
<addressOffset>0x0004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>FE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>PE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BE</name>
|
|
<description>BE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>OE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECR</name>
|
|
<description>Error Clear Register</description>
|
|
<addressOffset>0x0004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>FE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>PE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BE</name>
|
|
<description>BE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>OE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR</name>
|
|
<description>Flag Register</description>
|
|
<addressOffset>0x0018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>CTS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSR</name>
|
|
<description>DSR</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DCD</name>
|
|
<description>DCD</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>BUSY</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>RXFE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFF</name>
|
|
<description>TXFF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFF</name>
|
|
<description>RXFF</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>TXFE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>RI</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ILPR</name>
|
|
<description>IrDA Low-power Counter register</description>
|
|
<addressOffset>0x0020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILPDVSR</name>
|
|
<description>ILPDVSR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IBDR</name>
|
|
<description>Integer Baud Rate Register</description>
|
|
<addressOffset>0x0024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BAUDDIVINT</name>
|
|
<description>BAUDDIVINT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FBDR</name>
|
|
<description>Fractional Baud Rate Register</description>
|
|
<addressOffset>0x0028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BAUDDIVFRAC</name>
|
|
<description>BAUDDIVFRAC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCR_H</name>
|
|
<description>Line Control Register</description>
|
|
<addressOffset>0x002C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRK</name>
|
|
<description>BRK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PEN</name>
|
|
<description>PEN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPS</name>
|
|
<description>EPS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STP2</name>
|
|
<description>STP2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FEN</name>
|
|
<description>FEN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WLEN</name>
|
|
<description>WLEN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SPS</name>
|
|
<description>SPS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Cntrol Register</description>
|
|
<addressOffset>0x0030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UARTEN</name>
|
|
<description>UARTEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SIREN</name>
|
|
<description>SIREN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SIRLP</name>
|
|
<description>SIRLP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TXE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>RXE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTR</name>
|
|
<description>DTR</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTS</name>
|
|
<description>RTS</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>RTSEN</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTSEN</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFLS</name>
|
|
<description>Interrupt FIFO Level Select Register</description>
|
|
<addressOffset>0x0034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXIFLSEL</name>
|
|
<description>TXIFLSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXIFLSEL</name>
|
|
<description>RXIFLSEL</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMSC</name>
|
|
<description>Interrupt Mask set_Clear Register</description>
|
|
<addressOffset>0x0038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RIMIM</name>
|
|
<description>RIMIM</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSMIM</name>
|
|
<description>CTSMIM</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDMIM</name>
|
|
<description>DCDMIM</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRMIM</name>
|
|
<description>DSRMIM</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXIM</name>
|
|
<description>RXIM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXIM</name>
|
|
<description>TXIM</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTIM</name>
|
|
<description>RTIM</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FEIM</name>
|
|
<description>FEIM</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PEIM</name>
|
|
<description>PEIM</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BEIM</name>
|
|
<description>BEIM</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OEIM</name>
|
|
<description>OEIM</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>Raw Interrupt Status Register</description>
|
|
<addressOffset>0x003C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xfffffffffffffff1</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RIRMIS</name>
|
|
<description>RIRMIS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSRMIS</name>
|
|
<description>CTSRMIS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDRMIS</name>
|
|
<description>DCDRMIS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRRMIS</name>
|
|
<description>DSRRMIS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXRIS</name>
|
|
<description>RXRIS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRIS</name>
|
|
<description>TXRIS</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTRIS</name>
|
|
<description>RTRIS</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERIS</name>
|
|
<description>FERIS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERIS</name>
|
|
<description>PERIS</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BERIS</name>
|
|
<description>BERIS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OERIS</name>
|
|
<description>OERIS</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>Masked Interrupt Status Register</description>
|
|
<addressOffset>0x0040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xfffffffffffffff1</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RIMMIS</name>
|
|
<description>RIMMIS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSMMIS</name>
|
|
<description>CTSMMIS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDMMIS</name>
|
|
<description>DCDMMIS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRMMIS</name>
|
|
<description>DSRMMIS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXMIS</name>
|
|
<description>RXMIS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXMIS</name>
|
|
<description>TXMIS</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTMIS</name>
|
|
<description>RTMIS</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FEMIS</name>
|
|
<description>FEMIS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PEMIS</name>
|
|
<description>PEMIS</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BEMIS</name>
|
|
<description>BEMIS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OEMIS</name>
|
|
<description>OEMIS</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>Interrupt Clear Register</description>
|
|
<addressOffset>0x0044</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RIMIC</name>
|
|
<description>RIMIC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSMIC</name>
|
|
<description>CTSMIC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDMIC</name>
|
|
<description>DCDMIC</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSRMIC</name>
|
|
<description>DSRMIC</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXIC</name>
|
|
<description>RXIC</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXIC</name>
|
|
<description>TXIC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RTIC</name>
|
|
<description>RTIC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FEIC</name>
|
|
<description>FEIC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PEIC</name>
|
|
<description>PEIC</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BEIC</name>
|
|
<description>BEIC</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OEIC</name>
|
|
<description>OEIC</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACR</name>
|
|
<description>DMA Control Register</description>
|
|
<addressOffset>0x0048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDMAE</name>
|
|
<description>RXDMAE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAE</name>
|
|
<description>TXDMAE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAONERR</name>
|
|
<description>DMAONERR</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART4">
|
|
<name>UART5</name>
|
|
<baseAddress>0x40049000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMAA</name>
|
|
<description>DMA Controller</description>
|
|
<baseAddress>0x4004C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0x2c</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40</offset>
|
|
<size>0xc</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4c</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>DMA Status Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x101f0000</resetValue>
|
|
<resetMask>0xffffff0f</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASTER_ENABLE</name>
|
|
<description>MASTER_ENABLE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>DMA Configuration Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASTER_ENABLE</name>
|
|
<description>MASTER_ENABLE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBASEPTR</name>
|
|
<description>DMA Control Data Base Pointer Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL_BASE_PTR</name>
|
|
<description>CTRL_BASE_PTR</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>22</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTCTRLBASEPTR</name>
|
|
<description>DMA Channel Alternate Control Data Base Pointer Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ALT_CTRL_BASE_PTR</name>
|
|
<description>ALT_CTRL_BASE_PTR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNLSWREQUEST</name>
|
|
<description>DMA Channel Software Request Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_SW_REQUEST</name>
|
|
<description>CHNL_SW_REQUEST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNLUSEBURSTSET</name>
|
|
<description>DMA Channel Useburst Set Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_USEBURST_SET</name>
|
|
<description>CHNL_USEBURST_SET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNLUSEBURSTCLR</name>
|
|
<description>DMA Channel Useburst Clear Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_USEBURST_CLR</name>
|
|
<description>CHNL_USEBURST_CLR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNLREQMASKSET</name>
|
|
<description>DMA Channel Request Mask Set Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_REQ_MASK_SET</name>
|
|
<description>CHNL_REQ_MASK_SET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNLREQMASKCLR</name>
|
|
<description>DMA Channel Request Mask Clear Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_REQ_MASK_CLR</name>
|
|
<description>CHNL_REQ_MASK_CLR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNLENABLESET</name>
|
|
<description>DMA Channel Enable Set Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_ENABLE_SET</name>
|
|
<description>CHNL_ENABLE_SET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNLENABLECLR</name>
|
|
<description>DMA Channel Enable Clear Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_ENABLE_CLR</name>
|
|
<description>CHNL_ENABLE_CLR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNLPRIALTSET</name>
|
|
<description>DMA Channel Primary-Alternate Set Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_PRI_ALT_SET</name>
|
|
<description>CHNL_PRI_ALT_SET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNLPRIALTCLR</name>
|
|
<description>DMA Channel Primary-Alternate Clear Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_PRI_ALT_CLR</name>
|
|
<description>CHNL_PRI_ALT_CLR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNLPRIORITYSET</name>
|
|
<description>DMA Channel Priority Set Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_PRIORITY_SET</name>
|
|
<description>CHNL_PRIORITY_SET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHNLPRIORITYCLR</name>
|
|
<description>DMA Channel Priority Clear Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHNL_PRIORITY_CLR</name>
|
|
<description>CHNL_PRIORITY_CLR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERRCLR</name>
|
|
<description>DMA Bus Error Clear Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERR_CLR</name>
|
|
<description>ERR_CLR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DMAA">
|
|
<name>DMAB</name>
|
|
<baseAddress>0x4004D000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADA</name>
|
|
<description>Analog-to-Digital Converter (AD)</description>
|
|
<baseAddress>0x40050000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x24</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x54</offset>
|
|
<size>0x20</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x74</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CLK</name>
|
|
<description>AD Conversion Clock Setting Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCLK</name>
|
|
<description>ADCLK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADSH</name>
|
|
<description>ADSH</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD0</name>
|
|
<description>AD Mode Control Register 0</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADS</name>
|
|
<description>ADS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HPADS</name>
|
|
<description>HPADS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD1</name>
|
|
<description>AD Mode Control Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADHWE</name>
|
|
<description>ADHWE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADHWS</name>
|
|
<description>ADHWS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPADHWE</name>
|
|
<description>HPADHWE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPADHWS</name>
|
|
<description>HPADHWS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RCUT</name>
|
|
<description>RCUT</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2AD</name>
|
|
<description>I2AD</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACON</name>
|
|
<description>DACON</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD2</name>
|
|
<description>AD Mode Control Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCH</name>
|
|
<description>ADCH</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPADCH</name>
|
|
<description>HPADCH</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD3</name>
|
|
<description>AD Mode Control Register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCAN</name>
|
|
<description>SCAN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REPEAT</name>
|
|
<description>REPEAT</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ITM</name>
|
|
<description>ITM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD4</name>
|
|
<description>AD Mode Control Register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCANSTA</name>
|
|
<description>SCANSTA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANAREA</name>
|
|
<description>SCANAREA</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD5</name>
|
|
<description>AD Mode Control Register 5</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADBF</name>
|
|
<description>ADBF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOCF</name>
|
|
<description>EOCF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HPADBF</name>
|
|
<description>HPADBF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HPEOCF</name>
|
|
<description>HPEOCF</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD6</name>
|
|
<description>AD Mode Control Register 6</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRST</name>
|
|
<description>ADRST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPCR0</name>
|
|
<description>AD Monitoring Setting Register 0</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AINS0</name>
|
|
<description>AINS0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADBIG0</name>
|
|
<description>ADBIG0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPCOND0</name>
|
|
<description>CMPCOND0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMP0EN</name>
|
|
<description>CMP0EN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPCMT0</name>
|
|
<description>CMPCMT0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPCR1</name>
|
|
<description>AD Monitoring Setting Register 1</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AINS1</name>
|
|
<description>AINS1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADBIG1</name>
|
|
<description>ADBIG1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPCOND1</name>
|
|
<description>CMPCOND1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMP1EN</name>
|
|
<description>CMP1EN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPCMT1</name>
|
|
<description>CMPCMT1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP0</name>
|
|
<description>AD Conversion Result Comparison Register 0</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD0CMP</name>
|
|
<description>AD0CMP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1</name>
|
|
<description>AD Conversion Result Comparison Register 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD1CMP</name>
|
|
<description>AD1CMP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG00</name>
|
|
<description>AD Conversion Result Register 00</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG01</name>
|
|
<description>AD Conversion Result Register 01</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG02</name>
|
|
<description>AD Conversion Result Register 02</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG03</name>
|
|
<description>AD Conversion Result Register 03</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG04</name>
|
|
<description>AD Conversion Result Register 04</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG05</name>
|
|
<description>AD Conversion Result Register 05</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG06</name>
|
|
<description>AD Conversion Result Register 06</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG07</name>
|
|
<description>AD Conversion Result Register 07</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGSP</name>
|
|
<description>AD Conversion Result Register SP</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADSPR</name>
|
|
<description>ADSPR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADSPRF</name>
|
|
<description>ADSPRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRSPF</name>
|
|
<description>ADOVRSPF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADSPRF</name>
|
|
<description>_ADSPRF</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADOVRSPF</name>
|
|
<description>_ADOVRSPF</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADSPR</name>
|
|
<description>_ADSPR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADB</name>
|
|
<description>Analog-to-Digital Converter (AD)</description>
|
|
<baseAddress>0x40051000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x24</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x54</offset>
|
|
<size>0x20</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x74</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CLK</name>
|
|
<description>AD Conversion Clock Setting Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCLK</name>
|
|
<description>ADCLK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADSH</name>
|
|
<description>ADSH</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD0</name>
|
|
<description>AD Mode Control Register 0</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADS</name>
|
|
<description>ADS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HPADS</name>
|
|
<description>HPADS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD1</name>
|
|
<description>AD Mode Control Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADHWE</name>
|
|
<description>ADHWE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADHWS</name>
|
|
<description>ADHWS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPADHWE</name>
|
|
<description>HPADHWE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPADHWS</name>
|
|
<description>HPADHWS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RCUT</name>
|
|
<description>RCUT</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2AD</name>
|
|
<description>I2AD</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACON</name>
|
|
<description>DACON</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD2</name>
|
|
<description>AD Mode Control Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCH</name>
|
|
<description>ADCH</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPADCH</name>
|
|
<description>HPADCH</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD3</name>
|
|
<description>AD Mode Control Register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCAN</name>
|
|
<description>SCAN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REPEAT</name>
|
|
<description>REPEAT</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ITM</name>
|
|
<description>ITM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD4</name>
|
|
<description>AD Mode Control Register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCANSTA</name>
|
|
<description>SCANSTA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANAREA</name>
|
|
<description>SCANAREA</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD5</name>
|
|
<description>AD Mode Control Register 5</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADBF</name>
|
|
<description>ADBF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOCF</name>
|
|
<description>EOCF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HPADBF</name>
|
|
<description>HPADBF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HPEOCF</name>
|
|
<description>HPEOCF</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD6</name>
|
|
<description>AD Mode Control Register 6</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRST</name>
|
|
<description>ADRST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPCR0</name>
|
|
<description>AD Monitoring Setting Register 0</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AINS0</name>
|
|
<description>AINS0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADBIG0</name>
|
|
<description>ADBIG0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPCOND0</name>
|
|
<description>CMPCOND0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMP0EN</name>
|
|
<description>CMP0EN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPCMT0</name>
|
|
<description>CMPCMT0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPCR1</name>
|
|
<description>AD Monitoring Setting Register 1</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AINS1</name>
|
|
<description>AINS1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADBIG1</name>
|
|
<description>ADBIG1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPCOND1</name>
|
|
<description>CMPCOND1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMP1EN</name>
|
|
<description>CMP1EN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPCMT1</name>
|
|
<description>CMPCMT1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP0</name>
|
|
<description>AD Conversion Result Comparison Register 0</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD0CMP</name>
|
|
<description>AD0CMP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1</name>
|
|
<description>AD Conversion Result Comparison Register 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AD1CMP</name>
|
|
<description>AD1CMP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG00</name>
|
|
<description>AD Conversion Result Register 00</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG01</name>
|
|
<description>AD Conversion Result Register 01</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG02</name>
|
|
<description>AD Conversion Result Register 02</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG03</name>
|
|
<description>AD Conversion Result Register 03</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG04</name>
|
|
<description>AD Conversion Result Register 04</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG05</name>
|
|
<description>AD Conversion Result Register 05</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG06</name>
|
|
<description>AD Conversion Result Register 06</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG07</name>
|
|
<description>AD Conversion Result Register 07</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADR</name>
|
|
<description>ADR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF</name>
|
|
<description>ADRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF</name>
|
|
<description>ADOVRF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADRF_MIR</name>
|
|
<description>ADRF_MIR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRF_MIR</name>
|
|
<description>ADOVRF_MIR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADR</name>
|
|
<description>_ADR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGSP</name>
|
|
<description>AD Conversion Result Register SP</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADSPR</name>
|
|
<description>ADSPR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADSPRF</name>
|
|
<description>ADSPRF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADOVRSPF</name>
|
|
<description>ADOVRSPF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADSPRF</name>
|
|
<description>_ADSPRF</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADOVRSPF</name>
|
|
<description>_ADOVRSPF</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>_ADSPR</name>
|
|
<description>_ADSPR</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADILV</name>
|
|
<description>Dual ADC Configuration</description>
|
|
<baseAddress>0x40052000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MO1</name>
|
|
<description>Dual Unit Mode Trigger Controller START Register 1</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWATRG</name>
|
|
<description>SWATRG</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MO2</name>
|
|
<description>Dual Unit Mode Trigger Controller START Register 2</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000000e</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRGAEN</name>
|
|
<description>TRGAEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRGASEL</name>
|
|
<description>TRGASEL</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRGASTA</name>
|
|
<description>TRGASTA</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADILV</name>
|
|
<description>ADILV</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MO3</name>
|
|
<description>Dual Unit Mode Trigger Controller START Register 3</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000027</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CORCNT</name>
|
|
<description>CORCNT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DA0</name>
|
|
<description>Digital-to-Analog Converter (DA)</description>
|
|
<baseAddress>0x40054000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>DAC Control Register1</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OP</name>
|
|
<description>OP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFON</name>
|
|
<description>REFON</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG</name>
|
|
<description>DAC Data Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAC</name>
|
|
<description>DAC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCTL</name>
|
|
<description>DAC Output Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAVE</name>
|
|
<description>WAVE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMAEN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRGEN</name>
|
|
<description>TRGEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>TRGSEL</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AMPSEL</name>
|
|
<description>AMPSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET</name>
|
|
<description>OFFSET</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCTL</name>
|
|
<description>DAC Trigger Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWTRG</name>
|
|
<description>SWTRG</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DACCLR</name>
|
|
<description>DACCLR</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VCTL</name>
|
|
<description>DAC Control Register2</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000081</resetValue>
|
|
<resetMask>0x00ffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VHOLDCTF</name>
|
|
<description>VHOLDCTF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VHOLDCTB</name>
|
|
<description>VHOLDCTB</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DA0">
|
|
<name>DA1</name>
|
|
<baseAddress>0x40055000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EXB</name>
|
|
<description>External Bus Interface(EXB)</description>
|
|
<baseAddress>0x4005C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0xc</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x20</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x40</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>External Bus Mode Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXBSEL</name>
|
|
<description>EXBSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EXBWAIT</name>
|
|
<description>EXBWAIT</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AS0</name>
|
|
<description>External Bus Base Address and CS Space setting Register 0</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXAR</name>
|
|
<description>EXAR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SA</name>
|
|
<description>SA</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AS1</name>
|
|
<description>External Bus Base Address and CS Space setting Register 1</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXAR</name>
|
|
<description>EXAR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SA</name>
|
|
<description>SA</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AS2</name>
|
|
<description>External Bus Base Address and CS Space setting Register 2</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXAR</name>
|
|
<description>EXAR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SA</name>
|
|
<description>SA</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AS3</name>
|
|
<description>External Bus Base Address and CS Space setting Register 3</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXAR</name>
|
|
<description>EXAR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SA</name>
|
|
<description>SA</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CS0</name>
|
|
<description>Chip Select and Wait Controller Register 0</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x49150202</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSW0</name>
|
|
<description>CSW0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSW1</name>
|
|
<description>CSW1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSW2</name>
|
|
<description>CSW2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSIW</name>
|
|
<description>CSIW</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDS</name>
|
|
<description>RDS</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRS</name>
|
|
<description>WRS</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALEW</name>
|
|
<description>ALEW</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>RDR</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRR</name>
|
|
<description>WRR</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSR</name>
|
|
<description>CSR</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CS1</name>
|
|
<description>Chip Select and Wait Controller Register 1</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x49150202</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSW0</name>
|
|
<description>CSW0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSW1</name>
|
|
<description>CSW1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSW2</name>
|
|
<description>CSW2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSIW</name>
|
|
<description>CSIW</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDS</name>
|
|
<description>RDS</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRS</name>
|
|
<description>WRS</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALEW</name>
|
|
<description>ALEW</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>RDR</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRR</name>
|
|
<description>WRR</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSR</name>
|
|
<description>CSR</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CS2</name>
|
|
<description>Chip Select and Wait Controller Register 2</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x49150202</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSW0</name>
|
|
<description>CSW0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSW1</name>
|
|
<description>CSW1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSW2</name>
|
|
<description>CSW2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSIW</name>
|
|
<description>CSIW</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDS</name>
|
|
<description>RDS</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRS</name>
|
|
<description>WRS</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALEW</name>
|
|
<description>ALEW</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>RDR</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRR</name>
|
|
<description>WRR</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSR</name>
|
|
<description>CSR</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CS3</name>
|
|
<description>Chip Select and Wait Controller Register 3</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x49150202</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSW0</name>
|
|
<description>CSW0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSW1</name>
|
|
<description>CSW1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSW2</name>
|
|
<description>CSW2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSIW</name>
|
|
<description>CSIW</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDS</name>
|
|
<description>RDS</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRS</name>
|
|
<description>WRS</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALEW</name>
|
|
<description>ALEW</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>RDR</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRR</name>
|
|
<description>WRR</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSR</name>
|
|
<description>CSR</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PA</name>
|
|
<description>General Purpose Input_Output Port (PA)</description>
|
|
<baseAddress>0x400C0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1c</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1c</offset>
|
|
<size>0xc</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>PA Data Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PA0</name>
|
|
<description>PA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA1</name>
|
|
<description>PA1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA2</name>
|
|
<description>PA2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA3</name>
|
|
<description>PA3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA4</name>
|
|
<description>PA4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA5</name>
|
|
<description>PA5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA6</name>
|
|
<description>PA6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA7</name>
|
|
<description>PA7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>PA Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PA0C</name>
|
|
<description>PA0C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA1C</name>
|
|
<description>PA1C</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA2C</name>
|
|
<description>PA2C</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA3C</name>
|
|
<description>PA3C</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA4C</name>
|
|
<description>PA4C</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA5C</name>
|
|
<description>PA5C</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA6C</name>
|
|
<description>PA6C</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA7C</name>
|
|
<description>PA7C</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR1</name>
|
|
<description>PA Function Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000001f</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PA0F1</name>
|
|
<description>PA0F1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA1F1</name>
|
|
<description>PA1F1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA2F1</name>
|
|
<description>PA2F1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA3F1</name>
|
|
<description>PA3F1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA4F1</name>
|
|
<description>PA4F1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA5F1</name>
|
|
<description>PA5F1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA6F1</name>
|
|
<description>PA6F1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA7F1</name>
|
|
<description>PA7F1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR2</name>
|
|
<description>PA Function Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PA0F2</name>
|
|
<description>PA0F2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA1F2</name>
|
|
<description>PA1F2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA2F2</name>
|
|
<description>PA2F2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA3F2</name>
|
|
<description>PA3F2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA4F2</name>
|
|
<description>PA4F2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA5F2</name>
|
|
<description>PA5F2</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA6F2</name>
|
|
<description>PA6F2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA7F2</name>
|
|
<description>PA7F2</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR3</name>
|
|
<description>PA Function Register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PA3F3</name>
|
|
<description>PA3F3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA5F3</name>
|
|
<description>PA5F3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA6F3</name>
|
|
<description>PA6F3</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA7F3</name>
|
|
<description>PA7F3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR4</name>
|
|
<description>PA Function Register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PA7F4</name>
|
|
<description>PA7F4</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR5</name>
|
|
<description>PA Function Register 5</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PA7F5</name>
|
|
<description>PA7F5</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OD</name>
|
|
<description>PA Open Drain Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PA0OD</name>
|
|
<description>PA0OD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA1OD</name>
|
|
<description>PA1OD</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA2OD</name>
|
|
<description>PA2OD</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA3OD</name>
|
|
<description>PA3OD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA4OD</name>
|
|
<description>PA4OD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA5OD</name>
|
|
<description>PA5OD</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA6OD</name>
|
|
<description>PA6OD</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA7OD</name>
|
|
<description>PA7OD</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUP</name>
|
|
<description>PA Pull-Up Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000001a</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PA0UP</name>
|
|
<description>PA0UP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA1UP</name>
|
|
<description>PA1UP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA2UP</name>
|
|
<description>PA2UP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA3UP</name>
|
|
<description>PA3UP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA4UP</name>
|
|
<description>PA4UP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA5UP</name>
|
|
<description>PA5UP</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA6UP</name>
|
|
<description>PA6UP</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA7UP</name>
|
|
<description>PA7UP</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDN</name>
|
|
<description>PA Pull-Down Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000004</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PA0DN</name>
|
|
<description>PA0DN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA1DN</name>
|
|
<description>PA1DN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA2DN</name>
|
|
<description>PA2DN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA3DN</name>
|
|
<description>PA3DN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA4DN</name>
|
|
<description>PA4DN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA5DN</name>
|
|
<description>PA5DN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA6DN</name>
|
|
<description>PA6DN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA7DN</name>
|
|
<description>PA7DN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>PA Input Enable Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000001e</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PA0IE</name>
|
|
<description>PA0IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA1IE</name>
|
|
<description>PA1IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA2IE</name>
|
|
<description>PA2IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA3IE</name>
|
|
<description>PA3IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA4IE</name>
|
|
<description>PA4IE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA5IE</name>
|
|
<description>PA5IE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA6IE</name>
|
|
<description>PA6IE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA7IE</name>
|
|
<description>PA7IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PB</name>
|
|
<description>General Purpose Input_Output Port (PB)</description>
|
|
<baseAddress>0x400C0100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x10</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>PB Data Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB0</name>
|
|
<description>PB0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB1</name>
|
|
<description>PB1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB2</name>
|
|
<description>PB2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB3</name>
|
|
<description>PB3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB4</name>
|
|
<description>PB4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB5</name>
|
|
<description>PB5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB6</name>
|
|
<description>PB6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>PB Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB0C</name>
|
|
<description>PB0C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB1C</name>
|
|
<description>PB1C</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB2C</name>
|
|
<description>PB2C</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB3C</name>
|
|
<description>PB3C</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB4C</name>
|
|
<description>PB4C</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB5C</name>
|
|
<description>PB5C</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB6C</name>
|
|
<description>PB6C</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR1</name>
|
|
<description>PB Function Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB0F1</name>
|
|
<description>PB0F1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB1F1</name>
|
|
<description>PB1F1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB2F1</name>
|
|
<description>PB2F1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB3F1</name>
|
|
<description>PB3F1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB4F1</name>
|
|
<description>PB4F1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB5F1</name>
|
|
<description>PB5F1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB6F1</name>
|
|
<description>PB6F1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR2</name>
|
|
<description>PB Function Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB2F2</name>
|
|
<description>PB2F2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB3F2</name>
|
|
<description>PB3F2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB4F2</name>
|
|
<description>PB4F2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB5F2</name>
|
|
<description>PB5F2</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB6F2</name>
|
|
<description>PB6F2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR3</name>
|
|
<description>PB Function Register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB0F3</name>
|
|
<description>PB0F3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB1F3</name>
|
|
<description>PB1F3</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB2F3</name>
|
|
<description>PB2F3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB3F3</name>
|
|
<description>PB3F3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB4F3</name>
|
|
<description>PB4F3</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB5F3</name>
|
|
<description>PB5F3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR4</name>
|
|
<description>PB Function Register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB2F4</name>
|
|
<description>PB2F4</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB3F4</name>
|
|
<description>PB3F4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB4F4</name>
|
|
<description>PB4F4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB5F4</name>
|
|
<description>PB5F4</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB6F4</name>
|
|
<description>PB6F4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OD</name>
|
|
<description>PB Open Drain Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB0OD</name>
|
|
<description>PB0OD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB1OD</name>
|
|
<description>PB1OD</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB2OD</name>
|
|
<description>PB2OD</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB3OD</name>
|
|
<description>PB3OD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB4OD</name>
|
|
<description>PB4OD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB5OD</name>
|
|
<description>PB5OD</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB6OD</name>
|
|
<description>PB6OD</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUP</name>
|
|
<description>PB Pull-Up Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB0UP</name>
|
|
<description>PB0UP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB1UP</name>
|
|
<description>PB1UP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB2UP</name>
|
|
<description>PB2UP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB3UP</name>
|
|
<description>PB3UP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB4UP</name>
|
|
<description>PB4UP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB5UP</name>
|
|
<description>PB5UP</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB6UP</name>
|
|
<description>PB6UP</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDN</name>
|
|
<description>PB Pull-Down Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB0DN</name>
|
|
<description>PB0DN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB1DN</name>
|
|
<description>PB1DN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB2DN</name>
|
|
<description>PB2DN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB3DN</name>
|
|
<description>PB3DN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB4DN</name>
|
|
<description>PB4DN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB5DN</name>
|
|
<description>PB5DN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB6DN</name>
|
|
<description>PB6DN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>PB Input Enable Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB0IE</name>
|
|
<description>PB0IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB1IE</name>
|
|
<description>PB1IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB2IE</name>
|
|
<description>PB2IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB3IE</name>
|
|
<description>PB3IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB4IE</name>
|
|
<description>PB4IE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB5IE</name>
|
|
<description>PB5IE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB6IE</name>
|
|
<description>PB6IE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PE</name>
|
|
<description>General Purpose Input_Output Port (PE)</description>
|
|
<baseAddress>0x400C0400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1c</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1c</offset>
|
|
<size>0xc</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>PE Data Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE0</name>
|
|
<description>PE0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE1</name>
|
|
<description>PE1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE2</name>
|
|
<description>PE2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE3</name>
|
|
<description>PE3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE4</name>
|
|
<description>PE4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE5</name>
|
|
<description>PE5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE6</name>
|
|
<description>PE6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE7</name>
|
|
<description>PE7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>PE Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE0C</name>
|
|
<description>PE0C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE1C</name>
|
|
<description>PE1C</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE2C</name>
|
|
<description>PE2C</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE3C</name>
|
|
<description>PE3C</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE4C</name>
|
|
<description>PE4C</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE5C</name>
|
|
<description>PE5C</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE6C</name>
|
|
<description>PE6C</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE7C</name>
|
|
<description>PE7C</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR1</name>
|
|
<description>PE Function Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE1F1</name>
|
|
<description>PE1F1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE2F1</name>
|
|
<description>PE2F1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE3F1</name>
|
|
<description>PE3F1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE4F1</name>
|
|
<description>PE4F1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE5F1</name>
|
|
<description>PE5F1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE6F1</name>
|
|
<description>PE6F1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR2</name>
|
|
<description>PE Function Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE0F2</name>
|
|
<description>PE0F2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE1F2</name>
|
|
<description>PE1F2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE2F2</name>
|
|
<description>PE2F2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE3F2</name>
|
|
<description>PE3F2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE4F2</name>
|
|
<description>PE4F2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE5F2</name>
|
|
<description>PE5F2</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE6F2</name>
|
|
<description>PE6F2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE7F2</name>
|
|
<description>PE7F2</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR3</name>
|
|
<description>PE Function Register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE0F3</name>
|
|
<description>PE0F3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE1F3</name>
|
|
<description>PE1F3</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE2F3</name>
|
|
<description>PE2F3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE3F3</name>
|
|
<description>PE3F3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE4F3</name>
|
|
<description>PE4F3</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE5F3</name>
|
|
<description>PE5F3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE6F3</name>
|
|
<description>PE6F3</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE7F3</name>
|
|
<description>PE7F3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR4</name>
|
|
<description>PE Function Register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE0F4</name>
|
|
<description>PE0F4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE1F4</name>
|
|
<description>PE1F4</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE3F4</name>
|
|
<description>PE3F4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE4F4</name>
|
|
<description>PE4F4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE7F4</name>
|
|
<description>PE7F4</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR5</name>
|
|
<description>PE Function Register 5</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE0F5</name>
|
|
<description>PE0F5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE1F5</name>
|
|
<description>PE1F5</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE2F5</name>
|
|
<description>PE2F5</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE3F5</name>
|
|
<description>PE3F5</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE4F5</name>
|
|
<description>PE4F5</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE7F5</name>
|
|
<description>PE7F5</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OD</name>
|
|
<description>PE Open Drain Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE0OD</name>
|
|
<description>PE0OD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE1OD</name>
|
|
<description>PE1OD</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE2OD</name>
|
|
<description>PE2OD</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE3OD</name>
|
|
<description>PE3OD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE4OD</name>
|
|
<description>PE4OD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE5OD</name>
|
|
<description>PE5OD</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE6OD</name>
|
|
<description>PE6OD</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE7OD</name>
|
|
<description>PE7OD</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUP</name>
|
|
<description>PE Pull-Up Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE0UP</name>
|
|
<description>PE0UP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE1UP</name>
|
|
<description>PE1UP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE2UP</name>
|
|
<description>PE2UP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE3UP</name>
|
|
<description>PE3UP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE4UP</name>
|
|
<description>PE4UP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE5UP</name>
|
|
<description>PE5UP</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE6UP</name>
|
|
<description>PE6UP</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE7UP</name>
|
|
<description>PE7UP</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDN</name>
|
|
<description>PE Pull-Down Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE0DN</name>
|
|
<description>PE0DN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE1DN</name>
|
|
<description>PE1DN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE2DN</name>
|
|
<description>PE2DN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE3DN</name>
|
|
<description>PE3DN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE4DN</name>
|
|
<description>PE4DN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE5DN</name>
|
|
<description>PE5DN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE6DN</name>
|
|
<description>PE6DN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE7DN</name>
|
|
<description>PE7DN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>PE Input Enable Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PE0IE</name>
|
|
<description>PE0IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE1IE</name>
|
|
<description>PE1IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE2IE</name>
|
|
<description>PE2IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE3IE</name>
|
|
<description>PE3IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE4IE</name>
|
|
<description>PE4IE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE5IE</name>
|
|
<description>PE5IE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE6IE</name>
|
|
<description>PE6IE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE7IE</name>
|
|
<description>PE7IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PF</name>
|
|
<description>General Purpose Input_Output Port (PF)</description>
|
|
<baseAddress>0x400C0500</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x10</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>PF Data Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF0</name>
|
|
<description>PF0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF1</name>
|
|
<description>PF1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF2</name>
|
|
<description>PF2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF3</name>
|
|
<description>PF3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF4</name>
|
|
<description>PF4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF5</name>
|
|
<description>PF5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF6</name>
|
|
<description>PF6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF7</name>
|
|
<description>PF7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>PF Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF0C</name>
|
|
<description>PF0C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF1C</name>
|
|
<description>PF1C</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF2C</name>
|
|
<description>PF2C</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF3C</name>
|
|
<description>PF3C</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF4C</name>
|
|
<description>PF4C</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF5C</name>
|
|
<description>PF5C</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF6C</name>
|
|
<description>PF6C</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF7C</name>
|
|
<description>PF7C</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR1</name>
|
|
<description>PF Function Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF0F1</name>
|
|
<description>PF0F1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF1F1</name>
|
|
<description>PF1F1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF2F1</name>
|
|
<description>PF2F1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF3F1</name>
|
|
<description>PF3F1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF4F1</name>
|
|
<description>PF4F1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF5F1</name>
|
|
<description>PF5F1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF6F1</name>
|
|
<description>PF6F1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF7F1</name>
|
|
<description>PF7F1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR2</name>
|
|
<description>PF Function Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF4F2</name>
|
|
<description>PF4F2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF5F2</name>
|
|
<description>PF5F2</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF6F2</name>
|
|
<description>PF6F2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF7F2</name>
|
|
<description>PF7F2</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR3</name>
|
|
<description>PF Function Register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF0F3</name>
|
|
<description>PF0F3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF1F3</name>
|
|
<description>PF1F3</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF2F3</name>
|
|
<description>PF2F3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF3F3</name>
|
|
<description>PF3F3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF4F4</name>
|
|
<description>PF4F4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF5F3</name>
|
|
<description>PF5F3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF6F3</name>
|
|
<description>PF6F3</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF7F3</name>
|
|
<description>PF7F3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR4</name>
|
|
<description>PF Function Register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF1F4</name>
|
|
<description>PF1F4</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF2F4</name>
|
|
<description>PF2F4</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF5F4</name>
|
|
<description>PF5F4</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF6F4</name>
|
|
<description>PF6F4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF7F4</name>
|
|
<description>PF7F4</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OD</name>
|
|
<description>PF Open Drain Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF0OD</name>
|
|
<description>PF0OD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF1OD</name>
|
|
<description>PF1OD</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF2OD</name>
|
|
<description>PF2OD</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF3OD</name>
|
|
<description>PF3OD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF4OD</name>
|
|
<description>PF4OD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF5OD</name>
|
|
<description>PF5OD</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF6OD</name>
|
|
<description>PF6OD</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF7OD</name>
|
|
<description>PF7OD</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUP</name>
|
|
<description>PF Pull-Up Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF0UP</name>
|
|
<description>PF0UP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF1UP</name>
|
|
<description>PF1UP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF2UP</name>
|
|
<description>PF2UP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF3UP</name>
|
|
<description>PF3UP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF4UP</name>
|
|
<description>PF4UP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF5UP</name>
|
|
<description>PF5UP</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF6UP</name>
|
|
<description>PF6UP</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF7UP</name>
|
|
<description>PF7UP</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDN</name>
|
|
<description>PF Pull-Down Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF0DN</name>
|
|
<description>PF0DN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF1DN</name>
|
|
<description>PF1DN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF2DN</name>
|
|
<description>PF2DN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF3DN</name>
|
|
<description>PF3DN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF4DN</name>
|
|
<description>PF4DN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF5DN</name>
|
|
<description>PF5DN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF6DN</name>
|
|
<description>PF6DN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF7DN</name>
|
|
<description>PF7DN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>PF Input Enable Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PF0IE</name>
|
|
<description>PF0IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF1IE</name>
|
|
<description>PF1IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF2IE</name>
|
|
<description>PF2IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF3IE</name>
|
|
<description>PF3IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF4IE</name>
|
|
<description>PF4IE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF5IE</name>
|
|
<description>PF5IE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF6IE</name>
|
|
<description>PF6IE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF7IE</name>
|
|
<description>PF7IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PG</name>
|
|
<description>General Purpose Input_Output Port (PG)</description>
|
|
<baseAddress>0x400C0600</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x10</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>PG Data Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG0</name>
|
|
<description>PG0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG1</name>
|
|
<description>PG1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG2</name>
|
|
<description>PG2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG3</name>
|
|
<description>PG3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG4</name>
|
|
<description>PG4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG5</name>
|
|
<description>PG5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG6</name>
|
|
<description>PG6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG7</name>
|
|
<description>PG7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>PG Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG0C</name>
|
|
<description>PG0C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG1C</name>
|
|
<description>PG1C</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG2C</name>
|
|
<description>PG2C</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG3C</name>
|
|
<description>PG3C</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG4C</name>
|
|
<description>PG4C</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG5C</name>
|
|
<description>PG5C</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG6C</name>
|
|
<description>PG6C</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG7C</name>
|
|
<description>PG7C</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR1</name>
|
|
<description>PG Function Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG0F1</name>
|
|
<description>PG0F1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG1F1</name>
|
|
<description>PG1F1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG2F1</name>
|
|
<description>PG2F1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG3F1</name>
|
|
<description>PG3F1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG4F1</name>
|
|
<description>PG4F1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PG5F1</name>
|
|
<description>PG5F1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG6F1</name>
|
|
<description>PG6F1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PG7F1</name>
|
|
<description>PG7F1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR2</name>
|
|
<description>PG Function Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG1F2</name>
|
|
<description>PG1F2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG2F2</name>
|
|
<description>PG2F2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG3F2</name>
|
|
<description>PG3F2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG4F2</name>
|
|
<description>PG4F2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG5F2</name>
|
|
<description>PG5F2</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG6F2</name>
|
|
<description>PG6F2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG7F2</name>
|
|
<description>PG7F2</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR3</name>
|
|
<description>PG Function Register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG0F3</name>
|
|
<description>PG0F3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG1F3</name>
|
|
<description>PG1F3</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG2F3</name>
|
|
<description>PG2F3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG3F3</name>
|
|
<description>PG3F3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG4F3</name>
|
|
<description>PG4F3</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG5F3</name>
|
|
<description>PG5F3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG6F3</name>
|
|
<description>PG6F3</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG7F3</name>
|
|
<description>PG7F3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR4</name>
|
|
<description>PG Function Register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG2F4</name>
|
|
<description>PG2F4</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG3F4</name>
|
|
<description>PG3F4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OD</name>
|
|
<description>PG Open Drain Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG0OD</name>
|
|
<description>PG0OD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG1OD</name>
|
|
<description>PG1OD</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG2OD</name>
|
|
<description>PG2OD</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG3OD</name>
|
|
<description>PG3OD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG4OD</name>
|
|
<description>PG4OD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG5OD</name>
|
|
<description>PG5OD</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG6OD</name>
|
|
<description>PG6OD</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG7OD</name>
|
|
<description>PG7OD</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUP</name>
|
|
<description>PG Pull-Up Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG0UP</name>
|
|
<description>PG0UP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG1UP</name>
|
|
<description>PG1UP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG2UP</name>
|
|
<description>PG2UP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG3UP</name>
|
|
<description>PG3UP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG4UP</name>
|
|
<description>PG4UP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG5UP</name>
|
|
<description>PG5UP</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG6UP</name>
|
|
<description>PG6UP</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG7UP</name>
|
|
<description>PG7UP</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDN</name>
|
|
<description>PG Pull-Down Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG0DN</name>
|
|
<description>PG0DN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG1DN</name>
|
|
<description>PG1DN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG2DN</name>
|
|
<description>PG2DN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG3DN</name>
|
|
<description>PG3DN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG4DN</name>
|
|
<description>PG4DN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG5DN</name>
|
|
<description>PG5DN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG6DN</name>
|
|
<description>PG6DN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG7DN</name>
|
|
<description>PG7DN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>PG Input Enable Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PG0IE</name>
|
|
<description>PG0IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG1IE</name>
|
|
<description>PG1IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG2IE</name>
|
|
<description>PG2IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG3IE</name>
|
|
<description>PG3IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG4IE</name>
|
|
<description>PG4IE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG5IE</name>
|
|
<description>PG5IE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG6IE</name>
|
|
<description>PG6IE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PG7IE</name>
|
|
<description>PG7IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PH</name>
|
|
<description>General Purpose Input_Output Port (PH)</description>
|
|
<baseAddress>0x400C0700</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1c</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1c</offset>
|
|
<size>0xc</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>PH Data Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PH0</name>
|
|
<description>PH0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH1</name>
|
|
<description>PH1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH2</name>
|
|
<description>PH2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH3</name>
|
|
<description>PH3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>PH Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PH0C</name>
|
|
<description>PH0C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH1C</name>
|
|
<description>PH1C</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH2C</name>
|
|
<description>PH2C</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH3C</name>
|
|
<description>PH3C</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR1</name>
|
|
<description>PH Function Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PH0F1</name>
|
|
<description>PH0F1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH1F1</name>
|
|
<description>PH1F1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH2F1</name>
|
|
<description>PH2F1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH3F1</name>
|
|
<description>PH3F1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR2</name>
|
|
<description>PH Function Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PH0F2</name>
|
|
<description>PH0F2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH1F2</name>
|
|
<description>PH1F2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH2F2</name>
|
|
<description>PH2F2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH3F2</name>
|
|
<description>PH3F2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR3</name>
|
|
<description>PH Function Register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PH0F3</name>
|
|
<description>PH0F3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH1F3</name>
|
|
<description>PH1F3</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH2F3</name>
|
|
<description>PH2F3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH3F3</name>
|
|
<description>PH3F3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR4</name>
|
|
<description>PH Function Register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PH2F4</name>
|
|
<description>PH2F4</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH3F4</name>
|
|
<description>PH3F4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR5</name>
|
|
<description>PH Function Register 5</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PH0F5</name>
|
|
<description>PH0F5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH1F5</name>
|
|
<description>PH1F5</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH2F5</name>
|
|
<description>PH2F5</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH3F5</name>
|
|
<description>PH3F5</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OD</name>
|
|
<description>PH Open Drain Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PH0OD</name>
|
|
<description>PH0OD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH1OD</name>
|
|
<description>PH1OD</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH2OD</name>
|
|
<description>PH2OD</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH3OD</name>
|
|
<description>PH3OD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUP</name>
|
|
<description>PH Pull-Up Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PH0UP</name>
|
|
<description>PH0UP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH1UP</name>
|
|
<description>PH1UP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH2UP</name>
|
|
<description>PH2UP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH3UP</name>
|
|
<description>PH3UP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDN</name>
|
|
<description>PH Pull-Down Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PN0DN</name>
|
|
<description>PN0DN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PN1DN</name>
|
|
<description>PN1DN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PN2DN</name>
|
|
<description>PN2DN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PN3DN</name>
|
|
<description>PN3DN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>PH Input Enable Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PH0IE</name>
|
|
<description>PH0IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH1IE</name>
|
|
<description>PH1IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH2IE</name>
|
|
<description>PH2IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PH3IE</name>
|
|
<description>PH3IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PI</name>
|
|
<description>General Purpose Input_Output Port (PI)</description>
|
|
<baseAddress>0x400C0800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x18</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>PI Data Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PI0</name>
|
|
<description>PI0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI1</name>
|
|
<description>PI1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI2</name>
|
|
<description>PI2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI3</name>
|
|
<description>PI3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI4</name>
|
|
<description>PI4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI5</name>
|
|
<description>PI5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI6</name>
|
|
<description>PI6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI7</name>
|
|
<description>PI7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>PI Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000c0</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PI0C</name>
|
|
<description>PI0C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI1C</name>
|
|
<description>PI1C</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI2C</name>
|
|
<description>PI2C</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI3C</name>
|
|
<description>PI3C</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI4C</name>
|
|
<description>PI4C</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI5C</name>
|
|
<description>PI5C</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI6C</name>
|
|
<description>PI6C</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI7C</name>
|
|
<description>PI7C</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR1</name>
|
|
<description>PI Function Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PI0F1</name>
|
|
<description>PI0F1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI1F1</name>
|
|
<description>PI1F1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI2F1</name>
|
|
<description>PI2F1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI3F1</name>
|
|
<description>PI3F1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR2</name>
|
|
<description>PI Function Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PI3F2</name>
|
|
<description>PI3F2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OD</name>
|
|
<description>PI Open Drain Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PI0OD</name>
|
|
<description>PI0OD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI1OD</name>
|
|
<description>PI1OD</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI2OD</name>
|
|
<description>PI2OD</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI3OD</name>
|
|
<description>PI3OD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI4OD</name>
|
|
<description>PI4OD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI5OD</name>
|
|
<description>PI5OD</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI6OD</name>
|
|
<description>PI6OD</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI7OD</name>
|
|
<description>PI7OD</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUP</name>
|
|
<description>PI Pull-Up Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PI0UP</name>
|
|
<description>PI0UP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI1UP</name>
|
|
<description>PI1UP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI2UP</name>
|
|
<description>PI2UP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI3UP</name>
|
|
<description>PI3UP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI4UP</name>
|
|
<description>PI4UP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI5UP</name>
|
|
<description>PI5UP</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI6UP</name>
|
|
<description>PI6UP</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI7UP</name>
|
|
<description>PI7UP</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDN</name>
|
|
<description>PI Pull-Down Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PI0DN</name>
|
|
<description>PI0DN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI1DN</name>
|
|
<description>PI1DN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI2DN</name>
|
|
<description>PI2DN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI3DN</name>
|
|
<description>PI3DN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI4DN</name>
|
|
<description>PI4DN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI5DN</name>
|
|
<description>PI5DN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI6DN</name>
|
|
<description>PI6DN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI7DN</name>
|
|
<description>PI7DN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>PI Input Enable Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PI0IE</name>
|
|
<description>PI0IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI1IE</name>
|
|
<description>PI1IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI2IE</name>
|
|
<description>PI2IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI3IE</name>
|
|
<description>PI3IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI4IE</name>
|
|
<description>PI4IE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI5IE</name>
|
|
<description>PI5IE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI6IE</name>
|
|
<description>PI6IE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PI7IE</name>
|
|
<description>PI7IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PK</name>
|
|
<description>General Purpose Input_Output Port (PK)</description>
|
|
<baseAddress>0x400C0A00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x10</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>PK Data Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PK0</name>
|
|
<description>PK0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK1</name>
|
|
<description>PK1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK2</name>
|
|
<description>PK2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK3</name>
|
|
<description>PK3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK4</name>
|
|
<description>PK4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>PK Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PK0C</name>
|
|
<description>PK0C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK1C</name>
|
|
<description>PK1C</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK2C</name>
|
|
<description>PK2C</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK3C</name>
|
|
<description>PK3C</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK4C</name>
|
|
<description>PK4C</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR1</name>
|
|
<description>PK Function Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PK0F1</name>
|
|
<description>PK0F1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK1F1</name>
|
|
<description>PK1F1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK2F1</name>
|
|
<description>PK2F1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK3F1</name>
|
|
<description>PK3F1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK4F1</name>
|
|
<description>PK4F1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR2</name>
|
|
<description>PK Function Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PK1F2</name>
|
|
<description>PK1F2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK2F2</name>
|
|
<description>PK2F2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK3F2</name>
|
|
<description>PK3F2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK4F2</name>
|
|
<description>PK4F2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR3</name>
|
|
<description>PK Function Register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PK1F3</name>
|
|
<description>PK1F3</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK2F3</name>
|
|
<description>PK2F3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK3F3</name>
|
|
<description>PK3F3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK4F3</name>
|
|
<description>PK4F3</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR4</name>
|
|
<description>PK Function Register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PK1F4</name>
|
|
<description>PK1F4</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OD</name>
|
|
<description>PK Open Drain Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PK0OD</name>
|
|
<description>PK0OD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK1OD</name>
|
|
<description>PK1OD</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK2OD</name>
|
|
<description>PK2OD</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK3OD</name>
|
|
<description>PK3OD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK4OD</name>
|
|
<description>PK4OD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUP</name>
|
|
<description>PK Pull-Up Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PK0UP</name>
|
|
<description>PK0UP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK1UP</name>
|
|
<description>PK1UP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK2UP</name>
|
|
<description>PK2UP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK3UP</name>
|
|
<description>PK3UP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK4UP</name>
|
|
<description>PK4UP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDN</name>
|
|
<description>PK Pull-Down Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PK0DN</name>
|
|
<description>PK0DN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK1DN</name>
|
|
<description>PK1DN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK2DN</name>
|
|
<description>PK2DN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK3DN</name>
|
|
<description>PK3DN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK4DN</name>
|
|
<description>PK4DN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>PK Input Enable Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PK0IE</name>
|
|
<description>PK0IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK1IE</name>
|
|
<description>PK1IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK2IE</name>
|
|
<description>PK2IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK3IE</name>
|
|
<description>PK3IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK4IE</name>
|
|
<description>PK4IE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PL</name>
|
|
<description>General Purpose Input_Output Port (PL)</description>
|
|
<baseAddress>0x400C0B00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x8</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x34</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x38</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>PL Data Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL0</name>
|
|
<description>PL0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL1</name>
|
|
<description>PL1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL2</name>
|
|
<description>PL2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL3</name>
|
|
<description>PL3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>PL Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL0C</name>
|
|
<description>PL0C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL1C</name>
|
|
<description>PL1C</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL2C</name>
|
|
<description>PL2C</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL3C</name>
|
|
<description>PL3C</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR1</name>
|
|
<description>PL Function Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL0F1</name>
|
|
<description>PL0F1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL1F1</name>
|
|
<description>PL1F1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL2F1</name>
|
|
<description>PL2F1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL3F1</name>
|
|
<description>PL3F1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR2</name>
|
|
<description>PL Function Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL0F2</name>
|
|
<description>PL0F2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL1F2</name>
|
|
<description>PL1F2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL2F2</name>
|
|
<description>PL2F2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL3F2</name>
|
|
<description>PL3F2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR3</name>
|
|
<description>PL Function Register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL0F3</name>
|
|
<description>PL0F3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL1F3</name>
|
|
<description>PL1F3</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL2F3</name>
|
|
<description>PL2F3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL3F3</name>
|
|
<description>PL3F3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR4</name>
|
|
<description>PL Function Register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL0F4</name>
|
|
<description>PL0F4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL1F4</name>
|
|
<description>PL1F4</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL2F4</name>
|
|
<description>PL2F4</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL3F4</name>
|
|
<description>PL3F4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR5</name>
|
|
<description>PL Function Register 5</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL1F5</name>
|
|
<description>PL1F5</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL2F5</name>
|
|
<description>PL2F5</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL3F5</name>
|
|
<description>PL3F5</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR6</name>
|
|
<description>PL Function Register 6</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL3F6</name>
|
|
<description>PL3F6</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OD</name>
|
|
<description>PL Open Drain Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL0OD</name>
|
|
<description>PL0OD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL1OD</name>
|
|
<description>PL1OD</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL2OD</name>
|
|
<description>PL2OD</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL3OD</name>
|
|
<description>PL3OD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUP</name>
|
|
<description>PL Pull-Up Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL0UP</name>
|
|
<description>PL0UP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL1UP</name>
|
|
<description>PL1UP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL2UP</name>
|
|
<description>PL2UP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL3UP</name>
|
|
<description>PL3UP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDN</name>
|
|
<description>PL Pull-Down Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL0DN</name>
|
|
<description>PL0DN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL1DN</name>
|
|
<description>PL1DN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL2DN</name>
|
|
<description>PL2DN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL3DN</name>
|
|
<description>PL3DN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>PL Input Enable Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PL0IE</name>
|
|
<description>PL0IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL1IE</name>
|
|
<description>PL1IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL2IE</name>
|
|
<description>PL2IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL3IE</name>
|
|
<description>PL3IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TB0</name>
|
|
<description>16-bit Timer_Event Counter (TB)</description>
|
|
<baseAddress>0x400C4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x34</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>EN</name>
|
|
<description>TB Enable Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBHALT</name>
|
|
<description>TBHALT</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBEN</name>
|
|
<description>TBEN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RUN</name>
|
|
<description>TB RUN Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBRUN</name>
|
|
<description>TBRUN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBPRUN</name>
|
|
<description>TBPRUN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>TB Control Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSSEL</name>
|
|
<description>CSSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>TRGSEL</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBINSEL</name>
|
|
<description>TBINSEL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2TB</name>
|
|
<description>I2TB</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBSYNC</name>
|
|
<description>TBSYNC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBWBF</name>
|
|
<description>TBWBF</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>TB Mode Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000040</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBCLK</name>
|
|
<description>TBCLK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBCLE</name>
|
|
<description>TBCLE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBCPM</name>
|
|
<description>TBCPM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBCP</name>
|
|
<description>TBCP</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FFCR</name>
|
|
<description>TB Flip-Flop Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000c3</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBFF0C</name>
|
|
<description>TBFF0C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBE0T1</name>
|
|
<description>TBE0T1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBE1T1</name>
|
|
<description>TBE1T1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBC0T1</name>
|
|
<description>TBC0T1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBC1T1</name>
|
|
<description>TBC1T1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST</name>
|
|
<description>TB Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTTB0</name>
|
|
<description>INTTB0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INTTB1</name>
|
|
<description>INTTB1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INTTBOF</name>
|
|
<description>INTTBOF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IM</name>
|
|
<description>TB Interrupt Mask Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBIM0</name>
|
|
<description>TBIM0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBIM1</name>
|
|
<description>TBIM1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBIMOF</name>
|
|
<description>TBIMOF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UC</name>
|
|
<description>TB Read Capture Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBUC</name>
|
|
<description>TBUC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG0</name>
|
|
<description>TB RG0 Timer Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBRG0</name>
|
|
<description>TBRG0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG1</name>
|
|
<description>TB RG1 Timer Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBRG1</name>
|
|
<description>TBRG1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CP0</name>
|
|
<description>TB CP0 Capture Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffff0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBCP0</name>
|
|
<description>TBCP0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CP1</name>
|
|
<description>TB CP1 Capture Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffff0000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBCP1</name>
|
|
<description>TBCP1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA</name>
|
|
<description>TB DMA Enable Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xfffffff8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAEN0</name>
|
|
<description>DMAEN0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN1</name>
|
|
<description>DMAEN1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN2</name>
|
|
<description>DMAEN2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TB0">
|
|
<name>TB1</name>
|
|
<baseAddress>0x400C4100</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TB0">
|
|
<name>TB2</name>
|
|
<baseAddress>0x400C4200</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TB0">
|
|
<name>TB3</name>
|
|
<baseAddress>0x400C4300</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TB0">
|
|
<name>TB4</name>
|
|
<baseAddress>0x400C4400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TB0">
|
|
<name>TB5</name>
|
|
<baseAddress>0x400C4500</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TB0">
|
|
<name>TB6</name>
|
|
<baseAddress>0x400C4600</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TB0">
|
|
<name>TB7</name>
|
|
<baseAddress>0x400C4700</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MT0</name>
|
|
<description>16-bit Multi-Purpose Timer (MPT-TMR_IGBT)</description>
|
|
<baseAddress>0x400C7000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x58</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>EN</name>
|
|
<description>MPT Enable Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTMODE</name>
|
|
<description>MTMODE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTHALT</name>
|
|
<description>MTHALT</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTEN</name>
|
|
<description>MTEN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RUN</name>
|
|
<description>MPT RUN Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTRUN</name>
|
|
<description>MTRUN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTPRUN</name>
|
|
<description>MTPRUN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBCR</name>
|
|
<description>MPT Control Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTTBCSSEL</name>
|
|
<description>MTTBCSSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBTRGSEL</name>
|
|
<description>MTTBTRGSEL</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTI2TB</name>
|
|
<description>MTI2TB</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBWBF</name>
|
|
<description>MTTBWBF</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBMOD</name>
|
|
<description>MPT Mode Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000020</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTTBCLK</name>
|
|
<description>MTTBCLK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBCLE</name>
|
|
<description>MTTBCLE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBCPM</name>
|
|
<description>MTTBCPM</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBCP</name>
|
|
<description>MTTBCP</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBRSWR</name>
|
|
<description>MTTBRSWR</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBFFCR</name>
|
|
<description>MPT Flip-Flop Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000c3</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTTBFF0C</name>
|
|
<description>MTTBFF0C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBE0T1</name>
|
|
<description>MTTBE0T1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBE1T1</name>
|
|
<description>MTTBE1T1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBC0T1</name>
|
|
<description>MTTBC0T1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBC1T1</name>
|
|
<description>MTTBC1T1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBST</name>
|
|
<description>MPT Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTTBINTTB0</name>
|
|
<description>MTTBINTTB0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBINTTB1</name>
|
|
<description>MTTBINTTB1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBINTTBOF</name>
|
|
<description>MTTBINTTBOF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBIM</name>
|
|
<description>MPT Interrupt Mask Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTTBIM0</name>
|
|
<description>MTTBIM0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBIM1</name>
|
|
<description>MTTBIM1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTTBIMOF</name>
|
|
<description>MTTBIMOF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBUC</name>
|
|
<description>MPT Read Capture Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTUC</name>
|
|
<description>MTUC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG0</name>
|
|
<description>MPT RG0 Timer Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTRG0</name>
|
|
<description>MTRG0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG1</name>
|
|
<description>MPT RG1 Timer Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTRG1</name>
|
|
<description>MTRG1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CP0</name>
|
|
<description>MPT CP0 Capture Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTCP0</name>
|
|
<description>MTCP0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CP1</name>
|
|
<description>MPT CP1 Capture Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTCP1</name>
|
|
<description>MTCP1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IGCR</name>
|
|
<description>IGBT Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IGCLK</name>
|
|
<description>IGCLK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGSTA</name>
|
|
<description>IGSTA</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGSTP</name>
|
|
<description>IGSTP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGSNGL</name>
|
|
<description>IGSNGL</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGPRD</name>
|
|
<description>IGPRD</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGIDIS</name>
|
|
<description>IGIDIS</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IGRESTA</name>
|
|
<description>IGBT Timer Restart Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IGRESTA</name>
|
|
<description>IGRESTA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IGST</name>
|
|
<description>IGBT Timer Status Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IGST</name>
|
|
<description>IGST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IGICR</name>
|
|
<description>IGBT Input Control Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IGNCSEL</name>
|
|
<description>IGNCSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGTRGSEL</name>
|
|
<description>IGTRGSEL</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGTRGM</name>
|
|
<description>IGTRGM</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IGOCR</name>
|
|
<description>IGBT Output Control Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IGOEN0</name>
|
|
<description>IGOEN0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGOEN1</name>
|
|
<description>IGOEN1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGPOL0</name>
|
|
<description>IGPOL0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGPOL1</name>
|
|
<description>IGPOL1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IGRG2</name>
|
|
<description>IGBT RG2 Timer Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IGRG2</name>
|
|
<description>IGRG2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IGRG3</name>
|
|
<description>IGBT RG3 Timer Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IGRG3</name>
|
|
<description>IGRG3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IGRG4</name>
|
|
<description>IGBT RG4 Timer Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IGRG4</name>
|
|
<description>IGRG4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IGEMGCR</name>
|
|
<description>IGBT EMG Control Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IGEMGEN</name>
|
|
<description>IGEMGEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGEMGOC</name>
|
|
<description>IGEMGOC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGEMGRS</name>
|
|
<description>IGEMGRS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IGEMGCNT</name>
|
|
<description>IGEMGCNT</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IGEMGST</name>
|
|
<description>IGBT EMG Status Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IGEMGST</name>
|
|
<description>IGEMGST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IGEMGIN</name>
|
|
<description>IGEMGIN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="MT0">
|
|
<name>MT1</name>
|
|
<baseAddress>0x400C7100</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="MT0">
|
|
<name>MT2</name>
|
|
<baseAddress>0x400C7200</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="MT0">
|
|
<name>MT3</name>
|
|
<baseAddress>0x400C7300</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>Real Time Clock (RTC)</description>
|
|
<baseAddress>0x400CC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x3</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3</offset>
|
|
<size>0x1</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x9</offset>
|
|
<size>0x3</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0xc</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SECR</name>
|
|
<description>RTC Second Column Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x80</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>SE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MINR</name>
|
|
<description>RTC Minute Column Register</description>
|
|
<addressOffset>0x01</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x80</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MI</name>
|
|
<description>MI</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HOURR</name>
|
|
<description>RTC Hour Column Register</description>
|
|
<addressOffset>0x02</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xc0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HO</name>
|
|
<description>HO</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAYR</name>
|
|
<description>RTC Day of the Week Column Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xf8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WE</name>
|
|
<description>WE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATER</name>
|
|
<description>RTC Day Column Register</description>
|
|
<addressOffset>0x05</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xc0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DA</name>
|
|
<description>DA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MONTHR_A</name>
|
|
<description>RTC Month Column Register</description>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xe0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MO</name>
|
|
<description>MO</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MONTHR_B</name>
|
|
<description>RTC Month Column Register</description>
|
|
<alternateGroup>RTC_MONTHR</alternateGroup>
|
|
<addressOffset>0x06</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xfe</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MO0</name>
|
|
<description>MO0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>YEARR_A</name>
|
|
<description>RTC Year Column Register</description>
|
|
<addressOffset>0x07</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0x00</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>YE</name>
|
|
<description>YE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>YEARR_B</name>
|
|
<description>RTC Year Column Register</description>
|
|
<alternateGroup>RTC_YEARR</alternateGroup>
|
|
<addressOffset>0x07</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xfc</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LEAP</name>
|
|
<description>LEAP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PAGER</name>
|
|
<description>RTC PAGE Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xf3</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PAGE</name>
|
|
<description>PAGE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAALM</name>
|
|
<description>ENAALM</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENATMR</name>
|
|
<description>ENATMR</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADJUST</name>
|
|
<description>ADJUST</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTENA</name>
|
|
<description>INTENA</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESTR</name>
|
|
<description>RTC Reset Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xc7</resetValue>
|
|
<resetMask>0xff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIS8HZ</name>
|
|
<description>DIS8HZ</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS4HZ</name>
|
|
<description>DIS4HZ</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS2HZ</name>
|
|
<description>DIS2HZ</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTALM</name>
|
|
<description>RSTALM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTTMR</name>
|
|
<description>RSTTMR</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS16HZ</name>
|
|
<description>DIS16HZ</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS1HZ</name>
|
|
<description>DIS1HZ</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SBI0</name>
|
|
<description>Serial Bus Interface (SBI)</description>
|
|
<baseAddress>0x400E0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>SBI Control Register 0</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBIEN</name>
|
|
<description>SBIEN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1_A</name>
|
|
<description>SBI Control Register 1 (I2C Mode)</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x3fffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWRMON</name>
|
|
<description>SWRMON</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCK</name>
|
|
<description>SCK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>BC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1_B</name>
|
|
<description>SBI Control Register 1 (SIO Mode)</description>
|
|
<alternateGroup>SBI_CR1</alternateGroup>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCK</name>
|
|
<description>SCK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SIOM</name>
|
|
<description>SIOM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SIOINH</name>
|
|
<description>SIOINH</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SIOS</name>
|
|
<description>SIOS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBR</name>
|
|
<description>SBI Data Buffer Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DB</name>
|
|
<description>DB</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2CAR</name>
|
|
<description>SBI I2C Bus Address Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ALS</name>
|
|
<description>ALS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SA</name>
|
|
<description>SA</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>SBI Control Register 2 (I2C Mode)</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>SWRST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SBIM</name>
|
|
<description>SBIM</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PIN</name>
|
|
<description>PIN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BB</name>
|
|
<description>BB</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRX</name>
|
|
<description>TRX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MST</name>
|
|
<description>MST</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>SBI Status Register (I2C Mode)</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LRB</name>
|
|
<description>LRB</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADO</name>
|
|
<description>ADO</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AAS</name>
|
|
<description>AAS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AL</name>
|
|
<description>AL</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PIN</name>
|
|
<description>PIN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BB</name>
|
|
<description>BB</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRX</name>
|
|
<description>TRX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MST</name>
|
|
<description>MST</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BR0</name>
|
|
<description>SBI Baud Rate Register 0</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000be</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2SBI</name>
|
|
<description>I2SBI</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SBI0">
|
|
<name>SBI1</name>
|
|
<baseAddress>0x400E0100</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SBI0">
|
|
<name>SBI2</name>
|
|
<baseAddress>0x400E0200</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SC0</name>
|
|
<description>Serial Channel (SC)</description>
|
|
<baseAddress>0x400E1000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x34</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>EN</name>
|
|
<description>SC Enable Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIOE</name>
|
|
<description>SIOE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF</name>
|
|
<description>SC Buffer Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TB_RB</name>
|
|
<description>TB_RB</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>SC Control Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IOC</name>
|
|
<description>IOC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLKS</name>
|
|
<description>SCLKS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>FERR</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>PERR</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OERR</name>
|
|
<description>OERR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>PE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EVEN</name>
|
|
<description>EVEN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RB8</name>
|
|
<description>RB8</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD0</name>
|
|
<description>SC Mode Control Register 0</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SC</name>
|
|
<description>SC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SM</name>
|
|
<description>SM</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WU</name>
|
|
<description>WU</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>RXE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSE</name>
|
|
<description>CTSE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TB8</name>
|
|
<description>TB8</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRCR</name>
|
|
<description>SC Baud Rate Generator Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRS</name>
|
|
<description>BRS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRCK</name>
|
|
<description>BRCK</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRADDE</name>
|
|
<description>BRADDE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRADD</name>
|
|
<description>SC Baud Rate Generator Control Register 2</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRK</name>
|
|
<description>BRK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD1</name>
|
|
<description>SC Mode Control Register 1</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SINT</name>
|
|
<description>SINT</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TXE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FDPX</name>
|
|
<description>FDPX</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SC</name>
|
|
<description>I2SC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD2</name>
|
|
<description>SC Mode Control Register 2</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>SWRST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WBUF</name>
|
|
<description>WBUF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DRCHG</name>
|
|
<description>DRCHG</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SBLEN</name>
|
|
<description>SBLEN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXRUN</name>
|
|
<description>TXRUN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RBFLL</name>
|
|
<description>RBFLL</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TBEMP</name>
|
|
<description>TBEMP</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFC</name>
|
|
<description>SC RX FIFO Configuration Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RIL</name>
|
|
<description>RIL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFIS</name>
|
|
<description>RFIS</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFCS</name>
|
|
<description>RFCS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TFC</name>
|
|
<description>SC TX FIFO Configuration Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIL</name>
|
|
<description>TIL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TFIS</name>
|
|
<description>TFIS</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TFCS</name>
|
|
<description>TFCS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RST</name>
|
|
<description>SC RX FIFO Status Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RLVL</name>
|
|
<description>RLVL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ROR</name>
|
|
<description>ROR</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TST</name>
|
|
<description>SC TX FIFO Status Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TLVL</name>
|
|
<description>TLVL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TUR</name>
|
|
<description>TUR</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCNF</name>
|
|
<description>SC FIFO Configuration Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNFG</name>
|
|
<description>CNFG</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXTXCNT</name>
|
|
<description>RXTXCNT</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFIE</name>
|
|
<description>RFIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>TFIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFST</name>
|
|
<description>RFST</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SC0">
|
|
<name>SC1</name>
|
|
<baseAddress>0x400E1100</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SC0">
|
|
<name>SC2</name>
|
|
<baseAddress>0x400E1200</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SC0">
|
|
<name>SC3</name>
|
|
<baseAddress>0x400E1300</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RMC</name>
|
|
<description>Remote Control Signal Preprocessor (RMC)</description>
|
|
<baseAddress>0x400E7000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x38</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>EN</name>
|
|
<description>RMC Enable Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCEN</name>
|
|
<description>RMCEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REN</name>
|
|
<description>RMC Receive Enable Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCREN</name>
|
|
<description>RMCREN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RBUF1</name>
|
|
<description>RMC Receive Data Buffer Register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCRBUF</name>
|
|
<description>RMCRBUF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RBUF2</name>
|
|
<description>RMC Receive Data Buffer Register 2</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCRBUF</name>
|
|
<description>RMCRBUF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RBUF3</name>
|
|
<description>RMC Receive Data Buffer Register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCRBUF</name>
|
|
<description>RMCRBUF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR1</name>
|
|
<description>RMC Receive Control Register 1</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCLLMIN</name>
|
|
<description>RMCLLMIN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCLLMAX</name>
|
|
<description>RMCLLMAX</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCLCMIN</name>
|
|
<description>RMCLCMIN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCLCMAX</name>
|
|
<description>RMCLCMAX</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR2</name>
|
|
<description>RMC Receive Control Register 2</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000ffff</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCDMAX</name>
|
|
<description>RMCDMAX</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCLL</name>
|
|
<description>RMCLL</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCPHM</name>
|
|
<description>RMCPHM</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCLD</name>
|
|
<description>RMCLD</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCEDIEN</name>
|
|
<description>RMCEDIEN</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCLIEN</name>
|
|
<description>RMCLIEN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR3</name>
|
|
<description>RMC Receive Control Register 3</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCDATL</name>
|
|
<description>RMCDATL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCDATH</name>
|
|
<description>RMCDATH</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR4</name>
|
|
<description>RMC Receive Control Register 4</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCNC</name>
|
|
<description>RMCNC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCPO</name>
|
|
<description>RMCPO</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTAT</name>
|
|
<description>RMC Receive Status Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCRNUM</name>
|
|
<description>RMCRNUM</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCRLDR</name>
|
|
<description>RMCRLDR</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCEDIF</name>
|
|
<description>RMCEDIF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCDMAXIF</name>
|
|
<description>RMCDMAXIF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCLOIF</name>
|
|
<description>RMCLOIF</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RMCRLIF</name>
|
|
<description>RMCRLIF</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>END1</name>
|
|
<description>RMC Receive End Bit Number Register 1</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCEND1</name>
|
|
<description>RMCEND1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>END2</name>
|
|
<description>RMC Receive End Bit Number Register 2</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCEND2</name>
|
|
<description>RMCEND2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>END3</name>
|
|
<description>RMC Receive End Bit Number Register 3</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCEND3</name>
|
|
<description>RMCEND3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSSEL</name>
|
|
<description>RMC Frequency Selection Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMCCLK</name>
|
|
<description>RMCCLK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OFD</name>
|
|
<description>Oscillation Frequency Detector (OFD)</description>
|
|
<baseAddress>0x400F1000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>OFD Control Register 1</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000006</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFDWEN</name>
|
|
<description>OFDWEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>OFD Control Register 2</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFDEN</name>
|
|
<description>OFDEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MN0</name>
|
|
<description>OFD Lower Detection Frequency Setting Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFDMN0</name>
|
|
<description>OFDMN0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MN1</name>
|
|
<description>OFD Lower Detection Frequency Setting Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFDMN1</name>
|
|
<description>OFDMN1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MX0</name>
|
|
<description>OFD Higher Detection Frequency Setting Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFDMX0</name>
|
|
<description>OFDMX0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MX1</name>
|
|
<description>OFD Higher Detection Frequency Setting Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFDMX1</name>
|
|
<description>OFDMX1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RST</name>
|
|
<description>OFD Reset Enable Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFDRSTEN</name>
|
|
<description>OFDRSTEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>OFD Status Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x1ffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRQERR</name>
|
|
<description>FRQERR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OFDBUSY</name>
|
|
<description>OFDBUSY</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MON</name>
|
|
<description>OFD</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFDMON</name>
|
|
<description>OFDMON</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WD</name>
|
|
<description>Watchdog Timer (WD)</description>
|
|
<baseAddress>0x400F2000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>WD Mode Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000082</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESCR</name>
|
|
<description>RESCR</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2WDT</name>
|
|
<description>I2WDT</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDTP</name>
|
|
<description>WDTP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDTE</name>
|
|
<description>WDTE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>WD Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffff00</resetMask>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CG</name>
|
|
<description>Clock Generator (CG)</description>
|
|
<baseAddress>0x400F3000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x8</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x18</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1c</offset>
|
|
<size>0x20</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3c</offset>
|
|
<size>0x14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x50</offset>
|
|
<size>0x10</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x60</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SYSCR</name>
|
|
<description>System Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GEAR</name>
|
|
<description>GEAR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRCK</name>
|
|
<description>PRCK</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPSEL</name>
|
|
<description>FPSEL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCOSEL</name>
|
|
<description>SCOSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FCSTOP</name>
|
|
<description>FCSTOP</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSCCR</name>
|
|
<description>Oscillation Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x08010430</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WUEON</name>
|
|
<description>WUEON</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WUEF</name>
|
|
<description>WUEF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLON</name>
|
|
<description>PLLON</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WUPSEL1</name>
|
|
<description>WUPSEL1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XEN1</name>
|
|
<description>XEN1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XTEN</name>
|
|
<description>XTEN</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XEN3</name>
|
|
<description>XEN3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DRVOSCH</name>
|
|
<description>DRVOSCH</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DRVOSCL</name>
|
|
<description>DRVOSCL</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WUPTL</name>
|
|
<description>WUPTL</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XEN2</name>
|
|
<description>XEN2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCSEL</name>
|
|
<description>OSCSEL</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EHOSCSEL</name>
|
|
<description>EHOSCSEL</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WUPSEL2</name>
|
|
<description>WUPSEL2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WUPT</name>
|
|
<description>WUPT</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STBYCR</name>
|
|
<description>Standby Control Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STBY</name>
|
|
<description>STBY</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DRVE</name>
|
|
<description>DRVE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PTKEEP</name>
|
|
<description>PTKEEP</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLSEL</name>
|
|
<description>PLL Selection Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PLLSEL</name>
|
|
<description>PLLSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSET</name>
|
|
<description>PLLSET</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCKSTP</name>
|
|
<description>Peripheral Clock Stop Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USBDSTP</name>
|
|
<description>USBDSTP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBHSTP</name>
|
|
<description>USBHSTP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CANSTP</name>
|
|
<description>CANSTP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMSTP</name>
|
|
<description>EMSTP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PROTECT</name>
|
|
<description>Protect Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000c1</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CGPROTECT</name>
|
|
<description>CGPROTECT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMCGA</name>
|
|
<description>CG Interrupt Mode Control Register A</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20202020</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT0EN</name>
|
|
<description>INT0EN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMST0</name>
|
|
<description>EMST0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCG0</name>
|
|
<description>EMCG0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INT1EN</name>
|
|
<description>INT1EN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMST1</name>
|
|
<description>EMST1</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCG1</name>
|
|
<description>EMCG1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INT2EN</name>
|
|
<description>INT2EN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMST2</name>
|
|
<description>EMST2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCG2</name>
|
|
<description>EMCG2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INT3EN</name>
|
|
<description>INT3EN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMST3</name>
|
|
<description>EMST3</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCG3</name>
|
|
<description>EMCG3</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMCGB</name>
|
|
<description>CG Interrupt Mode Control Register B</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20202020</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT4EN</name>
|
|
<description>INT4EN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMST4</name>
|
|
<description>EMST4</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCG4</name>
|
|
<description>EMCG4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INT5EN</name>
|
|
<description>INT5EN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMST5</name>
|
|
<description>EMST5</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCG5</name>
|
|
<description>EMCG5</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INT6EN</name>
|
|
<description>INT6EN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMST6</name>
|
|
<description>EMST6</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCG6</name>
|
|
<description>EMCG6</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INT7EN</name>
|
|
<description>INT7EN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMST7</name>
|
|
<description>EMST7</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCG7</name>
|
|
<description>EMCG7</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMCGC</name>
|
|
<description>CG Interrupt Mode Control Register C</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20202020</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT8EN</name>
|
|
<description>INT8EN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMST8</name>
|
|
<description>EMST8</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCG8</name>
|
|
<description>EMCG8</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INT9EN</name>
|
|
<description>INT9EN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMST9</name>
|
|
<description>EMST9</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCG9</name>
|
|
<description>EMCG9</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTAEN</name>
|
|
<description>INTAEN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMSTA</name>
|
|
<description>EMSTA</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCGA</name>
|
|
<description>EMCGA</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTBEN</name>
|
|
<description>INTBEN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMSTB</name>
|
|
<description>EMSTB</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCGB</name>
|
|
<description>EMCGB</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMCGD</name>
|
|
<description>CG Interrupt Mode Control Register D</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20202020</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTUSBWKUPEN</name>
|
|
<description>INTUSBWKUPEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMSTUSBWKUP</name>
|
|
<description>EMSTUSBWKUP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCGUSBWKUP</name>
|
|
<description>EMCGUSBWKUP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTDEN</name>
|
|
<description>INTDEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMSTD</name>
|
|
<description>EMSTD</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCGD</name>
|
|
<description>EMCGD</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTRTCEN</name>
|
|
<description>INTRTCEN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMSTRTC</name>
|
|
<description>EMSTRTC</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCGRTC</name>
|
|
<description>EMCGRTC</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTRMCRXEN</name>
|
|
<description>INTRMCRXEN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMSTRMCRX</name>
|
|
<description>EMSTRMCRX</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMCGRMCRX</name>
|
|
<description>EMCGRMCRX</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICRCG</name>
|
|
<description>CG Interrupt Request Clear Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICRCG</name>
|
|
<description>ICRCG</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTFLG</name>
|
|
<description>Reset Flag Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PONRSTF</name>
|
|
<description>PONRSTF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINRSTF</name>
|
|
<description>PINRSTF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDTRSTF</name>
|
|
<description>WDTRSTF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP2RSTF</name>
|
|
<description>STOP2RSTF</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBGRSTF</name>
|
|
<description>DBGRSTF</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OFDRSTF</name>
|
|
<description>OFDRSTF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LVDRSTF</name>
|
|
<description>LVDRSTF</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMIFLG</name>
|
|
<description>NMI Flag Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NMIFLG0</name>
|
|
<description>NMIFLG0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NMIFLG1</name>
|
|
<description>NMIFLG1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NMIFLG2</name>
|
|
<description>NMIFLG2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NMIFLG3</name>
|
|
<description>NMIFLG3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USBPLL</name>
|
|
<description>Low Voltage detector control register</description>
|
|
<baseAddress>0x400F3100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>USB PLL Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USBPLLON</name>
|
|
<description>USBPLLON</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EN</name>
|
|
<description>USB PLL Enable Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USBDEN</name>
|
|
<description>USBDEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBHEN</name>
|
|
<description>USBHEN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL</name>
|
|
<description>USB PLL Select Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USBPLLSEL</name>
|
|
<description>USBPLLSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBPLLSET</name>
|
|
<description>USBPLLSET</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TRMOSC</name>
|
|
<description>Low Voltage detector control register</description>
|
|
<baseAddress>0x400F3200</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PRO</name>
|
|
<description>Protection Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PROTECT</name>
|
|
<description>PROTECT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EN</name>
|
|
<description>Enable Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIMEN</name>
|
|
<description>TRIMEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INIT</name>
|
|
<description>Initial Trimming Level Monitor Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffc0f0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIMINITF</name>
|
|
<description>TRIMINITF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIMINITC</name>
|
|
<description>TRIMINITC</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET</name>
|
|
<description>Trimming Level Setting Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIMSETF</name>
|
|
<description>TRIMSETF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIMSETC</name>
|
|
<description>TRIMSETC</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LVD</name>
|
|
<description>Low Voltage detector control register</description>
|
|
<baseAddress>0x400F4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>LVD-RESET Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000021</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVDEN1</name>
|
|
<description>LVDEN1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LVDLVL1</name>
|
|
<description>LVDLVL1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LVDRSTEN</name>
|
|
<description>LVDRSTEN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>LVD-NMI Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVDEN2</name>
|
|
<description>LVDEN2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LVDLVL2</name>
|
|
<description>LVDLVL2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTSEL</name>
|
|
<description>INTSEL</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LVDINTEN</name>
|
|
<description>LVDINTEN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>LVD Status Control Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVDST1</name>
|
|
<description>LVDST1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LVDST2</name>
|
|
<description>LVDST2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MTPD</name>
|
|
<description>16-bit Multi-Purpose Timer (MPT-PMD)</description>
|
|
<baseAddress>0x400F6000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x24</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x24</offset>
|
|
<size>0x4</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x28</offset>
|
|
<size>0x14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x3c</offset>
|
|
<size>0x8</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x44</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MDEN</name>
|
|
<description>PMD Enable Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMEN</name>
|
|
<description>PWMEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PORTMD</name>
|
|
<description>Port Output Mode Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PORTMD</name>
|
|
<description>PORTMD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDCR</name>
|
|
<description>PMD Control Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMMD</name>
|
|
<description>PWMMD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTPRD</name>
|
|
<description>INTPRD</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINT</name>
|
|
<description>PINT</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTYMD</name>
|
|
<description>DTYMD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYNTMD</name>
|
|
<description>SYNTMD</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWMCK</name>
|
|
<description>PWMCK</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTSTA</name>
|
|
<description>PWM Counter Status Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UPDWN</name>
|
|
<description>UPDWN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDCNT</name>
|
|
<description>PWM Counter Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MDCNT</name>
|
|
<description>MDCNT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDPRD</name>
|
|
<description>PWM Period Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MDPRD</name>
|
|
<description>MDPRD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPU</name>
|
|
<description>PWM Compare Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPU</name>
|
|
<description>CMPU</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPV</name>
|
|
<description>PWM Compare Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPV</name>
|
|
<description>CMPV</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPW</name>
|
|
<description>PWM Compare Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPW</name>
|
|
<description>CMPW</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDOUT</name>
|
|
<description>PMD Output Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UOC</name>
|
|
<description>UOC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VOC</name>
|
|
<description>VOC</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WOC</name>
|
|
<description>WOC</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UPWM</name>
|
|
<description>UPWM</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VPWM</name>
|
|
<description>VPWM</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPWM</name>
|
|
<description>WPWM</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDPOT</name>
|
|
<description>PMD Output Setting Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSYNCS</name>
|
|
<description>PSYNCS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POLL</name>
|
|
<description>POLL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POLH</name>
|
|
<description>POLH</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMGREL</name>
|
|
<description>EMG Release Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EMGREL</name>
|
|
<description>EMGREL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMGCR</name>
|
|
<description>EMG Control Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000039</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EMGEN</name>
|
|
<description>EMGEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMGRS</name>
|
|
<description>EMGRS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMGMD</name>
|
|
<description>EMGMD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INHEN</name>
|
|
<description>INHEN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMGCNT</name>
|
|
<description>EMGCNT</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMGSTA</name>
|
|
<description>EMG Status Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xfffffffd</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EMGST</name>
|
|
<description>EMGST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EMGI</name>
|
|
<description>EMGI</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTR</name>
|
|
<description>Dead Time Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTR</name>
|
|
<description>DTR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EN</name>
|
|
<description>Encoder Input (ENC)</description>
|
|
<baseAddress>0x400F7000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TNCR</name>
|
|
<description>Encoder Input Control Register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENDEV</name>
|
|
<description>ENDEV</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>INTEN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NR</name>
|
|
<description>NR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENRUN</name>
|
|
<description>ENRUN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ZEN</name>
|
|
<description>ZEN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMPEN</name>
|
|
<description>CMPEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ZESEL</name>
|
|
<description>ZESEL</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENCLR</name>
|
|
<description>ENCLR</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SFTCAP</name>
|
|
<description>SFTCAP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ZDET</name>
|
|
<description>ZDET</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UD</name>
|
|
<description>UD</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REVERR</name>
|
|
<description>REVERR</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMP</name>
|
|
<description>CMP</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>P3EN</name>
|
|
<description>P3EN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>MODE</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RELOAD</name>
|
|
<description>Encoder Counter Reload Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>RELOAD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT</name>
|
|
<description>Encoder Compare Register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT</name>
|
|
<description>INT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Encoder Counter Register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>CNT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FC</name>
|
|
<description>Flash Control (FC)</description>
|
|
<baseAddress>0x41FFF000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x10</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x14</offset>
|
|
<size>0xc</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SECBIT</name>
|
|
<description>FC Security Bit Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SECBIT</name>
|
|
<description>SECBIT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLCS</name>
|
|
<description>FC Flash Control Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xffffffffffff0001</resetValue>
|
|
<resetMask>0xffffffff</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDY_BSY</name>
|
|
<description>RDY_BSY</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BLPRO</name>
|
|
<description>BLPRO</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|