34785 lines
1.3 MiB
34785 lines
1.3 MiB
<?xml version="1.0" encoding="UTF-8"?>
|
|
|
|
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
|
|
<vendor>Texas Instruments</vendor>
|
|
<vendorID>ti.com</vendorID>
|
|
<name>MSP432E401Y</name>
|
|
<series>MSP432E4</series>
|
|
<version>3.200</version>
|
|
<description>ARM Cortex-M4 MSP432E4 Device</description>
|
|
<licenseText>
|
|
\n
|
|
Software License Agreement\n
|
|
\n
|
|
Texas Instruments (TI) is supplying this software for use solely and\n
|
|
exclusively on TI's microcontroller products. The software is owned by\n
|
|
TI and/or its suppliers, and is protected under applicable copyright\n
|
|
laws. You may not combine this software with "viral" open-source\n
|
|
software in order to form a larger program.\n
|
|
\n
|
|
THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.\n
|
|
NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT\n
|
|
NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n
|
|
A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY\n
|
|
CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL\n
|
|
DAMAGES, FOR ANY REASON WHATSOEVER.\n
|
|
\n
|
|
</licenseText>
|
|
<cpu>
|
|
<name>CM4</name>
|
|
<revision>r1p2</revision>
|
|
<endian>little</endian>
|
|
<mpuPresent>false</mpuPresent>
|
|
<fpuPresent>true</fpuPresent>
|
|
<nvicPrioBits>3</nvicPrioBits>
|
|
<vendorSystickConfig>false</vendorSystickConfig>
|
|
</cpu>
|
|
<addressUnitBits>8</addressUnitBits>
|
|
<width>32</width>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<peripherals>
|
|
<peripheral>
|
|
<name>WATCHDOG0</name>
|
|
<description>Register map for WATCHDOG0 peripheral</description>
|
|
<groupName>WATCHDOG</groupName>
|
|
<prependToName>WATCHDOG0</prependToName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>WATCHDOG0</name><value>18</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>LOAD</name>
|
|
<description>Watchdog Load</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_LOAD</name>
|
|
<description>Watchdog Load Value</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VALUE</name>
|
|
<description>Watchdog Value</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_VALUE</name>
|
|
<description>Watchdog Value</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>Watchdog Control</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_CTL_INTEN</name>
|
|
<description>Watchdog Interrupt Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTL_RESEN</name>
|
|
<description>Watchdog Reset Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTL_INTTYPE</name>
|
|
<description>Watchdog Interrupt Type</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTL_WRC</name>
|
|
<description>Write Complete</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>Watchdog Interrupt Clear</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_ICR</name>
|
|
<description>Watchdog Interrupt Clear</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>Watchdog Raw Interrupt Status</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_RIS_WDTRIS</name>
|
|
<description>Watchdog Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>Watchdog Masked Interrupt Status</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_MIS_WDTMIS</name>
|
|
<description>Watchdog Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEST</name>
|
|
<description>Watchdog Test</description>
|
|
<addressOffset>0x00000418</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_TEST_STALL</name>
|
|
<description>Watchdog Stall Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<description>Watchdog Lock</description>
|
|
<addressOffset>0x00000C00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_LOCK</name>
|
|
<description>Watchdog Lock</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDT_LOCK_UNLOCKED</name>
|
|
<description>Unlocked</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDT_LOCK_LOCKED</name>
|
|
<description>Locked</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="WATCHDOG0">
|
|
<name>WATCHDOG1</name>
|
|
<prependToName>WATCHDOG1</prependToName>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SSI0</name>
|
|
<description>Register map for SSI0 peripheral</description>
|
|
<groupName>SSI</groupName>
|
|
<prependToName>SSI0</prependToName>
|
|
<baseAddress>0x40008000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>SSI0</name><value>7</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>SSI Control 0</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_CR0_DSS</name>
|
|
<description>SSI Data Size Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_4</name>
|
|
<description>4-bit data</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_5</name>
|
|
<description>5-bit data</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_6</name>
|
|
<description>6-bit data</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_7</name>
|
|
<description>7-bit data</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_8</name>
|
|
<description>8-bit data</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_9</name>
|
|
<description>9-bit data</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_10</name>
|
|
<description>10-bit data</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_11</name>
|
|
<description>11-bit data</description>
|
|
<value>0xa</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_12</name>
|
|
<description>12-bit data</description>
|
|
<value>0xb</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_13</name>
|
|
<description>13-bit data</description>
|
|
<value>0xc</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_14</name>
|
|
<description>14-bit data</description>
|
|
<value>0xd</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_15</name>
|
|
<description>15-bit data</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_DSS_16</name>
|
|
<description>16-bit data</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR0_FRF</name>
|
|
<description>SSI Frame Format Select</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_FRF_MOTO</name>
|
|
<description>Freescale SPI Frame Format</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR0_FRF_TI</name>
|
|
<description>Synchronous Serial Frame Format</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR0_SPO</name>
|
|
<description>SSI Serial Clock Polarity</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR0_SPH</name>
|
|
<description>SSI Serial Clock Phase</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR0_SCR</name>
|
|
<description>SSI Serial Clock Rate</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>SSI Control 1</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_CR1_LBM</name>
|
|
<description>SSI Loopback Mode</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR1_SSE</name>
|
|
<description>SSI Synchronous Serial Port Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR1_MS</name>
|
|
<description>SSI Master/Slave Select</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR1_EOT</name>
|
|
<description>End of Transmission</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR1_MODE</name>
|
|
<description>SSI Mode</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSI_CR1_MODE_LEGACY</name>
|
|
<description>Legacy SSI mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR1_MODE_BI</name>
|
|
<description>Bi-SSI mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR1_MODE_QUAD</name>
|
|
<description>Quad-SSI Mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CR1_MODE_ADVANCED</name>
|
|
<description>Advanced SSI Mode with 8-bit packet size</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR1_DIR</name>
|
|
<description>SSI Direction of Operation</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR1_HSCLKEN</name>
|
|
<description>High Speed Clock Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR1_FSSHLDFRM</name>
|
|
<description>FSS Hold Frame</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_CR1_EOM</name>
|
|
<description>Stop Frame (End of Message)</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>SSI Data</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_DR_DATA</name>
|
|
<description>SSI Receive/Transmit Data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>SSI Status</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_SR_TFE</name>
|
|
<description>SSI Transmit FIFO Empty</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_SR_TNF</name>
|
|
<description>SSI Transmit FIFO Not Full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_SR_RNE</name>
|
|
<description>SSI Receive FIFO Not Empty</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_SR_RFF</name>
|
|
<description>SSI Receive FIFO Full</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_SR_BSY</name>
|
|
<description>SSI Busy Bit</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPSR</name>
|
|
<description>SSI Clock Prescale</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_CPSR_CPSDVSR</name>
|
|
<description>SSI Clock Prescale Divisor</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IM</name>
|
|
<description>SSI Interrupt Mask</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_IM_RORIM</name>
|
|
<description>SSI Receive Overrun Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_IM_RTIM</name>
|
|
<description>SSI Receive Time-Out Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_IM_RXIM</name>
|
|
<description>SSI Receive FIFO Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_IM_TXIM</name>
|
|
<description>SSI Transmit FIFO Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_IM_DMARXIM</name>
|
|
<description>SSI Receive DMA Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_IM_DMATXIM</name>
|
|
<description>SSI Transmit DMA Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_IM_EOTIM</name>
|
|
<description>End of Transmit Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>SSI Raw Interrupt Status</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_RIS_RORRIS</name>
|
|
<description>SSI Receive Overrun Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_RIS_RTRIS</name>
|
|
<description>SSI Receive Time-Out Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_RIS_RXRIS</name>
|
|
<description>SSI Receive FIFO Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_RIS_TXRIS</name>
|
|
<description>SSI Transmit FIFO Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_RIS_DMARXRIS</name>
|
|
<description>SSI Receive DMA Raw Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_RIS_DMATXRIS</name>
|
|
<description>SSI Transmit DMA Raw Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_RIS_EOTRIS</name>
|
|
<description>End of Transmit Raw Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>SSI Masked Interrupt Status</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_MIS_RORMIS</name>
|
|
<description>SSI Receive Overrun Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_MIS_RTMIS</name>
|
|
<description>SSI Receive Time-Out Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_MIS_RXMIS</name>
|
|
<description>SSI Receive FIFO Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_MIS_TXMIS</name>
|
|
<description>SSI Transmit FIFO Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_MIS_DMARXMIS</name>
|
|
<description>SSI Receive DMA Masked Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_MIS_DMATXMIS</name>
|
|
<description>SSI Transmit DMA Masked Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_MIS_EOTMIS</name>
|
|
<description>End of Transmit Masked Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>SSI Interrupt Clear</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_ICR_RORIC</name>
|
|
<description>SSI Receive Overrun Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSI_ICR_RTIC</name>
|
|
<description>SSI Receive Time-Out Interrupt Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSI_ICR_DMARXIC</name>
|
|
<description>SSI Receive DMA Interrupt Clear</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSI_ICR_DMATXIC</name>
|
|
<description>SSI Transmit DMA Interrupt Clear</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSI_ICR_EOTIC</name>
|
|
<description>End of Transmit Interrupt Clear</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACTL</name>
|
|
<description>SSI DMA Control</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_DMACTL_RXDMAE</name>
|
|
<description>Receive DMA Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_DMACTL_TXDMAE</name>
|
|
<description>Transmit DMA Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>SSI Peripheral Properties</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_PP_HSCLK</name>
|
|
<description>High Speed Capability</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_PP_MODE</name>
|
|
<description>Mode of Operation</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSI_PP_MODE_LEGACY</name>
|
|
<description>Legacy SSI mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_PP_MODE_ADVBI</name>
|
|
<description>Legacy mode, Advanced SSI mode and Bi-SSI mode enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_PP_MODE_ADVBIQUAD</name>
|
|
<description>Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode enabled</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSI_PP_FSSHLDFRM</name>
|
|
<description>FSS Hold Frame Capability</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC</name>
|
|
<description>SSI Clock Configuration</description>
|
|
<addressOffset>0x00000FC8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_CC_CS</name>
|
|
<description>SSI Baud Clock Source</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSI_CC_CS_SYSPLL</name>
|
|
<description>System clock (based on clock source and divisor factor)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSI_CC_CS_PIOSC</name>
|
|
<description>PIOSC</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SSI0">
|
|
<name>SSI1</name>
|
|
<prependToName>SSI1</prependToName>
|
|
<baseAddress>0x40009000</baseAddress>
|
|
<interrupt><name>SSI1</name><value>34</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SSI0">
|
|
<name>SSI2</name>
|
|
<prependToName>SSI2</prependToName>
|
|
<baseAddress>0x4000A000</baseAddress>
|
|
<interrupt><name>SSI2</name><value>54</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SSI0">
|
|
<name>SSI3</name>
|
|
<prependToName>SSI3</prependToName>
|
|
<baseAddress>0x4000B000</baseAddress>
|
|
<interrupt><name>SSI3</name><value>55</value></interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART0</name>
|
|
<description>Register map for UART0 peripheral</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART0</prependToName>
|
|
<baseAddress>0x4000C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>UART0</name><value>5</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>UART Data</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_DR_DATA</name>
|
|
<description>Data Transmitted or Received</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_DR_FE</name>
|
|
<description>UART Framing Error</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_DR_PE</name>
|
|
<description>UART Parity Error</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_DR_BE</name>
|
|
<description>UART Break Error</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_DR_OE</name>
|
|
<description>UART Overrun Error</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSR</name>
|
|
<description>UART Receive Status/Error Clear</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_RSR_FE</name>
|
|
<description>UART Framing Error</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RSR_PE</name>
|
|
<description>UART Parity Error</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RSR_BE</name>
|
|
<description>UART Break Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RSR_OE</name>
|
|
<description>UART Overrun Error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECR</name>
|
|
<description>UART Receive Status/Error Clear</description>
|
|
<alternateGroup>UART_ALT</alternateGroup>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_ECR_DATA</name>
|
|
<description>Error Clear</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR</name>
|
|
<description>UART Flag</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_FR_CTS</name>
|
|
<description>Clear To Send</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_DSR</name>
|
|
<description>Data Set Ready</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_DCD</name>
|
|
<description>Data Carrier Detect</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_BUSY</name>
|
|
<description>UART Busy</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_RXFE</name>
|
|
<description>UART Receive FIFO Empty</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_TXFF</name>
|
|
<description>UART Transmit FIFO Full</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_RXFF</name>
|
|
<description>UART Receive FIFO Full</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_TXFE</name>
|
|
<description>UART Transmit FIFO Empty</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_RI</name>
|
|
<description>Ring Indicator</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ILPR</name>
|
|
<description>UART IrDA Low-Power Register</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_ILPR_ILPDVSR</name>
|
|
<description>IrDA Low-Power Divisor</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IBRD</name>
|
|
<description>UART Integer Baud-Rate Divisor</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_IBRD_DIVINT</name>
|
|
<description>Integer Baud-Rate Divisor</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FBRD</name>
|
|
<description>UART Fractional Baud-Rate Divisor</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_FBRD_DIVFRAC</name>
|
|
<description>Fractional Baud-Rate Divisor</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCRH</name>
|
|
<description>UART Line Control</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_LCRH_BRK</name>
|
|
<description>UART Send Break</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_PEN</name>
|
|
<description>UART Parity Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_EPS</name>
|
|
<description>UART Even Parity Select</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_STP2</name>
|
|
<description>UART Two Stop Bits Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_FEN</name>
|
|
<description>UART Enable FIFOs</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_WLEN</name>
|
|
<description>UART Word Length</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART_LCRH_WLEN_5</name>
|
|
<description>5 bits (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_LCRH_WLEN_6</name>
|
|
<description>6 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_LCRH_WLEN_7</name>
|
|
<description>7 bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_LCRH_WLEN_8</name>
|
|
<description>8 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_SPS</name>
|
|
<description>UART Stick Parity Select</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>UART Control</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_CTL_UARTEN</name>
|
|
<description>UART Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_SIREN</name>
|
|
<description>UART SIR Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_SIRLP</name>
|
|
<description>UART SIR Low-Power Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_SMART</name>
|
|
<description>ISO 7816 Smart Card Support</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_EOT</name>
|
|
<description>End of Transmission</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_HSE</name>
|
|
<description>High-Speed Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_LBE</name>
|
|
<description>UART Loop Back Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_TXE</name>
|
|
<description>UART Transmit Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_RXE</name>
|
|
<description>UART Receive Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_DTR</name>
|
|
<description>Data Terminal Ready</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_RTS</name>
|
|
<description>Request to Send</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_RTSEN</name>
|
|
<description>Enable Request to Send</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_CTSEN</name>
|
|
<description>Enable Clear To Send</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFLS</name>
|
|
<description>UART Interrupt FIFO Level Select</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_IFLS_TX</name>
|
|
<description>UART Transmit Interrupt FIFO Level Select</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_TX1_8</name>
|
|
<description>TX FIFO &lt;= 1/8 full</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_TX2_8</name>
|
|
<description>TX FIFO &lt;= 1/4 full</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_TX4_8</name>
|
|
<description>TX FIFO &lt;= 1/2 full (default)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_TX6_8</name>
|
|
<description>TX FIFO &lt;= 3/4 full</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_TX7_8</name>
|
|
<description>TX FIFO &lt;= 7/8 full</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART_IFLS_RX</name>
|
|
<description>UART Receive Interrupt FIFO Level Select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_RX1_8</name>
|
|
<description>RX FIFO >= 1/8 full</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_RX2_8</name>
|
|
<description>RX FIFO >= 1/4 full</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_RX4_8</name>
|
|
<description>RX FIFO >= 1/2 full (default)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_RX6_8</name>
|
|
<description>RX FIFO >= 3/4 full</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_RX7_8</name>
|
|
<description>RX FIFO >= 7/8 full</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IM</name>
|
|
<description>UART Interrupt Mask</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_IM_RIMIM</name>
|
|
<description>UART Ring Indicator Modem Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_CTSMIM</name>
|
|
<description>UART Clear to Send Modem Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_DCDMIM</name>
|
|
<description>UART Data Carrier Detect Modem Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_DSRMIM</name>
|
|
<description>UART Data Set Ready Modem Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_RXIM</name>
|
|
<description>UART Receive Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_TXIM</name>
|
|
<description>UART Transmit Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_RTIM</name>
|
|
<description>UART Receive Time-Out Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_FEIM</name>
|
|
<description>UART Framing Error Interrupt Mask</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_PEIM</name>
|
|
<description>UART Parity Error Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_BEIM</name>
|
|
<description>UART Break Error Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_OEIM</name>
|
|
<description>UART Overrun Error Interrupt Mask</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_EOTIM</name>
|
|
<description>End of Transmission Interrupt Mask</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_9BITIM</name>
|
|
<description>9-Bit Mode Interrupt Mask</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_DMARXIM</name>
|
|
<description>Receive DMA Interrupt Mask</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_DMATXIM</name>
|
|
<description>Transmit DMA Interrupt Mask</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>UART Raw Interrupt Status</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_RIS_RIRIS</name>
|
|
<description>UART Ring Indicator Modem Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_CTSRIS</name>
|
|
<description>UART Clear to Send Modem Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_DCDRIS</name>
|
|
<description>UART Data Carrier Detect Modem Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_DSRRIS</name>
|
|
<description>UART Data Set Ready Modem Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_RXRIS</name>
|
|
<description>UART Receive Raw Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_TXRIS</name>
|
|
<description>UART Transmit Raw Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_RTRIS</name>
|
|
<description>UART Receive Time-Out Raw Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_FERIS</name>
|
|
<description>UART Framing Error Raw Interrupt Status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_PERIS</name>
|
|
<description>UART Parity Error Raw Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_BERIS</name>
|
|
<description>UART Break Error Raw Interrupt Status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_OERIS</name>
|
|
<description>UART Overrun Error Raw Interrupt Status</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_EOTRIS</name>
|
|
<description>End of Transmission Raw Interrupt Status</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_9BITRIS</name>
|
|
<description>9-Bit Mode Raw Interrupt Status</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_DMARXRIS</name>
|
|
<description>Receive DMA Raw Interrupt Status</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_DMATXRIS</name>
|
|
<description>Transmit DMA Raw Interrupt Status</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>UART Masked Interrupt Status</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_MIS_RIMIS</name>
|
|
<description>UART Ring Indicator Modem Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_CTSMIS</name>
|
|
<description>UART Clear to Send Modem Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_DCDMIS</name>
|
|
<description>UART Data Carrier Detect Modem Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_DSRMIS</name>
|
|
<description>UART Data Set Ready Modem Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_RXMIS</name>
|
|
<description>UART Receive Masked Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_TXMIS</name>
|
|
<description>UART Transmit Masked Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_RTMIS</name>
|
|
<description>UART Receive Time-Out Masked Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_FEMIS</name>
|
|
<description>UART Framing Error Masked Interrupt Status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_PEMIS</name>
|
|
<description>UART Parity Error Masked Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_BEMIS</name>
|
|
<description>UART Break Error Masked Interrupt Status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_OEMIS</name>
|
|
<description>UART Overrun Error Masked Interrupt Status</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_EOTMIS</name>
|
|
<description>End of Transmission Masked Interrupt Status</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_9BITMIS</name>
|
|
<description>9-Bit Mode Masked Interrupt Status</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_DMARXMIS</name>
|
|
<description>Receive DMA Masked Interrupt Status</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_DMATXMIS</name>
|
|
<description>Transmit DMA Masked Interrupt Status</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>UART Interrupt Clear</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UART_ICR_RIMIC</name>
|
|
<description>UART Ring Indicator Modem Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_CTSMIC</name>
|
|
<description>UART Clear to Send Modem Interrupt Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_DCDMIC</name>
|
|
<description>UART Data Carrier Detect Modem Interrupt Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_DSRMIC</name>
|
|
<description>UART Data Set Ready Modem Interrupt Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_RXIC</name>
|
|
<description>Receive Interrupt Clear</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_TXIC</name>
|
|
<description>Transmit Interrupt Clear</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_RTIC</name>
|
|
<description>Receive Time-Out Interrupt Clear</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_FEIC</name>
|
|
<description>Framing Error Interrupt Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_PEIC</name>
|
|
<description>Parity Error Interrupt Clear</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_BEIC</name>
|
|
<description>Break Error Interrupt Clear</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_OEIC</name>
|
|
<description>Overrun Error Interrupt Clear</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_EOTIC</name>
|
|
<description>End of Transmission Interrupt Clear</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_9BITIC</name>
|
|
<description>9-Bit Mode Interrupt Clear</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_DMARXIC</name>
|
|
<description>Receive DMA Interrupt Clear</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_DMATXIC</name>
|
|
<description>Transmit DMA Interrupt Clear</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACTL</name>
|
|
<description>UART DMA Control</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_DMACTL_RXDMAE</name>
|
|
<description>Receive DMA Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_DMACTL_TXDMAE</name>
|
|
<description>Transmit DMA Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_DMACTL_DMAERR</name>
|
|
<description>DMA on Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_9BITADDR</name>
|
|
<description>UART 9-Bit Self Address</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_9BITADDR_ADDR</name>
|
|
<description>Self Address for 9-Bit Mode</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_9BITADDR_9BITEN</name>
|
|
<description>Enable 9-Bit Mode</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_9BITAMASK</name>
|
|
<description>UART 9-Bit Self Address Mask</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_9BITAMASK_MASK</name>
|
|
<description>Self Address Mask for 9-Bit Mode</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>UART Peripheral Properties</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_PP_SC</name>
|
|
<description>Smart Card Support</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_PP_NB</name>
|
|
<description>9-Bit Support</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_PP_MS</name>
|
|
<description>Modem Support</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_PP_MSE</name>
|
|
<description>Modem Support Extended</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC</name>
|
|
<description>UART Clock Configuration</description>
|
|
<addressOffset>0x00000FC8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_CC_CS</name>
|
|
<description>UART Baud Clock Source</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART_CC_CS_SYSCLK</name>
|
|
<description>System clock (based on clock source and divisor factor)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_CC_CS_PIOSC</name>
|
|
<description>PIOSC</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART1</name>
|
|
<prependToName>UART1</prependToName>
|
|
<baseAddress>0x4000D000</baseAddress>
|
|
<interrupt><name>UART1</name><value>6</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART2</name>
|
|
<prependToName>UART2</prependToName>
|
|
<baseAddress>0x4000E000</baseAddress>
|
|
<interrupt><name>UART2</name><value>33</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART3</name>
|
|
<prependToName>UART3</prependToName>
|
|
<baseAddress>0x4000F000</baseAddress>
|
|
<interrupt><name>UART3</name><value>56</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART4</name>
|
|
<prependToName>UART4</prependToName>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<interrupt><name>UART4</name><value>57</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART5</name>
|
|
<prependToName>UART5</prependToName>
|
|
<baseAddress>0x40011000</baseAddress>
|
|
<interrupt><name>UART5</name><value>58</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART6</name>
|
|
<prependToName>UART6</prependToName>
|
|
<baseAddress>0x40012000</baseAddress>
|
|
<interrupt><name>UART6</name><value>59</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART7</name>
|
|
<prependToName>UART7</prependToName>
|
|
<baseAddress>0x40013000</baseAddress>
|
|
<interrupt><name>UART7</name><value>60</value></interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C0</name>
|
|
<description>Register map for I2C0 peripheral</description>
|
|
<groupName>I2C</groupName>
|
|
<prependToName>I2C0</prependToName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>I2C0</name><value>8</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MSA</name>
|
|
<description>I2C Master Slave Address</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MSA_RS</name>
|
|
<description>Receive not send</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MSA_SA</name>
|
|
<description>I2C Slave Address</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCS</name>
|
|
<description>I2C Master Control/Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MCS_RUN</name>
|
|
<description>I2C Master Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_START</name>
|
|
<description>Generate START</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_ADRACK</name>
|
|
<description>Acknowledge Address</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_ACK</name>
|
|
<description>Data Acknowledge Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_ARBLST</name>
|
|
<description>Arbitration Lost</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_IDLE</name>
|
|
<description>I2C Idle</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_BURST</name>
|
|
<description>Burst Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_CLKTO</name>
|
|
<description>Clock Timeout Error</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_ACTDMATX</name>
|
|
<description>DMA TX Active Status</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_ACTDMARX</name>
|
|
<description>DMA RX Active Status</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCS</name>
|
|
<description>I2C Master Control/Status</description>
|
|
<alternateGroup>I2C0_ALT</alternateGroup>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MCS_BUSY</name>
|
|
<description>I2C Busy</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_STOP</name>
|
|
<description>Generate STOP</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_DATACK</name>
|
|
<description>Acknowledge Data</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_HS</name>
|
|
<description>High-Speed Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_QCMD</name>
|
|
<description>Quick Command</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_BUSBSY</name>
|
|
<description>Bus Busy</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDR</name>
|
|
<description>I2C Master Data</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MDR_DATA</name>
|
|
<description>This byte contains the data transferred during a transaction</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MTPR</name>
|
|
<description>I2C Master Timer Period</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MTPR_TPR</name>
|
|
<description>Timer Period</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MTPR_HS</name>
|
|
<description>High-Speed Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MTPR_PULSEL</name>
|
|
<description>Glitch Suppression Pulse Width</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>I2C_MTPR_PULSEL_BYPASS</name>
|
|
<description>Bypass</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MTPR_PULSEL_1</name>
|
|
<description>1 clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MTPR_PULSEL_2</name>
|
|
<description>2 clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MTPR_PULSEL_3</name>
|
|
<description>3 clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MTPR_PULSEL_4</name>
|
|
<description>4 clocks</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MTPR_PULSEL_8</name>
|
|
<description>8 clocks</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MTPR_PULSEL_16</name>
|
|
<description>16 clocks</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C_MTPR_PULSEL_31</name>
|
|
<description>31 clocks</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIMR</name>
|
|
<description>I2C Master Interrupt Mask</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MIMR_IM</name>
|
|
<description>Master Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MIMR_CLKIM</name>
|
|
<description>Clock Timeout Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MIMR_DMARXIM</name>
|
|
<description>Receive DMA Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MIMR_DMATXIM</name>
|
|
<description>Transmit DMA Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MIMR_NACKIM</name>
|
|
<description>Address/Data NACK Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MIMR_STARTIM</name>
|
|
<description>START Detection Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MIMR_STOPIM</name>
|
|
<description>STOP Detection Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MIMR_ARBLOSTIM</name>
|
|
<description>Arbitration Lost Interrupt Mask</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MIMR_TXIM</name>
|
|
<description>Transmit FIFO Request Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MIMR_RXIM</name>
|
|
<description>Receive FIFO Request Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MIMR_TXFEIM</name>
|
|
<description>Transmit FIFO Empty Interrupt Mask</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MIMR_RXFFIM</name>
|
|
<description>Receive FIFO Full Interrupt Mask</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MRIS</name>
|
|
<description>I2C Master Raw Interrupt Status</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MRIS_RIS</name>
|
|
<description>Master Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MRIS_CLKRIS</name>
|
|
<description>Clock Timeout Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MRIS_DMARXRIS</name>
|
|
<description>Receive DMA Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MRIS_DMATXRIS</name>
|
|
<description>Transmit DMA Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MRIS_NACKRIS</name>
|
|
<description>Address/Data NACK Raw Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MRIS_STARTRIS</name>
|
|
<description>START Detection Raw Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MRIS_STOPRIS</name>
|
|
<description>STOP Detection Raw Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MRIS_ARBLOSTRIS</name>
|
|
<description>Arbitration Lost Raw Interrupt Status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MRIS_TXRIS</name>
|
|
<description>Transmit Request Raw Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MRIS_RXRIS</name>
|
|
<description>Receive FIFO Request Raw Interrupt Status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MRIS_TXFERIS</name>
|
|
<description>Transmit FIFO Empty Raw Interrupt Status</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MRIS_RXFFRIS</name>
|
|
<description>Receive FIFO Full Raw Interrupt Status</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMIS</name>
|
|
<description>I2C Master Masked Interrupt Status</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MMIS_MIS</name>
|
|
<description>Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MMIS_CLKMIS</name>
|
|
<description>Clock Timeout Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MMIS_DMARXMIS</name>
|
|
<description>Receive DMA Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MMIS_DMATXMIS</name>
|
|
<description>Transmit DMA Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MMIS_NACKMIS</name>
|
|
<description>Address/Data NACK Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MMIS_STARTMIS</name>
|
|
<description>START Detection Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MMIS_STOPMIS</name>
|
|
<description>STOP Detection Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MMIS_ARBLOSTMIS</name>
|
|
<description>Arbitration Lost Interrupt Mask</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MMIS_TXMIS</name>
|
|
<description>Transmit Request Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MMIS_RXMIS</name>
|
|
<description>Receive FIFO Request Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MMIS_TXFEMIS</name>
|
|
<description>Transmit FIFO Empty Interrupt Mask</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MMIS_RXFFMIS</name>
|
|
<description>Receive FIFO Full Interrupt Mask</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MICR</name>
|
|
<description>I2C Master Interrupt Clear</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MICR_IC</name>
|
|
<description>Master Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MICR_CLKIC</name>
|
|
<description>Clock Timeout Interrupt Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MICR_DMARXIC</name>
|
|
<description>Receive DMA Interrupt Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MICR_DMATXIC</name>
|
|
<description>Transmit DMA Interrupt Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MICR_NACKIC</name>
|
|
<description>Address/Data NACK Interrupt Clear</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MICR_STARTIC</name>
|
|
<description>START Detection Interrupt Clear</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MICR_STOPIC</name>
|
|
<description>STOP Detection Interrupt Clear</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MICR_ARBLOSTIC</name>
|
|
<description>Arbitration Lost Interrupt Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MICR_TXIC</name>
|
|
<description>Transmit FIFO Request Interrupt Clear</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MICR_RXIC</name>
|
|
<description>Receive FIFO Request Interrupt Clear</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MICR_TXFEIC</name>
|
|
<description>Transmit FIFO Empty Interrupt Clear</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MICR_RXFFIC</name>
|
|
<description>Receive FIFO Full Interrupt Clear</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>I2C Master Configuration</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MCR_LPBK</name>
|
|
<description>I2C Loopback</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCR_MFE</name>
|
|
<description>I2C Master Function Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCR_SFE</name>
|
|
<description>I2C Slave Function Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCLKOCNT</name>
|
|
<description>I2C Master Clock Low Timeout Count</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MCLKOCNT_CNTL</name>
|
|
<description>I2C Master Count</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MBMON</name>
|
|
<description>I2C Master Bus Monitor</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MBMON_SCL</name>
|
|
<description>I2C SCL Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MBMON_SDA</name>
|
|
<description>I2C SDA Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MBLEN</name>
|
|
<description>I2C Master Burst Length</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MBLEN_CNTL</name>
|
|
<description>I2C Burst Length</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MBCNT</name>
|
|
<description>I2C Master Burst Count</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MBCNT_CNTL</name>
|
|
<description>I2C Master Burst Count</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOAR</name>
|
|
<description>I2C Slave Own Address</description>
|
|
<addressOffset>0x00000800</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SOAR_OAR</name>
|
|
<description>I2C Slave Own Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCSR</name>
|
|
<description>I2C Slave Control/Status</description>
|
|
<addressOffset>0x00000804</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SCSR_RREQ</name>
|
|
<description>Receive Request</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SCSR_TXFIFO</name>
|
|
<description>TX FIFO Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SCSR_FBR</name>
|
|
<description>First Byte Received</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SCSR_OAR2SEL</name>
|
|
<description>OAR2 Address Matched</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SCSR_QCMDST</name>
|
|
<description>Quick Command Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SCSR_QCMDRW</name>
|
|
<description>Quick Command Read / Write</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SCSR_ACTDMATX</name>
|
|
<description>DMA TX Active Status</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SCSR_ACTDMARX</name>
|
|
<description>DMA RX Active Status</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCSR</name>
|
|
<description>I2C Slave Control/Status</description>
|
|
<alternateGroup>I2C0_ALT</alternateGroup>
|
|
<addressOffset>0x00000804</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SCSR_DA</name>
|
|
<description>Device Active</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SCSR_TREQ</name>
|
|
<description>Transmit Request</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SCSR_RXFIFO</name>
|
|
<description>RX FIFO Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDR</name>
|
|
<description>I2C Slave Data</description>
|
|
<addressOffset>0x00000808</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SDR_DATA</name>
|
|
<description>Data for Transfer</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIMR</name>
|
|
<description>I2C Slave Interrupt Mask</description>
|
|
<addressOffset>0x0000080C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SIMR_DATAIM</name>
|
|
<description>Data Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SIMR_STARTIM</name>
|
|
<description>Start Condition Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SIMR_STOPIM</name>
|
|
<description>Stop Condition Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SIMR_DMARXIM</name>
|
|
<description>Receive DMA Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SIMR_DMATXIM</name>
|
|
<description>Transmit DMA Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SIMR_TXIM</name>
|
|
<description>Transmit FIFO Request Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SIMR_RXIM</name>
|
|
<description>Receive FIFO Request Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SIMR_TXFEIM</name>
|
|
<description>Transmit FIFO Empty Interrupt Mask</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SIMR_RXFFIM</name>
|
|
<description>Receive FIFO Full Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRIS</name>
|
|
<description>I2C Slave Raw Interrupt Status</description>
|
|
<addressOffset>0x00000810</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SRIS_DATARIS</name>
|
|
<description>Data Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SRIS_STARTRIS</name>
|
|
<description>Start Condition Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SRIS_STOPRIS</name>
|
|
<description>Stop Condition Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SRIS_DMARXRIS</name>
|
|
<description>Receive DMA Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SRIS_DMATXRIS</name>
|
|
<description>Transmit DMA Raw Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SRIS_TXRIS</name>
|
|
<description>Transmit Request Raw Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SRIS_RXRIS</name>
|
|
<description>Receive FIFO Request Raw Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SRIS_TXFERIS</name>
|
|
<description>Transmit FIFO Empty Raw Interrupt Status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SRIS_RXFFRIS</name>
|
|
<description>Receive FIFO Full Raw Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMIS</name>
|
|
<description>I2C Slave Masked Interrupt Status</description>
|
|
<addressOffset>0x00000814</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SMIS_DATAMIS</name>
|
|
<description>Data Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SMIS_STARTMIS</name>
|
|
<description>Start Condition Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SMIS_STOPMIS</name>
|
|
<description>Stop Condition Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SMIS_DMARXMIS</name>
|
|
<description>Receive DMA Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SMIS_DMATXMIS</name>
|
|
<description>Transmit DMA Masked Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SMIS_TXMIS</name>
|
|
<description>Transmit FIFO Request Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SMIS_RXMIS</name>
|
|
<description>Receive FIFO Request Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SMIS_TXFEMIS</name>
|
|
<description>Transmit FIFO Empty Interrupt Mask</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SMIS_RXFFMIS</name>
|
|
<description>Receive FIFO Full Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SICR</name>
|
|
<description>I2C Slave Interrupt Clear</description>
|
|
<addressOffset>0x00000818</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SICR_DATAIC</name>
|
|
<description>Data Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SICR_STARTIC</name>
|
|
<description>Start Condition Interrupt Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SICR_STOPIC</name>
|
|
<description>Stop Condition Interrupt Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SICR_DMARXIC</name>
|
|
<description>Receive DMA Interrupt Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SICR_DMATXIC</name>
|
|
<description>Transmit DMA Interrupt Clear</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SICR_TXIC</name>
|
|
<description>Transmit Request Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SICR_RXIC</name>
|
|
<description>Receive Request Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SICR_TXFEIC</name>
|
|
<description>Transmit FIFO Empty Interrupt Mask</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SICR_RXFFIC</name>
|
|
<description>Receive FIFO Full Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOAR2</name>
|
|
<description>I2C Slave Own Address 2</description>
|
|
<addressOffset>0x0000081C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SOAR2_OAR2</name>
|
|
<description>I2C Slave Own Address 2</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SOAR2_OAR2EN</name>
|
|
<description>I2C Slave Own Address 2 Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SACKCTL</name>
|
|
<description>I2C Slave ACK Control</description>
|
|
<addressOffset>0x00000820</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SACKCTL_ACKOEN</name>
|
|
<description>I2C Slave ACK Override Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SACKCTL_ACKOVAL</name>
|
|
<description>I2C Slave ACK Override Value</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFODATA</name>
|
|
<description>I2C FIFO Data</description>
|
|
<addressOffset>0x00000F00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_FIFODATA_DATA</name>
|
|
<description>I2C TX FIFO Write Data Byte</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOCTL</name>
|
|
<description>I2C FIFO Control</description>
|
|
<addressOffset>0x00000F04</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_FIFOCTL_TXTRIG</name>
|
|
<description>TX FIFO Trigger</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOCTL_DMATXENA</name>
|
|
<description>DMA TX Channel Enable</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOCTL_TXFLUSH</name>
|
|
<description>TX FIFO Flush</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOCTL_TXASGNMT</name>
|
|
<description>TX Control Assignment</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOCTL_RXTRIG</name>
|
|
<description>RX FIFO Trigger</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOCTL_DMARXENA</name>
|
|
<description>DMA RX Channel Enable</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOCTL_RXFLUSH</name>
|
|
<description>RX FIFO Flush</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOCTL_RXASGNMT</name>
|
|
<description>RX Control Assignment</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOSTATUS</name>
|
|
<description>I2C FIFO Status</description>
|
|
<addressOffset>0x00000F08</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_FIFOSTATUS_TXFE</name>
|
|
<description>TX FIFO Empty</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOSTATUS_TXFF</name>
|
|
<description>TX FIFO Full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOSTATUS_TXBLWTRIG</name>
|
|
<description>TX FIFO Below Trigger Level</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOSTATUS_RXFE</name>
|
|
<description>RX FIFO Empty</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOSTATUS_RXFF</name>
|
|
<description>RX FIFO Full</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_FIFOSTATUS_RXABVTRIG</name>
|
|
<description>RX FIFO Above Trigger Level</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>I2C Peripheral Properties</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_PP_HS</name>
|
|
<description>High-Speed Capable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>I2C Peripheral Configuration</description>
|
|
<addressOffset>0x00000FC4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_PC_HS</name>
|
|
<description>High-Speed Capable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C1</name>
|
|
<prependToName>I2C1</prependToName>
|
|
<baseAddress>0x40021000</baseAddress>
|
|
<interrupt><name>I2C1</name><value>37</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C2</name>
|
|
<prependToName>I2C2</prependToName>
|
|
<baseAddress>0x40022000</baseAddress>
|
|
<interrupt><name>I2C2</name><value>61</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C3</name>
|
|
<prependToName>I2C3</prependToName>
|
|
<baseAddress>0x40023000</baseAddress>
|
|
<interrupt><name>I2C3</name><value>62</value></interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PWM0</name>
|
|
<description>Register map for PWM0 peripheral</description>
|
|
<groupName>PWM</groupName>
|
|
<prependToName>PWM0</prependToName>
|
|
<baseAddress>0x40028000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>PWM0_0</name><value>10</value></interrupt>
|
|
<interrupt><name>PWM0_1</name><value>11</value></interrupt>
|
|
<interrupt><name>PWM0_2</name><value>12</value></interrupt>
|
|
<interrupt><name>PWM0_3</name><value>43</value></interrupt>
|
|
<interrupt><name>PWM0_FAULT</name><value>9</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>PWM Master Control</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_CTL_GLOBALSYNC0</name>
|
|
<description>Update PWM Generator 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_CTL_GLOBALSYNC1</name>
|
|
<description>Update PWM Generator 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_CTL_GLOBALSYNC2</name>
|
|
<description>Update PWM Generator 2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_CTL_GLOBALSYNC3</name>
|
|
<description>Update PWM Generator 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>PWM Time Base Sync</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_SYNC_SYNC0</name>
|
|
<description>Reset Generator 0 Counter</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_SYNC_SYNC1</name>
|
|
<description>Reset Generator 1 Counter</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_SYNC_SYNC2</name>
|
|
<description>Reset Generator 2 Counter</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_SYNC_SYNC3</name>
|
|
<description>Reset Generator 3 Counter</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENABLE</name>
|
|
<description>PWM Output Enable</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM0EN</name>
|
|
<description>MnPWM0 Output Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM1EN</name>
|
|
<description>MnPWM1 Output Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM2EN</name>
|
|
<description>MnPWM2 Output Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM3EN</name>
|
|
<description>MnPWM3 Output Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM4EN</name>
|
|
<description>MnPWM4 Output Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM5EN</name>
|
|
<description>MnPWM5 Output Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM6EN</name>
|
|
<description>MnPWM6 Output Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM7EN</name>
|
|
<description>MnPWM7 Output Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INVERT</name>
|
|
<description>PWM Output Inversion</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_INVERT_PWM0INV</name>
|
|
<description>Invert MnPWM0 Signal</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM1INV</name>
|
|
<description>Invert MnPWM1 Signal</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM2INV</name>
|
|
<description>Invert MnPWM2 Signal</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM3INV</name>
|
|
<description>Invert MnPWM3 Signal</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM4INV</name>
|
|
<description>Invert MnPWM4 Signal</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM5INV</name>
|
|
<description>Invert MnPWM5 Signal</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM6INV</name>
|
|
<description>Invert MnPWM6 Signal</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM7INV</name>
|
|
<description>Invert MnPWM7 Signal</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FAULT</name>
|
|
<description>PWM Output Fault</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT0</name>
|
|
<description>MnPWM0 Fault</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT1</name>
|
|
<description>MnPWM1 Fault</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT2</name>
|
|
<description>MnPWM2 Fault</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT3</name>
|
|
<description>MnPWM3 Fault</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT4</name>
|
|
<description>MnPWM4 Fault</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT5</name>
|
|
<description>MnPWM5 Fault</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT6</name>
|
|
<description>MnPWM6 Fault</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT7</name>
|
|
<description>MnPWM7 Fault</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>PWM Interrupt Enable</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_INTEN_INTPWM0</name>
|
|
<description>PWM0 Interrupt Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INTEN_INTPWM1</name>
|
|
<description>PWM1 Interrupt Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INTEN_INTPWM2</name>
|
|
<description>PWM2 Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INTEN_INTPWM3</name>
|
|
<description>PWM3 Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INTEN_INTFAULT0</name>
|
|
<description>Interrupt Fault 0</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INTEN_INTFAULT1</name>
|
|
<description>Interrupt Fault 1</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INTEN_INTFAULT2</name>
|
|
<description>Interrupt Fault 2</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INTEN_INTFAULT3</name>
|
|
<description>Interrupt Fault 3</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>PWM Raw Interrupt Status</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_RIS_INTPWM0</name>
|
|
<description>PWM0 Interrupt Asserted</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_RIS_INTPWM1</name>
|
|
<description>PWM1 Interrupt Asserted</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_RIS_INTPWM2</name>
|
|
<description>PWM2 Interrupt Asserted</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_RIS_INTPWM3</name>
|
|
<description>PWM3 Interrupt Asserted</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_RIS_INTFAULT0</name>
|
|
<description>Interrupt Fault PWM 0</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_RIS_INTFAULT1</name>
|
|
<description>Interrupt Fault PWM 1</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_RIS_INTFAULT2</name>
|
|
<description>Interrupt Fault PWM 2</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_RIS_INTFAULT3</name>
|
|
<description>Interrupt Fault PWM 3</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISC</name>
|
|
<description>PWM Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_ISC_INTPWM0</name>
|
|
<description>PWM0 Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ISC_INTPWM1</name>
|
|
<description>PWM1 Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ISC_INTPWM2</name>
|
|
<description>PWM2 Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ISC_INTPWM3</name>
|
|
<description>PWM3 Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ISC_INTFAULT0</name>
|
|
<description>FAULT0 Interrupt Asserted</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ISC_INTFAULT1</name>
|
|
<description>FAULT1 Interrupt Asserted</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ISC_INTFAULT2</name>
|
|
<description>FAULT2 Interrupt Asserted</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ISC_INTFAULT3</name>
|
|
<description>FAULT3 Interrupt Asserted</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>PWM Status</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_STATUS_FAULT0</name>
|
|
<description>Generator 0 Fault Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_STATUS_FAULT1</name>
|
|
<description>Generator 1 Fault Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_STATUS_FAULT2</name>
|
|
<description>Generator 2 Fault Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_STATUS_FAULT3</name>
|
|
<description>Generator 3 Fault Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FAULTVAL</name>
|
|
<description>PWM Fault Condition Value</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_FAULTVAL_PWM0</name>
|
|
<description>MnPWM0 Fault Value</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULTVAL_PWM1</name>
|
|
<description>MnPWM1 Fault Value</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULTVAL_PWM2</name>
|
|
<description>MnPWM2 Fault Value</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULTVAL_PWM3</name>
|
|
<description>MnPWM3 Fault Value</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULTVAL_PWM4</name>
|
|
<description>MnPWM4 Fault Value</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULTVAL_PWM5</name>
|
|
<description>MnPWM5 Fault Value</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULTVAL_PWM6</name>
|
|
<description>MnPWM6 Fault Value</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULTVAL_PWM7</name>
|
|
<description>MnPWM7 Fault Value</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENUPD</name>
|
|
<description>PWM Enable Update</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_ENUPD_ENUPD0</name>
|
|
<description>MnPWM0 Enable Update Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD0_IMM</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD0_LSYNC</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD0_GSYNC</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENUPD_ENUPD1</name>
|
|
<description>MnPWM1 Enable Update Mode</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD1_IMM</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD1_LSYNC</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD1_GSYNC</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENUPD_ENUPD2</name>
|
|
<description>MnPWM2 Enable Update Mode</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD2_IMM</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD2_LSYNC</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD2_GSYNC</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENUPD_ENUPD3</name>
|
|
<description>MnPWM3 Enable Update Mode</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD3_IMM</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD3_LSYNC</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD3_GSYNC</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENUPD_ENUPD4</name>
|
|
<description>MnPWM4 Enable Update Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD4_IMM</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD4_LSYNC</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD4_GSYNC</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENUPD_ENUPD5</name>
|
|
<description>MnPWM5 Enable Update Mode</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD5_IMM</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD5_LSYNC</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD5_GSYNC</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENUPD_ENUPD6</name>
|
|
<description>MnPWM6 Enable Update Mode</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD6_IMM</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD6_LSYNC</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD6_GSYNC</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENUPD_ENUPD7</name>
|
|
<description>MnPWM7 Enable Update Mode</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD7_IMM</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD7_LSYNC</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_ENUPD_ENUPD7_GSYNC</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_CTL</name>
|
|
<description>PWM0 Control</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_CTL_ENABLE</name>
|
|
<description>PWM Block Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_MODE</name>
|
|
<description>Counter Mode</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_DEBUG</name>
|
|
<description>Debug Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_LOADUPD</name>
|
|
<description>Load Register Update Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_CMPAUPD</name>
|
|
<description>Comparator A Update Mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_CMPBUPD</name>
|
|
<description>Comparator B Update Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_GENAUPD</name>
|
|
<description>PWMnGENA Update Mode</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_GENAUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_GENAUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_GENAUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_GENBUPD</name>
|
|
<description>PWMnGENB Update Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_GENBUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_GENBUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_GENBUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_DBCTLUPD</name>
|
|
<description>PWMnDBCTL Update Mode</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_DBCTLUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_DBCTLUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_DBCTLUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_DBRISEUPD</name>
|
|
<description>PWMnDBRISE Update Mode</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_DBRISEUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_DBRISEUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_DBRISEUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_DBFALLUPD</name>
|
|
<description>PWMnDBFALL Update Mode</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_DBFALLUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_DBFALLUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_CTL_DBFALLUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_FLTSRC</name>
|
|
<description>Fault Condition Source</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_MINFLTPER</name>
|
|
<description>Minimum Fault Period</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_CTL_LATCH</name>
|
|
<description>Latch Fault Input</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_INTEN</name>
|
|
<description>PWM0 Interrupt and Trigger Enable</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_INTEN_INTCNTZERO</name>
|
|
<description>Interrupt for Counter=0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_INTEN_INTCNTLOAD</name>
|
|
<description>Interrupt for Counter=PWMnLOAD</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_INTEN_INTCMPAU</name>
|
|
<description>Interrupt for Counter=PWMnCMPA Up</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_INTEN_INTCMPAD</name>
|
|
<description>Interrupt for Counter=PWMnCMPA Down</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_INTEN_INTCMPBU</name>
|
|
<description>Interrupt for Counter=PWMnCMPB Up</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_INTEN_INTCMPBD</name>
|
|
<description>Interrupt for Counter=PWMnCMPB Down</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_INTEN_TRCNTZERO</name>
|
|
<description>Trigger for Counter=0</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_INTEN_TRCNTLOAD</name>
|
|
<description>Trigger for Counter=PWMnLOAD</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_INTEN_TRCMPAU</name>
|
|
<description>Trigger for Counter=PWMnCMPA Up</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_INTEN_TRCMPAD</name>
|
|
<description>Trigger for Counter=PWMnCMPA Down</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_INTEN_TRCMPBU</name>
|
|
<description>Trigger for Counter=PWMnCMPB Up</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_INTEN_TRCMPBD</name>
|
|
<description>Trigger for Counter=PWMnCMPB Down</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_RIS</name>
|
|
<description>PWM0 Raw Interrupt Status</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_RIS_INTCNTZERO</name>
|
|
<description>Counter=0 Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_RIS_INTCNTLOAD</name>
|
|
<description>Counter=Load Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_RIS_INTCMPAU</name>
|
|
<description>Comparator A Up Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_RIS_INTCMPAD</name>
|
|
<description>Comparator A Down Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_RIS_INTCMPBU</name>
|
|
<description>Comparator B Up Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_RIS_INTCMPBD</name>
|
|
<description>Comparator B Down Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_ISC</name>
|
|
<description>PWM0 Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_ISC_INTCNTZERO</name>
|
|
<description>Counter=0 Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_ISC_INTCNTLOAD</name>
|
|
<description>Counter=Load Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_ISC_INTCMPAU</name>
|
|
<description>Comparator A Up Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_ISC_INTCMPAD</name>
|
|
<description>Comparator A Down Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_ISC_INTCMPBU</name>
|
|
<description>Comparator B Up Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_ISC_INTCMPBD</name>
|
|
<description>Comparator B Down Interrupt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_LOAD</name>
|
|
<description>PWM0 Load</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_LOAD</name>
|
|
<description>Counter Load Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_COUNT</name>
|
|
<description>PWM0 Counter</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_CMPA</name>
|
|
<description>PWM0 Compare A</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_CMPA</name>
|
|
<description>Comparator A Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_CMPB</name>
|
|
<description>PWM0 Compare B</description>
|
|
<addressOffset>0x0000005C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_CMPB</name>
|
|
<description>Comparator B Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_GENA</name>
|
|
<description>PWM0 Generator A Control</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_GENA_ACTZERO</name>
|
|
<description>Action for Counter=0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTZERO_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTZERO_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTZERO_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTZERO_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_GENA_ACTLOAD</name>
|
|
<description>Action for Counter=LOAD</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTLOAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTLOAD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTLOAD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTLOAD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_GENA_ACTCMPAU</name>
|
|
<description>Action for Comparator A Up</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPAU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPAU_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPAU_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPAU_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_GENA_ACTCMPAD</name>
|
|
<description>Action for Comparator A Down</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPAD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPAD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPAD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_GENA_ACTCMPBU</name>
|
|
<description>Action for Comparator B Up</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPBU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPBU_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPBU_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPBU_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_GENA_ACTCMPBD</name>
|
|
<description>Action for Comparator B Down</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPBD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPBD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPBD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENA_ACTCMPBD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_GENB</name>
|
|
<description>PWM0 Generator B Control</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_GENB_ACTZERO</name>
|
|
<description>Action for Counter=0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTZERO_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTZERO_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTZERO_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTZERO_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_GENB_ACTLOAD</name>
|
|
<description>Action for Counter=LOAD</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTLOAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTLOAD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTLOAD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTLOAD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_GENB_ACTCMPAU</name>
|
|
<description>Action for Comparator A Up</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPAU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPAU_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPAU_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPAU_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_GENB_ACTCMPAD</name>
|
|
<description>Action for Comparator A Down</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPAD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPAD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPAD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_GENB_ACTCMPBU</name>
|
|
<description>Action for Comparator B Up</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPBU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPBU_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPBU_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPBU_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_GENB_ACTCMPBD</name>
|
|
<description>Action for Comparator B Down</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPBD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPBD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPBD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_0_GENB_ACTCMPBD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_DBCTL</name>
|
|
<description>PWM0 Dead-Band Control</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_DBCTL_ENABLE</name>
|
|
<description>Dead-Band Generator Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_DBRISE</name>
|
|
<description>PWM0 Dead-Band Rising-Edge Delay</description>
|
|
<addressOffset>0x0000006C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_DBRISE_DELAY</name>
|
|
<description>Dead-Band Rise Delay</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_DBFALL</name>
|
|
<description>PWM0 Dead-Band Falling-Edge-Delay</description>
|
|
<addressOffset>0x00000070</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_DBFALL_DELAY</name>
|
|
<description>Dead-Band Fall Delay</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_FLTSRC0</name>
|
|
<description>PWM0 Fault Source 0</description>
|
|
<addressOffset>0x00000074</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_FLTSRC0_FAULT0</name>
|
|
<description>Fault0 Input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSRC0_FAULT1</name>
|
|
<description>Fault1 Input</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSRC0_FAULT2</name>
|
|
<description>Fault2 Input</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSRC0_FAULT3</name>
|
|
<description>Fault3 Input</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_FLTSRC1</name>
|
|
<description>PWM0 Fault Source 1</description>
|
|
<addressOffset>0x00000078</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_FLTSRC1_DCMP0</name>
|
|
<description>Digital Comparator 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSRC1_DCMP1</name>
|
|
<description>Digital Comparator 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSRC1_DCMP2</name>
|
|
<description>Digital Comparator 2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSRC1_DCMP3</name>
|
|
<description>Digital Comparator 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSRC1_DCMP4</name>
|
|
<description>Digital Comparator 4</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSRC1_DCMP5</name>
|
|
<description>Digital Comparator 5</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSRC1_DCMP6</name>
|
|
<description>Digital Comparator 6</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSRC1_DCMP7</name>
|
|
<description>Digital Comparator 7</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_MINFLTPER</name>
|
|
<description>PWM0 Minimum Fault Period</description>
|
|
<addressOffset>0x0000007C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_MINFLTPER</name>
|
|
<description>Minimum Fault Period</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_CTL</name>
|
|
<description>PWM1 Control</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_CTL_ENABLE</name>
|
|
<description>PWM Block Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_MODE</name>
|
|
<description>Counter Mode</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_DEBUG</name>
|
|
<description>Debug Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_LOADUPD</name>
|
|
<description>Load Register Update Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_CMPAUPD</name>
|
|
<description>Comparator A Update Mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_CMPBUPD</name>
|
|
<description>Comparator B Update Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_GENAUPD</name>
|
|
<description>PWMnGENA Update Mode</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_GENAUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_GENAUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_GENAUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_GENBUPD</name>
|
|
<description>PWMnGENB Update Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_GENBUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_GENBUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_GENBUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_DBCTLUPD</name>
|
|
<description>PWMnDBCTL Update Mode</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_DBCTLUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_DBCTLUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_DBCTLUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_DBRISEUPD</name>
|
|
<description>PWMnDBRISE Update Mode</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_DBRISEUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_DBRISEUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_DBRISEUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_DBFALLUPD</name>
|
|
<description>PWMnDBFALL Update Mode</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_DBFALLUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_DBFALLUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_CTL_DBFALLUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_FLTSRC</name>
|
|
<description>Fault Condition Source</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_MINFLTPER</name>
|
|
<description>Minimum Fault Period</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_CTL_LATCH</name>
|
|
<description>Latch Fault Input</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_INTEN</name>
|
|
<description>PWM1 Interrupt and Trigger Enable</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_INTEN_INTCNTZERO</name>
|
|
<description>Interrupt for Counter=0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_INTEN_INTCNTLOAD</name>
|
|
<description>Interrupt for Counter=PWMnLOAD</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_INTEN_INTCMPAU</name>
|
|
<description>Interrupt for Counter=PWMnCMPA Up</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_INTEN_INTCMPAD</name>
|
|
<description>Interrupt for Counter=PWMnCMPA Down</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_INTEN_INTCMPBU</name>
|
|
<description>Interrupt for Counter=PWMnCMPB Up</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_INTEN_INTCMPBD</name>
|
|
<description>Interrupt for Counter=PWMnCMPB Down</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_INTEN_TRCNTZERO</name>
|
|
<description>Trigger for Counter=0</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_INTEN_TRCNTLOAD</name>
|
|
<description>Trigger for Counter=PWMnLOAD</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_INTEN_TRCMPAU</name>
|
|
<description>Trigger for Counter=PWMnCMPA Up</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_INTEN_TRCMPAD</name>
|
|
<description>Trigger for Counter=PWMnCMPA Down</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_INTEN_TRCMPBU</name>
|
|
<description>Trigger for Counter=PWMnCMPB Up</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_INTEN_TRCMPBD</name>
|
|
<description>Trigger for Counter=PWMnCMPB Down</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_RIS</name>
|
|
<description>PWM1 Raw Interrupt Status</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_RIS_INTCNTZERO</name>
|
|
<description>Counter=0 Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_RIS_INTCNTLOAD</name>
|
|
<description>Counter=Load Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_RIS_INTCMPAU</name>
|
|
<description>Comparator A Up Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_RIS_INTCMPAD</name>
|
|
<description>Comparator A Down Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_RIS_INTCMPBU</name>
|
|
<description>Comparator B Up Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_RIS_INTCMPBD</name>
|
|
<description>Comparator B Down Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_ISC</name>
|
|
<description>PWM1 Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_ISC_INTCNTZERO</name>
|
|
<description>Counter=0 Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_ISC_INTCNTLOAD</name>
|
|
<description>Counter=Load Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_ISC_INTCMPAU</name>
|
|
<description>Comparator A Up Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_ISC_INTCMPAD</name>
|
|
<description>Comparator A Down Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_ISC_INTCMPBU</name>
|
|
<description>Comparator B Up Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_ISC_INTCMPBD</name>
|
|
<description>Comparator B Down Interrupt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_LOAD</name>
|
|
<description>PWM1 Load</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_LOAD_LOAD</name>
|
|
<description>Counter Load Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_COUNT</name>
|
|
<description>PWM1 Counter</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_COUNT_COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_CMPA</name>
|
|
<description>PWM1 Compare A</description>
|
|
<addressOffset>0x00000098</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_CMPA_COMPA</name>
|
|
<description>Comparator A Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_CMPB</name>
|
|
<description>PWM1 Compare B</description>
|
|
<addressOffset>0x0000009C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_CMPB_COMPB</name>
|
|
<description>Comparator B Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_GENA</name>
|
|
<description>PWM1 Generator A Control</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_GENA_ACTZERO</name>
|
|
<description>Action for Counter=0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTZERO_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTZERO_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTZERO_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTZERO_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_GENA_ACTLOAD</name>
|
|
<description>Action for Counter=LOAD</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTLOAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTLOAD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTLOAD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTLOAD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_GENA_ACTCMPAU</name>
|
|
<description>Action for Comparator A Up</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPAU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPAU_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPAU_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPAU_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_GENA_ACTCMPAD</name>
|
|
<description>Action for Comparator A Down</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPAD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPAD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPAD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_GENA_ACTCMPBU</name>
|
|
<description>Action for Comparator B Up</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPBU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPBU_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPBU_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPBU_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_GENA_ACTCMPBD</name>
|
|
<description>Action for Comparator B Down</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPBD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPBD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPBD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENA_ACTCMPBD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_GENB</name>
|
|
<description>PWM1 Generator B Control</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_GENB_ACTZERO</name>
|
|
<description>Action for Counter=0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTZERO_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTZERO_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTZERO_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTZERO_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_GENB_ACTLOAD</name>
|
|
<description>Action for Counter=LOAD</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTLOAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTLOAD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTLOAD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTLOAD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_GENB_ACTCMPAU</name>
|
|
<description>Action for Comparator A Up</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPAU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPAU_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPAU_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPAU_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_GENB_ACTCMPAD</name>
|
|
<description>Action for Comparator A Down</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPAD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPAD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPAD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_GENB_ACTCMPBU</name>
|
|
<description>Action for Comparator B Up</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPBU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPBU_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPBU_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPBU_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_GENB_ACTCMPBD</name>
|
|
<description>Action for Comparator B Down</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPBD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPBD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPBD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_1_GENB_ACTCMPBD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_DBCTL</name>
|
|
<description>PWM1 Dead-Band Control</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_DBCTL_ENABLE</name>
|
|
<description>Dead-Band Generator Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_DBRISE</name>
|
|
<description>PWM1 Dead-Band Rising-Edge Delay</description>
|
|
<addressOffset>0x000000AC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_DBRISE_RISEDELAY</name>
|
|
<description>Dead-Band Rise Delay</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_DBFALL</name>
|
|
<description>PWM1 Dead-Band Falling-Edge-Delay</description>
|
|
<addressOffset>0x000000B0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_DBFALL_FALLDELAY</name>
|
|
<description>Dead-Band Fall Delay</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_FLTSRC0</name>
|
|
<description>PWM1 Fault Source 0</description>
|
|
<addressOffset>0x000000B4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_FLTSRC0_FAULT0</name>
|
|
<description>Fault0 Input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSRC0_FAULT1</name>
|
|
<description>Fault1 Input</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSRC0_FAULT2</name>
|
|
<description>Fault2 Input</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSRC0_FAULT3</name>
|
|
<description>Fault3 Input</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_FLTSRC1</name>
|
|
<description>PWM1 Fault Source 1</description>
|
|
<addressOffset>0x000000B8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_FLTSRC1_DCMP0</name>
|
|
<description>Digital Comparator 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSRC1_DCMP1</name>
|
|
<description>Digital Comparator 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSRC1_DCMP2</name>
|
|
<description>Digital Comparator 2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSRC1_DCMP3</name>
|
|
<description>Digital Comparator 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSRC1_DCMP4</name>
|
|
<description>Digital Comparator 4</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSRC1_DCMP5</name>
|
|
<description>Digital Comparator 5</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSRC1_DCMP6</name>
|
|
<description>Digital Comparator 6</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSRC1_DCMP7</name>
|
|
<description>Digital Comparator 7</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_MINFLTPER</name>
|
|
<description>PWM1 Minimum Fault Period</description>
|
|
<addressOffset>0x000000BC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_MINFLTPER_MFP</name>
|
|
<description>Minimum Fault Period</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_CTL</name>
|
|
<description>PWM2 Control</description>
|
|
<addressOffset>0x000000C0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_CTL_ENABLE</name>
|
|
<description>PWM Block Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_MODE</name>
|
|
<description>Counter Mode</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_DEBUG</name>
|
|
<description>Debug Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_LOADUPD</name>
|
|
<description>Load Register Update Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_CMPAUPD</name>
|
|
<description>Comparator A Update Mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_CMPBUPD</name>
|
|
<description>Comparator B Update Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_GENAUPD</name>
|
|
<description>PWMnGENA Update Mode</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_GENAUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_GENAUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_GENAUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_GENBUPD</name>
|
|
<description>PWMnGENB Update Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_GENBUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_GENBUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_GENBUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_DBCTLUPD</name>
|
|
<description>PWMnDBCTL Update Mode</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_DBCTLUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_DBCTLUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_DBCTLUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_DBRISEUPD</name>
|
|
<description>PWMnDBRISE Update Mode</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_DBRISEUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_DBRISEUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_DBRISEUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_DBFALLUPD</name>
|
|
<description>PWMnDBFALL Update Mode</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_DBFALLUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_DBFALLUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_CTL_DBFALLUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_FLTSRC</name>
|
|
<description>Fault Condition Source</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_MINFLTPER</name>
|
|
<description>Minimum Fault Period</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_CTL_LATCH</name>
|
|
<description>Latch Fault Input</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_INTEN</name>
|
|
<description>PWM2 Interrupt and Trigger Enable</description>
|
|
<addressOffset>0x000000C4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_INTEN_INTCNTZERO</name>
|
|
<description>Interrupt for Counter=0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_INTEN_INTCNTLOAD</name>
|
|
<description>Interrupt for Counter=PWMnLOAD</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_INTEN_INTCMPAU</name>
|
|
<description>Interrupt for Counter=PWMnCMPA Up</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_INTEN_INTCMPAD</name>
|
|
<description>Interrupt for Counter=PWMnCMPA Down</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_INTEN_INTCMPBU</name>
|
|
<description>Interrupt for Counter=PWMnCMPB Up</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_INTEN_INTCMPBD</name>
|
|
<description>Interrupt for Counter=PWMnCMPB Down</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_INTEN_TRCNTZERO</name>
|
|
<description>Trigger for Counter=0</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_INTEN_TRCNTLOAD</name>
|
|
<description>Trigger for Counter=PWMnLOAD</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_INTEN_TRCMPAU</name>
|
|
<description>Trigger for Counter=PWMnCMPA Up</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_INTEN_TRCMPAD</name>
|
|
<description>Trigger for Counter=PWMnCMPA Down</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_INTEN_TRCMPBU</name>
|
|
<description>Trigger for Counter=PWMnCMPB Up</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_INTEN_TRCMPBD</name>
|
|
<description>Trigger for Counter=PWMnCMPB Down</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_RIS</name>
|
|
<description>PWM2 Raw Interrupt Status</description>
|
|
<addressOffset>0x000000C8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_RIS_INTCNTZERO</name>
|
|
<description>Counter=0 Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_RIS_INTCNTLOAD</name>
|
|
<description>Counter=Load Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_RIS_INTCMPAU</name>
|
|
<description>Comparator A Up Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_RIS_INTCMPAD</name>
|
|
<description>Comparator A Down Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_RIS_INTCMPBU</name>
|
|
<description>Comparator B Up Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_RIS_INTCMPBD</name>
|
|
<description>Comparator B Down Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_ISC</name>
|
|
<description>PWM2 Interrupt Status and Clear</description>
|
|
<addressOffset>0x000000CC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_ISC_INTCNTZERO</name>
|
|
<description>Counter=0 Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_ISC_INTCNTLOAD</name>
|
|
<description>Counter=Load Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_ISC_INTCMPAU</name>
|
|
<description>Comparator A Up Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_ISC_INTCMPAD</name>
|
|
<description>Comparator A Down Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_ISC_INTCMPBU</name>
|
|
<description>Comparator B Up Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_ISC_INTCMPBD</name>
|
|
<description>Comparator B Down Interrupt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_LOAD</name>
|
|
<description>PWM2 Load</description>
|
|
<addressOffset>0x000000D0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_LOAD_LOAD</name>
|
|
<description>Counter Load Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_COUNT</name>
|
|
<description>PWM2 Counter</description>
|
|
<addressOffset>0x000000D4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_COUNT_COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_CMPA</name>
|
|
<description>PWM2 Compare A</description>
|
|
<addressOffset>0x000000D8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_CMPA_COMPA</name>
|
|
<description>Comparator A Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_CMPB</name>
|
|
<description>PWM2 Compare B</description>
|
|
<addressOffset>0x000000DC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_CMPB_COMPB</name>
|
|
<description>Comparator B Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_GENA</name>
|
|
<description>PWM2 Generator A Control</description>
|
|
<addressOffset>0x000000E0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_GENA_ACTZERO</name>
|
|
<description>Action for Counter=0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTZERO_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTZERO_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTZERO_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTZERO_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_GENA_ACTLOAD</name>
|
|
<description>Action for Counter=LOAD</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTLOAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTLOAD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTLOAD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTLOAD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_GENA_ACTCMPAU</name>
|
|
<description>Action for Comparator A Up</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPAU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPAU_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPAU_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPAU_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_GENA_ACTCMPAD</name>
|
|
<description>Action for Comparator A Down</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPAD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPAD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPAD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_GENA_ACTCMPBU</name>
|
|
<description>Action for Comparator B Up</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPBU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPBU_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPBU_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPBU_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_GENA_ACTCMPBD</name>
|
|
<description>Action for Comparator B Down</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPBD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPBD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPBD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENA_ACTCMPBD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_GENB</name>
|
|
<description>PWM2 Generator B Control</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_GENB_ACTZERO</name>
|
|
<description>Action for Counter=0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTZERO_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTZERO_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTZERO_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTZERO_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_GENB_ACTLOAD</name>
|
|
<description>Action for Counter=LOAD</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTLOAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTLOAD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTLOAD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTLOAD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_GENB_ACTCMPAU</name>
|
|
<description>Action for Comparator A Up</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPAU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPAU_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPAU_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPAU_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_GENB_ACTCMPAD</name>
|
|
<description>Action for Comparator A Down</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPAD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPAD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPAD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_GENB_ACTCMPBU</name>
|
|
<description>Action for Comparator B Up</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPBU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPBU_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPBU_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPBU_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_GENB_ACTCMPBD</name>
|
|
<description>Action for Comparator B Down</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPBD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPBD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPBD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_2_GENB_ACTCMPBD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_DBCTL</name>
|
|
<description>PWM2 Dead-Band Control</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_DBCTL_ENABLE</name>
|
|
<description>Dead-Band Generator Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_DBRISE</name>
|
|
<description>PWM2 Dead-Band Rising-Edge Delay</description>
|
|
<addressOffset>0x000000EC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_DBRISE_RISEDELAY</name>
|
|
<description>Dead-Band Rise Delay</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_DBFALL</name>
|
|
<description>PWM2 Dead-Band Falling-Edge-Delay</description>
|
|
<addressOffset>0x000000F0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_DBFALL_FALLDELAY</name>
|
|
<description>Dead-Band Fall Delay</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_FLTSRC0</name>
|
|
<description>PWM2 Fault Source 0</description>
|
|
<addressOffset>0x000000F4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_FLTSRC0_FAULT0</name>
|
|
<description>Fault0 Input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSRC0_FAULT1</name>
|
|
<description>Fault1 Input</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSRC0_FAULT2</name>
|
|
<description>Fault2 Input</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSRC0_FAULT3</name>
|
|
<description>Fault3 Input</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_FLTSRC1</name>
|
|
<description>PWM2 Fault Source 1</description>
|
|
<addressOffset>0x000000F8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_FLTSRC1_DCMP0</name>
|
|
<description>Digital Comparator 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSRC1_DCMP1</name>
|
|
<description>Digital Comparator 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSRC1_DCMP2</name>
|
|
<description>Digital Comparator 2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSRC1_DCMP3</name>
|
|
<description>Digital Comparator 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSRC1_DCMP4</name>
|
|
<description>Digital Comparator 4</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSRC1_DCMP5</name>
|
|
<description>Digital Comparator 5</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSRC1_DCMP6</name>
|
|
<description>Digital Comparator 6</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSRC1_DCMP7</name>
|
|
<description>Digital Comparator 7</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_MINFLTPER</name>
|
|
<description>PWM2 Minimum Fault Period</description>
|
|
<addressOffset>0x000000FC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_MINFLTPER_MFP</name>
|
|
<description>Minimum Fault Period</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_CTL</name>
|
|
<description>PWM3 Control</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_CTL_ENABLE</name>
|
|
<description>PWM Block Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_MODE</name>
|
|
<description>Counter Mode</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_DEBUG</name>
|
|
<description>Debug Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_LOADUPD</name>
|
|
<description>Load Register Update Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_CMPAUPD</name>
|
|
<description>Comparator A Update Mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_CMPBUPD</name>
|
|
<description>Comparator B Update Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_GENAUPD</name>
|
|
<description>PWMnGENA Update Mode</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_GENAUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_GENAUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_GENAUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_GENBUPD</name>
|
|
<description>PWMnGENB Update Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_GENBUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_GENBUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_GENBUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_DBCTLUPD</name>
|
|
<description>PWMnDBCTL Update Mode</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_DBCTLUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_DBCTLUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_DBCTLUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_DBRISEUPD</name>
|
|
<description>PWMnDBRISE Update Mode</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_DBRISEUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_DBRISEUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_DBRISEUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_DBFALLUPD</name>
|
|
<description>PWMnDBFALL Update Mode</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_DBFALLUPD_I</name>
|
|
<description>Immediate</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_DBFALLUPD_LS</name>
|
|
<description>Locally Synchronized</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_CTL_DBFALLUPD_GS</name>
|
|
<description>Globally Synchronized</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_FLTSRC</name>
|
|
<description>Fault Condition Source</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_MINFLTPER</name>
|
|
<description>Minimum Fault Period</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_CTL_LATCH</name>
|
|
<description>Latch Fault Input</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_INTEN</name>
|
|
<description>PWM3 Interrupt and Trigger Enable</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_INTEN_INTCNTZERO</name>
|
|
<description>Interrupt for Counter=0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_INTEN_INTCNTLOAD</name>
|
|
<description>Interrupt for Counter=PWMnLOAD</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_INTEN_INTCMPAU</name>
|
|
<description>Interrupt for Counter=PWMnCMPA Up</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_INTEN_INTCMPAD</name>
|
|
<description>Interrupt for Counter=PWMnCMPA Down</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_INTEN_INTCMPBU</name>
|
|
<description>Interrupt for Counter=PWMnCMPB Up</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_INTEN_INTCMPBD</name>
|
|
<description>Interrupt for Counter=PWMnCMPB Down</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_INTEN_TRCNTZERO</name>
|
|
<description>Trigger for Counter=0</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_INTEN_TRCNTLOAD</name>
|
|
<description>Trigger for Counter=PWMnLOAD</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_INTEN_TRCMPAU</name>
|
|
<description>Trigger for Counter=PWMnCMPA Up</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_INTEN_TRCMPAD</name>
|
|
<description>Trigger for Counter=PWMnCMPA Down</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_INTEN_TRCMPBU</name>
|
|
<description>Trigger for Counter=PWMnCMPB Up</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_INTEN_TRCMPBD</name>
|
|
<description>Trigger for Counter=PWMnCMPB Down</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_RIS</name>
|
|
<description>PWM3 Raw Interrupt Status</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_RIS_INTCNTZERO</name>
|
|
<description>Counter=0 Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_RIS_INTCNTLOAD</name>
|
|
<description>Counter=Load Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_RIS_INTCMPAU</name>
|
|
<description>Comparator A Up Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_RIS_INTCMPAD</name>
|
|
<description>Comparator A Down Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_RIS_INTCMPBU</name>
|
|
<description>Comparator B Up Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_RIS_INTCMPBD</name>
|
|
<description>Comparator B Down Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_ISC</name>
|
|
<description>PWM3 Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_ISC_INTCNTZERO</name>
|
|
<description>Counter=0 Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_ISC_INTCNTLOAD</name>
|
|
<description>Counter=Load Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_ISC_INTCMPAU</name>
|
|
<description>Comparator A Up Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_ISC_INTCMPAD</name>
|
|
<description>Comparator A Down Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_ISC_INTCMPBU</name>
|
|
<description>Comparator B Up Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_ISC_INTCMPBD</name>
|
|
<description>Comparator B Down Interrupt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_LOAD</name>
|
|
<description>PWM3 Load</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_LOAD_LOAD</name>
|
|
<description>Counter Load Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_COUNT</name>
|
|
<description>PWM3 Counter</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_COUNT_COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_CMPA</name>
|
|
<description>PWM3 Compare A</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_CMPA_COMPA</name>
|
|
<description>Comparator A Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_CMPB</name>
|
|
<description>PWM3 Compare B</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_CMPB_COMPB</name>
|
|
<description>Comparator B Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_GENA</name>
|
|
<description>PWM3 Generator A Control</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_GENA_ACTZERO</name>
|
|
<description>Action for Counter=0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTZERO_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTZERO_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTZERO_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTZERO_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_GENA_ACTLOAD</name>
|
|
<description>Action for Counter=LOAD</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTLOAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTLOAD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTLOAD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTLOAD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_GENA_ACTCMPAU</name>
|
|
<description>Action for Comparator A Up</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPAU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPAU_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPAU_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPAU_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_GENA_ACTCMPAD</name>
|
|
<description>Action for Comparator A Down</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPAD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPAD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPAD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_GENA_ACTCMPBU</name>
|
|
<description>Action for Comparator B Up</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPBU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPBU_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPBU_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPBU_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_GENA_ACTCMPBD</name>
|
|
<description>Action for Comparator B Down</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPBD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPBD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPBD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENA_ACTCMPBD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_GENB</name>
|
|
<description>PWM3 Generator B Control</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_GENB_ACTZERO</name>
|
|
<description>Action for Counter=0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTZERO_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTZERO_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTZERO_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTZERO_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_GENB_ACTLOAD</name>
|
|
<description>Action for Counter=LOAD</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTLOAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTLOAD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTLOAD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTLOAD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_GENB_ACTCMPAU</name>
|
|
<description>Action for Comparator A Up</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPAU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPAU_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPAU_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPAU_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_GENB_ACTCMPAD</name>
|
|
<description>Action for Comparator A Down</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPAD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPAD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPAD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_GENB_ACTCMPBU</name>
|
|
<description>Action for Comparator B Up</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPBU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPBU_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPBU_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPBU_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_GENB_ACTCMPBD</name>
|
|
<description>Action for Comparator B Down</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPBD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPBD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPBD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_3_GENB_ACTCMPBD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_DBCTL</name>
|
|
<description>PWM3 Dead-Band Control</description>
|
|
<addressOffset>0x00000128</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_DBCTL_ENABLE</name>
|
|
<description>Dead-Band Generator Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_DBRISE</name>
|
|
<description>PWM3 Dead-Band Rising-Edge Delay</description>
|
|
<addressOffset>0x0000012C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_DBRISE_RISEDELAY</name>
|
|
<description>Dead-Band Rise Delay</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_DBFALL</name>
|
|
<description>PWM3 Dead-Band Falling-Edge-Delay</description>
|
|
<addressOffset>0x00000130</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_DBFALL_FALLDELAY</name>
|
|
<description>Dead-Band Fall Delay</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_FLTSRC0</name>
|
|
<description>PWM3 Fault Source 0</description>
|
|
<addressOffset>0x00000134</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_FLTSRC0_FAULT0</name>
|
|
<description>Fault0 Input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSRC0_FAULT1</name>
|
|
<description>Fault1 Input</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSRC0_FAULT2</name>
|
|
<description>Fault2 Input</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSRC0_FAULT3</name>
|
|
<description>Fault3 Input</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_FLTSRC1</name>
|
|
<description>PWM3 Fault Source 1</description>
|
|
<addressOffset>0x00000138</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_FLTSRC1_DCMP0</name>
|
|
<description>Digital Comparator 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSRC1_DCMP1</name>
|
|
<description>Digital Comparator 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSRC1_DCMP2</name>
|
|
<description>Digital Comparator 2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSRC1_DCMP3</name>
|
|
<description>Digital Comparator 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSRC1_DCMP4</name>
|
|
<description>Digital Comparator 4</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSRC1_DCMP5</name>
|
|
<description>Digital Comparator 5</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSRC1_DCMP6</name>
|
|
<description>Digital Comparator 6</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSRC1_DCMP7</name>
|
|
<description>Digital Comparator 7</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_MINFLTPER</name>
|
|
<description>PWM3 Minimum Fault Period</description>
|
|
<addressOffset>0x0000013C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_MINFLTPER_MFP</name>
|
|
<description>Minimum Fault Period</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_FLTSEN</name>
|
|
<description>PWM0 Fault Pin Logic Sense</description>
|
|
<addressOffset>0x00000800</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_FLTSEN_FAULT0</name>
|
|
<description>Fault0 Sense</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSEN_FAULT1</name>
|
|
<description>Fault1 Sense</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSEN_FAULT2</name>
|
|
<description>Fault2 Sense</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSEN_FAULT3</name>
|
|
<description>Fault3 Sense</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_FLTSTAT0</name>
|
|
<description>PWM0 Fault Status 0</description>
|
|
<addressOffset>0x00000804</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT0_FAULT0</name>
|
|
<description>Fault Input 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT0_FAULT1</name>
|
|
<description>Fault Input 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT0_FAULT2</name>
|
|
<description>Fault Input 2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT0_FAULT3</name>
|
|
<description>Fault Input 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_FLTSTAT1</name>
|
|
<description>PWM0 Fault Status 1</description>
|
|
<addressOffset>0x00000808</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT1_DCMP0</name>
|
|
<description>Digital Comparator 0 Trigger</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT1_DCMP1</name>
|
|
<description>Digital Comparator 1 Trigger</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT1_DCMP2</name>
|
|
<description>Digital Comparator 2 Trigger</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT1_DCMP3</name>
|
|
<description>Digital Comparator 3 Trigger</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT1_DCMP4</name>
|
|
<description>Digital Comparator 4 Trigger</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT1_DCMP5</name>
|
|
<description>Digital Comparator 5 Trigger</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT1_DCMP6</name>
|
|
<description>Digital Comparator 6 Trigger</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_0_FLTSTAT1_DCMP7</name>
|
|
<description>Digital Comparator 7 Trigger</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_FLTSEN</name>
|
|
<description>PWM1 Fault Pin Logic Sense</description>
|
|
<addressOffset>0x00000880</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_FLTSEN_FAULT0</name>
|
|
<description>Fault0 Sense</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSEN_FAULT1</name>
|
|
<description>Fault1 Sense</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSEN_FAULT2</name>
|
|
<description>Fault2 Sense</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSEN_FAULT3</name>
|
|
<description>Fault3 Sense</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_FLTSTAT0</name>
|
|
<description>PWM1 Fault Status 0</description>
|
|
<addressOffset>0x00000884</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT0_FAULT0</name>
|
|
<description>Fault Input 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT0_FAULT1</name>
|
|
<description>Fault Input 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT0_FAULT2</name>
|
|
<description>Fault Input 2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT0_FAULT3</name>
|
|
<description>Fault Input 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_FLTSTAT1</name>
|
|
<description>PWM1 Fault Status 1</description>
|
|
<addressOffset>0x00000888</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT1_DCMP0</name>
|
|
<description>Digital Comparator 0 Trigger</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT1_DCMP1</name>
|
|
<description>Digital Comparator 1 Trigger</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT1_DCMP2</name>
|
|
<description>Digital Comparator 2 Trigger</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT1_DCMP3</name>
|
|
<description>Digital Comparator 3 Trigger</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT1_DCMP4</name>
|
|
<description>Digital Comparator 4 Trigger</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT1_DCMP5</name>
|
|
<description>Digital Comparator 5 Trigger</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT1_DCMP6</name>
|
|
<description>Digital Comparator 6 Trigger</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_1_FLTSTAT1_DCMP7</name>
|
|
<description>Digital Comparator 7 Trigger</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_FLTSEN</name>
|
|
<description>PWM2 Fault Pin Logic Sense</description>
|
|
<addressOffset>0x00000900</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_FLTSEN_FAULT0</name>
|
|
<description>Fault0 Sense</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSEN_FAULT1</name>
|
|
<description>Fault1 Sense</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSEN_FAULT2</name>
|
|
<description>Fault2 Sense</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSEN_FAULT3</name>
|
|
<description>Fault3 Sense</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_FLTSTAT0</name>
|
|
<description>PWM2 Fault Status 0</description>
|
|
<addressOffset>0x00000904</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT0_FAULT0</name>
|
|
<description>Fault Input 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT0_FAULT1</name>
|
|
<description>Fault Input 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT0_FAULT2</name>
|
|
<description>Fault Input 2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT0_FAULT3</name>
|
|
<description>Fault Input 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_2_FLTSTAT1</name>
|
|
<description>PWM2 Fault Status 1</description>
|
|
<addressOffset>0x00000908</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT1_DCMP0</name>
|
|
<description>Digital Comparator 0 Trigger</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT1_DCMP1</name>
|
|
<description>Digital Comparator 1 Trigger</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT1_DCMP2</name>
|
|
<description>Digital Comparator 2 Trigger</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT1_DCMP3</name>
|
|
<description>Digital Comparator 3 Trigger</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT1_DCMP4</name>
|
|
<description>Digital Comparator 4 Trigger</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT1_DCMP5</name>
|
|
<description>Digital Comparator 5 Trigger</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT1_DCMP6</name>
|
|
<description>Digital Comparator 6 Trigger</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_2_FLTSTAT1_DCMP7</name>
|
|
<description>Digital Comparator 7 Trigger</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_FLTSEN</name>
|
|
<description>PWM3 Fault Pin Logic Sense</description>
|
|
<addressOffset>0x00000980</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_FLTSEN_FAULT0</name>
|
|
<description>Fault0 Sense</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSEN_FAULT1</name>
|
|
<description>Fault1 Sense</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSEN_FAULT2</name>
|
|
<description>Fault2 Sense</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSEN_FAULT3</name>
|
|
<description>Fault3 Sense</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_FLTSTAT0</name>
|
|
<description>PWM3 Fault Status 0</description>
|
|
<addressOffset>0x00000984</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT0_FAULT0</name>
|
|
<description>Fault Input 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT0_FAULT1</name>
|
|
<description>Fault Input 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT0_FAULT2</name>
|
|
<description>Fault Input 2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT0_FAULT3</name>
|
|
<description>Fault Input 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_3_FLTSTAT1</name>
|
|
<description>PWM3 Fault Status 1</description>
|
|
<addressOffset>0x00000988</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT1_DCMP0</name>
|
|
<description>Digital Comparator 0 Trigger</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT1_DCMP1</name>
|
|
<description>Digital Comparator 1 Trigger</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT1_DCMP2</name>
|
|
<description>Digital Comparator 2 Trigger</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT1_DCMP3</name>
|
|
<description>Digital Comparator 3 Trigger</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT1_DCMP4</name>
|
|
<description>Digital Comparator 4 Trigger</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT1_DCMP5</name>
|
|
<description>Digital Comparator 5 Trigger</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT1_DCMP6</name>
|
|
<description>Digital Comparator 6 Trigger</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM_3_FLTSTAT1_DCMP7</name>
|
|
<description>Digital Comparator 7 Trigger</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>PWM Peripheral Properties</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_PP_GCNT</name>
|
|
<description>Generators</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_PP_FCNT</name>
|
|
<description>Fault Inputs (per PWM unit)</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_PP_ESYNC</name>
|
|
<description>Extended Synchronization</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_PP_EFAULT</name>
|
|
<description>Extended Fault</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_PP_ONE</name>
|
|
<description>One-Shot Mode</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC</name>
|
|
<description>PWM Clock Configuration</description>
|
|
<addressOffset>0x00000FC8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_CC_PWMDIV</name>
|
|
<description>PWM Clock Divider</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_CC_PWMDIV_2</name>
|
|
<description>/2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_CC_PWMDIV_4</name>
|
|
<description>/4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_CC_PWMDIV_8</name>
|
|
<description>/8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_CC_PWMDIV_16</name>
|
|
<description>/16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_CC_PWMDIV_32</name>
|
|
<description>/32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_CC_PWMDIV_64</name>
|
|
<description>/64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_CC_USEPWM</name>
|
|
<description>Use PWM Clock Divisor</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>QEI0</name>
|
|
<description>Register map for QEI0 peripheral</description>
|
|
<groupName>QEI</groupName>
|
|
<prependToName>QEI0</prependToName>
|
|
<baseAddress>0x4002C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>QEI0</name><value>13</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>QEI Control</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>QEI_CTL_ENABLE</name>
|
|
<description>Enable QEI</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_SWAP</name>
|
|
<description>Swap Signals</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_SIGMODE</name>
|
|
<description>Signal Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_CAPMODE</name>
|
|
<description>Capture Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_RESMODE</name>
|
|
<description>Reset Mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_VELEN</name>
|
|
<description>Capture Velocity</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_VELDIV</name>
|
|
<description>Predivide Velocity</description>
|
|
<bitRange>[8:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>QEI_CTL_VELDIV_1</name>
|
|
<description>QEI clock /1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QEI_CTL_VELDIV_2</name>
|
|
<description>QEI clock /2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QEI_CTL_VELDIV_4</name>
|
|
<description>QEI clock /4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QEI_CTL_VELDIV_8</name>
|
|
<description>QEI clock /8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QEI_CTL_VELDIV_16</name>
|
|
<description>QEI clock /16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QEI_CTL_VELDIV_32</name>
|
|
<description>QEI clock /32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QEI_CTL_VELDIV_64</name>
|
|
<description>QEI clock /64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QEI_CTL_VELDIV_128</name>
|
|
<description>QEI clock /128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_INVA</name>
|
|
<description>Invert PhA</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_INVB</name>
|
|
<description>Invert PhB</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_INVI</name>
|
|
<description>Invert Index Pulse</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_STALLEN</name>
|
|
<description>Stall QEI</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_FILTEN</name>
|
|
<description>Enable Input Filter</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CTL_FILTCNT</name>
|
|
<description>Input Filter Prescale Count</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>QEI Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>QEI_STAT_ERROR</name>
|
|
<description>Error Detected</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_STAT_DIRECTION</name>
|
|
<description>Direction of Rotation</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POS</name>
|
|
<description>QEI Position</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>QEI_POS</name>
|
|
<description>Current Position Integrator Value</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAXPOS</name>
|
|
<description>QEI Maximum Position</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>QEI_MAXPOS</name>
|
|
<description>Maximum Position Integrator Value</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOAD</name>
|
|
<description>QEI Timer Load</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>QEI_LOAD</name>
|
|
<description>Velocity Timer Load Value</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIME</name>
|
|
<description>QEI Timer</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>QEI_TIME</name>
|
|
<description>Velocity Timer Current Value</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>QEI Velocity Counter</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>QEI_COUNT</name>
|
|
<description>Velocity Pulse Count</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPEED</name>
|
|
<description>QEI Velocity</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>QEI_SPEED</name>
|
|
<description>Velocity</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>QEI Interrupt Enable</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>QEI_INTEN_INDEX</name>
|
|
<description>Index Pulse Detected Interrupt Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_INTEN_TIMER</name>
|
|
<description>Timer Expires Interrupt Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_INTEN_DIR</name>
|
|
<description>Direction Change Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_INTEN_ERROR</name>
|
|
<description>Phase Error Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>QEI Raw Interrupt Status</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>QEI_RIS_INDEX</name>
|
|
<description>Index Pulse Asserted</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_RIS_TIMER</name>
|
|
<description>Velocity Timer Expired</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_RIS_DIR</name>
|
|
<description>Direction Change Detected</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_RIS_ERROR</name>
|
|
<description>Phase Error Detected</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISC</name>
|
|
<description>QEI Interrupt Status and Clear</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>QEI_ISC_INDEX</name>
|
|
<description>Index Pulse Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_ISC_TIMER</name>
|
|
<description>Velocity Timer Expired Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_ISC_DIR</name>
|
|
<description>Direction Change Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_ISC_ERROR</name>
|
|
<description>Phase Error Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER0</name>
|
|
<description>Register map for TIMER0 peripheral</description>
|
|
<groupName>TIMER</groupName>
|
|
<prependToName>TIMER0</prependToName>
|
|
<baseAddress>0x40030000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>TIMER0A</name><value>19</value></interrupt>
|
|
<interrupt><name>TIMER0B</name><value>20</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>GPTM Configuration</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_CFG</name>
|
|
<description>GPTM Configuration</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CFG_32_BIT_TIMER</name>
|
|
<description>For a 16/32-bit timer, this value selects the 32-bit timer configuration</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CFG_32_BIT_RTC</name>
|
|
<description>For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CFG_16_BIT</name>
|
|
<description>For a 16/32-bit timer, this value selects the 16-bit timer configuration</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMR</name>
|
|
<description>GPTM Timer A Mode</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TAMR_TAMR</name>
|
|
<description>GPTM Timer A Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TAMR_1_SHOT</name>
|
|
<description>One-Shot Timer mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TAMR_PERIOD</name>
|
|
<description>Periodic Timer mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TAMR_CAP</name>
|
|
<description>Capture mode</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TACMR</name>
|
|
<description>GPTM Timer A Capture Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TAAMS</name>
|
|
<description>GPTM Timer A Alternate Mode Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TACDIR</name>
|
|
<description>GPTM Timer A Count Direction</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TAMIE</name>
|
|
<description>GPTM Timer A Match Interrupt Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TAWOT</name>
|
|
<description>GPTM Timer A Wait-on-Trigger</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TASNAPS</name>
|
|
<description>GPTM Timer A Snap-Shot Mode</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TAILD</name>
|
|
<description>GPTM Timer A Interval Load Write</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TAPWMIE</name>
|
|
<description>GPTM Timer A PWM Interrupt Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TAMRSU</name>
|
|
<description>GPTM Timer A Match Register Update</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TAPLO</name>
|
|
<description>GPTM Timer A PWM Legacy Operation</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TACINTD</name>
|
|
<description>One-shot/Periodic Interrupt Disable</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TCACT</name>
|
|
<description>Timer Compare Action Select</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TCACT_NONE</name>
|
|
<description>Disable compare operations</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TCACT_TOGGLE</name>
|
|
<description>Toggle State on Time-Out</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TCACT_CLRTO</name>
|
|
<description>Clear CCP on Time-Out</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TCACT_SETTO</name>
|
|
<description>Set CCP on Time-Out</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TCACT_SETTOGTO</name>
|
|
<description>Set CCP immediately and toggle on Time-Out</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TCACT_CLRTOGTO</name>
|
|
<description>Clear CCP immediately and toggle on Time-Out</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TCACT_SETCLRTO</name>
|
|
<description>Set CCP immediately and clear on Time-Out</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TCACT_CLRSETTO</name>
|
|
<description>Clear CCP immediately and set on Time-Out</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBMR</name>
|
|
<description>GPTM Timer B Mode</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TBMR_TBMR</name>
|
|
<description>GPTM Timer B Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TBMR_1_SHOT</name>
|
|
<description>One-Shot Timer mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TBMR_PERIOD</name>
|
|
<description>Periodic Timer mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TBMR_CAP</name>
|
|
<description>Capture mode</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBCMR</name>
|
|
<description>GPTM Timer B Capture Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBAMS</name>
|
|
<description>GPTM Timer B Alternate Mode Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBCDIR</name>
|
|
<description>GPTM Timer B Count Direction</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBMIE</name>
|
|
<description>GPTM Timer B Match Interrupt Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBWOT</name>
|
|
<description>GPTM Timer B Wait-on-Trigger</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBSNAPS</name>
|
|
<description>GPTM Timer B Snap-Shot Mode</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBILD</name>
|
|
<description>GPTM Timer B Interval Load Write</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBPWMIE</name>
|
|
<description>GPTM Timer B PWM Interrupt Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBMRSU</name>
|
|
<description>GPTM Timer B Match Register Update</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBPLO</name>
|
|
<description>GPTM Timer B PWM Legacy Operation</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBCINTD</name>
|
|
<description>One-Shot/Periodic Interrupt Disable</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TCACT</name>
|
|
<description>Timer Compare Action Select</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TCACT_NONE</name>
|
|
<description>Disable compare operations</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TCACT_TOGGLE</name>
|
|
<description>Toggle State on Time-Out</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TCACT_CLRTO</name>
|
|
<description>Clear CCP on Time-Out</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TCACT_SETTO</name>
|
|
<description>Set CCP on Time-Out</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TCACT_SETTOGTO</name>
|
|
<description>Set CCP immediately and toggle on Time-Out</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TCACT_CLRTOGTO</name>
|
|
<description>Clear CCP immediately and toggle on Time-Out</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TCACT_SETCLRTO</name>
|
|
<description>Set CCP immediately and clear on Time-Out</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TCACT_CLRSETTO</name>
|
|
<description>Clear CCP immediately and set on Time-Out</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>GPTM Control</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_CTL_TAEN</name>
|
|
<description>GPTM Timer A Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TASTALL</name>
|
|
<description>GPTM Timer A Stall Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TAEVENT</name>
|
|
<description>GPTM Timer A Event Mode</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TAEVENT_POS</name>
|
|
<description>Positive edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TAEVENT_NEG</name>
|
|
<description>Negative edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TAEVENT_BOTH</name>
|
|
<description>Both edges</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_RTCEN</name>
|
|
<description>GPTM RTC Stall Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TAOTE</name>
|
|
<description>GPTM Timer A Output Trigger Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TAPWML</name>
|
|
<description>GPTM Timer A PWM Output Level</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TBEN</name>
|
|
<description>GPTM Timer B Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TBSTALL</name>
|
|
<description>GPTM Timer B Stall Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TBEVENT</name>
|
|
<description>GPTM Timer B Event Mode</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TBEVENT_POS</name>
|
|
<description>Positive edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TBEVENT_NEG</name>
|
|
<description>Negative edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TBEVENT_BOTH</name>
|
|
<description>Both edges</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TBOTE</name>
|
|
<description>GPTM Timer B Output Trigger Enable</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TBPWML</name>
|
|
<description>GPTM Timer B PWM Output Level</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>GPTM Synchronize</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_SYNC_SYNCT0</name>
|
|
<description>Synchronize GPTM Timer 0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT0_NONE</name>
|
|
<description>GPTM0 is not affected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT0_TA</name>
|
|
<description>A timeout event for Timer A of GPTM0 is triggered</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT0_TB</name>
|
|
<description>A timeout event for Timer B of GPTM0 is triggered</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT0_TATB</name>
|
|
<description>A timeout event for both Timer A and Timer B of GPTM0 is triggered</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_SYNC_SYNCT1</name>
|
|
<description>Synchronize GPTM Timer 1</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT1_NONE</name>
|
|
<description>GPTM1 is not affected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT1_TA</name>
|
|
<description>A timeout event for Timer A of GPTM1 is triggered</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT1_TB</name>
|
|
<description>A timeout event for Timer B of GPTM1 is triggered</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT1_TATB</name>
|
|
<description>A timeout event for both Timer A and Timer B of GPTM1 is triggered</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_SYNC_SYNCT2</name>
|
|
<description>Synchronize GPTM Timer 2</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT2_NONE</name>
|
|
<description>GPTM2 is not affected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT2_TA</name>
|
|
<description>A timeout event for Timer A of GPTM2 is triggered</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT2_TB</name>
|
|
<description>A timeout event for Timer B of GPTM2 is triggered</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT2_TATB</name>
|
|
<description>A timeout event for both Timer A and Timer B of GPTM2 is triggered</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_SYNC_SYNCT3</name>
|
|
<description>Synchronize GPTM Timer 3</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT3_NONE</name>
|
|
<description>GPTM3 is not affected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT3_TA</name>
|
|
<description>A timeout event for Timer A of GPTM3 is triggered</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT3_TB</name>
|
|
<description>A timeout event for Timer B of GPTM3 is triggered</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT3_TATB</name>
|
|
<description>A timeout event for both Timer A and Timer B of GPTM3 is triggered</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_SYNC_SYNCT4</name>
|
|
<description>Synchronize GPTM Timer 4</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT4_NONE</name>
|
|
<description>GPTM4 is not affected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT4_TA</name>
|
|
<description>A timeout event for Timer A of GPTM4 is triggered</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT4_TB</name>
|
|
<description>A timeout event for Timer B of GPTM4 is triggered</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT4_TATB</name>
|
|
<description>A timeout event for both Timer A and Timer B of GPTM4 is triggered</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_SYNC_SYNCT5</name>
|
|
<description>Synchronize GPTM Timer 5</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT5_NONE</name>
|
|
<description>GPTM5 is not affected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT5_TA</name>
|
|
<description>A timeout event for Timer A of GPTM5 is triggered</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT5_TB</name>
|
|
<description>A timeout event for Timer B of GPTM5 is triggered</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT5_TATB</name>
|
|
<description>A timeout event for both Timer A and Timer B of GPTM5 is triggered</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_SYNC_SYNCT6</name>
|
|
<description>Synchronize GPTM Timer 6</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT6_NONE</name>
|
|
<description>GPTM6 is not affected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT6_TA</name>
|
|
<description>A timeout event for Timer A of GPTM6 is triggered</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT6_TB</name>
|
|
<description>A timeout event for Timer B of GPTM6 is triggered</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT6_TATB</name>
|
|
<description>A timeout event for both Timer A and Timer B of GPTM6 is triggered</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_SYNC_SYNCT7</name>
|
|
<description>Synchronize GPTM Timer 7</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT7_NONE</name>
|
|
<description>GPT7 is not affected</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT7_TA</name>
|
|
<description>A timeout event for Timer A of GPTM7 is triggered</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT7_TB</name>
|
|
<description>A timeout event for Timer B of GPTM7 is triggered</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_SYNC_SYNCT7_TATB</name>
|
|
<description>A timeout event for both Timer A and Timer B of GPTM7 is triggered</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>GPTM Interrupt Mask</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_IMR_TATOIM</name>
|
|
<description>GPTM Timer A Time-Out Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_CAMIM</name>
|
|
<description>GPTM Timer A Capture Mode Match Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_CAEIM</name>
|
|
<description>GPTM Timer A Capture Mode Event Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_RTCIM</name>
|
|
<description>GPTM RTC Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_TAMIM</name>
|
|
<description>GPTM Timer A Match Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_DMAAIM</name>
|
|
<description>GPTM Timer A DMA Done Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_TBTOIM</name>
|
|
<description>GPTM Timer B Time-Out Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_CBMIM</name>
|
|
<description>GPTM Timer B Capture Mode Match Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_CBEIM</name>
|
|
<description>GPTM Timer B Capture Mode Event Interrupt Mask</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_TBMIM</name>
|
|
<description>GPTM Timer B Match Interrupt Mask</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_DMABIM</name>
|
|
<description>GPTM Timer B DMA Done Interrupt Mask</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>GPTM Raw Interrupt Status</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_RIS_TATORIS</name>
|
|
<description>GPTM Timer A Time-Out Raw Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_CAMRIS</name>
|
|
<description>GPTM Timer A Capture Mode Match Raw Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_CAERIS</name>
|
|
<description>GPTM Timer A Capture Mode Event Raw Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_RTCRIS</name>
|
|
<description>GPTM RTC Raw Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_TAMRIS</name>
|
|
<description>GPTM Timer A Match Raw Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_DMAARIS</name>
|
|
<description>GPTM Timer A DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_TBTORIS</name>
|
|
<description>GPTM Timer B Time-Out Raw Interrupt</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_CBMRIS</name>
|
|
<description>GPTM Timer B Capture Mode Match Raw Interrupt</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_CBERIS</name>
|
|
<description>GPTM Timer B Capture Mode Event Raw Interrupt</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_TBMRIS</name>
|
|
<description>GPTM Timer B Match Raw Interrupt</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_DMABRIS</name>
|
|
<description>GPTM Timer B DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>GPTM Masked Interrupt Status</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_MIS_TATOMIS</name>
|
|
<description>GPTM Timer A Time-Out Masked Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_CAMMIS</name>
|
|
<description>GPTM Timer A Capture Mode Match Masked Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_CAEMIS</name>
|
|
<description>GPTM Timer A Capture Mode Event Masked Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_RTCMIS</name>
|
|
<description>GPTM RTC Masked Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_TAMMIS</name>
|
|
<description>GPTM Timer A Match Masked Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_DMAAMIS</name>
|
|
<description>GPTM Timer A DMA Done Masked Interrupt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_TBTOMIS</name>
|
|
<description>GPTM Timer B Time-Out Masked Interrupt</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_CBMMIS</name>
|
|
<description>GPTM Timer B Capture Mode Match Masked Interrupt</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_CBEMIS</name>
|
|
<description>GPTM Timer B Capture Mode Event Masked Interrupt</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_TBMMIS</name>
|
|
<description>GPTM Timer B Match Masked Interrupt</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_DMABMIS</name>
|
|
<description>GPTM Timer B DMA Done Masked Interrupt</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>GPTM Interrupt Clear</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_ICR_TATOCINT</name>
|
|
<description>GPTM Timer A Time-Out Raw Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_CAMCINT</name>
|
|
<description>GPTM Timer A Capture Mode Match Interrupt Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_CAECINT</name>
|
|
<description>GPTM Timer A Capture Mode Event Interrupt Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_RTCCINT</name>
|
|
<description>GPTM RTC Interrupt Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_TAMCINT</name>
|
|
<description>GPTM Timer A Match Interrupt Clear</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_DMAAINT</name>
|
|
<description>GPTM Timer A DMA Done Interrupt Clear</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_TBTOCINT</name>
|
|
<description>GPTM Timer B Time-Out Interrupt Clear</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_CBMCINT</name>
|
|
<description>GPTM Timer B Capture Mode Match Interrupt Clear</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_CBECINT</name>
|
|
<description>GPTM Timer B Capture Mode Event Interrupt Clear</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_TBMCINT</name>
|
|
<description>GPTM Timer B Match Interrupt Clear</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_DMABINT</name>
|
|
<description>GPTM Timer B DMA Done Interrupt Clear</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAILR</name>
|
|
<description>GPTM Timer A Interval Load</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TBILR</name>
|
|
<description>GPTM Timer B Interval Load</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TAMATCHR</name>
|
|
<description>GPTM Timer A Match</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TBMATCHR</name>
|
|
<description>GPTM Timer B Match</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TAPR</name>
|
|
<description>GPTM Timer A Prescale</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TAPR_TAPSR</name>
|
|
<description>GPTM Timer A Prescale</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBPR</name>
|
|
<description>GPTM Timer B Prescale</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TBPR_TBPSR</name>
|
|
<description>GPTM Timer B Prescale</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAPMR</name>
|
|
<description>GPTM TimerA Prescale Match</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TAPMR_TAPSMR</name>
|
|
<description>GPTM TimerA Prescale Match</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBPMR</name>
|
|
<description>GPTM TimerB Prescale Match</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TBPMR_TBPSMR</name>
|
|
<description>GPTM TimerB Prescale Match</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAR</name>
|
|
<description>GPTM Timer A</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TBR</name>
|
|
<description>GPTM Timer B</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TAV</name>
|
|
<description>GPTM Timer A Value</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TBV</name>
|
|
<description>GPTM Timer B Value</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>RTCPD</name>
|
|
<description>GPTM RTC Predivide</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_RTCPD_RTCPD</name>
|
|
<description>RTC Predivide Counter Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAPS</name>
|
|
<description>GPTM Timer A Prescale Snapshot</description>
|
|
<addressOffset>0x0000005C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TAPS_PSS</name>
|
|
<description>GPTM Timer A Prescaler Snapshot</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBPS</name>
|
|
<description>GPTM Timer B Prescale Snapshot</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TBPS_PSS</name>
|
|
<description>GPTM Timer A Prescaler Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAPV</name>
|
|
<description>GPTM Timer A Prescale Value</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TBPV</name>
|
|
<description>GPTM Timer B Prescale Value</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DMAEV</name>
|
|
<description>GPTM DMA Event</description>
|
|
<addressOffset>0x0000006C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_DMAEV_TATODMAEN</name>
|
|
<description>GPTM A Time-Out Event DMA Trigger Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_DMAEV_CAMDMAEN</name>
|
|
<description>GPTM A Capture Match Event DMA Trigger Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_DMAEV_CAEDMAEN</name>
|
|
<description>GPTM A Capture Event DMA Trigger Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_DMAEV_RTCDMAEN</name>
|
|
<description>GPTM A RTC Match Event DMA Trigger Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_DMAEV_TAMDMAEN</name>
|
|
<description>GPTM A Mode Match Event DMA Trigger Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_DMAEV_TBTODMAEN</name>
|
|
<description>GPTM B Time-Out Event DMA Trigger Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_DMAEV_CBMDMAEN</name>
|
|
<description>GPTM B Capture Match Event DMA Trigger Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_DMAEV_CBEDMAEN</name>
|
|
<description>GPTM B Capture Event DMA Trigger Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_DMAEV_TBMDMAEN</name>
|
|
<description>GPTM B Mode Match Event DMA Trigger Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCEV</name>
|
|
<description>GPTM ADC Event</description>
|
|
<addressOffset>0x00000070</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_ADCEV_TATOADCEN</name>
|
|
<description>GPTM A Time-Out Event ADC Trigger Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ADCEV_CAMADCEN</name>
|
|
<description>GPTM A Capture Match Event ADC Trigger Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ADCEV_CAEADCEN</name>
|
|
<description>GPTM A Capture Event ADC Trigger Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ADCEV_RTCADCEN</name>
|
|
<description>GPTM RTC Match Event ADC Trigger Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ADCEV_TAMADCEN</name>
|
|
<description>GPTM A Mode Match Event ADC Trigger Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ADCEV_TBTOADCEN</name>
|
|
<description>GPTM B Time-Out Event ADC Trigger Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ADCEV_CBMADCEN</name>
|
|
<description>GPTM B Capture Match Event ADC Trigger Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ADCEV_CBEADCEN</name>
|
|
<description>GPTM B Capture Event ADC Trigger Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ADCEV_TBMADCEN</name>
|
|
<description>GPTM B Mode Match Event ADC Trigger Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>GPTM Peripheral Properties</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_PP_SIZE</name>
|
|
<description>Count Size</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_PP_SIZE_16</name>
|
|
<description>Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_PP_SIZE_32</name>
|
|
<description>Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_PP_CHAIN</name>
|
|
<description>Chain with Other Timers</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_PP_SYNCCNT</name>
|
|
<description>Synchronize Start</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER1</name>
|
|
<prependToName>TIMER1</prependToName>
|
|
<baseAddress>0x40031000</baseAddress>
|
|
<interrupt><name>TIMER1A</name><value>21</value></interrupt>
|
|
<interrupt><name>TIMER1B</name><value>22</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER2</name>
|
|
<prependToName>TIMER2</prependToName>
|
|
<baseAddress>0x40032000</baseAddress>
|
|
<interrupt><name>TIMER2A</name><value>23</value></interrupt>
|
|
<interrupt><name>TIMER2B</name><value>24</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER3</name>
|
|
<prependToName>TIMER3</prependToName>
|
|
<baseAddress>0x40033000</baseAddress>
|
|
<interrupt><name>TIMER3A</name><value>35</value></interrupt>
|
|
<interrupt><name>TIMER3B</name><value>36</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER4</name>
|
|
<prependToName>TIMER4</prependToName>
|
|
<baseAddress>0x40034000</baseAddress>
|
|
<interrupt><name>TIMER4A</name><value>63</value></interrupt>
|
|
<interrupt><name>TIMER4B</name><value>64</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER5</name>
|
|
<prependToName>TIMER5</prependToName>
|
|
<baseAddress>0x40035000</baseAddress>
|
|
<interrupt><name>TIMER5A</name><value>65</value></interrupt>
|
|
<interrupt><name>TIMER5B</name><value>66</value></interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC0</name>
|
|
<description>Register map for ADC0 peripheral</description>
|
|
<groupName>ADC</groupName>
|
|
<prependToName>ADC0</prependToName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>ADC0SS0</name><value>14</value></interrupt>
|
|
<interrupt><name>ADC0SS1</name><value>15</value></interrupt>
|
|
<interrupt><name>ADC0SS2</name><value>16</value></interrupt>
|
|
<interrupt><name>ADC0SS3</name><value>17</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ACTSS</name>
|
|
<description>ADC Active Sample Sequencer</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_ACTSS_ASEN0</name>
|
|
<description>ADC SS0 Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACTSS_ASEN1</name>
|
|
<description>ADC SS1 Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACTSS_ASEN2</name>
|
|
<description>ADC SS2 Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACTSS_ASEN3</name>
|
|
<description>ADC SS3 Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACTSS_ADEN0</name>
|
|
<description>ADC SS1 DMA Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACTSS_ADEN1</name>
|
|
<description>ADC SS1 DMA Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACTSS_ADEN2</name>
|
|
<description>ADC SS2 DMA Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACTSS_ADEN3</name>
|
|
<description>ADC SS3 DMA Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACTSS_BUSY</name>
|
|
<description>ADC Busy</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>ADC Raw Interrupt Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_RIS_INR0</name>
|
|
<description>SS0 Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_RIS_INR1</name>
|
|
<description>SS1 Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_RIS_INR2</name>
|
|
<description>SS2 Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_RIS_INR3</name>
|
|
<description>SS3 Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_RIS_DMAINR0</name>
|
|
<description>SS0 DMA Raw Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_RIS_DMAINR1</name>
|
|
<description>SS1 DMA Raw Interrupt Status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_RIS_DMAINR2</name>
|
|
<description>SS2 DMA Raw Interrupt Status</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_RIS_DMAINR3</name>
|
|
<description>SS3 DMA Raw Interrupt Status</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_RIS_INRDC</name>
|
|
<description>Digital Comparator Raw Interrupt Status</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IM</name>
|
|
<description>ADC Interrupt Mask</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_IM_MASK0</name>
|
|
<description>SS0 Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_MASK1</name>
|
|
<description>SS1 Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_MASK2</name>
|
|
<description>SS2 Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_MASK3</name>
|
|
<description>SS3 Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_DMAMASK0</name>
|
|
<description>SS0 DMA Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_DMAMASK1</name>
|
|
<description>SS1 DMA Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_DMAMASK2</name>
|
|
<description>SS2 DMA Interrupt Mask</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_DMAMASK3</name>
|
|
<description>SS3 DMA Interrupt Mask</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_DCONSS0</name>
|
|
<description>Digital Comparator Interrupt on SS0</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_DCONSS1</name>
|
|
<description>Digital Comparator Interrupt on SS1</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_DCONSS2</name>
|
|
<description>Digital Comparator Interrupt on SS2</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_DCONSS3</name>
|
|
<description>Digital Comparator Interrupt on SS3</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISC</name>
|
|
<description>ADC Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_ISC_IN0</name>
|
|
<description>SS0 Interrupt Status and Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_IN1</name>
|
|
<description>SS1 Interrupt Status and Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_IN2</name>
|
|
<description>SS2 Interrupt Status and Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_IN3</name>
|
|
<description>SS3 Interrupt Status and Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_DMAIN0</name>
|
|
<description>SS0 DMA Interrupt Status and Clear</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_DMAIN1</name>
|
|
<description>SS1 DMA Interrupt Status and Clear</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_DMAIN2</name>
|
|
<description>SS2 DMA Interrupt Status and Clear</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_DMAIN3</name>
|
|
<description>SS3 DMA Interrupt Status and Clear</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_DCINSS0</name>
|
|
<description>Digital Comparator Interrupt Status on SS0</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_DCINSS1</name>
|
|
<description>Digital Comparator Interrupt Status on SS1</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_DCINSS2</name>
|
|
<description>Digital Comparator Interrupt Status on SS2</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_DCINSS3</name>
|
|
<description>Digital Comparator Interrupt Status on SS3</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSTAT</name>
|
|
<description>ADC Overflow Status</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_OSTAT_OV0</name>
|
|
<description>SS0 FIFO Overflow</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_OSTAT_OV1</name>
|
|
<description>SS1 FIFO Overflow</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_OSTAT_OV2</name>
|
|
<description>SS2 FIFO Overflow</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_OSTAT_OV3</name>
|
|
<description>SS3 FIFO Overflow</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMUX</name>
|
|
<description>ADC Event Multiplexer Select</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_EMUX_EM0</name>
|
|
<description>SS0 Trigger Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_PROCESSOR</name>
|
|
<description>Processor (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_COMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_COMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_COMP2</name>
|
|
<description>Analog Comparator 2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_EXTERNAL</name>
|
|
<description>External (GPIO Pins)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_TIMER</name>
|
|
<description>Timer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_PWM0</name>
|
|
<description>PWM generator 0</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_PWM1</name>
|
|
<description>PWM generator 1</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_PWM2</name>
|
|
<description>PWM generator 2</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_PWM3</name>
|
|
<description>PWM generator 3</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_NEVER</name>
|
|
<description>Never Trigger</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_ALWAYS</name>
|
|
<description>Always (continuously sample)</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_EMUX_EM1</name>
|
|
<description>SS1 Trigger Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_PROCESSOR</name>
|
|
<description>Processor (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_COMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_COMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_COMP2</name>
|
|
<description>Analog Comparator 2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_EXTERNAL</name>
|
|
<description>External (GPIO Pins)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_TIMER</name>
|
|
<description>Timer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_PWM0</name>
|
|
<description>PWM generator 0</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_PWM1</name>
|
|
<description>PWM generator 1</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_PWM2</name>
|
|
<description>PWM generator 2</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_PWM3</name>
|
|
<description>PWM generator 3</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_NEVER</name>
|
|
<description>Never Trigger</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_ALWAYS</name>
|
|
<description>Always (continuously sample)</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_EMUX_EM2</name>
|
|
<description>SS2 Trigger Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_PROCESSOR</name>
|
|
<description>Processor (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_COMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_COMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_COMP2</name>
|
|
<description>Analog Comparator 2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_EXTERNAL</name>
|
|
<description>External (GPIO Pins)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_TIMER</name>
|
|
<description>Timer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_PWM0</name>
|
|
<description>PWM generator 0</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_PWM1</name>
|
|
<description>PWM generator 1</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_PWM2</name>
|
|
<description>PWM generator 2</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_PWM3</name>
|
|
<description>PWM generator 3</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_NEVER</name>
|
|
<description>Never Trigger</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_ALWAYS</name>
|
|
<description>Always (continuously sample)</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_EMUX_EM3</name>
|
|
<description>SS3 Trigger Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_PROCESSOR</name>
|
|
<description>Processor (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_COMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_COMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_COMP2</name>
|
|
<description>Analog Comparator 2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_EXTERNAL</name>
|
|
<description>External (GPIO Pins)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_TIMER</name>
|
|
<description>Timer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_PWM0</name>
|
|
<description>PWM generator 0</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_PWM1</name>
|
|
<description>PWM generator 1</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_PWM2</name>
|
|
<description>PWM generator 2</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_PWM3</name>
|
|
<description>PWM generator 3</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_NEVER</name>
|
|
<description>Never Trigger</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_ALWAYS</name>
|
|
<description>Always (continuously sample)</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USTAT</name>
|
|
<description>ADC Underflow Status</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_USTAT_UV0</name>
|
|
<description>SS0 FIFO Underflow</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_USTAT_UV1</name>
|
|
<description>SS1 FIFO Underflow</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_USTAT_UV2</name>
|
|
<description>SS2 FIFO Underflow</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_USTAT_UV3</name>
|
|
<description>SS3 FIFO Underflow</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSSEL</name>
|
|
<description>ADC Trigger Source Select</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_TSSEL_PS0</name>
|
|
<description>Generator 0 PWM Module Trigger Select</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_TSSEL_PS0_0</name>
|
|
<description>Use Generator 0 (and its trigger) in PWM module 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_TSSEL_PS1</name>
|
|
<description>Generator 1 PWM Module Trigger Select</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_TSSEL_PS1_0</name>
|
|
<description>Use Generator 1 (and its trigger) in PWM module 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_TSSEL_PS2</name>
|
|
<description>Generator 2 PWM Module Trigger Select</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_TSSEL_PS2_0</name>
|
|
<description>Use Generator 2 (and its trigger) in PWM module 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_TSSEL_PS3</name>
|
|
<description>Generator 3 PWM Module Trigger Select</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_TSSEL_PS3_0</name>
|
|
<description>Use Generator 3 (and its trigger) in PWM module 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSPRI</name>
|
|
<description>ADC Sample Sequencer Priority</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSPRI_SS0</name>
|
|
<description>SS0 Priority</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSPRI_SS1</name>
|
|
<description>SS1 Priority</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSPRI_SS2</name>
|
|
<description>SS2 Priority</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSPRI_SS3</name>
|
|
<description>SS3 Priority</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPC</name>
|
|
<description>ADC Sample Phase Control</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SPC_PHASE</name>
|
|
<description>Phase Difference</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_0</name>
|
|
<description>ADC sample lags by 0.0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_22_5</name>
|
|
<description>ADC sample lags by 22.5</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_45</name>
|
|
<description>ADC sample lags by 45.0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_67_5</name>
|
|
<description>ADC sample lags by 67.5</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_90</name>
|
|
<description>ADC sample lags by 90.0</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_112_5</name>
|
|
<description>ADC sample lags by 112.5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_135</name>
|
|
<description>ADC sample lags by 135.0</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_157_5</name>
|
|
<description>ADC sample lags by 157.5</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_180</name>
|
|
<description>ADC sample lags by 180.0</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_202_5</name>
|
|
<description>ADC sample lags by 202.5</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_225</name>
|
|
<description>ADC sample lags by 225.0</description>
|
|
<value>0xa</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_247_5</name>
|
|
<description>ADC sample lags by 247.5</description>
|
|
<value>0xb</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_270</name>
|
|
<description>ADC sample lags by 270.0</description>
|
|
<value>0xc</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_292_5</name>
|
|
<description>ADC sample lags by 292.5</description>
|
|
<value>0xd</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_315</name>
|
|
<description>ADC sample lags by 315.0</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SPC_PHASE_337_5</name>
|
|
<description>ADC sample lags by 337.5</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSSI</name>
|
|
<description>ADC Processor Sample Sequence Initiate</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_PSSI_SS0</name>
|
|
<description>SS0 Initiate</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PSSI_SS1</name>
|
|
<description>SS1 Initiate</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PSSI_SS2</name>
|
|
<description>SS2 Initiate</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PSSI_SS3</name>
|
|
<description>SS3 Initiate</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PSSI_SYNCWAIT</name>
|
|
<description>Synchronize Wait</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PSSI_GSYNC</name>
|
|
<description>Global Synchronize</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SAC</name>
|
|
<description>ADC Sample Averaging Control</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SAC_AVG</name>
|
|
<description>Hardware Averaging Control</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_OFF</name>
|
|
<description>No hardware oversampling</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_2X</name>
|
|
<description>2x hardware oversampling</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_4X</name>
|
|
<description>4x hardware oversampling</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_8X</name>
|
|
<description>8x hardware oversampling</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_16X</name>
|
|
<description>16x hardware oversampling</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_32X</name>
|
|
<description>32x hardware oversampling</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_64X</name>
|
|
<description>64x hardware oversampling</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCISC</name>
|
|
<description>ADC Digital Comparator Interrupt Status and Clear</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCISC_DCINT0</name>
|
|
<description>Digital Comparator 0 Interrupt Status and Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCISC_DCINT1</name>
|
|
<description>Digital Comparator 1 Interrupt Status and Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCISC_DCINT2</name>
|
|
<description>Digital Comparator 2 Interrupt Status and Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCISC_DCINT3</name>
|
|
<description>Digital Comparator 3 Interrupt Status and Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCISC_DCINT4</name>
|
|
<description>Digital Comparator 4 Interrupt Status and Clear</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCISC_DCINT5</name>
|
|
<description>Digital Comparator 5 Interrupt Status and Clear</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCISC_DCINT6</name>
|
|
<description>Digital Comparator 6 Interrupt Status and Clear</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCISC_DCINT7</name>
|
|
<description>Digital Comparator 7 Interrupt Status and Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>ADC Control</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_CTL_VREF</name>
|
|
<description>Voltage Reference Select</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_CTL_VREF_INTERNAL</name>
|
|
<description>VDDA and GNDA are the voltage references</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_CTL_VREF_EXT_3V</name>
|
|
<description>The external VREFA+ and VREFA- inputs are the voltage references</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_CTL_DITHER</name>
|
|
<description>Dither Mode Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSMUX0</name>
|
|
<description>ADC Sample Sequence Input Multiplexer Select 0</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX0</name>
|
|
<description>1st Sample Input Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX1</name>
|
|
<description>2nd Sample Input Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX2</name>
|
|
<description>3rd Sample Input Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX3</name>
|
|
<description>4th Sample Input Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX4</name>
|
|
<description>5th Sample Input Select</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX5</name>
|
|
<description>6th Sample Input Select</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX6</name>
|
|
<description>7th Sample Input Select</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX7</name>
|
|
<description>8th Sample Input Select</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSCTL0</name>
|
|
<description>ADC Sample Sequence Control 0</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSCTL0_D0</name>
|
|
<description>1st Sample Differential Input Select</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END0</name>
|
|
<description>1st Sample is End of Sequence</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE0</name>
|
|
<description>1st Sample Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS0</name>
|
|
<description>1st Sample Temp Sensor Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D1</name>
|
|
<description>2nd Sample Differential Input Select</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END1</name>
|
|
<description>2nd Sample is End of Sequence</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE1</name>
|
|
<description>2nd Sample Interrupt Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS1</name>
|
|
<description>2nd Sample Temp Sensor Select</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D2</name>
|
|
<description>3rd Sample Differential Input Select</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END2</name>
|
|
<description>3rd Sample is End of Sequence</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE2</name>
|
|
<description>3rd Sample Interrupt Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS2</name>
|
|
<description>3rd Sample Temp Sensor Select</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D3</name>
|
|
<description>4th Sample Differential Input Select</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END3</name>
|
|
<description>4th Sample is End of Sequence</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE3</name>
|
|
<description>4th Sample Interrupt Enable</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS3</name>
|
|
<description>4th Sample Temp Sensor Select</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D4</name>
|
|
<description>5th Sample Differential Input Select</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END4</name>
|
|
<description>5th Sample is End of Sequence</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE4</name>
|
|
<description>5th Sample Interrupt Enable</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS4</name>
|
|
<description>5th Sample Temp Sensor Select</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D5</name>
|
|
<description>6th Sample Differential Input Select</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END5</name>
|
|
<description>6th Sample is End of Sequence</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE5</name>
|
|
<description>6th Sample Interrupt Enable</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS5</name>
|
|
<description>6th Sample Temp Sensor Select</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D6</name>
|
|
<description>7th Sample Differential Input Select</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END6</name>
|
|
<description>7th Sample is End of Sequence</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE6</name>
|
|
<description>7th Sample Interrupt Enable</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS6</name>
|
|
<description>7th Sample Temp Sensor Select</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D7</name>
|
|
<description>8th Sample Differential Input Select</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END7</name>
|
|
<description>8th Sample is End of Sequence</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE7</name>
|
|
<description>8th Sample Interrupt Enable</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS7</name>
|
|
<description>8th Sample Temp Sensor Select</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFIFO0</name>
|
|
<description>ADC Sample Sequence Result FIFO 0</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFIFO0_DATA</name>
|
|
<description>Conversion Result Data</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFSTAT0</name>
|
|
<description>ADC Sample Sequence FIFO 0 Status</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFSTAT0_TPTR</name>
|
|
<description>FIFO Tail Pointer</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT0_HPTR</name>
|
|
<description>FIFO Head Pointer</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT0_EMPTY</name>
|
|
<description>FIFO Empty</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT0_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSOP0</name>
|
|
<description>ADC Sample Sequence 0 Operation</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSOP0_S0DCOP</name>
|
|
<description>Sample 0 Digital Comparator Operation</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP0_S1DCOP</name>
|
|
<description>Sample 1 Digital Comparator Operation</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP0_S2DCOP</name>
|
|
<description>Sample 2 Digital Comparator Operation</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP0_S3DCOP</name>
|
|
<description>Sample 3 Digital Comparator Operation</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP0_S4DCOP</name>
|
|
<description>Sample 4 Digital Comparator Operation</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP0_S5DCOP</name>
|
|
<description>Sample 5 Digital Comparator Operation</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP0_S6DCOP</name>
|
|
<description>Sample 6 Digital Comparator Operation</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP0_S7DCOP</name>
|
|
<description>Sample 7 Digital Comparator Operation</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSDC0</name>
|
|
<description>ADC Sample Sequence 0 Digital Comparator Select</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSDC0_S0DCSEL</name>
|
|
<description>Sample 0 Digital Comparator Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC0_S1DCSEL</name>
|
|
<description>Sample 1 Digital Comparator Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC0_S2DCSEL</name>
|
|
<description>Sample 2 Digital Comparator Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC0_S3DCSEL</name>
|
|
<description>Sample 3 Digital Comparator Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC0_S4DCSEL</name>
|
|
<description>Sample 4 Digital Comparator Select</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC0_S5DCSEL</name>
|
|
<description>Sample 5 Digital Comparator Select</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC0_S6DCSEL</name>
|
|
<description>Sample 6 Digital Comparator Select</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC0_S7DCSEL</name>
|
|
<description>Sample 7 Digital Comparator Select</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSEMUX0</name>
|
|
<description>ADC Sample Sequence Extended Input Multiplexer Select 0</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSEMUX0_EMUX0</name>
|
|
<description>1st Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX0_EMUX1</name>
|
|
<description>2th Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX0_EMUX2</name>
|
|
<description>3rd Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX0_EMUX3</name>
|
|
<description>4th Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX0_EMUX4</name>
|
|
<description>5th Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX0_EMUX5</name>
|
|
<description>6th Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX0_EMUX6</name>
|
|
<description>7th Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX0_EMUX7</name>
|
|
<description>8th Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSTSH0</name>
|
|
<description>ADC Sample Sequence 0 Sample and Hold Time</description>
|
|
<addressOffset>0x0000005C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSTSH0_TSH0</name>
|
|
<description>1st Sample and Hold Period Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH0_TSH1</name>
|
|
<description>2nd Sample and Hold Period Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH0_TSH2</name>
|
|
<description>3rd Sample and Hold Period Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH0_TSH3</name>
|
|
<description>4th Sample and Hold Period Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH0_TSH4</name>
|
|
<description>5th Sample and Hold Period Select</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH0_TSH5</name>
|
|
<description>6th Sample and Hold Period Select</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH0_TSH6</name>
|
|
<description>7th Sample and Hold Period Select</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH0_TSH7</name>
|
|
<description>8th Sample and Hold Period Select</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSMUX1</name>
|
|
<description>ADC Sample Sequence Input Multiplexer Select 1</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSMUX1_MUX0</name>
|
|
<description>1st Sample Input Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX1_MUX1</name>
|
|
<description>2nd Sample Input Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX1_MUX2</name>
|
|
<description>3rd Sample Input Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX1_MUX3</name>
|
|
<description>4th Sample Input Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSCTL1</name>
|
|
<description>ADC Sample Sequence Control 1</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSCTL1_D0</name>
|
|
<description>1st Sample Differential Input Select</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_END0</name>
|
|
<description>1st Sample is End of Sequence</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_IE0</name>
|
|
<description>1st Sample Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_TS0</name>
|
|
<description>1st Sample Temp Sensor Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_D1</name>
|
|
<description>2nd Sample Differential Input Select</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_END1</name>
|
|
<description>2nd Sample is End of Sequence</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_IE1</name>
|
|
<description>2nd Sample Interrupt Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_TS1</name>
|
|
<description>2nd Sample Temp Sensor Select</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_D2</name>
|
|
<description>3rd Sample Differential Input Select</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_END2</name>
|
|
<description>3rd Sample is End of Sequence</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_IE2</name>
|
|
<description>3rd Sample Interrupt Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_TS2</name>
|
|
<description>3rd Sample Temp Sensor Select</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_D3</name>
|
|
<description>4th Sample Differential Input Select</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_END3</name>
|
|
<description>4th Sample is End of Sequence</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_IE3</name>
|
|
<description>4th Sample Interrupt Enable</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_TS3</name>
|
|
<description>4th Sample Temp Sensor Select</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFIFO1</name>
|
|
<description>ADC Sample Sequence Result FIFO 1</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFIFO1_DATA</name>
|
|
<description>Conversion Result Data</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFSTAT1</name>
|
|
<description>ADC Sample Sequence FIFO 1 Status</description>
|
|
<addressOffset>0x0000006C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFSTAT1_TPTR</name>
|
|
<description>FIFO Tail Pointer</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT1_HPTR</name>
|
|
<description>FIFO Head Pointer</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT1_EMPTY</name>
|
|
<description>FIFO Empty</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT1_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSOP1</name>
|
|
<description>ADC Sample Sequence 1 Operation</description>
|
|
<addressOffset>0x00000070</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSOP1_S0DCOP</name>
|
|
<description>Sample 0 Digital Comparator Operation</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP1_S1DCOP</name>
|
|
<description>Sample 1 Digital Comparator Operation</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP1_S2DCOP</name>
|
|
<description>Sample 2 Digital Comparator Operation</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP1_S3DCOP</name>
|
|
<description>Sample 3 Digital Comparator Operation</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSDC1</name>
|
|
<description>ADC Sample Sequence 1 Digital Comparator Select</description>
|
|
<addressOffset>0x00000074</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSDC1_S0DCSEL</name>
|
|
<description>Sample 0 Digital Comparator Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC1_S1DCSEL</name>
|
|
<description>Sample 1 Digital Comparator Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC1_S2DCSEL</name>
|
|
<description>Sample 2 Digital Comparator Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC1_S3DCSEL</name>
|
|
<description>Sample 3 Digital Comparator Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSEMUX1</name>
|
|
<description>ADC Sample Sequence Extended Input Multiplexer Select 1</description>
|
|
<addressOffset>0x00000078</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSEMUX1_EMUX0</name>
|
|
<description>1st Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX1_EMUX1</name>
|
|
<description>2th Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX1_EMUX2</name>
|
|
<description>3rd Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX1_EMUX3</name>
|
|
<description>4th Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSTSH1</name>
|
|
<description>ADC Sample Sequence 1 Sample and Hold Time</description>
|
|
<addressOffset>0x0000007C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSTSH1_TSH0</name>
|
|
<description>1st Sample and Hold Period Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH1_TSH1</name>
|
|
<description>2nd Sample and Hold Period Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH1_TSH2</name>
|
|
<description>3rd Sample and Hold Period Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH1_TSH3</name>
|
|
<description>4th Sample and Hold Period Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSMUX2</name>
|
|
<description>ADC Sample Sequence Input Multiplexer Select 2</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSMUX2_MUX0</name>
|
|
<description>1st Sample Input Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX2_MUX1</name>
|
|
<description>2nd Sample Input Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX2_MUX2</name>
|
|
<description>3rd Sample Input Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX2_MUX3</name>
|
|
<description>4th Sample Input Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSCTL2</name>
|
|
<description>ADC Sample Sequence Control 2</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSCTL2_D0</name>
|
|
<description>1st Sample Differential Input Select</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_END0</name>
|
|
<description>1st Sample is End of Sequence</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_IE0</name>
|
|
<description>1st Sample Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_TS0</name>
|
|
<description>1st Sample Temp Sensor Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_D1</name>
|
|
<description>2nd Sample Differential Input Select</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_END1</name>
|
|
<description>2nd Sample is End of Sequence</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_IE1</name>
|
|
<description>2nd Sample Interrupt Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_TS1</name>
|
|
<description>2nd Sample Temp Sensor Select</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_D2</name>
|
|
<description>3rd Sample Differential Input Select</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_END2</name>
|
|
<description>3rd Sample is End of Sequence</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_IE2</name>
|
|
<description>3rd Sample Interrupt Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_TS2</name>
|
|
<description>3rd Sample Temp Sensor Select</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_D3</name>
|
|
<description>4th Sample Differential Input Select</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_END3</name>
|
|
<description>4th Sample is End of Sequence</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_IE3</name>
|
|
<description>4th Sample Interrupt Enable</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_TS3</name>
|
|
<description>4th Sample Temp Sensor Select</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFIFO2</name>
|
|
<description>ADC Sample Sequence Result FIFO 2</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFIFO2_DATA</name>
|
|
<description>Conversion Result Data</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFSTAT2</name>
|
|
<description>ADC Sample Sequence FIFO 2 Status</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFSTAT2_TPTR</name>
|
|
<description>FIFO Tail Pointer</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT2_HPTR</name>
|
|
<description>FIFO Head Pointer</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT2_EMPTY</name>
|
|
<description>FIFO Empty</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT2_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSOP2</name>
|
|
<description>ADC Sample Sequence 2 Operation</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSOP2_S0DCOP</name>
|
|
<description>Sample 0 Digital Comparator Operation</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP2_S1DCOP</name>
|
|
<description>Sample 1 Digital Comparator Operation</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP2_S2DCOP</name>
|
|
<description>Sample 2 Digital Comparator Operation</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSOP2_S3DCOP</name>
|
|
<description>Sample 3 Digital Comparator Operation</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSDC2</name>
|
|
<description>ADC Sample Sequence 2 Digital Comparator Select</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSDC2_S0DCSEL</name>
|
|
<description>Sample 0 Digital Comparator Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC2_S1DCSEL</name>
|
|
<description>Sample 1 Digital Comparator Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC2_S2DCSEL</name>
|
|
<description>Sample 2 Digital Comparator Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSDC2_S3DCSEL</name>
|
|
<description>Sample 3 Digital Comparator Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSEMUX2</name>
|
|
<description>ADC Sample Sequence Extended Input Multiplexer Select 2</description>
|
|
<addressOffset>0x00000098</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSEMUX2_EMUX0</name>
|
|
<description>1st Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX2_EMUX1</name>
|
|
<description>2th Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX2_EMUX2</name>
|
|
<description>3rd Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSEMUX2_EMUX3</name>
|
|
<description>4th Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSTSH2</name>
|
|
<description>ADC Sample Sequence 2 Sample and Hold Time</description>
|
|
<addressOffset>0x0000009C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSTSH2_TSH0</name>
|
|
<description>1st Sample and Hold Period Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH2_TSH1</name>
|
|
<description>2nd Sample and Hold Period Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH2_TSH2</name>
|
|
<description>3rd Sample and Hold Period Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSTSH2_TSH3</name>
|
|
<description>4th Sample and Hold Period Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSMUX3</name>
|
|
<description>ADC Sample Sequence Input Multiplexer Select 3</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSMUX3_MUX0</name>
|
|
<description>1st Sample Input Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSCTL3</name>
|
|
<description>ADC Sample Sequence Control 3</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSCTL3_D0</name>
|
|
<description>Sample Differential Input Select</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL3_END0</name>
|
|
<description>End of Sequence</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL3_IE0</name>
|
|
<description>Sample Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL3_TS0</name>
|
|
<description>1st Sample Temp Sensor Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFIFO3</name>
|
|
<description>ADC Sample Sequence Result FIFO 3</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFIFO3_DATA</name>
|
|
<description>Conversion Result Data</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFSTAT3</name>
|
|
<description>ADC Sample Sequence FIFO 3 Status</description>
|
|
<addressOffset>0x000000AC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFSTAT3_TPTR</name>
|
|
<description>FIFO Tail Pointer</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT3_HPTR</name>
|
|
<description>FIFO Head Pointer</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT3_EMPTY</name>
|
|
<description>FIFO Empty</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT3_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSOP3</name>
|
|
<description>ADC Sample Sequence 3 Operation</description>
|
|
<addressOffset>0x000000B0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSOP3_S0DCOP</name>
|
|
<description>Sample 0 Digital Comparator Operation</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSDC3</name>
|
|
<description>ADC Sample Sequence 3 Digital Comparator Select</description>
|
|
<addressOffset>0x000000B4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSDC3_S0DCSEL</name>
|
|
<description>Sample 0 Digital Comparator Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSEMUX3</name>
|
|
<description>ADC Sample Sequence Extended Input Multiplexer Select 3</description>
|
|
<addressOffset>0x000000B8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSEMUX3_EMUX0</name>
|
|
<description>1st Sample Input Select (Upper Bit)</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSTSH3</name>
|
|
<description>ADC Sample Sequence 3 Sample and Hold Time</description>
|
|
<addressOffset>0x000000BC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSTSH3_TSH0</name>
|
|
<description>1st Sample and Hold Period Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCRIC</name>
|
|
<description>ADC Digital Comparator Reset Initial Conditions</description>
|
|
<addressOffset>0x00000D00</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCRIC_DCINT0</name>
|
|
<description>Digital Comparator Interrupt 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCINT1</name>
|
|
<description>Digital Comparator Interrupt 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCINT2</name>
|
|
<description>Digital Comparator Interrupt 2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCINT3</name>
|
|
<description>Digital Comparator Interrupt 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCINT4</name>
|
|
<description>Digital Comparator Interrupt 4</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCINT5</name>
|
|
<description>Digital Comparator Interrupt 5</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCINT6</name>
|
|
<description>Digital Comparator Interrupt 6</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCINT7</name>
|
|
<description>Digital Comparator Interrupt 7</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCTRIG0</name>
|
|
<description>Digital Comparator Trigger 0</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCTRIG1</name>
|
|
<description>Digital Comparator Trigger 1</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCTRIG2</name>
|
|
<description>Digital Comparator Trigger 2</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCTRIG3</name>
|
|
<description>Digital Comparator Trigger 3</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCTRIG4</name>
|
|
<description>Digital Comparator Trigger 4</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCTRIG5</name>
|
|
<description>Digital Comparator Trigger 5</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCTRIG6</name>
|
|
<description>Digital Comparator Trigger 6</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCRIC_DCTRIG7</name>
|
|
<description>Digital Comparator Trigger 7</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCTL0</name>
|
|
<description>ADC Digital Comparator Control 0</description>
|
|
<addressOffset>0x00000E00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCTL0_CIM</name>
|
|
<description>Comparison Interrupt Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CIM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CIM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CIM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CIM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL0_CIC</name>
|
|
<description>Comparison Interrupt Condition</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CIC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CIC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CIC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL0_CIE</name>
|
|
<description>Comparison Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL0_CTM</name>
|
|
<description>Comparison Trigger Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CTM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CTM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CTM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CTM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL0_CTC</name>
|
|
<description>Comparison Trigger Condition</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CTC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CTC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL0_CTC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL0_CTE</name>
|
|
<description>Comparison Trigger Enable</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCTL1</name>
|
|
<description>ADC Digital Comparator Control 1</description>
|
|
<addressOffset>0x00000E04</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCTL1_CIM</name>
|
|
<description>Comparison Interrupt Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CIM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CIM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CIM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CIM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL1_CIC</name>
|
|
<description>Comparison Interrupt Condition</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CIC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CIC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CIC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL1_CIE</name>
|
|
<description>Comparison Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL1_CTM</name>
|
|
<description>Comparison Trigger Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CTM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CTM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CTM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CTM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL1_CTC</name>
|
|
<description>Comparison Trigger Condition</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CTC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CTC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL1_CTC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL1_CTE</name>
|
|
<description>Comparison Trigger Enable</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCTL2</name>
|
|
<description>ADC Digital Comparator Control 2</description>
|
|
<addressOffset>0x00000E08</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCTL2_CIM</name>
|
|
<description>Comparison Interrupt Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CIM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CIM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CIM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CIM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL2_CIC</name>
|
|
<description>Comparison Interrupt Condition</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CIC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CIC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CIC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL2_CIE</name>
|
|
<description>Comparison Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL2_CTM</name>
|
|
<description>Comparison Trigger Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CTM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CTM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CTM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CTM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL2_CTC</name>
|
|
<description>Comparison Trigger Condition</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CTC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CTC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL2_CTC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL2_CTE</name>
|
|
<description>Comparison Trigger Enable</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCTL3</name>
|
|
<description>ADC Digital Comparator Control 3</description>
|
|
<addressOffset>0x00000E0C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCTL3_CIM</name>
|
|
<description>Comparison Interrupt Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CIM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CIM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CIM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CIM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL3_CIC</name>
|
|
<description>Comparison Interrupt Condition</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CIC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CIC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CIC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL3_CIE</name>
|
|
<description>Comparison Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL3_CTM</name>
|
|
<description>Comparison Trigger Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CTM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CTM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CTM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CTM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL3_CTC</name>
|
|
<description>Comparison Trigger Condition</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CTC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CTC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL3_CTC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL3_CTE</name>
|
|
<description>Comparison Trigger Enable</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCTL4</name>
|
|
<description>ADC Digital Comparator Control 4</description>
|
|
<addressOffset>0x00000E10</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCTL4_CIM</name>
|
|
<description>Comparison Interrupt Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CIM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CIM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CIM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CIM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL4_CIC</name>
|
|
<description>Comparison Interrupt Condition</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CIC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CIC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CIC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL4_CIE</name>
|
|
<description>Comparison Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL4_CTM</name>
|
|
<description>Comparison Trigger Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CTM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CTM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CTM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CTM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL4_CTC</name>
|
|
<description>Comparison Trigger Condition</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CTC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CTC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL4_CTC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL4_CTE</name>
|
|
<description>Comparison Trigger Enable</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCTL5</name>
|
|
<description>ADC Digital Comparator Control 5</description>
|
|
<addressOffset>0x00000E14</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCTL5_CIM</name>
|
|
<description>Comparison Interrupt Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CIM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CIM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CIM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CIM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL5_CIC</name>
|
|
<description>Comparison Interrupt Condition</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CIC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CIC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CIC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL5_CIE</name>
|
|
<description>Comparison Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL5_CTM</name>
|
|
<description>Comparison Trigger Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CTM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CTM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CTM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CTM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL5_CTC</name>
|
|
<description>Comparison Trigger Condition</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CTC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CTC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL5_CTC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL5_CTE</name>
|
|
<description>Comparison Trigger Enable</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCTL6</name>
|
|
<description>ADC Digital Comparator Control 6</description>
|
|
<addressOffset>0x00000E18</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCTL6_CIM</name>
|
|
<description>Comparison Interrupt Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CIM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CIM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CIM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CIM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL6_CIC</name>
|
|
<description>Comparison Interrupt Condition</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CIC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CIC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CIC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL6_CIE</name>
|
|
<description>Comparison Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL6_CTM</name>
|
|
<description>Comparison Trigger Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CTM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CTM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CTM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CTM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL6_CTC</name>
|
|
<description>Comparison Trigger Condition</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CTC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CTC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL6_CTC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL6_CTE</name>
|
|
<description>Comparison Trigger Enable</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCTL7</name>
|
|
<description>ADC Digital Comparator Control 7</description>
|
|
<addressOffset>0x00000E1C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCTL7_CIM</name>
|
|
<description>Comparison Interrupt Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CIM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CIM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CIM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CIM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL7_CIC</name>
|
|
<description>Comparison Interrupt Condition</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CIC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CIC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CIC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL7_CIE</name>
|
|
<description>Comparison Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL7_CTM</name>
|
|
<description>Comparison Trigger Mode</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CTM_ALWAYS</name>
|
|
<description>Always</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CTM_ONCE</name>
|
|
<description>Once</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CTM_HALWAYS</name>
|
|
<description>Hysteresis Always</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CTM_HONCE</name>
|
|
<description>Hysteresis Once</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL7_CTC</name>
|
|
<description>Comparison Trigger Condition</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CTC_LOW</name>
|
|
<description>Low Band</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CTC_MID</name>
|
|
<description>Mid Band</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_DCCTL7_CTC_HIGH</name>
|
|
<description>High Band</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCTL7_CTE</name>
|
|
<description>Comparison Trigger Enable</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCMP0</name>
|
|
<description>ADC Digital Comparator Range 0</description>
|
|
<addressOffset>0x00000E40</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCMP0_COMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCMP0_COMP1</name>
|
|
<description>Compare 1</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCMP1</name>
|
|
<description>ADC Digital Comparator Range 1</description>
|
|
<addressOffset>0x00000E44</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCMP1_COMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCMP1_COMP1</name>
|
|
<description>Compare 1</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCMP2</name>
|
|
<description>ADC Digital Comparator Range 2</description>
|
|
<addressOffset>0x00000E48</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCMP2_COMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCMP2_COMP1</name>
|
|
<description>Compare 1</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCMP3</name>
|
|
<description>ADC Digital Comparator Range 3</description>
|
|
<addressOffset>0x00000E4C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCMP3_COMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCMP3_COMP1</name>
|
|
<description>Compare 1</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCMP4</name>
|
|
<description>ADC Digital Comparator Range 4</description>
|
|
<addressOffset>0x00000E50</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCMP4_COMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCMP4_COMP1</name>
|
|
<description>Compare 1</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCMP5</name>
|
|
<description>ADC Digital Comparator Range 5</description>
|
|
<addressOffset>0x00000E54</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCMP5_COMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCMP5_COMP1</name>
|
|
<description>Compare 1</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCMP6</name>
|
|
<description>ADC Digital Comparator Range 6</description>
|
|
<addressOffset>0x00000E58</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCMP6_COMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCMP6_COMP1</name>
|
|
<description>Compare 1</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCMP7</name>
|
|
<description>ADC Digital Comparator Range 7</description>
|
|
<addressOffset>0x00000E5C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_DCCMP7_COMP0</name>
|
|
<description>Compare 0</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DCCMP7_COMP1</name>
|
|
<description>Compare 1</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>ADC Peripheral Properties</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_PP_MCR</name>
|
|
<description>Maximum Conversion Rate</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_PP_MCR_FULL</name>
|
|
<description>Full conversion rate (FCONV) as defined by TADC and NSH</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PP_CH</name>
|
|
<description>ADC Channel Count</description>
|
|
<bitRange>[9:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PP_DC</name>
|
|
<description>Digital Comparator Count</description>
|
|
<bitRange>[15:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PP_TYPE</name>
|
|
<description>ADC Architecture</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_PP_TYPE_SAR</name>
|
|
<description>SAR</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PP_RSL</name>
|
|
<description>Resolution</description>
|
|
<bitRange>[22:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PP_TS</name>
|
|
<description>Temperature Sensor</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PP_APSHT</name>
|
|
<description>Application-Programmable Sample-and-Hold Time</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>ADC Peripheral Configuration</description>
|
|
<addressOffset>0x00000FC4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_PC_MCR</name>
|
|
<description>Conversion Rate</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_PC_MCR_1_8</name>
|
|
<description>Eighth conversion rate. After a conversion completes, the logic pauses for 112 TADC periods before starting the next conversion</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_PC_MCR_1_4</name>
|
|
<description>Quarter conversion rate. After a conversion completes, the logic pauses for 48 TADC periods before starting the next conversion</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_PC_MCR_1_2</name>
|
|
<description>Half conversion rate. After a conversion completes, the logic pauses for 16 TADC periods before starting the next conversion</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_PC_MCR_FULL</name>
|
|
<description>Full conversion rate (FCONV) as defined by TADC and NSH</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC</name>
|
|
<description>ADC Clock Configuration</description>
|
|
<addressOffset>0x00000FC8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_CC_CS</name>
|
|
<description>ADC Clock Source</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_CC_CS_SYSPLL</name>
|
|
<description>PLL VCO divided by CLKDIV</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_CC_CS_PIOSC</name>
|
|
<description>PIOSC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_CC_CS_MOSC</name>
|
|
<description>MOSC</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_CC_CLKDIV</name>
|
|
<description>PLL VCO Clock Divisor</description>
|
|
<bitRange>[9:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ADC0">
|
|
<name>ADC1</name>
|
|
<prependToName>ADC1</prependToName>
|
|
<baseAddress>0x40039000</baseAddress>
|
|
<interrupt><name>ADC1SS0</name><value>46</value></interrupt>
|
|
<interrupt><name>ADC1SS1</name><value>47</value></interrupt>
|
|
<interrupt><name>ADC1SS2</name><value>48</value></interrupt>
|
|
<interrupt><name>ADC1SS3</name><value>49</value></interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>COMP</name>
|
|
<description>Register map for COMP peripheral</description>
|
|
<groupName>COMP</groupName>
|
|
<prependToName>COMP</prependToName>
|
|
<baseAddress>0x4003C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>COMP0</name><value>25</value></interrupt>
|
|
<interrupt><name>COMP1</name><value>26</value></interrupt>
|
|
<interrupt><name>COMP2</name><value>27</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ACMIS</name>
|
|
<description>Analog Comparator Masked Interrupt Status</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACMIS_IN0</name>
|
|
<description>Comparator 0 Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACMIS_IN1</name>
|
|
<description>Comparator 1 Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACMIS_IN2</name>
|
|
<description>Comparator 2 Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACRIS</name>
|
|
<description>Analog Comparator Raw Interrupt Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACRIS_IN0</name>
|
|
<description>Comparator 0 Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACRIS_IN1</name>
|
|
<description>Comparator 1 Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACRIS_IN2</name>
|
|
<description>Comparator 2 Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACINTEN</name>
|
|
<description>Analog Comparator Interrupt Enable</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACINTEN_IN0</name>
|
|
<description>Comparator 0 Interrupt Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACINTEN_IN1</name>
|
|
<description>Comparator 1 Interrupt Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACINTEN_IN2</name>
|
|
<description>Comparator 2 Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACREFCTL</name>
|
|
<description>Analog Comparator Reference Voltage Control</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACREFCTL_VREF</name>
|
|
<description>Resistor Ladder Voltage Ref</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACREFCTL_RNG</name>
|
|
<description>Resistor Ladder Range</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACREFCTL_EN</name>
|
|
<description>Resistor Ladder Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACSTAT0</name>
|
|
<description>Analog Comparator Status 0</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACSTAT0_OVAL</name>
|
|
<description>Comparator Output Value</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACCTL0</name>
|
|
<description>Analog Comparator Control 0</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACCTL0_CINV</name>
|
|
<description>Comparator Output Invert</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_ISEN</name>
|
|
<description>Interrupt Sense</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ISEN_LEVEL</name>
|
|
<description>Level sense, see ISLVAL</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ISEN_FALL</name>
|
|
<description>Falling edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ISEN_RISE</name>
|
|
<description>Rising edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ISEN_BOTH</name>
|
|
<description>Either edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_ISLVAL</name>
|
|
<description>Interrupt Sense Level Value</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_TSEN</name>
|
|
<description>Trigger Sense</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_TSEN_LEVEL</name>
|
|
<description>Level sense, see TSLVAL</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_TSEN_FALL</name>
|
|
<description>Falling edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_TSEN_RISE</name>
|
|
<description>Rising edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_TSEN_BOTH</name>
|
|
<description>Either edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_TSLVAL</name>
|
|
<description>Trigger Sense Level Value</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_ASRCP</name>
|
|
<description>Analog Source Positive</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ASRCP_PIN</name>
|
|
<description>Pin value of Cn+</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ASRCP_PIN0</name>
|
|
<description>Pin value of C0+</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ASRCP_REF</name>
|
|
<description>Internal voltage reference</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_TOEN</name>
|
|
<description>Trigger Output Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACSTAT1</name>
|
|
<description>Analog Comparator Status 1</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACSTAT1_OVAL</name>
|
|
<description>Comparator Output Value</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACCTL1</name>
|
|
<description>Analog Comparator Control 1</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACCTL1_CINV</name>
|
|
<description>Comparator Output Invert</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL1_ISEN</name>
|
|
<description>Interrupt Sense</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL1_ISEN_LEVEL</name>
|
|
<description>Level sense, see ISLVAL</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL1_ISEN_FALL</name>
|
|
<description>Falling edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL1_ISEN_RISE</name>
|
|
<description>Rising edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL1_ISEN_BOTH</name>
|
|
<description>Either edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL1_ISLVAL</name>
|
|
<description>Interrupt Sense Level Value</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL1_TSEN</name>
|
|
<description>Trigger Sense</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL1_TSEN_LEVEL</name>
|
|
<description>Level sense, see TSLVAL</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL1_TSEN_FALL</name>
|
|
<description>Falling edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL1_TSEN_RISE</name>
|
|
<description>Rising edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL1_TSEN_BOTH</name>
|
|
<description>Either edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL1_TSLVAL</name>
|
|
<description>Trigger Sense Level Value</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL1_ASRCP</name>
|
|
<description>Analog Source Positive</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL1_ASRCP_PIN</name>
|
|
<description>Pin value of Cn+</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL1_ASRCP_PIN0</name>
|
|
<description>Pin value of C0+</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL1_ASRCP_REF</name>
|
|
<description>Internal voltage reference</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL1_TOEN</name>
|
|
<description>Trigger Output Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACSTAT2</name>
|
|
<description>Analog Comparator Status 2</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACSTAT2_OVAL</name>
|
|
<description>Comparator Output Value</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACCTL2</name>
|
|
<description>Analog Comparator Control 2</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACCTL2_CINV</name>
|
|
<description>Comparator Output Invert</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL2_ISEN</name>
|
|
<description>Interrupt Sense</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL2_ISEN_LEVEL</name>
|
|
<description>Level sense, see ISLVAL</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL2_ISEN_FALL</name>
|
|
<description>Falling edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL2_ISEN_RISE</name>
|
|
<description>Rising edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL2_ISEN_BOTH</name>
|
|
<description>Either edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL2_ISLVAL</name>
|
|
<description>Interrupt Sense Level Value</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL2_TSEN</name>
|
|
<description>Trigger Sense</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL2_TSEN_LEVEL</name>
|
|
<description>Level sense, see TSLVAL</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL2_TSEN_FALL</name>
|
|
<description>Falling edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL2_TSEN_RISE</name>
|
|
<description>Rising edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL2_TSEN_BOTH</name>
|
|
<description>Either edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL2_TSLVAL</name>
|
|
<description>Trigger Sense Level Value</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL2_ASRCP</name>
|
|
<description>Analog Source Positive</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL2_ASRCP_PIN</name>
|
|
<description>Pin value of Cn+</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL2_ASRCP_PIN0</name>
|
|
<description>Pin value of C0+</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL2_ASRCP_REF</name>
|
|
<description>Internal voltage reference</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL2_TOEN</name>
|
|
<description>Trigger Output Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>Analog Comparator Peripheral Properties</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_PP_CMP0</name>
|
|
<description>Comparator 0 Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_PP_CMP1</name>
|
|
<description>Comparator 1 Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_PP_CMP2</name>
|
|
<description>Comparator 2 Present</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_PP_C0O</name>
|
|
<description>Comparator Output 0 Present</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_PP_C1O</name>
|
|
<description>Comparator Output 1 Present</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_PP_C2O</name>
|
|
<description>Comparator Output 2 Present</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CAN0</name>
|
|
<description>Register map for CAN0 peripheral</description>
|
|
<groupName>CAN</groupName>
|
|
<prependToName>CAN0</prependToName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>CAN0</name><value>38</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>CAN Control</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_CTL_INIT</name>
|
|
<description>Initialization</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_CTL_IE</name>
|
|
<description>CAN Interrupt Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_CTL_SIE</name>
|
|
<description>Status Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_CTL_EIE</name>
|
|
<description>Error Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_CTL_DAR</name>
|
|
<description>Disable Automatic-Retransmission</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_CTL_CCE</name>
|
|
<description>Configuration Change Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_CTL_TEST</name>
|
|
<description>Test Mode Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STS</name>
|
|
<description>CAN Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_STS_LEC</name>
|
|
<description>Last Error Code</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAN_STS_LEC_NONE</name>
|
|
<description>No Error</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_STS_LEC_STUFF</name>
|
|
<description>Stuff Error</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_STS_LEC_FORM</name>
|
|
<description>Format Error</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_STS_LEC_ACK</name>
|
|
<description>ACK Error</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_STS_LEC_BIT1</name>
|
|
<description>Bit 1 Error</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_STS_LEC_BIT0</name>
|
|
<description>Bit 0 Error</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_STS_LEC_CRC</name>
|
|
<description>CRC Error</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_STS_LEC_NOEVENT</name>
|
|
<description>No Event</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAN_STS_TXOK</name>
|
|
<description>Transmitted a Message Successfully</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_STS_RXOK</name>
|
|
<description>Received a Message Successfully</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_STS_EPASS</name>
|
|
<description>Error Passive</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_STS_EWARN</name>
|
|
<description>Warning Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_STS_BOFF</name>
|
|
<description>Bus-Off Status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERR</name>
|
|
<description>CAN Error Counter</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_ERR_TEC</name>
|
|
<description>Transmit Error Counter</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_ERR_REC</name>
|
|
<description>Receive Error Counter</description>
|
|
<bitRange>[14:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_ERR_RP</name>
|
|
<description>Received Error Passive</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BIT</name>
|
|
<description>CAN Bit Timing</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_BIT_BRP</name>
|
|
<description>Baud Rate Prescaler</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_BIT_SJW</name>
|
|
<description>(Re)Synchronization Jump Width</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_BIT_TSEG1</name>
|
|
<description>Time Segment Before Sample Point</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_BIT_TSEG2</name>
|
|
<description>Time Segment after Sample Point</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT</name>
|
|
<description>CAN Interrupt</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_INT_INTID</name>
|
|
<description>Interrupt Identifier</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TST</name>
|
|
<description>CAN Test</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_TST_BASIC</name>
|
|
<description>Basic Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_TST_SILENT</name>
|
|
<description>Silent Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_TST_LBACK</name>
|
|
<description>Loopback Mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_TST_TX</name>
|
|
<description>Transmit Control</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAN_TST_TX_CANCTL</name>
|
|
<description>CAN Module Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_TST_TX_SAMPLE</name>
|
|
<description>Sample Point</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_TST_TX_DOMINANT</name>
|
|
<description>Driven Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAN_TST_TX_RECESSIVE</name>
|
|
<description>Driven High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAN_TST_RX</name>
|
|
<description>Receive Observation</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRPE</name>
|
|
<description>CAN Baud Rate Prescaler Extension</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_BRPE_BRPE</name>
|
|
<description>Baud Rate Prescaler Extension</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1CRQ</name>
|
|
<description>CAN IF1 Command Request</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1CRQ_MNUM</name>
|
|
<description>Message Number</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1CRQ_BUSY</name>
|
|
<description>Busy Flag</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1CMSK</name>
|
|
<description>CAN IF1 Command Mask</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1CMSK_DATAB</name>
|
|
<description>Access Data Byte 4 to 7</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1CMSK_DATAA</name>
|
|
<description>Access Data Byte 0 to 3</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1CMSK_NEWDAT</name>
|
|
<description>Access New Data</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1CMSK_CLRINTPND</name>
|
|
<description>Clear Interrupt Pending Bit</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1CMSK_CONTROL</name>
|
|
<description>Access Control Bits</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1CMSK_ARB</name>
|
|
<description>Access Arbitration Bits</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1CMSK_MASK</name>
|
|
<description>Access Mask Bits</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1CMSK_WRNRD</name>
|
|
<description>Write, Not Read</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1CMSK</name>
|
|
<description>CAN IF1 Command Mask</description>
|
|
<alternateGroup>CAN0_ALT</alternateGroup>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1CMSK_TXRQST</name>
|
|
<description>Access Transmission Request</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1MSK1</name>
|
|
<description>CAN IF1 Mask 1</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1MSK1_IDMSK</name>
|
|
<description>Identifier Mask</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1MSK2</name>
|
|
<description>CAN IF1 Mask 2</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1MSK2_IDMSK</name>
|
|
<description>Identifier Mask</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1MSK2_MDIR</name>
|
|
<description>Mask Message Direction</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1MSK2_MXTD</name>
|
|
<description>Mask Extended Identifier</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1ARB1</name>
|
|
<description>CAN IF1 Arbitration 1</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1ARB1_ID</name>
|
|
<description>Message Identifier</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1ARB2</name>
|
|
<description>CAN IF1 Arbitration 2</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1ARB2_ID</name>
|
|
<description>Message Identifier</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1ARB2_DIR</name>
|
|
<description>Message Direction</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1ARB2_XTD</name>
|
|
<description>Extended Identifier</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1ARB2_MSGVAL</name>
|
|
<description>Message Valid</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1MCTL</name>
|
|
<description>CAN IF1 Message Control</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1MCTL_DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1MCTL_EOB</name>
|
|
<description>End of Buffer</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1MCTL_TXRQST</name>
|
|
<description>Transmit Request</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1MCTL_RMTEN</name>
|
|
<description>Remote Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1MCTL_RXIE</name>
|
|
<description>Receive Interrupt Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1MCTL_TXIE</name>
|
|
<description>Transmit Interrupt Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1MCTL_UMASK</name>
|
|
<description>Use Acceptance Mask</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1MCTL_INTPND</name>
|
|
<description>Interrupt Pending</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1MCTL_MSGLST</name>
|
|
<description>Message Lost</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF1MCTL_NEWDAT</name>
|
|
<description>New Data</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1DA1</name>
|
|
<description>CAN IF1 Data A1</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1DA1_DATA</name>
|
|
<description>Data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1DA2</name>
|
|
<description>CAN IF1 Data A2</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1DA2_DATA</name>
|
|
<description>Data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1DB1</name>
|
|
<description>CAN IF1 Data B1</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1DB1_DATA</name>
|
|
<description>Data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF1DB2</name>
|
|
<description>CAN IF1 Data B2</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF1DB2_DATA</name>
|
|
<description>Data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2CRQ</name>
|
|
<description>CAN IF2 Command Request</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2CRQ_MNUM</name>
|
|
<description>Message Number</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2CRQ_BUSY</name>
|
|
<description>Busy Flag</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2CMSK</name>
|
|
<description>CAN IF2 Command Mask</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2CMSK_DATAB</name>
|
|
<description>Access Data Byte 4 to 7</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2CMSK_DATAA</name>
|
|
<description>Access Data Byte 0 to 3</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2CMSK_NEWDAT</name>
|
|
<description>Access New Data</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2CMSK_CLRINTPND</name>
|
|
<description>Clear Interrupt Pending Bit</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2CMSK_CONTROL</name>
|
|
<description>Access Control Bits</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2CMSK_ARB</name>
|
|
<description>Access Arbitration Bits</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2CMSK_MASK</name>
|
|
<description>Access Mask Bits</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2CMSK_WRNRD</name>
|
|
<description>Write, Not Read</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2CMSK</name>
|
|
<description>CAN IF2 Command Mask</description>
|
|
<alternateGroup>CAN0_ALT</alternateGroup>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2CMSK_TXRQST</name>
|
|
<description>Access Transmission Request</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2MSK1</name>
|
|
<description>CAN IF2 Mask 1</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2MSK1_IDMSK</name>
|
|
<description>Identifier Mask</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2MSK2</name>
|
|
<description>CAN IF2 Mask 2</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2MSK2_IDMSK</name>
|
|
<description>Identifier Mask</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2MSK2_MDIR</name>
|
|
<description>Mask Message Direction</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2MSK2_MXTD</name>
|
|
<description>Mask Extended Identifier</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2ARB1</name>
|
|
<description>CAN IF2 Arbitration 1</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2ARB1_ID</name>
|
|
<description>Message Identifier</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2ARB2</name>
|
|
<description>CAN IF2 Arbitration 2</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2ARB2_ID</name>
|
|
<description>Message Identifier</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2ARB2_DIR</name>
|
|
<description>Message Direction</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2ARB2_XTD</name>
|
|
<description>Extended Identifier</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2ARB2_MSGVAL</name>
|
|
<description>Message Valid</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2MCTL</name>
|
|
<description>CAN IF2 Message Control</description>
|
|
<addressOffset>0x00000098</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2MCTL_DLC</name>
|
|
<description>Data Length Code</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2MCTL_EOB</name>
|
|
<description>End of Buffer</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2MCTL_TXRQST</name>
|
|
<description>Transmit Request</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2MCTL_RMTEN</name>
|
|
<description>Remote Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2MCTL_RXIE</name>
|
|
<description>Receive Interrupt Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2MCTL_TXIE</name>
|
|
<description>Transmit Interrupt Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2MCTL_UMASK</name>
|
|
<description>Use Acceptance Mask</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2MCTL_INTPND</name>
|
|
<description>Interrupt Pending</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2MCTL_MSGLST</name>
|
|
<description>Message Lost</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_IF2MCTL_NEWDAT</name>
|
|
<description>New Data</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2DA1</name>
|
|
<description>CAN IF2 Data A1</description>
|
|
<addressOffset>0x0000009C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2DA1_DATA</name>
|
|
<description>Data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2DA2</name>
|
|
<description>CAN IF2 Data A2</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2DA2_DATA</name>
|
|
<description>Data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2DB1</name>
|
|
<description>CAN IF2 Data B1</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2DB1_DATA</name>
|
|
<description>Data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF2DB2</name>
|
|
<description>CAN IF2 Data B2</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_IF2DB2_DATA</name>
|
|
<description>Data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXRQ1</name>
|
|
<description>CAN Transmission Request 1</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_TXRQ1_TXRQST</name>
|
|
<description>Transmission Request Bits</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXRQ2</name>
|
|
<description>CAN Transmission Request 2</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_TXRQ2_TXRQST</name>
|
|
<description>Transmission Request Bits</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NWDA1</name>
|
|
<description>CAN New Data 1</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_NWDA1_NEWDAT</name>
|
|
<description>New Data Bits</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NWDA2</name>
|
|
<description>CAN New Data 2</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_NWDA2_NEWDAT</name>
|
|
<description>New Data Bits</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSG1INT</name>
|
|
<description>CAN Message 1 Interrupt Pending</description>
|
|
<addressOffset>0x00000140</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_MSG1INT_INTPND</name>
|
|
<description>Interrupt Pending Bits</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSG2INT</name>
|
|
<description>CAN Message 2 Interrupt Pending</description>
|
|
<addressOffset>0x00000144</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_MSG2INT_INTPND</name>
|
|
<description>Interrupt Pending Bits</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSG1VAL</name>
|
|
<description>CAN Message 1 Valid</description>
|
|
<addressOffset>0x00000160</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_MSG1VAL_MSGVAL</name>
|
|
<description>Message Valid Bits</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSG2VAL</name>
|
|
<description>CAN Message 2 Valid</description>
|
|
<addressOffset>0x00000164</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CAN_MSG2VAL_MSGVAL</name>
|
|
<description>Message Valid Bits</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="CAN0">
|
|
<name>CAN1</name>
|
|
<prependToName>CAN1</prependToName>
|
|
<baseAddress>0x40041000</baseAddress>
|
|
<interrupt><name>CAN1</name><value>39</value></interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB0</name>
|
|
<description>Register map for USB0 peripheral</description>
|
|
<groupName>USB</groupName>
|
|
<prependToName>USB0</prependToName>
|
|
<baseAddress>0x40050000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>USB0</name><value>42</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FADDR</name>
|
|
<description>USB Device Functional Address</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FADDR</name>
|
|
<description>Function Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POWER</name>
|
|
<description>USB Power</description>
|
|
<addressOffset>0x00000001</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_POWER_PWRDNPHY</name>
|
|
<description>Power Down PHY</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_POWER_SUSPEND</name>
|
|
<description>SUSPEND Mode</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_POWER_RESUME</name>
|
|
<description>RESUME Signaling</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_POWER_RESET</name>
|
|
<description>RESET Signaling</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_POWER_HSMODE</name>
|
|
<description>High Speed Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_POWER_HSENAB</name>
|
|
<description>High Speed Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_POWER_SOFTCONN</name>
|
|
<description>Soft Connect/Disconnect</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_POWER_ISOUP</name>
|
|
<description>Isochronous Update</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXIS</name>
|
|
<description>USB Transmit Interrupt Status</description>
|
|
<addressOffset>0x00000002</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXIS_EP0</name>
|
|
<description>TX and RX Endpoint 0 Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIS_EP1</name>
|
|
<description>TX Endpoint 1 Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIS_EP2</name>
|
|
<description>TX Endpoint 2 Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIS_EP3</name>
|
|
<description>TX Endpoint 3 Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIS_EP4</name>
|
|
<description>TX Endpoint 4 Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIS_EP5</name>
|
|
<description>TX Endpoint 5 Interrupt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIS_EP6</name>
|
|
<description>TX Endpoint 6 Interrupt</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIS_EP7</name>
|
|
<description>TX Endpoint 7 Interrupt</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXIS</name>
|
|
<description>USB Receive Interrupt Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXIS_EP1</name>
|
|
<description>RX Endpoint 1 Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIS_EP2</name>
|
|
<description>RX Endpoint 2 Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIS_EP3</name>
|
|
<description>RX Endpoint 3 Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIS_EP4</name>
|
|
<description>RX Endpoint 4 Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIS_EP5</name>
|
|
<description>RX Endpoint 5 Interrupt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIS_EP6</name>
|
|
<description>RX Endpoint 6 Interrupt</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIS_EP7</name>
|
|
<description>RX Endpoint 7 Interrupt</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXIE</name>
|
|
<description>USB Transmit Interrupt Enable</description>
|
|
<addressOffset>0x00000006</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXIE_EP0</name>
|
|
<description>TX and RX Endpoint 0 Interrupt Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIE_EP1</name>
|
|
<description>TX Endpoint 1 Interrupt Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIE_EP2</name>
|
|
<description>TX Endpoint 2 Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIE_EP3</name>
|
|
<description>TX Endpoint 3 Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIE_EP4</name>
|
|
<description>TX Endpoint 4 Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIE_EP5</name>
|
|
<description>TX Endpoint 5 Interrupt Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIE_EP6</name>
|
|
<description>TX Endpoint 6 Interrupt Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXIE_EP7</name>
|
|
<description>TX Endpoint 7 Interrupt Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXIE</name>
|
|
<description>USB Receive Interrupt Enable</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXIE_EP1</name>
|
|
<description>RX Endpoint 1 Interrupt Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIE_EP2</name>
|
|
<description>RX Endpoint 2 Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIE_EP3</name>
|
|
<description>RX Endpoint 3 Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIE_EP4</name>
|
|
<description>RX Endpoint 4 Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIE_EP5</name>
|
|
<description>RX Endpoint 5 Interrupt Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIE_EP6</name>
|
|
<description>RX Endpoint 6 Interrupt Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXIE_EP7</name>
|
|
<description>RX Endpoint 7 Interrupt Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IS</name>
|
|
<description>USB General Interrupt Status</description>
|
|
<addressOffset>0x0000000A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_IS_SUSPEND</name>
|
|
<description>SUSPEND Signaling Detected</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IS_RESUME</name>
|
|
<description>RESUME Signaling Detected</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IS_BABBLE</name>
|
|
<description>Babble Detected</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IS_SOF</name>
|
|
<description>Start of Frame</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IS_CONN</name>
|
|
<description>Session Connect</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IS_DISCON</name>
|
|
<description>Session Disconnect (OTG only)</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IS_SESREQ</name>
|
|
<description>SESSION REQUEST (OTG only)</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IS_VBUSERR</name>
|
|
<description>VBUS Error (OTG only)</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IS</name>
|
|
<description>USB General Interrupt Status</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000000A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_IS_RESET</name>
|
|
<description>RESET Signaling Detected</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>USB Interrupt Enable</description>
|
|
<addressOffset>0x0000000B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_IE_SUSPND</name>
|
|
<description>Enable SUSPEND Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IE_RESUME</name>
|
|
<description>Enable RESUME Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IE_BABBLE</name>
|
|
<description>Enable Babble Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IE_SOF</name>
|
|
<description>Enable Start-of-Frame Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IE_CONN</name>
|
|
<description>Enable Connect Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IE_DISCON</name>
|
|
<description>Enable Disconnect Interrupt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IE_SESREQ</name>
|
|
<description>Enable Session Request (OTG only)</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_IE_VBUSERR</name>
|
|
<description>Enable VBUS Error Interrupt (OTG only)</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>USB Interrupt Enable</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000000B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_IE_RESET</name>
|
|
<description>Enable RESET Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRAME</name>
|
|
<description>USB Frame Value</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FRAME</name>
|
|
<description>Frame Number</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPIDX</name>
|
|
<description>USB Endpoint Index</description>
|
|
<addressOffset>0x0000000E</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_EPIDX_EPIDX</name>
|
|
<description>Endpoint Index</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEST</name>
|
|
<description>USB Test Mode</description>
|
|
<addressOffset>0x0000000F</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TEST_TESTSE0NAK</name>
|
|
<description>Test_SE0_NAK Test Mode Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TEST_TESTJ</name>
|
|
<description>Test_J Mode Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TEST_TESTK</name>
|
|
<description>Test_K Mode Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TEST_TESTPKT</name>
|
|
<description>Test Packet Mode Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TEST_FORCEHS</name>
|
|
<description>Force High-Speed Mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TEST_FORCEFS</name>
|
|
<description>Force Full-Speed Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TEST_FIFOACC</name>
|
|
<description>FIFO Access</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TEST_FORCEH</name>
|
|
<description>Force Host Mode</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO0</name>
|
|
<description>USB FIFO Endpoint 0</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FIFO0_EPDATA</name>
|
|
<description>Endpoint Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO1</name>
|
|
<description>USB FIFO Endpoint 1</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FIFO1_EPDATA</name>
|
|
<description>Endpoint Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO2</name>
|
|
<description>USB FIFO Endpoint 2</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FIFO2_EPDATA</name>
|
|
<description>Endpoint Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO3</name>
|
|
<description>USB FIFO Endpoint 3</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FIFO3_EPDATA</name>
|
|
<description>Endpoint Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO4</name>
|
|
<description>USB FIFO Endpoint 4</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FIFO4_EPDATA</name>
|
|
<description>Endpoint Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO5</name>
|
|
<description>USB FIFO Endpoint 5</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FIFO5_EPDATA</name>
|
|
<description>Endpoint Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO6</name>
|
|
<description>USB FIFO Endpoint 6</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FIFO6_EPDATA</name>
|
|
<description>Endpoint Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO7</name>
|
|
<description>USB FIFO Endpoint 7</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FIFO7_EPDATA</name>
|
|
<description>Endpoint Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVCTL</name>
|
|
<description>USB Device Control</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DEVCTL_SESSION</name>
|
|
<description>Session Start/End (OTG only)</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DEVCTL_HOSTREQ</name>
|
|
<description>Host Request (OTG only)</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DEVCTL_HOST</name>
|
|
<description>Host Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DEVCTL_VBUS</name>
|
|
<description>VBUS Level (OTG only)</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_DEVCTL_VBUS_NONE</name>
|
|
<description>Below SessionEnd</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DEVCTL_VBUS_SEND</name>
|
|
<description>Above SessionEnd, below AValid</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DEVCTL_VBUS_AVALID</name>
|
|
<description>Above AValid, below VBUSValid</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DEVCTL_VBUS_VALID</name>
|
|
<description>Above VBUSValid</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_DEVCTL_LSDEV</name>
|
|
<description>Low-Speed Device Detected</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DEVCTL_FSDEV</name>
|
|
<description>Full-Speed Device Detected</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DEVCTL_DEV</name>
|
|
<description>Device Mode (OTG only)</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCONF</name>
|
|
<description>USB Common Configuration</description>
|
|
<addressOffset>0x00000061</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_CCONF_RXEDMA</name>
|
|
<description>TX Early DMA Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_CCONF_TXEDMA</name>
|
|
<description>TX Early DMA Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFIFOSZ</name>
|
|
<description>USB Transmit Dynamic FIFO Sizing</description>
|
|
<addressOffset>0x00000062</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXFIFOSZ_SIZE</name>
|
|
<description>Max Packet Size</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXFIFOSZ_SIZE_8</name>
|
|
<description>8</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXFIFOSZ_SIZE_16</name>
|
|
<description>16</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXFIFOSZ_SIZE_32</name>
|
|
<description>32</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXFIFOSZ_SIZE_64</name>
|
|
<description>64</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXFIFOSZ_SIZE_128</name>
|
|
<description>128</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXFIFOSZ_SIZE_256</name>
|
|
<description>256</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXFIFOSZ_SIZE_512</name>
|
|
<description>512</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXFIFOSZ_SIZE_1024</name>
|
|
<description>1024</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXFIFOSZ_SIZE_2048</name>
|
|
<description>2048</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXFIFOSZ_DPB</name>
|
|
<description>Double Packet Buffer Support</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFOSZ</name>
|
|
<description>USB Receive Dynamic FIFO Sizing</description>
|
|
<addressOffset>0x00000063</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXFIFOSZ_SIZE</name>
|
|
<description>Max Packet Size</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXFIFOSZ_SIZE_8</name>
|
|
<description>8</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXFIFOSZ_SIZE_16</name>
|
|
<description>16</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXFIFOSZ_SIZE_32</name>
|
|
<description>32</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXFIFOSZ_SIZE_64</name>
|
|
<description>64</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXFIFOSZ_SIZE_128</name>
|
|
<description>128</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXFIFOSZ_SIZE_256</name>
|
|
<description>256</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXFIFOSZ_SIZE_512</name>
|
|
<description>512</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXFIFOSZ_SIZE_1024</name>
|
|
<description>1024</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXFIFOSZ_SIZE_2048</name>
|
|
<description>2048</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXFIFOSZ_DPB</name>
|
|
<description>Double Packet Buffer Support</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFIFOADD</name>
|
|
<description>USB Transmit FIFO Start Address</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXFIFOADD_ADDR</name>
|
|
<description>Transmit/Receive Start Address</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFOADD</name>
|
|
<description>USB Receive FIFO Start Address</description>
|
|
<addressOffset>0x00000066</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXFIFOADD_ADDR</name>
|
|
<description>Transmit/Receive Start Address</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ULPIVBUSCTL</name>
|
|
<description>USB ULPI VBUS Control</description>
|
|
<addressOffset>0x00000070</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_ULPIVBUSCTL_USEEXTVBUS</name>
|
|
<description>Use External VBUS</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_ULPIVBUSCTL_USEEXTVBUSIND</name>
|
|
<description>Use External VBUS Indicator</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ULPIREGDATA</name>
|
|
<description>USB ULPI Register Data</description>
|
|
<addressOffset>0x00000074</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_ULPIREGDATA_REGDATA</name>
|
|
<description>Register Data</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ULPIREGADDR</name>
|
|
<description>USB ULPI Register Address</description>
|
|
<addressOffset>0x00000075</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_ULPIREGADDR_ADDR</name>
|
|
<description>Register Address</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ULPIREGCTL</name>
|
|
<description>USB ULPI Register Control</description>
|
|
<addressOffset>0x00000076</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_ULPIREGCTL_REGACC</name>
|
|
<description>Initiate Register Access</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_ULPIREGCTL_REGCMPLT</name>
|
|
<description>Register Access Complete</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_ULPIREGCTL_RDWR</name>
|
|
<description>Read/Write Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPINFO</name>
|
|
<description>USB Endpoint Information</description>
|
|
<addressOffset>0x00000078</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_EPINFO_TXEP</name>
|
|
<description>TX Endpoints</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_EPINFO_RXEP</name>
|
|
<description>RX Endpoints</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAMINFO</name>
|
|
<description>USB RAM Information</description>
|
|
<addressOffset>0x00000079</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RAMINFO_RAMBITS</name>
|
|
<description>RAM Address Bus Width</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RAMINFO_DMACHAN</name>
|
|
<description>DMA Channels</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTIM</name>
|
|
<description>USB Connect Timing</description>
|
|
<addressOffset>0x0000007A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_CONTIM_WTID</name>
|
|
<description>Wait ID</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_CONTIM_WTCON</name>
|
|
<description>Connect Wait</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VPLEN</name>
|
|
<description>USB OTG VBUS Pulse Timing</description>
|
|
<addressOffset>0x0000007B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_VPLEN_VPLEN</name>
|
|
<description>VBUS Pulse Length</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSEOF</name>
|
|
<description>USB High-Speed Last Transaction to End of Frame Timing</description>
|
|
<addressOffset>0x0000007C</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_HSEOF_HSEOFG</name>
|
|
<description>HIgh-Speed End-of-Frame Gap</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSEOF</name>
|
|
<description>USB Full-Speed Last Transaction to End of Frame Timing</description>
|
|
<addressOffset>0x0000007D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_FSEOF_FSEOFG</name>
|
|
<description>Full-Speed End-of-Frame Gap</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSEOF</name>
|
|
<description>USB Low-Speed Last Transaction to End of Frame Timing</description>
|
|
<addressOffset>0x0000007E</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_LSEOF_LSEOFG</name>
|
|
<description>Low-Speed End-of-Frame Gap</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFUNCADDR0</name>
|
|
<description>USB Transmit Functional Address Endpoint 0</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXFUNCADDR0_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBADDR0</name>
|
|
<description>USB Transmit Hub Address Endpoint 0</description>
|
|
<addressOffset>0x00000082</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBADDR0_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBPORT0</name>
|
|
<description>USB Transmit Hub Port Endpoint 0</description>
|
|
<addressOffset>0x00000083</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBPORT0_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFUNCADDR1</name>
|
|
<description>USB Transmit Functional Address Endpoint 1</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXFUNCADDR1_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBADDR1</name>
|
|
<description>USB Transmit Hub Address Endpoint 1</description>
|
|
<addressOffset>0x0000008A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBADDR1_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBPORT1</name>
|
|
<description>USB Transmit Hub Port Endpoint 1</description>
|
|
<addressOffset>0x0000008B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBPORT1_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFUNCADDR1</name>
|
|
<description>USB Receive Functional Address Endpoint 1</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXFUNCADDR1_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBADDR1</name>
|
|
<description>USB Receive Hub Address Endpoint 1</description>
|
|
<addressOffset>0x0000008E</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBADDR1_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBPORT1</name>
|
|
<description>USB Receive Hub Port Endpoint 1</description>
|
|
<addressOffset>0x0000008F</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBPORT1_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFUNCADDR2</name>
|
|
<description>USB Transmit Functional Address Endpoint 2</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXFUNCADDR2_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBADDR2</name>
|
|
<description>USB Transmit Hub Address Endpoint 2</description>
|
|
<addressOffset>0x00000092</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBADDR2_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBPORT2</name>
|
|
<description>USB Transmit Hub Port Endpoint 2</description>
|
|
<addressOffset>0x00000093</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBPORT2_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFUNCADDR2</name>
|
|
<description>USB Receive Functional Address Endpoint 2</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXFUNCADDR2_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBADDR2</name>
|
|
<description>USB Receive Hub Address Endpoint 2</description>
|
|
<addressOffset>0x00000096</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBADDR2_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBPORT2</name>
|
|
<description>USB Receive Hub Port Endpoint 2</description>
|
|
<addressOffset>0x00000097</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBPORT2_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFUNCADDR3</name>
|
|
<description>USB Transmit Functional Address Endpoint 3</description>
|
|
<addressOffset>0x00000098</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXFUNCADDR3_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBADDR3</name>
|
|
<description>USB Transmit Hub Address Endpoint 3</description>
|
|
<addressOffset>0x0000009A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBADDR3_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBPORT3</name>
|
|
<description>USB Transmit Hub Port Endpoint 3</description>
|
|
<addressOffset>0x0000009B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBPORT3_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFUNCADDR3</name>
|
|
<description>USB Receive Functional Address Endpoint 3</description>
|
|
<addressOffset>0x0000009C</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXFUNCADDR3_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBADDR3</name>
|
|
<description>USB Receive Hub Address Endpoint 3</description>
|
|
<addressOffset>0x0000009E</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBADDR3_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBPORT3</name>
|
|
<description>USB Receive Hub Port Endpoint 3</description>
|
|
<addressOffset>0x0000009F</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBPORT3_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFUNCADDR4</name>
|
|
<description>USB Transmit Functional Address Endpoint 4</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXFUNCADDR4_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBADDR4</name>
|
|
<description>USB Transmit Hub Address Endpoint 4</description>
|
|
<addressOffset>0x000000A2</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBADDR4_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBPORT4</name>
|
|
<description>USB Transmit Hub Port Endpoint 4</description>
|
|
<addressOffset>0x000000A3</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBPORT4_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFUNCADDR4</name>
|
|
<description>USB Receive Functional Address Endpoint 4</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXFUNCADDR4_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBADDR4</name>
|
|
<description>USB Receive Hub Address Endpoint 4</description>
|
|
<addressOffset>0x000000A6</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBADDR4_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBPORT4</name>
|
|
<description>USB Receive Hub Port Endpoint 4</description>
|
|
<addressOffset>0x000000A7</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBPORT4_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFUNCADDR5</name>
|
|
<description>USB Transmit Functional Address Endpoint 5</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXFUNCADDR5_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBADDR5</name>
|
|
<description>USB Transmit Hub Address Endpoint 5</description>
|
|
<addressOffset>0x000000AA</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBADDR5_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBPORT5</name>
|
|
<description>USB Transmit Hub Port Endpoint 5</description>
|
|
<addressOffset>0x000000AB</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBPORT5_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFUNCADDR5</name>
|
|
<description>USB Receive Functional Address Endpoint 5</description>
|
|
<addressOffset>0x000000AC</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXFUNCADDR5_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBADDR5</name>
|
|
<description>USB Receive Hub Address Endpoint 5</description>
|
|
<addressOffset>0x000000AE</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBADDR5_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBPORT5</name>
|
|
<description>USB Receive Hub Port Endpoint 5</description>
|
|
<addressOffset>0x000000AF</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBPORT5_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFUNCADDR6</name>
|
|
<description>USB Transmit Functional Address Endpoint 6</description>
|
|
<addressOffset>0x000000B0</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXFUNCADDR6_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBADDR6</name>
|
|
<description>USB Transmit Hub Address Endpoint 6</description>
|
|
<addressOffset>0x000000B2</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBADDR6_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBPORT6</name>
|
|
<description>USB Transmit Hub Port Endpoint 6</description>
|
|
<addressOffset>0x000000B3</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBPORT6_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFUNCADDR6</name>
|
|
<description>USB Receive Functional Address Endpoint 6</description>
|
|
<addressOffset>0x000000B4</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXFUNCADDR6_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBADDR6</name>
|
|
<description>USB Receive Hub Address Endpoint 6</description>
|
|
<addressOffset>0x000000B6</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBADDR6_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBPORT6</name>
|
|
<description>USB Receive Hub Port Endpoint 6</description>
|
|
<addressOffset>0x000000B7</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBPORT6_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFUNCADDR7</name>
|
|
<description>USB Transmit Functional Address Endpoint 7</description>
|
|
<addressOffset>0x000000B8</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXFUNCADDR7_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBADDR7</name>
|
|
<description>USB Transmit Hub Address Endpoint 7</description>
|
|
<addressOffset>0x000000BA</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBADDR7_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXHUBPORT7</name>
|
|
<description>USB Transmit Hub Port Endpoint 7</description>
|
|
<addressOffset>0x000000BB</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXHUBPORT7_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFUNCADDR7</name>
|
|
<description>USB Receive Functional Address Endpoint 7</description>
|
|
<addressOffset>0x000000BC</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXFUNCADDR7_ADDR</name>
|
|
<description>Device Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBADDR7</name>
|
|
<description>USB Receive Hub Address Endpoint 7</description>
|
|
<addressOffset>0x000000BE</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBADDR7_ADDR</name>
|
|
<description>Hub Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXHUBPORT7</name>
|
|
<description>USB Receive Hub Port Endpoint 7</description>
|
|
<addressOffset>0x000000BF</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXHUBPORT7_PORT</name>
|
|
<description>Hub Port</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSRL0</name>
|
|
<description>USB Control and Status Endpoint 0 Low</description>
|
|
<addressOffset>0x00000102</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>USB_CSRL0_RXRDY</name>
|
|
<description>Receive Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRL0_TXRDY</name>
|
|
<description>Transmit Packet Ready</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRL0_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRL0_DATAEND</name>
|
|
<description>Data End</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRL0_SETEND</name>
|
|
<description>Setup End</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRL0_STALL</name>
|
|
<description>Send Stall</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRL0_RXRDYC</name>
|
|
<description>RXRDY Clear</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRL0_SETENDC</name>
|
|
<description>Setup End Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSRL0</name>
|
|
<description>USB Control and Status Endpoint 0 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000102</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>USB_CSRL0_SETUP</name>
|
|
<description>Setup Packet</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRL0_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRL0_REQPKT</name>
|
|
<description>Request Packet</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRL0_STATUS</name>
|
|
<description>STATUS Packet</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRL0_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSRH0</name>
|
|
<description>USB Control and Status Endpoint 0 High</description>
|
|
<addressOffset>0x00000103</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>USB_CSRH0_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRH0_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRH0_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USB_CSRH0_DISPING</name>
|
|
<description>PING Disable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT0</name>
|
|
<description>USB Receive Byte Count Endpoint 0</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_COUNT0_COUNT</name>
|
|
<description>FIFO Count</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TYPE0</name>
|
|
<description>USB Type Endpoint 0</description>
|
|
<addressOffset>0x0000010A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TYPE0_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TYPE0_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TYPE0_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TYPE0_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NAKLMT</name>
|
|
<description>USB NAK Limit</description>
|
|
<addressOffset>0x0000010B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_NAKLMT_NAKLMT</name>
|
|
<description>EP0 NAK Limit</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMAXP1</name>
|
|
<description>USB Maximum Transmit Data Endpoint 1</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXMAXP1_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL1</name>
|
|
<description>USB Transmit Control and Status Endpoint 1 Low</description>
|
|
<addressOffset>0x00000112</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL1_TXRDY</name>
|
|
<description>Transmit Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL1_FIFONE</name>
|
|
<description>FIFO Not Empty</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL1_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL1_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL1_SETUP</name>
|
|
<description>Setup Packet</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL1_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL1_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL1_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL1</name>
|
|
<description>USB Transmit Control and Status Endpoint 1 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000112</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL1_UNDRN</name>
|
|
<description>Underrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL1_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRH1</name>
|
|
<description>USB Transmit Control and Status Endpoint 1 High</description>
|
|
<addressOffset>0x00000113</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRH1_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH1_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH1_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH1_FDT</name>
|
|
<description>Force Data Toggle</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH1_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH1_MODE</name>
|
|
<description>Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH1_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH1_AUTOSET</name>
|
|
<description>Auto Set</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXMAXP1</name>
|
|
<description>USB Maximum Receive Data Endpoint 1</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXMAXP1_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL1</name>
|
|
<description>USB Receive Control and Status Endpoint 1 Low</description>
|
|
<addressOffset>0x00000116</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL1_RXRDY</name>
|
|
<description>Receive Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL1_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL1_OVER</name>
|
|
<description>Overrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL1_DATAERR</name>
|
|
<description>Data Error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL1_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL1_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL1_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL1_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL1</name>
|
|
<description>USB Receive Control and Status Endpoint 1 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000116</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL1_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL1_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL1_REQPKT</name>
|
|
<description>Request Packet</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH1</name>
|
|
<description>USB Receive Control and Status Endpoint 1 High</description>
|
|
<addressOffset>0x00000117</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH1_INCOMPRX</name>
|
|
<description>Incomplete RX Transmission Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH1_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH1_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH1_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH1_PIDERR</name>
|
|
<description>PID Error</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH1_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH1_AUTORQ</name>
|
|
<description>Auto Request</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH1_AUTOCL</name>
|
|
<description>Auto Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH1</name>
|
|
<description>USB Receive Control and Status Endpoint 1 High</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000117</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH1_DISNYET</name>
|
|
<description>Disable NYET</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH1_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCOUNT1</name>
|
|
<description>USB Receive Byte Count Endpoint 1</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCOUNT1_COUNT</name>
|
|
<description>Receive Packet Count</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXTYPE1</name>
|
|
<description>USB Host Transmit Configure Type Endpoint 1</description>
|
|
<addressOffset>0x0000011A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXTYPE1_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE1_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE1_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE1_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE1_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE1_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE1_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE1_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE1_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE1_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE1_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL1</name>
|
|
<description>USB Host Transmit Interval Endpoint 1</description>
|
|
<addressOffset>0x0000011B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL1_TXPOLL</name>
|
|
<description>TX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL1</name>
|
|
<description>USB Host Transmit Interval Endpoint 1</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000011B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL1_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXTYPE1</name>
|
|
<description>USB Host Configure Receive Type Endpoint 1</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXTYPE1_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE1_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE1_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE1_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE1_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE1_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE1_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE1_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE1_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE1_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE1_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL1</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 1</description>
|
|
<addressOffset>0x0000011D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL1_TXPOLL</name>
|
|
<description>RX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL1</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 1</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000011D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL1_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMAXP2</name>
|
|
<description>USB Maximum Transmit Data Endpoint 2</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXMAXP2_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL2</name>
|
|
<description>USB Transmit Control and Status Endpoint 2 Low</description>
|
|
<addressOffset>0x00000122</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL2_TXRDY</name>
|
|
<description>Transmit Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL2_FIFONE</name>
|
|
<description>FIFO Not Empty</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL2_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL2_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL2_SETUP</name>
|
|
<description>Setup Packet</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL2_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL2_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL2_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL2</name>
|
|
<description>USB Transmit Control and Status Endpoint 2 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000122</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL2_UNDRN</name>
|
|
<description>Underrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL2_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRH2</name>
|
|
<description>USB Transmit Control and Status Endpoint 2 High</description>
|
|
<addressOffset>0x00000123</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRH2_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH2_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH2_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH2_FDT</name>
|
|
<description>Force Data Toggle</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH2_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH2_MODE</name>
|
|
<description>Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH2_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH2_AUTOSET</name>
|
|
<description>Auto Set</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXMAXP2</name>
|
|
<description>USB Maximum Receive Data Endpoint 2</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXMAXP2_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL2</name>
|
|
<description>USB Receive Control and Status Endpoint 2 Low</description>
|
|
<addressOffset>0x00000126</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL2_RXRDY</name>
|
|
<description>Receive Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL2_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL2_OVER</name>
|
|
<description>Overrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL2_DATAERR</name>
|
|
<description>Data Error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL2_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL2_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL2_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL2_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL2</name>
|
|
<description>USB Receive Control and Status Endpoint 2 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000126</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL2_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL2_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL2_REQPKT</name>
|
|
<description>Request Packet</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH2</name>
|
|
<description>USB Receive Control and Status Endpoint 2 High</description>
|
|
<addressOffset>0x00000127</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH2_INCOMPRX</name>
|
|
<description>Incomplete RX Transmission Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH2_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH2_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH2_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH2_PIDERR</name>
|
|
<description>PID Error</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH2_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH2_AUTORQ</name>
|
|
<description>Auto Request</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH2_AUTOCL</name>
|
|
<description>Auto Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH2</name>
|
|
<description>USB Receive Control and Status Endpoint 2 High</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000127</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH2_DISNYET</name>
|
|
<description>Disable NYET</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH2_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCOUNT2</name>
|
|
<description>USB Receive Byte Count Endpoint 2</description>
|
|
<addressOffset>0x00000128</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCOUNT2_COUNT</name>
|
|
<description>Receive Packet Count</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXTYPE2</name>
|
|
<description>USB Host Transmit Configure Type Endpoint 2</description>
|
|
<addressOffset>0x0000012A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXTYPE2_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE2_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE2_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE2_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE2_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE2_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE2_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE2_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE2_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE2_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE2_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL2</name>
|
|
<description>USB Host Transmit Interval Endpoint 2</description>
|
|
<addressOffset>0x0000012B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL2_TXPOLL</name>
|
|
<description>TX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL2</name>
|
|
<description>USB Host Transmit Interval Endpoint 2</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000012B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL2_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXTYPE2</name>
|
|
<description>USB Host Configure Receive Type Endpoint 2</description>
|
|
<addressOffset>0x0000012C</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXTYPE2_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE2_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE2_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE2_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE2_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE2_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE2_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE2_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE2_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE2_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE2_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL2</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 2</description>
|
|
<addressOffset>0x0000012D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL2_TXPOLL</name>
|
|
<description>RX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL2</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 2</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000012D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL2_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMAXP3</name>
|
|
<description>USB Maximum Transmit Data Endpoint 3</description>
|
|
<addressOffset>0x00000130</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXMAXP3_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL3</name>
|
|
<description>USB Transmit Control and Status Endpoint 3 Low</description>
|
|
<addressOffset>0x00000132</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL3_TXRDY</name>
|
|
<description>Transmit Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL3_FIFONE</name>
|
|
<description>FIFO Not Empty</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL3_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL3_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL3_SETUP</name>
|
|
<description>Setup Packet</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL3_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL3_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL3_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL3</name>
|
|
<description>USB Transmit Control and Status Endpoint 3 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000132</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL3_UNDRN</name>
|
|
<description>Underrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL3_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRH3</name>
|
|
<description>USB Transmit Control and Status Endpoint 3 High</description>
|
|
<addressOffset>0x00000133</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRH3_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH3_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH3_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH3_FDT</name>
|
|
<description>Force Data Toggle</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH3_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH3_MODE</name>
|
|
<description>Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH3_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH3_AUTOSET</name>
|
|
<description>Auto Set</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXMAXP3</name>
|
|
<description>USB Maximum Receive Data Endpoint 3</description>
|
|
<addressOffset>0x00000134</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXMAXP3_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL3</name>
|
|
<description>USB Receive Control and Status Endpoint 3 Low</description>
|
|
<addressOffset>0x00000136</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL3_RXRDY</name>
|
|
<description>Receive Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL3_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL3_OVER</name>
|
|
<description>Overrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL3_DATAERR</name>
|
|
<description>Data Error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL3_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL3_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL3_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL3_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL3</name>
|
|
<description>USB Receive Control and Status Endpoint 3 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000136</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL3_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL3_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL3_REQPKT</name>
|
|
<description>Request Packet</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH3</name>
|
|
<description>USB Receive Control and Status Endpoint 3 High</description>
|
|
<addressOffset>0x00000137</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH3_INCOMPRX</name>
|
|
<description>Incomplete RX Transmission Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH3_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH3_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH3_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH3_PIDERR</name>
|
|
<description>PID Error</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH3_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH3_AUTORQ</name>
|
|
<description>Auto Request</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH3_AUTOCL</name>
|
|
<description>Auto Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH3</name>
|
|
<description>USB Receive Control and Status Endpoint 3 High</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000137</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH3_DISNYET</name>
|
|
<description>Disable NYET</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH3_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCOUNT3</name>
|
|
<description>USB Receive Byte Count Endpoint 3</description>
|
|
<addressOffset>0x00000138</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCOUNT3_COUNT</name>
|
|
<description>Receive Packet Count</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXTYPE3</name>
|
|
<description>USB Host Transmit Configure Type Endpoint 3</description>
|
|
<addressOffset>0x0000013A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXTYPE3_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE3_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE3_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE3_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE3_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE3_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE3_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE3_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE3_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE3_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE3_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL3</name>
|
|
<description>USB Host Transmit Interval Endpoint 3</description>
|
|
<addressOffset>0x0000013B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL3_TXPOLL</name>
|
|
<description>TX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL3</name>
|
|
<description>USB Host Transmit Interval Endpoint 3</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000013B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL3_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXTYPE3</name>
|
|
<description>USB Host Configure Receive Type Endpoint 3</description>
|
|
<addressOffset>0x0000013C</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXTYPE3_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE3_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE3_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE3_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE3_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE3_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE3_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE3_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE3_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE3_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE3_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL3</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 3</description>
|
|
<addressOffset>0x0000013D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL3_TXPOLL</name>
|
|
<description>RX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL3</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 3</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000013D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL3_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMAXP4</name>
|
|
<description>USB Maximum Transmit Data Endpoint 4</description>
|
|
<addressOffset>0x00000140</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXMAXP4_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL4</name>
|
|
<description>USB Transmit Control and Status Endpoint 4 Low</description>
|
|
<addressOffset>0x00000142</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL4_TXRDY</name>
|
|
<description>Transmit Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL4_FIFONE</name>
|
|
<description>FIFO Not Empty</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL4_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL4_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL4_SETUP</name>
|
|
<description>Setup Packet</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL4_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL4_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL4_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL4</name>
|
|
<description>USB Transmit Control and Status Endpoint 4 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000142</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL4_UNDRN</name>
|
|
<description>Underrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL4_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRH4</name>
|
|
<description>USB Transmit Control and Status Endpoint 4 High</description>
|
|
<addressOffset>0x00000143</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRH4_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH4_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH4_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH4_FDT</name>
|
|
<description>Force Data Toggle</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH4_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH4_MODE</name>
|
|
<description>Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH4_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH4_AUTOSET</name>
|
|
<description>Auto Set</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXMAXP4</name>
|
|
<description>USB Maximum Receive Data Endpoint 4</description>
|
|
<addressOffset>0x00000144</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXMAXP4_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL4</name>
|
|
<description>USB Receive Control and Status Endpoint 4 Low</description>
|
|
<addressOffset>0x00000146</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL4_RXRDY</name>
|
|
<description>Receive Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL4_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL4_OVER</name>
|
|
<description>Overrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL4_DATAERR</name>
|
|
<description>Data Error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL4_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL4_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL4_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL4_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL4</name>
|
|
<description>USB Receive Control and Status Endpoint 4 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000146</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL4_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL4_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL4_REQPKT</name>
|
|
<description>Request Packet</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH4</name>
|
|
<description>USB Receive Control and Status Endpoint 4 High</description>
|
|
<addressOffset>0x00000147</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH4_INCOMPRX</name>
|
|
<description>Incomplete RX Transmission Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH4_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH4_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH4_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH4_PIDERR</name>
|
|
<description>PID Error</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH4_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH4_AUTORQ</name>
|
|
<description>Auto Request</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH4_AUTOCL</name>
|
|
<description>Auto Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH4</name>
|
|
<description>USB Receive Control and Status Endpoint 4 High</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000147</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH4_DISNYET</name>
|
|
<description>Disable NYET</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH4_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCOUNT4</name>
|
|
<description>USB Receive Byte Count Endpoint 4</description>
|
|
<addressOffset>0x00000148</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCOUNT4_COUNT</name>
|
|
<description>Receive Packet Count</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXTYPE4</name>
|
|
<description>USB Host Transmit Configure Type Endpoint 4</description>
|
|
<addressOffset>0x0000014A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXTYPE4_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE4_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE4_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE4_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE4_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE4_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE4_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE4_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE4_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE4_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE4_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL4</name>
|
|
<description>USB Host Transmit Interval Endpoint 4</description>
|
|
<addressOffset>0x0000014B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL4_TXPOLL</name>
|
|
<description>TX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL4</name>
|
|
<description>USB Host Transmit Interval Endpoint 4</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000014B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL4_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXTYPE4</name>
|
|
<description>USB Host Configure Receive Type Endpoint 4</description>
|
|
<addressOffset>0x0000014C</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXTYPE4_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE4_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE4_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE4_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE4_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE4_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE4_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE4_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE4_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE4_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE4_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL4</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 4</description>
|
|
<addressOffset>0x0000014D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL4_TXPOLL</name>
|
|
<description>RX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL4</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 4</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000014D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL4_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMAXP5</name>
|
|
<description>USB Maximum Transmit Data Endpoint 5</description>
|
|
<addressOffset>0x00000150</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXMAXP5_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL5</name>
|
|
<description>USB Transmit Control and Status Endpoint 5 Low</description>
|
|
<addressOffset>0x00000152</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL5_TXRDY</name>
|
|
<description>Transmit Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL5_FIFONE</name>
|
|
<description>FIFO Not Empty</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL5_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL5_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL5_SETUP</name>
|
|
<description>Setup Packet</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL5_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL5_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL5_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL5</name>
|
|
<description>USB Transmit Control and Status Endpoint 5 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000152</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL5_UNDRN</name>
|
|
<description>Underrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL5_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRH5</name>
|
|
<description>USB Transmit Control and Status Endpoint 5 High</description>
|
|
<addressOffset>0x00000153</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRH5_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH5_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH5_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH5_FDT</name>
|
|
<description>Force Data Toggle</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH5_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH5_MODE</name>
|
|
<description>Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH5_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH5_AUTOSET</name>
|
|
<description>Auto Set</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXMAXP5</name>
|
|
<description>USB Maximum Receive Data Endpoint 5</description>
|
|
<addressOffset>0x00000154</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXMAXP5_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL5</name>
|
|
<description>USB Receive Control and Status Endpoint 5 Low</description>
|
|
<addressOffset>0x00000156</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL5_RXRDY</name>
|
|
<description>Receive Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL5_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL5_OVER</name>
|
|
<description>Overrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL5_DATAERR</name>
|
|
<description>Data Error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL5_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL5_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL5_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL5_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL5</name>
|
|
<description>USB Receive Control and Status Endpoint 5 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000156</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL5_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL5_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL5_REQPKT</name>
|
|
<description>Request Packet</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH5</name>
|
|
<description>USB Receive Control and Status Endpoint 5 High</description>
|
|
<addressOffset>0x00000157</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH5_INCOMPRX</name>
|
|
<description>Incomplete RX Transmission Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH5_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH5_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH5_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH5_PIDERR</name>
|
|
<description>PID Error</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH5_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH5_AUTORQ</name>
|
|
<description>Auto Request</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH5_AUTOCL</name>
|
|
<description>Auto Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH5</name>
|
|
<description>USB Receive Control and Status Endpoint 5 High</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000157</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH5_DISNYET</name>
|
|
<description>Disable NYET</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH5_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCOUNT5</name>
|
|
<description>USB Receive Byte Count Endpoint 5</description>
|
|
<addressOffset>0x00000158</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCOUNT5_COUNT</name>
|
|
<description>Receive Packet Count</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXTYPE5</name>
|
|
<description>USB Host Transmit Configure Type Endpoint 5</description>
|
|
<addressOffset>0x0000015A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXTYPE5_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE5_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE5_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE5_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE5_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE5_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE5_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE5_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE5_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE5_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE5_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL5</name>
|
|
<description>USB Host Transmit Interval Endpoint 5</description>
|
|
<addressOffset>0x0000015B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL5_TXPOLL</name>
|
|
<description>TX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL5</name>
|
|
<description>USB Host Transmit Interval Endpoint 5</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000015B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL5_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXTYPE5</name>
|
|
<description>USB Host Configure Receive Type Endpoint 5</description>
|
|
<addressOffset>0x0000015C</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXTYPE5_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE5_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE5_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE5_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE5_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE5_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE5_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE5_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE5_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE5_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE5_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL5</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 5</description>
|
|
<addressOffset>0x0000015D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL5_TXPOLL</name>
|
|
<description>RX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL5</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 5</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000015D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL5_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMAXP6</name>
|
|
<description>USB Maximum Transmit Data Endpoint 6</description>
|
|
<addressOffset>0x00000160</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXMAXP6_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL6</name>
|
|
<description>USB Transmit Control and Status Endpoint 6 Low</description>
|
|
<addressOffset>0x00000162</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL6_TXRDY</name>
|
|
<description>Transmit Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL6_FIFONE</name>
|
|
<description>FIFO Not Empty</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL6_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL6_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL6_SETUP</name>
|
|
<description>Setup Packet</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL6_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL6_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL6_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL6</name>
|
|
<description>USB Transmit Control and Status Endpoint 6 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000162</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL6_UNDRN</name>
|
|
<description>Underrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL6_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRH6</name>
|
|
<description>USB Transmit Control and Status Endpoint 6 High</description>
|
|
<addressOffset>0x00000163</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRH6_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH6_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH6_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH6_FDT</name>
|
|
<description>Force Data Toggle</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH6_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH6_MODE</name>
|
|
<description>Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH6_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH6_AUTOSET</name>
|
|
<description>Auto Set</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXMAXP6</name>
|
|
<description>USB Maximum Receive Data Endpoint 6</description>
|
|
<addressOffset>0x00000164</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXMAXP6_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL6</name>
|
|
<description>USB Receive Control and Status Endpoint 6 Low</description>
|
|
<addressOffset>0x00000166</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL6_RXRDY</name>
|
|
<description>Receive Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL6_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL6_OVER</name>
|
|
<description>Overrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL6_DATAERR</name>
|
|
<description>Data Error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL6_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL6_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL6_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL6_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL6</name>
|
|
<description>USB Receive Control and Status Endpoint 6 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000166</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL6_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL6_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL6_REQPKT</name>
|
|
<description>Request Packet</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH6</name>
|
|
<description>USB Receive Control and Status Endpoint 6 High</description>
|
|
<addressOffset>0x00000167</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH6_INCOMPRX</name>
|
|
<description>Incomplete RX Transmission Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH6_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH6_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH6_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH6_PIDERR</name>
|
|
<description>PID Error</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH6_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH6_AUTORQ</name>
|
|
<description>Auto Request</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH6_AUTOCL</name>
|
|
<description>Auto Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH6</name>
|
|
<description>USB Receive Control and Status Endpoint 6 High</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000167</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH6_DISNYET</name>
|
|
<description>Disable NYET</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH6_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCOUNT6</name>
|
|
<description>USB Receive Byte Count Endpoint 6</description>
|
|
<addressOffset>0x00000168</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCOUNT6_COUNT</name>
|
|
<description>Receive Packet Count</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXTYPE6</name>
|
|
<description>USB Host Transmit Configure Type Endpoint 6</description>
|
|
<addressOffset>0x0000016A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXTYPE6_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE6_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE6_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE6_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE6_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE6_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE6_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE6_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE6_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE6_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE6_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL6</name>
|
|
<description>USB Host Transmit Interval Endpoint 6</description>
|
|
<addressOffset>0x0000016B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL6_TXPOLL</name>
|
|
<description>TX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL6</name>
|
|
<description>USB Host Transmit Interval Endpoint 6</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000016B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL6_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXTYPE6</name>
|
|
<description>USB Host Configure Receive Type Endpoint 6</description>
|
|
<addressOffset>0x0000016C</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXTYPE6_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE6_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE6_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE6_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE6_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE6_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE6_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE6_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE6_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE6_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE6_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL6</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 6</description>
|
|
<addressOffset>0x0000016D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL6_TXPOLL</name>
|
|
<description>RX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL6</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 6</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000016D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL6_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMAXP7</name>
|
|
<description>USB Maximum Transmit Data Endpoint 7</description>
|
|
<addressOffset>0x00000170</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXMAXP7_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL7</name>
|
|
<description>USB Transmit Control and Status Endpoint 7 Low</description>
|
|
<addressOffset>0x00000172</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL7_TXRDY</name>
|
|
<description>Transmit Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL7_FIFONE</name>
|
|
<description>FIFO Not Empty</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL7_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL7_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL7_SETUP</name>
|
|
<description>Setup Packet</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL7_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL7_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL7_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRL7</name>
|
|
<description>USB Transmit Control and Status Endpoint 7 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000172</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRL7_UNDRN</name>
|
|
<description>Underrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRL7_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCSRH7</name>
|
|
<description>USB Transmit Control and Status Endpoint 7 High</description>
|
|
<addressOffset>0x00000173</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXCSRH7_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH7_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH7_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH7_FDT</name>
|
|
<description>Force Data Toggle</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH7_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH7_MODE</name>
|
|
<description>Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH7_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXCSRH7_AUTOSET</name>
|
|
<description>Auto Set</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXMAXP7</name>
|
|
<description>USB Maximum Receive Data Endpoint 7</description>
|
|
<addressOffset>0x00000174</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXMAXP7_MAXLOAD</name>
|
|
<description>Maximum Payload</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL7</name>
|
|
<description>USB Receive Control and Status Endpoint 7 Low</description>
|
|
<addressOffset>0x00000176</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL7_RXRDY</name>
|
|
<description>Receive Packet Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL7_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL7_OVER</name>
|
|
<description>Overrun</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL7_DATAERR</name>
|
|
<description>Data Error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL7_FLUSH</name>
|
|
<description>Flush FIFO</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL7_STALL</name>
|
|
<description>Send STALL</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL7_STALLED</name>
|
|
<description>Endpoint Stalled</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL7_CLRDT</name>
|
|
<description>Clear Data Toggle</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRL7</name>
|
|
<description>USB Receive Control and Status Endpoint 7 Low</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000176</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRL7_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL7_NAKTO</name>
|
|
<description>NAK Timeout</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRL7_REQPKT</name>
|
|
<description>Request Packet</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH7</name>
|
|
<description>USB Receive Control and Status Endpoint 7 High</description>
|
|
<addressOffset>0x00000177</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH7_INCOMPRX</name>
|
|
<description>Incomplete RX Transmission Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH7_DT</name>
|
|
<description>Data Toggle</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH7_DTWE</name>
|
|
<description>Data Toggle Write Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH7_DMAMOD</name>
|
|
<description>DMA Request Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH7_PIDERR</name>
|
|
<description>PID Error</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH7_DMAEN</name>
|
|
<description>DMA Request Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH7_AUTORQ</name>
|
|
<description>Auto Request</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH7_AUTOCL</name>
|
|
<description>Auto Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCSRH7</name>
|
|
<description>USB Receive Control and Status Endpoint 7 High</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x00000177</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCSRH7_DISNYET</name>
|
|
<description>Disable NYET</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXCSRH7_ISO</name>
|
|
<description>Isochronous Transfers</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCOUNT7</name>
|
|
<description>USB Receive Byte Count Endpoint 7</description>
|
|
<addressOffset>0x00000178</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXCOUNT7_COUNT</name>
|
|
<description>Receive Packet Count</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXTYPE7</name>
|
|
<description>USB Host Transmit Configure Type Endpoint 7</description>
|
|
<addressOffset>0x0000017A</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXTYPE7_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE7_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE7_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE7_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE7_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE7_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXTYPE7_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE7_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE7_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE7_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_TXTYPE7_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL7</name>
|
|
<description>USB Host Transmit Interval Endpoint 7</description>
|
|
<addressOffset>0x0000017B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL7_TXPOLL</name>
|
|
<description>TX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXINTERVAL7</name>
|
|
<description>USB Host Transmit Interval Endpoint 7</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000017B</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXINTERVAL7_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXTYPE7</name>
|
|
<description>USB Host Configure Receive Type Endpoint 7</description>
|
|
<addressOffset>0x0000017C</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXTYPE7_TEP</name>
|
|
<description>Target Endpoint Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE7_PROTO</name>
|
|
<description>Protocol</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE7_PROTO_CTRL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE7_PROTO_ISOC</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE7_PROTO_BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE7_PROTO_INT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXTYPE7_SPEED</name>
|
|
<description>Operating Speed</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE7_SPEED_DFLT</name>
|
|
<description>Default</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE7_SPEED_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE7_SPEED_FULL</name>
|
|
<description>Full</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_RXTYPE7_SPEED_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL7</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 7</description>
|
|
<addressOffset>0x0000017D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL7_TXPOLL</name>
|
|
<description>RX Polling</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTERVAL7</name>
|
|
<description>USB Host Receive Polling Interval Endpoint 7</description>
|
|
<alternateGroup>USB0_ALT</alternateGroup>
|
|
<addressOffset>0x0000017D</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXINTERVAL7_NAKLMT</name>
|
|
<description>NAK Limit</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAINTR</name>
|
|
<description>USB DMA Interrupt</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMAINTR_CH0</name>
|
|
<description>Channel 0 DMA Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMAINTR_CH1</name>
|
|
<description>Channel 1 DMA Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMAINTR_CH2</name>
|
|
<description>Channel 2 DMA Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMAINTR_CH3</name>
|
|
<description>Channel 3 DMA Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMAINTR_CH4</name>
|
|
<description>Channel 4 DMA Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMAINTR_CH5</name>
|
|
<description>Channel 5 DMA Interrupt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMAINTR_CH6</name>
|
|
<description>Channel 6 DMA Interrupt</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMAINTR_CH7</name>
|
|
<description>Channel 7 DMA Interrupt</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACTL0</name>
|
|
<description>USB DMA Control 0</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACTL0_ENABLE</name>
|
|
<description>DMA Transfer Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL0_DIR</name>
|
|
<description>DMA Direction</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL0_MODE</name>
|
|
<description>DMA Transfer Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL0_IE</name>
|
|
<description>DMA Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL0_EP</name>
|
|
<description>Endpoint number</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL0_ERR</name>
|
|
<description>Bus Error Bit</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL0_BRSTM</name>
|
|
<description>Burst Mode</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL0_BRSTM_ANY</name>
|
|
<description>Bursts of unspecified length</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL0_BRSTM_INC4</name>
|
|
<description>INCR4 or unspecified length</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL0_BRSTM_INC8</name>
|
|
<description>INCR8, INCR4 or unspecified length</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL0_BRSTM_INC16</name>
|
|
<description>INCR16, INCR8, INCR4 or unspecified length</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAADDR0</name>
|
|
<description>USB DMA Address 0</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMAADDR0_ADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACOUNT0</name>
|
|
<description>USB DMA Count 0</description>
|
|
<addressOffset>0x0000020C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACOUNT0_COUNT</name>
|
|
<description>DMA Count</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACTL1</name>
|
|
<description>USB DMA Control 1</description>
|
|
<addressOffset>0x00000214</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACTL1_ENABLE</name>
|
|
<description>DMA Transfer Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL1_DIR</name>
|
|
<description>DMA Direction</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL1_MODE</name>
|
|
<description>DMA Transfer Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL1_IE</name>
|
|
<description>DMA Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL1_EP</name>
|
|
<description>Endpoint number</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL1_ERR</name>
|
|
<description>Bus Error Bit</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL1_BRSTM</name>
|
|
<description>Burst Mode</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL1_BRSTM_ANY</name>
|
|
<description>Bursts of unspecified length</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL1_BRSTM_INC4</name>
|
|
<description>INCR4 or unspecified length</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL1_BRSTM_INC8</name>
|
|
<description>INCR8, INCR4 or unspecified length</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL1_BRSTM_INC16</name>
|
|
<description>INCR16, INCR8, INCR4 or unspecified length</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAADDR1</name>
|
|
<description>USB DMA Address 1</description>
|
|
<addressOffset>0x00000218</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMAADDR1_ADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACOUNT1</name>
|
|
<description>USB DMA Count 1</description>
|
|
<addressOffset>0x0000021C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACOUNT1_COUNT</name>
|
|
<description>DMA Count</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACTL2</name>
|
|
<description>USB DMA Control 2</description>
|
|
<addressOffset>0x00000224</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACTL2_ENABLE</name>
|
|
<description>DMA Transfer Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL2_DIR</name>
|
|
<description>DMA Direction</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL2_MODE</name>
|
|
<description>DMA Transfer Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL2_IE</name>
|
|
<description>DMA Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL2_EP</name>
|
|
<description>Endpoint number</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL2_ERR</name>
|
|
<description>Bus Error Bit</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL2_BRSTM</name>
|
|
<description>Burst Mode</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL2_BRSTM_ANY</name>
|
|
<description>Bursts of unspecified length</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL2_BRSTM_INC4</name>
|
|
<description>INCR4 or unspecified length</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL2_BRSTM_INC8</name>
|
|
<description>INCR8, INCR4 or unspecified length</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL2_BRSTM_INC16</name>
|
|
<description>INCR16, INCR8, INCR4 or unspecified length</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAADDR2</name>
|
|
<description>USB DMA Address 2</description>
|
|
<addressOffset>0x00000228</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMAADDR2_ADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACOUNT2</name>
|
|
<description>USB DMA Count 2</description>
|
|
<addressOffset>0x0000022C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACOUNT2_COUNT</name>
|
|
<description>DMA Count</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACTL3</name>
|
|
<description>USB DMA Control 3</description>
|
|
<addressOffset>0x00000234</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACTL3_ENABLE</name>
|
|
<description>DMA Transfer Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL3_DIR</name>
|
|
<description>DMA Direction</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL3_MODE</name>
|
|
<description>DMA Transfer Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL3_IE</name>
|
|
<description>DMA Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL3_EP</name>
|
|
<description>Endpoint number</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL3_ERR</name>
|
|
<description>Bus Error Bit</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL3_BRSTM</name>
|
|
<description>Burst Mode</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL3_BRSTM_ANY</name>
|
|
<description>Bursts of unspecified length</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL3_BRSTM_INC4</name>
|
|
<description>INCR4 or unspecified length</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL3_BRSTM_INC8</name>
|
|
<description>INCR8, INCR4 or unspecified length</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL3_BRSTM_INC16</name>
|
|
<description>INCR16, INCR8, INCR4 or unspecified length</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAADDR3</name>
|
|
<description>USB DMA Address 3</description>
|
|
<addressOffset>0x00000238</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMAADDR3_ADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACOUNT3</name>
|
|
<description>USB DMA Count 3</description>
|
|
<addressOffset>0x0000023C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACOUNT3_COUNT</name>
|
|
<description>DMA Count</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACTL4</name>
|
|
<description>USB DMA Control 4</description>
|
|
<addressOffset>0x00000244</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACTL4_ENABLE</name>
|
|
<description>DMA Transfer Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL4_DIR</name>
|
|
<description>DMA Direction</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL4_MODE</name>
|
|
<description>DMA Transfer Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL4_IE</name>
|
|
<description>DMA Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL4_EP</name>
|
|
<description>Endpoint number</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL4_ERR</name>
|
|
<description>Bus Error Bit</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL4_BRSTM</name>
|
|
<description>Burst Mode</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL4_BRSTM_ANY</name>
|
|
<description>Bursts of unspecified length</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL4_BRSTM_INC4</name>
|
|
<description>INCR4 or unspecified length</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL4_BRSTM_INC8</name>
|
|
<description>INCR8, INCR4 or unspecified length</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL4_BRSTM_INC16</name>
|
|
<description>INCR16, INCR8, INCR4 or unspecified length</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAADDR4</name>
|
|
<description>USB DMA Address 4</description>
|
|
<addressOffset>0x00000248</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMAADDR4_ADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACOUNT4</name>
|
|
<description>USB DMA Count 4</description>
|
|
<addressOffset>0x0000024C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACOUNT4_COUNT</name>
|
|
<description>DMA Count</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACTL5</name>
|
|
<description>USB DMA Control 5</description>
|
|
<addressOffset>0x00000254</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACTL5_ENABLE</name>
|
|
<description>DMA Transfer Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL5_DIR</name>
|
|
<description>DMA Direction</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL5_MODE</name>
|
|
<description>DMA Transfer Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL5_IE</name>
|
|
<description>DMA Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL5_EP</name>
|
|
<description>Endpoint number</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL5_ERR</name>
|
|
<description>Bus Error Bit</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL5_BRSTM</name>
|
|
<description>Burst Mode</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL5_BRSTM_ANY</name>
|
|
<description>Bursts of unspecified length</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL5_BRSTM_INC4</name>
|
|
<description>INCR4 or unspecified length</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL5_BRSTM_INC8</name>
|
|
<description>INCR8, INCR4 or unspecified length</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL5_BRSTM_INC16</name>
|
|
<description>INCR16, INCR8, INCR4 or unspecified length</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAADDR5</name>
|
|
<description>USB DMA Address 5</description>
|
|
<addressOffset>0x00000258</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMAADDR5_ADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACOUNT5</name>
|
|
<description>USB DMA Count 5</description>
|
|
<addressOffset>0x0000025C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACOUNT5_COUNT</name>
|
|
<description>DMA Count</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACTL6</name>
|
|
<description>USB DMA Control 6</description>
|
|
<addressOffset>0x00000264</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACTL6_ENABLE</name>
|
|
<description>DMA Transfer Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL6_DIR</name>
|
|
<description>DMA Direction</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL6_MODE</name>
|
|
<description>DMA Transfer Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL6_IE</name>
|
|
<description>DMA Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL6_EP</name>
|
|
<description>Endpoint number</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL6_ERR</name>
|
|
<description>Bus Error Bit</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL6_BRSTM</name>
|
|
<description>Burst Mode</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL6_BRSTM_ANY</name>
|
|
<description>Bursts of unspecified length</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL6_BRSTM_INC4</name>
|
|
<description>INCR4 or unspecified length</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL6_BRSTM_INC8</name>
|
|
<description>INCR8, INCR4 or unspecified length</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL6_BRSTM_INC16</name>
|
|
<description>INCR16, INCR8, INCR4 or unspecified length</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAADDR6</name>
|
|
<description>USB DMA Address 6</description>
|
|
<addressOffset>0x00000268</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMAADDR6_ADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACOUNT6</name>
|
|
<description>USB DMA Count 6</description>
|
|
<addressOffset>0x0000026C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACOUNT6_COUNT</name>
|
|
<description>DMA Count</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACTL7</name>
|
|
<description>USB DMA Control 7</description>
|
|
<addressOffset>0x00000274</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACTL7_ENABLE</name>
|
|
<description>DMA Transfer Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL7_DIR</name>
|
|
<description>DMA Direction</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL7_MODE</name>
|
|
<description>DMA Transfer Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL7_IE</name>
|
|
<description>DMA Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL7_EP</name>
|
|
<description>Endpoint number</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL7_ERR</name>
|
|
<description>Bus Error Bit</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_DMACTL7_BRSTM</name>
|
|
<description>Burst Mode</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL7_BRSTM_ANY</name>
|
|
<description>Bursts of unspecified length</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL7_BRSTM_INC4</name>
|
|
<description>INCR4 or unspecified length</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL7_BRSTM_INC8</name>
|
|
<description>INCR8, INCR4 or unspecified length</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_DMACTL7_BRSTM_INC16</name>
|
|
<description>INCR16, INCR8, INCR4 or unspecified length</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAADDR7</name>
|
|
<description>USB DMA Address 7</description>
|
|
<addressOffset>0x00000278</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMAADDR7_ADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACOUNT7</name>
|
|
<description>USB DMA Count 7</description>
|
|
<addressOffset>0x0000027C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DMACOUNT7_COUNT</name>
|
|
<description>DMA Count</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RQPKTCOUNT1</name>
|
|
<description>USB Request Packet Count in Block Transfer Endpoint 1</description>
|
|
<addressOffset>0x00000304</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RQPKTCOUNT1</name>
|
|
<description>Block Transfer Packet Count</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RQPKTCOUNT2</name>
|
|
<description>USB Request Packet Count in Block Transfer Endpoint 2</description>
|
|
<addressOffset>0x00000308</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RQPKTCOUNT2</name>
|
|
<description>Block Transfer Packet Count</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RQPKTCOUNT3</name>
|
|
<description>USB Request Packet Count in Block Transfer Endpoint 3</description>
|
|
<addressOffset>0x0000030C</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RQPKTCOUNT3</name>
|
|
<description>Block Transfer Packet Count</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RQPKTCOUNT4</name>
|
|
<description>USB Request Packet Count in Block Transfer Endpoint 4</description>
|
|
<addressOffset>0x00000310</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RQPKTCOUNT4_COUNT</name>
|
|
<description>Block Transfer Packet Count</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RQPKTCOUNT5</name>
|
|
<description>USB Request Packet Count in Block Transfer Endpoint 5</description>
|
|
<addressOffset>0x00000314</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RQPKTCOUNT5_COUNT</name>
|
|
<description>Block Transfer Packet Count</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RQPKTCOUNT6</name>
|
|
<description>USB Request Packet Count in Block Transfer Endpoint 6</description>
|
|
<addressOffset>0x00000318</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RQPKTCOUNT6_COUNT</name>
|
|
<description>Block Transfer Packet Count</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RQPKTCOUNT7</name>
|
|
<description>USB Request Packet Count in Block Transfer Endpoint 7</description>
|
|
<addressOffset>0x0000031C</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RQPKTCOUNT7_COUNT</name>
|
|
<description>Block Transfer Packet Count</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDPKTBUFDIS</name>
|
|
<description>USB Receive Double Packet Buffer Disable</description>
|
|
<addressOffset>0x00000340</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_RXDPKTBUFDIS_EP1</name>
|
|
<description>EP1 RX Double-Packet Buffer Disable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXDPKTBUFDIS_EP2</name>
|
|
<description>EP2 RX Double-Packet Buffer Disable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXDPKTBUFDIS_EP3</name>
|
|
<description>EP3 RX Double-Packet Buffer Disable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXDPKTBUFDIS_EP4</name>
|
|
<description>EP4 RX Double-Packet Buffer Disable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXDPKTBUFDIS_EP5</name>
|
|
<description>EP5 RX Double-Packet Buffer Disable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXDPKTBUFDIS_EP6</name>
|
|
<description>EP6 RX Double-Packet Buffer Disable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_RXDPKTBUFDIS_EP7</name>
|
|
<description>EP7 RX Double-Packet Buffer Disable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDPKTBUFDIS</name>
|
|
<description>USB Transmit Double Packet Buffer Disable</description>
|
|
<addressOffset>0x00000342</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_TXDPKTBUFDIS_EP1</name>
|
|
<description>EP1 TX Double-Packet Buffer Disable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXDPKTBUFDIS_EP2</name>
|
|
<description>EP2 TX Double-Packet Buffer Disable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXDPKTBUFDIS_EP3</name>
|
|
<description>EP3 TX Double-Packet Buffer Disable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXDPKTBUFDIS_EP4</name>
|
|
<description>EP4 TX Double-Packet Buffer Disable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXDPKTBUFDIS_EP5</name>
|
|
<description>EP5 TX Double-Packet Buffer Disable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXDPKTBUFDIS_EP6</name>
|
|
<description>EP6 TX Double-Packet Buffer Disable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_TXDPKTBUFDIS_EP7</name>
|
|
<description>EP7 TX Double-Packet Buffer Disable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTO</name>
|
|
<description>USB Chirp Timeout</description>
|
|
<addressOffset>0x00000344</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_CTO_CCTV</name>
|
|
<description>Configurable Chirp Timeout Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HHSRTN</name>
|
|
<description>USB High Speed to UTM Operating Delay</description>
|
|
<addressOffset>0x00000346</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_HHSRTN_HHSRTN</name>
|
|
<description>HIgh Speed to UTM Operating Delay</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSBT</name>
|
|
<description>USB High Speed Time-out Adder</description>
|
|
<addressOffset>0x00000348</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_HSBT_HSBT</name>
|
|
<description>High Speed Timeout Adder</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPMATTR</name>
|
|
<description>USB LPM Attributes</description>
|
|
<addressOffset>0x00000360</addressOffset>
|
|
<size>16</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_LPMATTR_LS</name>
|
|
<description>Link State</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_LPMATTR_LS_L1</name>
|
|
<description>Sleep State (L1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMATTR_HIRD</name>
|
|
<description>Host Initiated Resume Duration</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMATTR_RMTWAK</name>
|
|
<description>Remote Wake</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMATTR_ENDPT</name>
|
|
<description>Endpoint</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPMCNTRL</name>
|
|
<description>USB LPM Control</description>
|
|
<addressOffset>0x00000362</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_LPMCNTRL_TXLPM</name>
|
|
<description>Transmit LPM Transaction Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMCNTRL_RES</name>
|
|
<description>LPM Resume</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMCNTRL_EN</name>
|
|
<description>LPM Enable</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_LPMCNTRL_EN_NONE</name>
|
|
<description>LPM and Extended transactions are not supported. In this case, the USB does not respond to LPM transactions and LPM transactions cause a timeout</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_LPMCNTRL_EN_EXT</name>
|
|
<description>LPM is not supported but extended transactions are supported. In this case, the USB does respond to an LPM transaction with a STALL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_LPMCNTRL_EN_LPMEXT</name>
|
|
<description>The USB supports LPM extended transactions. In this case, the USB responds with a NYET or an ACK as determined by the value of TXLPM and other conditions</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMCNTRL_NAK</name>
|
|
<description>LPM NAK</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPMIM</name>
|
|
<description>USB LPM Interrupt Mask</description>
|
|
<addressOffset>0x00000363</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_LPMIM_STALL</name>
|
|
<description>LPM STALL Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMIM_NY</name>
|
|
<description>LPM NY Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMIM_ACK</name>
|
|
<description>LPM ACK Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMIM_NC</name>
|
|
<description>LPM NC Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMIM_RES</name>
|
|
<description>LPM Resume Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMIM_ERR</name>
|
|
<description>LPM Error Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPMRIS</name>
|
|
<description>USB LPM Raw Interrupt Status</description>
|
|
<addressOffset>0x00000364</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_LPMRIS_LPMST</name>
|
|
<description>LPM STALL Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMRIS_NY</name>
|
|
<description>LPM NY Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMRIS_ACK</name>
|
|
<description>LPM ACK Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMRIS_NC</name>
|
|
<description>LPM NC Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMRIS_RES</name>
|
|
<description>LPM Resume Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_LPMRIS_ERR</name>
|
|
<description>LPM Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPMFADDR</name>
|
|
<description>USB LPM Function Address</description>
|
|
<addressOffset>0x00000365</addressOffset>
|
|
<size>8</size>
|
|
<fields>
|
|
<field>
|
|
<name>USB_LPMFADDR_ADDR</name>
|
|
<description>LPM Function Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPC</name>
|
|
<description>USB External Power Control</description>
|
|
<addressOffset>0x00000400</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_EPC_EPEN</name>
|
|
<description>External Power Supply Enable Configuration</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_EPC_EPEN_LOW</name>
|
|
<description>Power Enable Active Low</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_EPC_EPEN_HIGH</name>
|
|
<description>Power Enable Active High</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_EPC_EPEN_VBLOW</name>
|
|
<description>Power Enable High if VBUS Low (OTG only)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_EPC_EPEN_VBHIGH</name>
|
|
<description>Power Enable High if VBUS High (OTG only)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_EPC_EPENDE</name>
|
|
<description>EPEN Drive Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_EPC_PFLTEN</name>
|
|
<description>Power Fault Input Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_EPC_PFLTSEN_HIGH</name>
|
|
<description>Power Fault Sense</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_EPC_PFLTAEN</name>
|
|
<description>Power Fault Action Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_EPC_PFLTACT</name>
|
|
<description>Power Fault Action</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_EPC_PFLTACT_UNCHG</name>
|
|
<description>Unchanged</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_EPC_PFLTACT_TRIS</name>
|
|
<description>Tristate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_EPC_PFLTACT_LOW</name>
|
|
<description>Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_EPC_PFLTACT_HIGH</name>
|
|
<description>High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPCRIS</name>
|
|
<description>USB External Power Control Raw Interrupt Status</description>
|
|
<addressOffset>0x00000404</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_EPCRIS_PF</name>
|
|
<description>USB Power Fault Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPCIM</name>
|
|
<description>USB External Power Control Interrupt Mask</description>
|
|
<addressOffset>0x00000408</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_EPCIM_PF</name>
|
|
<description>USB Power Fault Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPCISC</name>
|
|
<description>USB External Power Control Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000040C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_EPCISC_PF</name>
|
|
<description>USB Power Fault Interrupt Status and Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DRRIS</name>
|
|
<description>USB Device RESUME Raw Interrupt Status</description>
|
|
<addressOffset>0x00000410</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DRRIS_RESUME</name>
|
|
<description>RESUME Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DRIM</name>
|
|
<description>USB Device RESUME Interrupt Mask</description>
|
|
<addressOffset>0x00000414</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DRIM_RESUME</name>
|
|
<description>RESUME Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DRISC</name>
|
|
<description>USB Device RESUME Interrupt Status and Clear</description>
|
|
<addressOffset>0x00000418</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>USB_DRISC_RESUME</name>
|
|
<description>RESUME Interrupt Status and Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCS</name>
|
|
<description>USB General-Purpose Control and Status</description>
|
|
<addressOffset>0x0000041C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_GPCS_DEVMOD</name>
|
|
<description>Device Mode</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_GPCS_DEVMOD_OTG</name>
|
|
<description>Use USB0VBUS and USB0ID pin</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_GPCS_DEVMOD_HOST</name>
|
|
<description>Force USB0VBUS and USB0ID low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_GPCS_DEVMOD_DEV</name>
|
|
<description>Force USB0VBUS and USB0ID high</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_GPCS_DEVMOD_HOSTVBUS</name>
|
|
<description>Use USB0VBUS and force USB0ID low</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_GPCS_DEVMOD_DEVVBUS</name>
|
|
<description>Use USB0VBUS and force USB0ID high</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VDC</name>
|
|
<description>USB VBUS Droop Control</description>
|
|
<addressOffset>0x00000430</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_VDC_VBDEN</name>
|
|
<description>VBUS Droop Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VDCRIS</name>
|
|
<description>USB VBUS Droop Control Raw Interrupt Status</description>
|
|
<addressOffset>0x00000434</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_VDCRIS_VD</name>
|
|
<description>VBUS Droop Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VDCIM</name>
|
|
<description>USB VBUS Droop Control Interrupt Mask</description>
|
|
<addressOffset>0x00000438</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_VDCIM_VD</name>
|
|
<description>VBUS Droop Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VDCISC</name>
|
|
<description>USB VBUS Droop Control Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000043C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_VDCISC_VD</name>
|
|
<description>VBUS Droop Interrupt Status and Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>USB Peripheral Properties</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_PP_TYPE</name>
|
|
<description>Controller Type</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_PP_TYPE_0</name>
|
|
<description>The first-generation USB controller revision</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_PP_TYPE_1</name>
|
|
<description>The second-generation USB controller revision</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_PP_PHY</name>
|
|
<description>PHY Present</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_PP_ULPI</name>
|
|
<description>ULPI Present</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_PP_USB</name>
|
|
<description>USB Capability</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_PP_USB_DEVICE</name>
|
|
<description>DEVICE</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_PP_USB_HOSTDEVICE</name>
|
|
<description>HOST</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_PP_USB_OTG</name>
|
|
<description>OTG</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_PP_ECNT</name>
|
|
<description>Endpoint Count</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>USB Peripheral Configuration</description>
|
|
<addressOffset>0x00000FC4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_PC_ULPIEN</name>
|
|
<description>ULPI Enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC</name>
|
|
<description>USB Clock Configuration</description>
|
|
<addressOffset>0x00000FC8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>USB_CC_CLKDIV</name>
|
|
<description>PLL Clock Divisor</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_CC_CSD</name>
|
|
<description>Clock Source/Direction</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB_CC_CLKEN</name>
|
|
<description>USB Clock Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOA</name>
|
|
<description>Register map for GPIOA peripheral</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOA</prependToName>
|
|
<baseAddress>0x40058000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>GPIOA</name><value>0</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>GPIO Data</description>
|
|
<addressOffset>0x000003FC</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DIR</name>
|
|
<description>GPIO Direction</description>
|
|
<addressOffset>0x00000400</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>IS</name>
|
|
<description>GPIO Interrupt Sense</description>
|
|
<addressOffset>0x00000404</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>IBE</name>
|
|
<description>GPIO Interrupt Both Edges</description>
|
|
<addressOffset>0x00000408</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>IEV</name>
|
|
<description>GPIO Interrupt Event</description>
|
|
<addressOffset>0x0000040C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>IM</name>
|
|
<description>GPIO Interrupt Mask</description>
|
|
<addressOffset>0x00000410</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_IM_GPIO</name>
|
|
<description>GPIO Interrupt Mask Enable</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_IM_DMAIME</name>
|
|
<description>GPIO uDMA Done Interrupt Mask Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>GPIO Raw Interrupt Status</description>
|
|
<addressOffset>0x00000414</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_RIS_GPIO</name>
|
|
<description>GPIO Interrupt Raw Status</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_RIS_DMARIS</name>
|
|
<description>GPIO uDMA Done Interrupt Raw Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>GPIO Masked Interrupt Status</description>
|
|
<addressOffset>0x00000418</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_MIS_GPIO</name>
|
|
<description>GPIO Masked Interrupt Status</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_MIS_DMAMIS</name>
|
|
<description>GPIO uDMA Done Masked Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>GPIO Interrupt Clear</description>
|
|
<addressOffset>0x0000041C</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_ICR_GPIO</name>
|
|
<description>GPIO Interrupt Clear</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_ICR_DMAIC</name>
|
|
<description>GPIO uDMA Interrupt Clear</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSEL</name>
|
|
<description>GPIO Alternate Function Select</description>
|
|
<addressOffset>0x00000420</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DR2R</name>
|
|
<description>GPIO 2-mA Drive Select</description>
|
|
<addressOffset>0x00000500</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DR4R</name>
|
|
<description>GPIO 4-mA Drive Select</description>
|
|
<addressOffset>0x00000504</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DR8R</name>
|
|
<description>GPIO 8-mA Drive Select</description>
|
|
<addressOffset>0x00000508</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>ODR</name>
|
|
<description>GPIO Open Drain Select</description>
|
|
<addressOffset>0x0000050C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>PUR</name>
|
|
<description>GPIO Pull-Up Select</description>
|
|
<addressOffset>0x00000510</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>PDR</name>
|
|
<description>GPIO Pull-Down Select</description>
|
|
<addressOffset>0x00000514</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>SLR</name>
|
|
<description>GPIO Slew Rate Control Select</description>
|
|
<addressOffset>0x00000518</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DEN</name>
|
|
<description>GPIO Digital Enable</description>
|
|
<addressOffset>0x0000051C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<description>GPIO Lock</description>
|
|
<addressOffset>0x00000520</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_LOCK</name>
|
|
<description>GPIO Lock</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_LOCK_UNLOCKED</name>
|
|
<description>The GPIOCR register is unlocked and may be modified</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_LOCK_LOCKED</name>
|
|
<description>The GPIOCR register is locked and may not be modified</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>GPIO Commit</description>
|
|
<addressOffset>0x00000524</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>AMSEL</name>
|
|
<description>GPIO Analog Mode Select</description>
|
|
<addressOffset>0x00000528</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>PCTL</name>
|
|
<description>GPIO Port Control</description>
|
|
<addressOffset>0x0000052C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>ADCCTL</name>
|
|
<description>GPIO ADC Control</description>
|
|
<addressOffset>0x00000530</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DMACTL</name>
|
|
<description>GPIO DMA Control</description>
|
|
<addressOffset>0x00000534</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>SI</name>
|
|
<description>GPIO Select Interrupt</description>
|
|
<addressOffset>0x00000538</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_SI_SUM</name>
|
|
<description>Summary Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR12R</name>
|
|
<description>GPIO 12-mA Drive Select</description>
|
|
<addressOffset>0x0000053C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_DR12R_DRV12</name>
|
|
<description>Output Pad 12-mA Drive Enable</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_DR12R_DRV12_12MA</name>
|
|
<description>The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAKEPEN</name>
|
|
<description>GPIO Wake Pin Enable</description>
|
|
<addressOffset>0x00000540</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_WAKEPEN_WAKEP4</name>
|
|
<description>P[4] Wake Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAKELVL</name>
|
|
<description>GPIO Wake Level</description>
|
|
<addressOffset>0x00000544</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_WAKELVL_WAKELVL4</name>
|
|
<description>P[4] Wake Level</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAKESTAT</name>
|
|
<description>GPIO Wake Status</description>
|
|
<addressOffset>0x00000548</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_WAKESTAT_STAT4</name>
|
|
<description>P[4] Wake Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>GPIO Peripheral Property</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_PP_EDE</name>
|
|
<description>Extended Drive Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>GPIO Peripheral Configuration</description>
|
|
<addressOffset>0x00000FC4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_PC_EDM0</name>
|
|
<description>Extended Drive Mode Bit 0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_PC_EDM0_DISABLE</name>
|
|
<description>Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PC_EDM0_6MA</name>
|
|
<description>An additional 6 mA option is provided</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PC_EDM0_PLUS2MA</name>
|
|
<description>A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_PC_EDM1</name>
|
|
<description>Extended Drive Mode Bit 1</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_PC_EDM2</name>
|
|
<description>Extended Drive Mode Bit 2</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_PC_EDM3</name>
|
|
<description>Extended Drive Mode Bit 3</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_PC_EDM4</name>
|
|
<description>Extended Drive Mode Bit 4</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_PC_EDM5</name>
|
|
<description>Extended Drive Mode Bit 5</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_PC_EDM6</name>
|
|
<description>Extended Drive Mode Bit 6</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_PC_EDM7</name>
|
|
<description>Extended Drive Mode Bit 7</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOB</name>
|
|
<prependToName>GPIOB</prependToName>
|
|
<baseAddress>0x40059000</baseAddress>
|
|
<interrupt><name>GPIOB</name><value>1</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOC</name>
|
|
<prependToName>GPIOC</prependToName>
|
|
<baseAddress>0x4005A000</baseAddress>
|
|
<interrupt><name>GPIOC</name><value>2</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOD</name>
|
|
<prependToName>GPIOD</prependToName>
|
|
<baseAddress>0x4005B000</baseAddress>
|
|
<interrupt><name>GPIOD</name><value>3</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOE</name>
|
|
<prependToName>GPIOE</prependToName>
|
|
<baseAddress>0x4005C000</baseAddress>
|
|
<interrupt><name>GPIOE</name><value>4</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOF</name>
|
|
<prependToName>GPIOF</prependToName>
|
|
<baseAddress>0x4005D000</baseAddress>
|
|
<interrupt><name>GPIOF</name><value>30</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOG</name>
|
|
<prependToName>GPIOG</prependToName>
|
|
<baseAddress>0x4005E000</baseAddress>
|
|
<interrupt><name>GPIOG</name><value>31</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOH</name>
|
|
<prependToName>GPIOH</prependToName>
|
|
<baseAddress>0x4005F000</baseAddress>
|
|
<interrupt><name>GPIOH</name><value>32</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOJ</name>
|
|
<prependToName>GPIOJ</prependToName>
|
|
<baseAddress>0x40060000</baseAddress>
|
|
<interrupt><name>GPIOJ</name><value>51</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOK</name>
|
|
<prependToName>GPIOK</prependToName>
|
|
<baseAddress>0x40061000</baseAddress>
|
|
<interrupt><name>GPIOK</name><value>52</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOL</name>
|
|
<prependToName>GPIOL</prependToName>
|
|
<baseAddress>0x40062000</baseAddress>
|
|
<interrupt><name>GPIOL</name><value>53</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOM</name>
|
|
<prependToName>GPIOM</prependToName>
|
|
<baseAddress>0x40063000</baseAddress>
|
|
<interrupt><name>GPIOM</name><value>72</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPION</name>
|
|
<prependToName>GPION</prependToName>
|
|
<baseAddress>0x40064000</baseAddress>
|
|
<interrupt><name>GPION</name><value>73</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOP</name>
|
|
<prependToName>GPIOP</prependToName>
|
|
<baseAddress>0x40065000</baseAddress>
|
|
<interrupt><name>GPIOP0</name><value>76</value></interrupt>
|
|
<interrupt><name>GPIOP1</name><value>77</value></interrupt>
|
|
<interrupt><name>GPIOP2</name><value>78</value></interrupt>
|
|
<interrupt><name>GPIOP3</name><value>79</value></interrupt>
|
|
<interrupt><name>GPIOP4</name><value>80</value></interrupt>
|
|
<interrupt><name>GPIOP5</name><value>81</value></interrupt>
|
|
<interrupt><name>GPIOP6</name><value>82</value></interrupt>
|
|
<interrupt><name>GPIOP7</name><value>83</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOQ</name>
|
|
<prependToName>GPIOQ</prependToName>
|
|
<baseAddress>0x40066000</baseAddress>
|
|
<interrupt><name>GPIOQ0</name><value>84</value></interrupt>
|
|
<interrupt><name>GPIOQ1</name><value>85</value></interrupt>
|
|
<interrupt><name>GPIOQ2</name><value>86</value></interrupt>
|
|
<interrupt><name>GPIOQ3</name><value>87</value></interrupt>
|
|
<interrupt><name>GPIOQ4</name><value>88</value></interrupt>
|
|
<interrupt><name>GPIOQ5</name><value>89</value></interrupt>
|
|
<interrupt><name>GPIOQ6</name><value>90</value></interrupt>
|
|
<interrupt><name>GPIOQ7</name><value>91</value></interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EEPROM</name>
|
|
<description>Register map for EEPROM peripheral</description>
|
|
<groupName>EEPROM</groupName>
|
|
<prependToName>EEPROM</prependToName>
|
|
<baseAddress>0x400AF000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>EESIZE</name>
|
|
<description>EEPROM Size Information</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EESIZE_WORDCNT</name>
|
|
<description>Number of 32-Bit Words</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_EESIZE_BLKCNT</name>
|
|
<description>Number of 16-Word Blocks</description>
|
|
<bitRange>[26:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEBLOCK</name>
|
|
<description>EEPROM Current Block</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEBLOCK_BLOCK</name>
|
|
<description>Current Block</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEOFFSET</name>
|
|
<description>EEPROM Current Offset</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEOFFSET_OFFSET</name>
|
|
<description>Current Address Offset</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EERDWR</name>
|
|
<description>EEPROM Read-Write</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EERDWR_VALUE</name>
|
|
<description>EEPROM Read or Write Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EERDWRINC</name>
|
|
<description>EEPROM Read-Write with Increment</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EERDWRINC_VALUE</name>
|
|
<description>EEPROM Read or Write Data with Increment</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEDONE</name>
|
|
<description>EEPROM Done Status</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEDONE_WORKING</name>
|
|
<description>EEPROM Working</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_EEDONE_WKERASE</name>
|
|
<description>Working on an Erase</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_EEDONE_WKCOPY</name>
|
|
<description>Working on a Copy</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_EEDONE_NOPERM</name>
|
|
<description>Write Without Permission</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_EEDONE_WRBUSY</name>
|
|
<description>Write Busy</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EESUPP</name>
|
|
<description>EEPROM Support Control and Status</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EESUPP_ERETRY</name>
|
|
<description>Erase Must Be Retried</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_EESUPP_PRETRY</name>
|
|
<description>Programming Must Be Retried</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEUNLOCK</name>
|
|
<description>EEPROM Unlock</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEUNLOCK_UNLOCK</name>
|
|
<description>EEPROM Unlock</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEPROT</name>
|
|
<description>EEPROM Protection</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEPROT_PROT</name>
|
|
<description>Protection Control</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEPROM_EEPROT_PROT_RWNPW</name>
|
|
<description>This setting is the default. If there is no password, the block is not protected and is readable and writable</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEPROM_EEPROT_PROT_RWPW</name>
|
|
<description>If there is a password, the block is readable or writable only when unlocked</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEPROM_EEPROT_PROT_RONPW</name>
|
|
<description>If there is no password, the block is readable, not writable</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_EEPROT_ACC</name>
|
|
<description>Access Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEPASS0</name>
|
|
<description>EEPROM Password</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEPASS0_PASS</name>
|
|
<description>Password</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEPASS1</name>
|
|
<description>EEPROM Password</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEPASS1_PASS</name>
|
|
<description>Password</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEPASS2</name>
|
|
<description>EEPROM Password</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEPASS2_PASS</name>
|
|
<description>Password</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEINT</name>
|
|
<description>EEPROM Interrupt</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEINT_INT</name>
|
|
<description>Interrupt Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEHIDE0</name>
|
|
<description>EEPROM Block Hide 0</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEHIDE0_HN</name>
|
|
<description>Hide Block</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEHIDE1</name>
|
|
<description>EEPROM Block Hide 1</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEHIDE1_HN</name>
|
|
<description>Hide Block</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEHIDE2</name>
|
|
<description>EEPROM Block Hide 2</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEHIDE2_HN</name>
|
|
<description>Hide Block</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEDBGME</name>
|
|
<description>EEPROM Debug Mass Erase</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_EEDBGME_ME</name>
|
|
<description>Mass Erase</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_EEDBGME_KEY</name>
|
|
<description>Erase Key</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>EEPROM Peripheral Properties</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EEPROM_PP_SIZE</name>
|
|
<description>EEPROM Size</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C8</name>
|
|
<prependToName>I2C8</prependToName>
|
|
<baseAddress>0x400B8000</baseAddress>
|
|
<interrupt><name>I2C8</name><value>109</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C9</name>
|
|
<prependToName>I2C9</prependToName>
|
|
<baseAddress>0x400B9000</baseAddress>
|
|
<interrupt><name>I2C9</name><value>110</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C4</name>
|
|
<prependToName>I2C4</prependToName>
|
|
<baseAddress>0x400C0000</baseAddress>
|
|
<interrupt><name>I2C4</name><value>70</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C5</name>
|
|
<prependToName>I2C5</prependToName>
|
|
<baseAddress>0x400C1000</baseAddress>
|
|
<interrupt><name>I2C5</name><value>71</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C6</name>
|
|
<prependToName>I2C6</prependToName>
|
|
<baseAddress>0x400C2000</baseAddress>
|
|
<interrupt><name>I2C6</name><value>102</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C7</name>
|
|
<prependToName>I2C7</prependToName>
|
|
<baseAddress>0x400C3000</baseAddress>
|
|
<interrupt><name>I2C7</name><value>103</value></interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EPI0</name>
|
|
<description>Register map for EPI0 peripheral</description>
|
|
<groupName>EPI</groupName>
|
|
<prependToName>EPI0</prependToName>
|
|
<baseAddress>0x400D0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>EPI0</name><value>50</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>EPI Configuration</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_CFG_MODE</name>
|
|
<description>Mode Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_CFG_MODE_NONE</name>
|
|
<description>General Purpose</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_CFG_MODE_SDRAM</name>
|
|
<description>SDRAM</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_CFG_MODE_HB8</name>
|
|
<description>8-Bit Host-Bus (HB8)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_CFG_MODE_HB16</name>
|
|
<description>16-Bit Host-Bus (HB16)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_CFG_BLKEN</name>
|
|
<description>Block Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_CFG_INTDIV</name>
|
|
<description>Integer Clock Divider Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>EPI Main Baud Rate</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_BAUD_COUNT0</name>
|
|
<description>Baud Rate Counter 0</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_BAUD_COUNT1</name>
|
|
<description>Baud Rate Counter 1</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD2</name>
|
|
<description>EPI Main Baud Rate</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_BAUD2_COUNT0</name>
|
|
<description>CS2n Baud Rate Counter 0</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_BAUD2_COUNT1</name>
|
|
<description>CS3n Baud Rate Counter 1</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB16CFG</name>
|
|
<description>EPI Host-Bus 16 Configuration</description>
|
|
<alternateGroup>EPI_ALT16</alternateGroup>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB16CFG_MODE</name>
|
|
<description>Host Bus Sub-Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_MODE_ADMUX</name>
|
|
<description>ADMUX - AD[15:0]</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_MODE_ADNMUX</name>
|
|
<description>ADNONMUX - D[15:0]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_MODE_SRAM</name>
|
|
<description>Continuous Read - D[15:0]</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_MODE_XFIFO</name>
|
|
<description>XFIFO - D[15:0]</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_BSEL</name>
|
|
<description>Byte Select Configuration</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_RDWS</name>
|
|
<description>Read Wait States</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_RDWS_2</name>
|
|
<description>Active RDn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_RDWS_4</name>
|
|
<description>Active RDn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_RDWS_6</name>
|
|
<description>Active RDn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_RDWS_8</name>
|
|
<description>Active RDn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_WRWS</name>
|
|
<description>Write Wait States</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_WRWS_2</name>
|
|
<description>Active WRn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_WRWS_4</name>
|
|
<description>Active WRn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_WRWS_6</name>
|
|
<description>Active WRn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG_WRWS_8</name>
|
|
<description>Active WRn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_MAXWAIT</name>
|
|
<description>Maximum Wait</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_BURST</name>
|
|
<description>Burst Mode</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_RDCRE</name>
|
|
<description>PSRAM Configuration Register Read</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_WRCRE</name>
|
|
<description>PSRAM Configuration Register Write</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_ALEHIGH</name>
|
|
<description>ALE Strobe Polarity</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_RDHIGH</name>
|
|
<description>READ Strobe Polarity</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_WRHIGH</name>
|
|
<description>WRITE Strobe Polarity</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_XFEEN</name>
|
|
<description>External FIFO EMPTY Enable</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_XFFEN</name>
|
|
<description>External FIFO FULL Enable</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_IRDYINV</name>
|
|
<description>Input Ready Invert</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_RDYEN</name>
|
|
<description>Input Ready Enable</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_CLKINV</name>
|
|
<description>Invert Output Clock Enable</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_CLKGATEI</name>
|
|
<description>Clock Gated Idle</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG_CLKGATE</name>
|
|
<description>Clock Gated</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCFG</name>
|
|
<description>EPI General-Purpose Configuration</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_GPCFG_DSIZE</name>
|
|
<description>Size of Data Bus</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_GPCFG_DSIZE_4BIT</name>
|
|
<description>8 Bits Wide (EPI0S0 to EPI0S7)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_GPCFG_DSIZE_16BIT</name>
|
|
<description>16 Bits Wide (EPI0S0 to EPI0S15)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_GPCFG_DSIZE_24BIT</name>
|
|
<description>24 Bits Wide (EPI0S0 to EPI0S23)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_GPCFG_DSIZE_32BIT</name>
|
|
<description>32 Bits Wide (EPI0S0 to EPI0S31)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_GPCFG_ASIZE</name>
|
|
<description>Address Bus Size</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_GPCFG_ASIZE_NONE</name>
|
|
<description>No address</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_GPCFG_ASIZE_4BIT</name>
|
|
<description>Up to 4 bits wide</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_GPCFG_ASIZE_12BIT</name>
|
|
<description>Up to 12 bits wide. This size cannot be used with 24-bit data</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_GPCFG_ASIZE_20BIT</name>
|
|
<description>Up to 20 bits wide. This size cannot be used with data sizes other than 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_GPCFG_WR2CYC</name>
|
|
<description>2-Cycle Writes</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_GPCFG_FRMCNT</name>
|
|
<description>Frame Count</description>
|
|
<bitRange>[25:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_GPCFG_FRM50</name>
|
|
<description>50/50 Frame</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_GPCFG_CLKGATE</name>
|
|
<description>Clock Gated</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_GPCFG_CLKPIN</name>
|
|
<description>Clock Pin</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDRAMCFG</name>
|
|
<description>EPI SDRAM Configuration</description>
|
|
<alternateGroup>EPI_ALTSD</alternateGroup>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_SDRAMCFG_SIZE</name>
|
|
<description>Size of SDRAM</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_SDRAMCFG_SIZE_8MB</name>
|
|
<description>64 megabits (8MB)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_SDRAMCFG_SIZE_16MB</name>
|
|
<description>128 megabits (16MB)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_SDRAMCFG_SIZE_32MB</name>
|
|
<description>256 megabits (32MB)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_SDRAMCFG_SIZE_64MB</name>
|
|
<description>512 megabits (64MB)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_SDRAMCFG_SLEEP</name>
|
|
<description>Sleep Mode</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_SDRAMCFG_RFSH</name>
|
|
<description>Refresh Counter</description>
|
|
<bitRange>[26:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_SDRAMCFG_FREQ</name>
|
|
<description>EPI Frequency Range</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_SDRAMCFG_FREQ_NONE</name>
|
|
<description>0 - 15 MHz</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_SDRAMCFG_FREQ_15MHZ</name>
|
|
<description>15 - 30 MHz</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_SDRAMCFG_FREQ_30MHZ</name>
|
|
<description>30 - 50 MHz</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB8CFG</name>
|
|
<description>EPI Host-Bus 8 Configuration</description>
|
|
<alternateGroup>EPI_ALT8</alternateGroup>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB8CFG_MODE</name>
|
|
<description>Host Bus Sub-Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_MODE_MUX</name>
|
|
<description>ADMUX - AD[7:0]</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_MODE_NMUX</name>
|
|
<description>ADNONMUX - D[7:0]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_MODE_SRAM</name>
|
|
<description>Continuous Read - D[7:0]</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_MODE_FIFO</name>
|
|
<description>XFIFO - D[7:0]</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_RDWS</name>
|
|
<description>Read Wait States</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_RDWS_2</name>
|
|
<description>Active RDn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_RDWS_4</name>
|
|
<description>Active RDn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_RDWS_6</name>
|
|
<description>Active RDn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_RDWS_8</name>
|
|
<description>Active RDn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_WRWS</name>
|
|
<description>Write Wait States</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_WRWS_2</name>
|
|
<description>Active WRn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_WRWS_4</name>
|
|
<description>Active WRn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_WRWS_6</name>
|
|
<description>Active WRn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG_WRWS_8</name>
|
|
<description>Active WRn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_MAXWAIT</name>
|
|
<description>Maximum Wait</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_ALEHIGH</name>
|
|
<description>ALE Strobe Polarity</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_RDHIGH</name>
|
|
<description>READ Strobe Polarity</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_WRHIGH</name>
|
|
<description>WRITE Strobe Polarity</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_XFEEN</name>
|
|
<description>External FIFO EMPTY Enable</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_XFFEN</name>
|
|
<description>External FIFO FULL Enable</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_IRDYINV</name>
|
|
<description>Input Ready Invert</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_RDYEN</name>
|
|
<description>Input Ready Enable</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_CLKINV</name>
|
|
<description>Invert Output Clock Enable</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_CLKGATEI</name>
|
|
<description>Clock Gated when Idle</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG_CLKGATE</name>
|
|
<description>Clock Gated</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB8CFG2</name>
|
|
<description>EPI Host-Bus 8 Configuration 2</description>
|
|
<alternateGroup>EPI_ALT8</alternateGroup>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB8CFG2_MODE</name>
|
|
<description>CS1n Host Bus Sub-Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_MODE_ADMUX</name>
|
|
<description>ADMUX - AD[7:0]</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_MODE_AD</name>
|
|
<description>ADNONMUX - D[7:0]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG2_RDWS</name>
|
|
<description>CS1n Read Wait States</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_RDWS_2</name>
|
|
<description>Active RDn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_RDWS_4</name>
|
|
<description>Active RDn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_RDWS_6</name>
|
|
<description>Active RDn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_RDWS_8</name>
|
|
<description>Active RDn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG2_WRWS</name>
|
|
<description>CS1n Write Wait States</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_WRWS_2</name>
|
|
<description>Active WRn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_WRWS_4</name>
|
|
<description>Active WRn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_WRWS_6</name>
|
|
<description>Active WRn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_WRWS_8</name>
|
|
<description>Active WRn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG2_ALEHIGH</name>
|
|
<description>CS1n ALE Strobe Polarity</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG2_RDHIGH</name>
|
|
<description>CS1n READ Strobe Polarity</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG2_WRHIGH</name>
|
|
<description>CS1n WRITE Strobe Polarity</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG2_CSCFG</name>
|
|
<description>Chip Select Configuration</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_CSCFG_ALE</name>
|
|
<description>ALE Configuration</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_CSCFG_CS</name>
|
|
<description>CSn Configuration</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_CSCFG_DCS</name>
|
|
<description>Dual CSn Configuration</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG2_CSCFG_ADCS</name>
|
|
<description>ALE with Dual CSn Configuration</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG2_CSBAUD</name>
|
|
<description>Chip Select Baud Rate and Multiple Sub-Mode Configuration enable</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG2_CSCFGEXT</name>
|
|
<description>Chip Select Extended Configuration</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB16CFG2</name>
|
|
<description>EPI Host-Bus 16 Configuration 2</description>
|
|
<alternateGroup>EPI_ALT16</alternateGroup>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB16CFG2_MODE</name>
|
|
<description>CS1n Host Bus Sub-Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_MODE_ADMUX</name>
|
|
<description>ADMUX - AD[15:0]</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_MODE_AD</name>
|
|
<description>ADNONMUX - D[15:0]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG2_RDWS</name>
|
|
<description>CS1n Read Wait States</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_RDWS_2</name>
|
|
<description>Active RDn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_RDWS_4</name>
|
|
<description>Active RDn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_RDWS_6</name>
|
|
<description>Active RDn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_RDWS_8</name>
|
|
<description>Active RDn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG2_WRWS</name>
|
|
<description>CS1n Write Wait States</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_WRWS_2</name>
|
|
<description>Active WRn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_WRWS_4</name>
|
|
<description>Active WRn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_WRWS_6</name>
|
|
<description>Active WRn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_WRWS_8</name>
|
|
<description>Active WRn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG2_BURST</name>
|
|
<description>CS1n Burst Mode</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG2_RDCRE</name>
|
|
<description>CS1n PSRAM Configuration Register Read</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG2_WRCRE</name>
|
|
<description>CS1n PSRAM Configuration Register Write</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG2_ALEHIGH</name>
|
|
<description>CS1n ALE Strobe Polarity</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG2_RDHIGH</name>
|
|
<description>CS1n READ Strobe Polarity</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG2_WRHIGH</name>
|
|
<description>CS1n WRITE Strobe Polarity</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG2_CSCFG</name>
|
|
<description>Chip Select Configuration</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_CSCFG_ALE</name>
|
|
<description>ALE Configuration</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_CSCFG_CS</name>
|
|
<description>CSn Configuration</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_CSCFG_DCS</name>
|
|
<description>Dual CSn Configuration</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG2_CSCFG_ADCS</name>
|
|
<description>ALE with Dual CSn Configuration</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG2_CSBAUD</name>
|
|
<description>Chip Select Baud Rate and Multiple Sub-Mode Configuration enable</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG2_CSCFGEXT</name>
|
|
<description>Chip Select Extended Configuration</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDRMAP</name>
|
|
<description>EPI Address Map</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_ADDRMAP_ERADR</name>
|
|
<description>External RAM Address</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ERADR_NONE</name>
|
|
<description>Not mapped</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ERADR_6000</name>
|
|
<description>At 0x6000.0000</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ERADR_8000</name>
|
|
<description>At 0x8000.0000</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ERADR_HBQS</name>
|
|
<description>Only to be used with Host Bus quad chip select. In quad chip select mode, CS0n maps to 0x6000.0000 and CS1n maps to 0x8000.0000</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_ADDRMAP_ERSZ</name>
|
|
<description>External RAM Size</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ERSZ_256B</name>
|
|
<description>256 bytes; lower address range: 0x00 to 0xFF</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ERSZ_64KB</name>
|
|
<description>64 KB; lower address range: 0x0000 to 0xFFFF</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ERSZ_16MB</name>
|
|
<description>16 MB; lower address range: 0x00.0000 to 0xFF.FFFF</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ERSZ_256MB</name>
|
|
<description>256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_ADDRMAP_EPADR</name>
|
|
<description>External Peripheral Address</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_EPADR_NONE</name>
|
|
<description>Not mapped</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_EPADR_A000</name>
|
|
<description>At 0xA000.0000</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_EPADR_C000</name>
|
|
<description>At 0xC000.0000</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_EPADR_HBQS</name>
|
|
<description>Only to be used with Host Bus quad chip select. In quad chip select mode, CS2n maps to 0xA000.0000 and CS3n maps to 0xC000.0000</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_ADDRMAP_EPSZ</name>
|
|
<description>External Peripheral Size</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_EPSZ_256B</name>
|
|
<description>256 bytes; lower address range: 0x00 to 0xFF</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_EPSZ_64KB</name>
|
|
<description>64 KB; lower address range: 0x0000 to 0xFFFF</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_EPSZ_16MB</name>
|
|
<description>16 MB; lower address range: 0x00.0000 to 0xFF.FFFF</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_EPSZ_256MB</name>
|
|
<description>256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_ADDRMAP_ECADR</name>
|
|
<description>External Code Address</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ECADR_NONE</name>
|
|
<description>Not mapped</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ECADR_1000</name>
|
|
<description>At 0x1000.0000</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_ADDRMAP_ECSZ</name>
|
|
<description>External Code Size</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ECSZ_256B</name>
|
|
<description>256 bytes; lower address range: 0x00 to 0xFF</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ECSZ_64KB</name>
|
|
<description>64 KB; lower address range: 0x0000 to 0xFFFF</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ECSZ_16MB</name>
|
|
<description>16 MB; lower address range: 0x00.0000 to 0xFF.FFFF</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_ADDRMAP_ECSZ_256MB</name>
|
|
<description>256MB; lower address range: 0x000.0000 to 0x0FFF.FFFF</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSIZE0</name>
|
|
<description>EPI Read Size 0</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_RSIZE0_SIZE</name>
|
|
<description>Current Size</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_RSIZE0_SIZE_8BIT</name>
|
|
<description>Byte (8 bits)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_RSIZE0_SIZE_16BIT</name>
|
|
<description>Half-word (16 bits)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_RSIZE0_SIZE_32BIT</name>
|
|
<description>Word (32 bits)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RADDR0</name>
|
|
<description>EPI Read Address 0</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_RADDR0_ADDR</name>
|
|
<description>Current Address</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPSTD0</name>
|
|
<description>EPI Non-Blocking Read Data 0</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_RPSTD0_POSTCNT</name>
|
|
<description>Post Count</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSIZE1</name>
|
|
<description>EPI Read Size 1</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_RSIZE1_SIZE</name>
|
|
<description>Current Size</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_RSIZE1_SIZE_8BIT</name>
|
|
<description>Byte (8 bits)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_RSIZE1_SIZE_16BIT</name>
|
|
<description>Half-word (16 bits)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_RSIZE1_SIZE_32BIT</name>
|
|
<description>Word (32 bits)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RADDR1</name>
|
|
<description>EPI Read Address 1</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_RADDR1_ADDR</name>
|
|
<description>Current Address</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPSTD1</name>
|
|
<description>EPI Non-Blocking Read Data 1</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_RPSTD1_POSTCNT</name>
|
|
<description>Post Count</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>EPI Status</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_STAT_ACTIVE</name>
|
|
<description>Register Active</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_STAT_NBRBUSY</name>
|
|
<description>Non-Blocking Read Busy</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_STAT_WBUSY</name>
|
|
<description>Write Busy</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_STAT_INITSEQ</name>
|
|
<description>Initialization Sequence</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_STAT_XFEMPTY</name>
|
|
<description>External FIFO Empty</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_STAT_XFFULL</name>
|
|
<description>External FIFO Full</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFIFOCNT</name>
|
|
<description>EPI Read FIFO Count</description>
|
|
<addressOffset>0x0000006C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_RFIFOCNT_COUNT</name>
|
|
<description>FIFO Count</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>READFIFO0</name>
|
|
<description>EPI Read FIFO</description>
|
|
<addressOffset>0x00000070</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_READFIFO0_DATA</name>
|
|
<description>Reads Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>READFIFO1</name>
|
|
<description>EPI Read FIFO Alias 1</description>
|
|
<addressOffset>0x00000074</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_READFIFO1_DATA</name>
|
|
<description>Reads Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>READFIFO2</name>
|
|
<description>EPI Read FIFO Alias 2</description>
|
|
<addressOffset>0x00000078</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_READFIFO2_DATA</name>
|
|
<description>Reads Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>READFIFO3</name>
|
|
<description>EPI Read FIFO Alias 3</description>
|
|
<addressOffset>0x0000007C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_READFIFO3_DATA</name>
|
|
<description>Reads Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>READFIFO4</name>
|
|
<description>EPI Read FIFO Alias 4</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_READFIFO4_DATA</name>
|
|
<description>Reads Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>READFIFO5</name>
|
|
<description>EPI Read FIFO Alias 5</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_READFIFO5_DATA</name>
|
|
<description>Reads Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>READFIFO6</name>
|
|
<description>EPI Read FIFO Alias 6</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_READFIFO6_DATA</name>
|
|
<description>Reads Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>READFIFO7</name>
|
|
<description>EPI Read FIFO Alias 7</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_READFIFO7_DATA</name>
|
|
<description>Reads Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOLVL</name>
|
|
<description>EPI FIFO Level Selects</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_FIFOLVL_RDFIFO</name>
|
|
<description>Read FIFO</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_FIFOLVL_RDFIFO_1</name>
|
|
<description>Trigger when there are 1 or more entries in the NBRFIFO</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_FIFOLVL_RDFIFO_2</name>
|
|
<description>Trigger when there are 2 or more entries in the NBRFIFO</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_FIFOLVL_RDFIFO_4</name>
|
|
<description>Trigger when there are 4 or more entries in the NBRFIFO</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_FIFOLVL_RDFIFO_6</name>
|
|
<description>Trigger when there are 6 or more entries in the NBRFIFO</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_FIFOLVL_RDFIFO_7</name>
|
|
<description>Trigger when there are 7 or more entries in the NBRFIFO</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_FIFOLVL_RDFIFO_8</name>
|
|
<description>Trigger when there are 8 entries in the NBRFIFO</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_FIFOLVL_WRFIFO</name>
|
|
<description>Write FIFO</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_FIFOLVL_WRFIFO_EMPT</name>
|
|
<description>Interrupt is triggered while WRFIFO is empty.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_FIFOLVL_WRFIFO_2</name>
|
|
<description>Interrupt is triggered until there are only two slots available. Thus, trigger is deasserted when there are two WRFIFO entries present. This configuration is optimized for bursts of 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_FIFOLVL_WRFIFO_1</name>
|
|
<description>Interrupt is triggered until there is one WRFIFO entry available. This configuration expects only single writes</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_FIFOLVL_WRFIFO_NFULL</name>
|
|
<description>Trigger interrupt when WRFIFO is not full, meaning trigger will continue to assert until there are four entries in the WRFIFO</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_FIFOLVL_RSERR</name>
|
|
<description>Read Stall Error</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_FIFOLVL_WFERR</name>
|
|
<description>Write Full Error</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WFIFOCNT</name>
|
|
<description>EPI Write FIFO Count</description>
|
|
<addressOffset>0x00000204</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_WFIFOCNT_WTAV</name>
|
|
<description>Available Write Transactions</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMATXCNT</name>
|
|
<description>EPI DMA Transmit Count</description>
|
|
<addressOffset>0x00000208</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_DMATXCNT_TXCNT</name>
|
|
<description>DMA Count</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IM</name>
|
|
<description>EPI Interrupt Mask</description>
|
|
<addressOffset>0x00000210</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_IM_ERRIM</name>
|
|
<description>Error Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_IM_RDIM</name>
|
|
<description>Read FIFO Full Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_IM_WRIM</name>
|
|
<description>Write FIFO Empty Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_IM_DMARDIM</name>
|
|
<description>Read uDMA Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_IM_DMAWRIM</name>
|
|
<description>Write uDMA Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>EPI Raw Interrupt Status</description>
|
|
<addressOffset>0x00000214</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_RIS_ERRRIS</name>
|
|
<description>Error Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_RIS_RDRIS</name>
|
|
<description>Read Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_RIS_WRRIS</name>
|
|
<description>Write Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_RIS_DMARDRIS</name>
|
|
<description>Read uDMA Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_RIS_DMAWRRIS</name>
|
|
<description>Write uDMA Raw Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>EPI Masked Interrupt Status</description>
|
|
<addressOffset>0x00000218</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_MIS_ERRMIS</name>
|
|
<description>Error Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_MIS_RDMIS</name>
|
|
<description>Read Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_MIS_WRMIS</name>
|
|
<description>Write Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_MIS_DMARDMIS</name>
|
|
<description>Read uDMA Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_MIS_DMAWRMIS</name>
|
|
<description>Write uDMA Masked Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EISC</name>
|
|
<description>EPI Error and Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000021C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_EISC_TOUT</name>
|
|
<description>Timeout Error</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_EISC_RSTALL</name>
|
|
<description>Read Stalled Error</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_EISC_WTFULL</name>
|
|
<description>Write FIFO Full Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_EISC_DMARDIC</name>
|
|
<description>Read uDMA Interrupt Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_EISC_DMAWRIC</name>
|
|
<description>Write uDMA Interrupt Clear</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB8CFG3</name>
|
|
<description>EPI Host-Bus 8 Configuration 3</description>
|
|
<addressOffset>0x00000308</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB8CFG3_MODE</name>
|
|
<description>CS2n Host Bus Sub-Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG3_MODE_ADMUX</name>
|
|
<description>ADMUX - AD[7:0]</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG3_MODE_AD</name>
|
|
<description>ADNONMUX - D[7:0]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG3_RDWS</name>
|
|
<description>CS2n Read Wait States</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG3_RDWS_2</name>
|
|
<description>Active RDn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG3_RDWS_4</name>
|
|
<description>Active RDn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG3_RDWS_6</name>
|
|
<description>Active RDn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG3_RDWS_8</name>
|
|
<description>Active RDn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG3_WRWS</name>
|
|
<description>CS2n Write Wait States</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG3_WRWS_2</name>
|
|
<description>Active WRn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG3_WRWS_4</name>
|
|
<description>Active WRn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG3_WRWS_6</name>
|
|
<description>Active WRn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG3_WRWS_8</name>
|
|
<description>Active WRn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG3_ALEHIGH</name>
|
|
<description>CS2n ALE Strobe Polarity</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG3_RDHIGH</name>
|
|
<description>CS2n READ Strobe Polarity</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG3_WRHIGH</name>
|
|
<description>CS2n WRITE Strobe Polarity</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB16CFG3</name>
|
|
<description>EPI Host-Bus 16 Configuration 3</description>
|
|
<alternateGroup>EPI_ALT16</alternateGroup>
|
|
<addressOffset>0x00000308</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB16CFG3_MODE</name>
|
|
<description>CS2n Host Bus Sub-Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG3_MODE_ADMUX</name>
|
|
<description>ADMUX - AD[15:0]</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG3_MODE_AD</name>
|
|
<description>ADNONMUX - D[15:0]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG3_RDWS</name>
|
|
<description>CS2n Read Wait States</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG3_RDWS_2</name>
|
|
<description>Active RDn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG3_RDWS_4</name>
|
|
<description>Active RDn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG3_RDWS_6</name>
|
|
<description>Active RDn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG3_RDWS_8</name>
|
|
<description>Active RDn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG3_WRWS</name>
|
|
<description>CS2n Write Wait States</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG3_WRWS_2</name>
|
|
<description>Active WRn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG3_WRWS_4</name>
|
|
<description>Active WRn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG3_WRWS_6</name>
|
|
<description>Active WRn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG3_WRWS_8</name>
|
|
<description>Active WRn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG3_BURST</name>
|
|
<description>CS2n Burst Mode</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG3_RDCRE</name>
|
|
<description>CS2n PSRAM Configuration Register Read</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG3_WRCRE</name>
|
|
<description>CS2n PSRAM Configuration Register Write</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG3_ALEHIGH</name>
|
|
<description>CS2n ALE Strobe Polarity</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG3_RDHIGH</name>
|
|
<description>CS2n READ Strobe Polarity</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG3_WRHIGH</name>
|
|
<description>CS2n WRITE Strobe Polarity</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB16CFG4</name>
|
|
<description>EPI Host-Bus 16 Configuration 4</description>
|
|
<addressOffset>0x0000030C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB16CFG4_MODE</name>
|
|
<description>CS3n Host Bus Sub-Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG4_MODE_ADMUX</name>
|
|
<description>ADMUX - AD[15:0]</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG4_MODE_AD</name>
|
|
<description>ADNONMUX - D[15:0]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG4_RDWS</name>
|
|
<description>CS3n Read Wait States</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG4_RDWS_2</name>
|
|
<description>Active RDn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG4_RDWS_4</name>
|
|
<description>Active RDn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG4_RDWS_6</name>
|
|
<description>Active RDn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG4_RDWS_8</name>
|
|
<description>Active RDn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG4_WRWS</name>
|
|
<description>CS3n Write Wait States</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG4_WRWS_2</name>
|
|
<description>Active WRn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG4_WRWS_4</name>
|
|
<description>Active WRn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG4_WRWS_6</name>
|
|
<description>Active WRn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16CFG4_WRWS_8</name>
|
|
<description>Active WRn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG4_BURST</name>
|
|
<description>CS3n Burst Mode</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG4_RDCRE</name>
|
|
<description>CS3n PSRAM Configuration Register Read</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG4_WRCRE</name>
|
|
<description>CS3n PSRAM Configuration Register Write</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG4_ALEHIGH</name>
|
|
<description>CS3n ALE Strobe Polarity</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG4_RDHIGH</name>
|
|
<description>CS3n READ Strobe Polarity</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16CFG4_WRHIGH</name>
|
|
<description>CS3n WRITE Strobe Polarity</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB8CFG4</name>
|
|
<description>EPI Host-Bus 8 Configuration 4</description>
|
|
<alternateGroup>EPI_ALT8</alternateGroup>
|
|
<addressOffset>0x0000030C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB8CFG4_MODE</name>
|
|
<description>CS3n Host Bus Sub-Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG4_MODE_ADMUX</name>
|
|
<description>ADMUX - AD[7:0]</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG4_MODE_AD</name>
|
|
<description>ADNONMUX - D[7:0]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG4_RDWS</name>
|
|
<description>CS3n Read Wait States</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG4_RDWS_2</name>
|
|
<description>Active RDn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG4_RDWS_4</name>
|
|
<description>Active RDn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG4_RDWS_6</name>
|
|
<description>Active RDn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG4_RDWS_8</name>
|
|
<description>Active RDn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG4_WRWS</name>
|
|
<description>CS3n Write Wait States</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG4_WRWS_2</name>
|
|
<description>Active WRn is 2 EPI clocks</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG4_WRWS_4</name>
|
|
<description>Active WRn is 4 EPI clocks</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG4_WRWS_6</name>
|
|
<description>Active WRn is 6 EPI clocks</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB8CFG4_WRWS_8</name>
|
|
<description>Active WRn is 8 EPI clocks</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG4_ALEHIGH</name>
|
|
<description>CS3n ALE Strobe Polarity</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG4_RDHIGH</name>
|
|
<description>CS2n READ Strobe Polarity</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8CFG4_WRHIGH</name>
|
|
<description>CS3n WRITE Strobe Polarity</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB8TIME</name>
|
|
<description>EPI Host-Bus 8 Timing Extension</description>
|
|
<addressOffset>0x00000310</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB8TIME_RDWSM</name>
|
|
<description>Read Wait State Minus One</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME_WRWSM</name>
|
|
<description>Write Wait State Minus One</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME_CAPWIDTH</name>
|
|
<description>CS0n Inter-transfer Capture Width</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME_IRDYDLY</name>
|
|
<description>CS0n Input Ready Delay</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB16TIME</name>
|
|
<description>EPI Host-Bus 16 Timing Extension</description>
|
|
<alternateGroup>EPI_ALT16</alternateGroup>
|
|
<addressOffset>0x00000310</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB16TIME_RDWSM</name>
|
|
<description>Read Wait State Minus One</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME_WRWSM</name>
|
|
<description>Write Wait State Minus One</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME_CAPWIDTH</name>
|
|
<description>CS0n Inter-transfer Capture Width</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME_PSRAMSZ</name>
|
|
<description>PSRAM Row Size</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME_PSRAMSZ_0</name>
|
|
<description>No row size limitation</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME_PSRAMSZ_128B</name>
|
|
<description>128 B</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME_PSRAMSZ_256B</name>
|
|
<description>256 B</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME_PSRAMSZ_512B</name>
|
|
<description>512 B</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME_PSRAMSZ_1KB</name>
|
|
<description>1024 B</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME_PSRAMSZ_2KB</name>
|
|
<description>2048 B</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME_PSRAMSZ_4KB</name>
|
|
<description>4096 B</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME_PSRAMSZ_8KB</name>
|
|
<description>8192 B</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME_IRDYDLY</name>
|
|
<description>CS0n Input Ready Delay</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB8TIME2</name>
|
|
<description>EPI Host-Bus 8 Timing Extension</description>
|
|
<addressOffset>0x00000314</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB8TIME2_RDWSM</name>
|
|
<description>CS1n Read Wait State Minus One</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME2_WRWSM</name>
|
|
<description>CS1n Write Wait State Minus One</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME2_CAPWIDTH</name>
|
|
<description>CS1n Inter-transfer Capture Width</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME2_IRDYDLY</name>
|
|
<description>CS1n Input Ready Delay</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB16TIME2</name>
|
|
<description>EPI Host-Bus 16 Timing Extension</description>
|
|
<alternateGroup>EPI_ALT16</alternateGroup>
|
|
<addressOffset>0x00000314</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB16TIME2_RDWSM</name>
|
|
<description>CS1n Read Wait State Minus One</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME2_WRWSM</name>
|
|
<description>CS1n Write Wait State Minus One</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME2_CAPWIDTH</name>
|
|
<description>CS1n Inter-transfer Capture Width</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME2_PSRAMSZ</name>
|
|
<description>PSRAM Row Size</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME2_PSRAMSZ_0</name>
|
|
<description>No row size limitation</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME2_PSRAMSZ_128B</name>
|
|
<description>128 B</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME2_PSRAMSZ_256B</name>
|
|
<description>256 B</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME2_PSRAMSZ_512B</name>
|
|
<description>512 B</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME2_PSRAMSZ_1KB</name>
|
|
<description>1024 B</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME2_PSRAMSZ_2KB</name>
|
|
<description>2048 B</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME2_PSRAMSZ_4KB</name>
|
|
<description>4096 B</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME2_PSRAMSZ_8KB</name>
|
|
<description>8192 B</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME2_IRDYDLY</name>
|
|
<description>CS1n Input Ready Delay</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB16TIME3</name>
|
|
<description>EPI Host-Bus 16 Timing Extension</description>
|
|
<addressOffset>0x00000318</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB16TIME3_RDWSM</name>
|
|
<description>CS2n Read Wait State Minus One</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME3_WRWSM</name>
|
|
<description>CS2n Write Wait State Minus One</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME3_CAPWIDTH</name>
|
|
<description>CS2n Inter-transfer Capture Width</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME3_PSRAMSZ</name>
|
|
<description>PSRAM Row Size</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME3_PSRAMSZ_0</name>
|
|
<description>No row size limitation</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME3_PSRAMSZ_128B</name>
|
|
<description>128 B</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME3_PSRAMSZ_256B</name>
|
|
<description>256 B</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME3_PSRAMSZ_512B</name>
|
|
<description>512 B</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME3_PSRAMSZ_1KB</name>
|
|
<description>1024 B</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME3_PSRAMSZ_2KB</name>
|
|
<description>2048 B</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME3_PSRAMSZ_4KB</name>
|
|
<description>4096 B</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME3_PSRAMSZ_8KB</name>
|
|
<description>8192 B</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME3_IRDYDLY</name>
|
|
<description>CS2n Input Ready Delay</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB8TIME3</name>
|
|
<description>EPI Host-Bus 8 Timing Extension</description>
|
|
<alternateGroup>EPI_ALT8</alternateGroup>
|
|
<addressOffset>0x00000318</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB8TIME3_RDWSM</name>
|
|
<description>CS2n Read Wait State Minus One</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME3_WRWSM</name>
|
|
<description>CS2n Write Wait State Minus One</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME3_CAPWIDTH</name>
|
|
<description>CS2n Inter-transfer Capture Width</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME3_IRDYDLY</name>
|
|
<description>CS2n Input Ready Delay</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB8TIME4</name>
|
|
<description>EPI Host-Bus 8 Timing Extension</description>
|
|
<alternateGroup>EPI_ALT8</alternateGroup>
|
|
<addressOffset>0x0000031C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB8TIME4_RDWSM</name>
|
|
<description>CS3n Read Wait State Minus One</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME4_WRWSM</name>
|
|
<description>CS3n Write Wait State Minus One</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME4_CAPWIDTH</name>
|
|
<description>CS3n Inter-transfer Capture Width</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB8TIME4_IRDYDLY</name>
|
|
<description>CS3n Input Ready Delay</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HB16TIME4</name>
|
|
<description>EPI Host-Bus 16 Timing Extension</description>
|
|
<addressOffset>0x0000031C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HB16TIME4_RDWSM</name>
|
|
<description>CS3n Read Wait State Minus One</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME4_WRWSM</name>
|
|
<description>CS3n Write Wait State Minus One</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME4_CAPWIDTH</name>
|
|
<description>CS3n Inter-transfer Capture Width</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME4_PSRAMSZ</name>
|
|
<description>PSRAM Row Size</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME4_PSRAMSZ_0</name>
|
|
<description>No row size limitation</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME4_PSRAMSZ_128B</name>
|
|
<description>128 B</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME4_PSRAMSZ_256B</name>
|
|
<description>256 B</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME4_PSRAMSZ_512B</name>
|
|
<description>512 B</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME4_PSRAMSZ_1KB</name>
|
|
<description>1024 B</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME4_PSRAMSZ_2KB</name>
|
|
<description>2048 B</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME4_PSRAMSZ_4KB</name>
|
|
<description>4096 B</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPI_HB16TIME4_PSRAMSZ_8KB</name>
|
|
<description>8192 B</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPI_HB16TIME4_IRDYDLY</name>
|
|
<description>CS3n Input Ready Delay</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HBPSRAM</name>
|
|
<description>EPI Host-Bus PSRAM</description>
|
|
<addressOffset>0x00000360</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EPI_HBPSRAM_CR</name>
|
|
<description>PSRAM Config Register</description>
|
|
<bitRange>[20:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER6</name>
|
|
<prependToName>TIMER6</prependToName>
|
|
<baseAddress>0x400E0000</baseAddress>
|
|
<interrupt><name>TIMER6A</name><value>98</value></interrupt>
|
|
<interrupt><name>TIMER6B</name><value>99</value></interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER7</name>
|
|
<prependToName>TIMER7</prependToName>
|
|
<baseAddress>0x400E1000</baseAddress>
|
|
<interrupt><name>TIMER7A</name><value>100</value></interrupt>
|
|
<interrupt><name>TIMER7B</name><value>101</value></interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EMAC0</name>
|
|
<description>Register map for EMAC0 peripheral</description>
|
|
<groupName>MAC</groupName>
|
|
<prependToName>EMAC0</prependToName>
|
|
<baseAddress>0x400EC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>EMAC0</name><value>40</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>Ethernet MAC Configuration</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_CFG_PRELEN</name>
|
|
<description>Preamble Length for Transmit Frames</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_PRELEN_7</name>
|
|
<description>7 bytes of preamble</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_PRELEN_5</name>
|
|
<description>5 bytes of preamble</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_PRELEN_3</name>
|
|
<description>3 bytes of preamble</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_DC</name>
|
|
<description>Deferral Check</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_BL</name>
|
|
<description>Back-Off Limit</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_BL_1024</name>
|
|
<description>k = min (n,10)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_BL_256</name>
|
|
<description>k = min (n,8)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_BL_8</name>
|
|
<description>k = min (n,4)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_BL_2</name>
|
|
<description>k = min (n,1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_ACS</name>
|
|
<description>Automatic Pad or CRC Stripping</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_DR</name>
|
|
<description>Disable Retry</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_IPC</name>
|
|
<description>Checksum Offload</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_DUPM</name>
|
|
<description>Duplex Mode</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_LOOPBM</name>
|
|
<description>Loopback Mode</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_DRO</name>
|
|
<description>Disable Receive Own</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_FES</name>
|
|
<description>Speed</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_PS</name>
|
|
<description>Port Select</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_DISCRS</name>
|
|
<description>Disable Carrier Sense During Transmission</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_IFG</name>
|
|
<description>Inter-Frame Gap (IFG)</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_IFG_96</name>
|
|
<description>96 bit times</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_IFG_88</name>
|
|
<description>88 bit times</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_IFG_80</name>
|
|
<description>80 bit times</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_IFG_72</name>
|
|
<description>72 bit times</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_IFG_64</name>
|
|
<description>64 bit times</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_IFG_56</name>
|
|
<description>56 bit times</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_IFG_48</name>
|
|
<description>48 bit times</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_CFG_IFG_40</name>
|
|
<description>40 bit times</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_JFEN</name>
|
|
<description>Jumbo Frame Enable</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_JD</name>
|
|
<description>Jabber Disable</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_WDDIS</name>
|
|
<description>Watchdog Disable</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_CST</name>
|
|
<description>CRC Stripping for Type Frames</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CFG_TWOKPEN</name>
|
|
<description>IEEE 802</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRAMEFLTR</name>
|
|
<description>Ethernet MAC Frame Filter</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_PR</name>
|
|
<description>Promiscuous Mode</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_HUC</name>
|
|
<description>Hash Unicast</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_HMC</name>
|
|
<description>Hash Multicast</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_DAIF</name>
|
|
<description>Destination Address (DA) Inverse Filtering</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_PM</name>
|
|
<description>Pass All Multicast</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_DBF</name>
|
|
<description>Disable Broadcast Frames</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_PCF</name>
|
|
<description>Pass Control Frames</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_FRAMEFLTR_PCF_ALL</name>
|
|
<description>The MAC filters all control frames from reaching application</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_FRAMEFLTR_PCF_PAUSE</name>
|
|
<description>MAC forwards all control frames except PAUSE control frames to application even if they fail the address filter</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_FRAMEFLTR_PCF_NONE</name>
|
|
<description>MAC forwards all control frames to application even if they fail the address Filter</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_FRAMEFLTR_PCF_ADDR</name>
|
|
<description>MAC forwards control frames that pass the address Filter</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_SAIF</name>
|
|
<description>Source Address (SA) Inverse Filtering</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_SAF</name>
|
|
<description>Source Address Filter Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_HPF</name>
|
|
<description>Hash or Perfect Filter</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_VTFE</name>
|
|
<description>VLAN Tag Filter Enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FRAMEFLTR_RA</name>
|
|
<description>Receive All</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HASHTBLH</name>
|
|
<description>Ethernet MAC Hash Table High</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_HASHTBLH_HTH</name>
|
|
<description>Hash Table High</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HASHTBLL</name>
|
|
<description>Ethernet MAC Hash Table Low</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_HASHTBLL_HTL</name>
|
|
<description>Hash Table Low</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIIADDR</name>
|
|
<description>Ethernet MAC MII Address</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_MIIADDR_MIIB</name>
|
|
<description>MII Busy</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MIIADDR_MIIW</name>
|
|
<description>MII Write</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MIIADDR_CR</name>
|
|
<description>Clock Reference Frequency Selection</description>
|
|
<bitRange>[5:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_MIIADDR_CR_60_100</name>
|
|
<description>The frequency of the System Clock is 60 to 100 MHz providing a MDIO clock of SYSCLK/42</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_MIIADDR_CR_100_150</name>
|
|
<description>The frequency of the System Clock is 100 to 150 MHz providing a MDIO clock of SYSCLK/62</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_MIIADDR_CR_20_35</name>
|
|
<description>The frequency of the System Clock is 20-35 MHz providing a MDIO clock of System Clock/16</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_MIIADDR_CR_35_60</name>
|
|
<description>The frequency of the System Clock is 35 to 60 MHz providing a MDIO clock of System Clock/26</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MIIADDR_MII</name>
|
|
<description>MII Register</description>
|
|
<bitRange>[10:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MIIADDR_PLA</name>
|
|
<description>Physical Layer Address</description>
|
|
<bitRange>[15:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIIDATA</name>
|
|
<description>Ethernet MAC MII Data Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_MIIDATA_DATA</name>
|
|
<description>MII Data</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLOWCTL</name>
|
|
<description>Ethernet MAC Flow Control</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_FLOWCTL_FCBBPA</name>
|
|
<description>Flow Control Busy or Back-pressure Activate</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FLOWCTL_TFE</name>
|
|
<description>Transmit Flow Control Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FLOWCTL_RFE</name>
|
|
<description>Receive Flow Control Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FLOWCTL_UP</name>
|
|
<description>Unicast Pause Frame Detect</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FLOWCTL_PLT</name>
|
|
<description>Pause Low Threshold</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_FLOWCTL_PLT_4</name>
|
|
<description>The threshold is Pause time minus 4 slot times (PT - 4 slot times)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_FLOWCTL_PLT_28</name>
|
|
<description>The threshold is Pause time minus 28 slot times (PT - 28 slot times)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_FLOWCTL_PLT_144</name>
|
|
<description>The threshold is Pause time minus 144 slot times (PT - 144 slot times)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_FLOWCTL_PLT_156</name>
|
|
<description>The threshold is Pause time minus 256 slot times (PT - 256 slot times)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FLOWCTL_DZQP</name>
|
|
<description>Disable Zero-Quanta Pause</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_FLOWCTL_PT</name>
|
|
<description>Pause Time</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VLANTG</name>
|
|
<description>Ethernet MAC VLAN Tag</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_VLANTG_VL</name>
|
|
<description>VLAN Tag Identifier for Receive Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_VLANTG_ETV</name>
|
|
<description>Enable 12-Bit VLAN Tag Comparison</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_VLANTG_VTIM</name>
|
|
<description>VLAN Tag Inverse Match Enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_VLANTG_ESVL</name>
|
|
<description>Enable S-VLAN</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_VLANTG_VTHM</name>
|
|
<description>VLAN Tag Hash Table Match Enable</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Ethernet MAC Status</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_STATUS_RPE</name>
|
|
<description>MAC MII Receive Protocol Engine Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_STATUS_RFCFC</name>
|
|
<description>MAC Receive Frame Controller FIFO Status</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_STATUS_RWC</name>
|
|
<description>TX/RX Controller RX FIFO Write Controller Active Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_STATUS_RRC</name>
|
|
<description>TX/RX Controller Read Controller State</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_RRC_IDLE</name>
|
|
<description>IDLE state</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_RRC_STATUS</name>
|
|
<description>Reading frame data</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_RRC_DATA</name>
|
|
<description>Reading frame status (or timestamp)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_RRC_FLUSH</name>
|
|
<description>Flushing the frame data and status</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_STATUS_RXF</name>
|
|
<description>TX/RX Controller RX FIFO Fill-level Status</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_RXF_EMPTY</name>
|
|
<description>RX FIFO Empty</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_RXF_BELOW</name>
|
|
<description>RX FIFO fill level is below the flow-control deactivate threshold</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_RXF_ABOVE</name>
|
|
<description>RX FIFO fill level is above the flow-control activate threshold</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_RXF_FULL</name>
|
|
<description>RX FIFO Full</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_STATUS_TPE</name>
|
|
<description>MAC MII Transmit Protocol Engine Status</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_STATUS_TFC</name>
|
|
<description>MAC Transmit Frame Controller Status</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_TFC_IDLE</name>
|
|
<description>IDLE state</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_TFC_STATUS</name>
|
|
<description>Waiting for status of previous frame or IFG or backoff period to be over</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_TFC_PAUSE</name>
|
|
<description>Generating and transmitting a PAUSE control frame (in the full-duplex mode)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_TFC_INPUT</name>
|
|
<description>Transferring input frame for transmission</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_STATUS_TXPAUSED</name>
|
|
<description>MAC Transmitter PAUSE</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_STATUS_TRC</name>
|
|
<description>TX/RX Controller's TX FIFO Read Controller Status</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_TRC_IDLE</name>
|
|
<description>IDLE state</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_TRC_READ</name>
|
|
<description>READ state (transferring data to MAC transmitter)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_TRC_WAIT</name>
|
|
<description>Waiting for TX Status from MAC transmitter</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_STATUS_TRC_WRFLUSH</name>
|
|
<description>Writing the received TX Status or flushing the TX FIFO</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_STATUS_TWC</name>
|
|
<description>TX/RX Controller TX FIFO Write Controller Active Status</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_STATUS_TXFE</name>
|
|
<description>TX/RX Controller TX FIFO Not Empty Status</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_STATUS_TXFF</name>
|
|
<description>TX/RX Controller TX FIFO Full Status</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RWUFF</name>
|
|
<description>Ethernet MAC Remote Wake-Up Frame Filter</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_RWUFF_WAKEUPFIL</name>
|
|
<description>Remote Wake-Up Frame Filter</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMTCTLSTAT</name>
|
|
<description>Ethernet MAC PMT Control and Status Register</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_PMTCTLSTAT_PWRDWN</name>
|
|
<description>Power Down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PMTCTLSTAT_MGKPKTEN</name>
|
|
<description>Magic Packet Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PMTCTLSTAT_WUPFREN</name>
|
|
<description>Wake-Up Frame Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PMTCTLSTAT_MGKPRX</name>
|
|
<description>Magic Packet Received</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PMTCTLSTAT_WUPRX</name>
|
|
<description>Wake-Up Frame Received</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PMTCTLSTAT_GLBLUCAST</name>
|
|
<description>Global Unicast</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PMTCTLSTAT_RWKPTR</name>
|
|
<description>Remote Wake-Up FIFO Pointer</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PMTCTLSTAT_WUPFRRST</name>
|
|
<description>Wake-Up Frame Filter Register Pointer Reset</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPICTLSTAT</name>
|
|
<description>Ethernet MAC Low Power Idle Control and Status Register</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_LPICTLSTAT_TLPIEN</name>
|
|
<description>Transmit LPI Entry</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_LPICTLSTAT_TLPIEX</name>
|
|
<description>Transmit LPI Exit</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_LPICTLSTAT_RLPIEN</name>
|
|
<description>Receive LPI Entry</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_LPICTLSTAT_RLPIEX</name>
|
|
<description>Receive LPI Exit</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_LPICTLSTAT_TLPIST</name>
|
|
<description>Transmit LPI State</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_LPICTLSTAT_RLPIST</name>
|
|
<description>Receive LPI State</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_LPICTLSTAT_LPIEN</name>
|
|
<description>LPI Enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_LPICTLSTAT_PLS</name>
|
|
<description>PHY Link Status</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_LPICTLSTAT_PLSEN</name>
|
|
<description>PHY Link Status Enable</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_LPICTLSTAT_LPITXA</name>
|
|
<description>LPI TX Automate</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPITIMERCTL</name>
|
|
<description>Ethernet MAC Low Power Idle Timer Control Register</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_LPITIMERCTL_TWT</name>
|
|
<description>LPI TW Timer</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_LPITIMERCTL_LST</name>
|
|
<description>LPI LS Timer</description>
|
|
<bitRange>[25:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>Ethernet MAC Raw Interrupt Status</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_RIS_PMT</name>
|
|
<description>PMT Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_RIS_MMC</name>
|
|
<description>MMC Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_RIS_MMCRX</name>
|
|
<description>MMC Receive Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_RIS_MMCTX</name>
|
|
<description>MMC Transmit Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_RIS_TS</name>
|
|
<description>Timestamp Interrupt Status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_RIS_LPI</name>
|
|
<description>LPI Interrupt Status</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IM</name>
|
|
<description>Ethernet MAC Interrupt Mask</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_IM_PMT</name>
|
|
<description>PMT Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_IM_TSI</name>
|
|
<description>Timestamp Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_IM_LPII</name>
|
|
<description>LPI Interrupt Mask</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR0H</name>
|
|
<description>Ethernet MAC Address 0 High</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_ADDR0H_ADDRHI</name>
|
|
<description>MAC Address0 [47:32]</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_ADDR0H_AE</name>
|
|
<description>Address Enable</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR0L</name>
|
|
<description>Ethernet MAC Address 0 Low Register</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_ADDR0L_ADDRLO</name>
|
|
<description>MAC Address0 [31:0]</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR1H</name>
|
|
<description>Ethernet MAC Address 1 High</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_ADDR1H_ADDRHI</name>
|
|
<description>MAC Address1 [47:32]</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_ADDR1H_MBC</name>
|
|
<description>Mask Byte Control</description>
|
|
<bitRange>[29:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_ADDR1H_SA</name>
|
|
<description>Source Address</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_ADDR1H_AE</name>
|
|
<description>Address Enable</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR1L</name>
|
|
<description>Ethernet MAC Address 1 Low</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_ADDR1L_ADDRLO</name>
|
|
<description>MAC Address1 [31:0]</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR2H</name>
|
|
<description>Ethernet MAC Address 2 High</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_ADDR2H_ADDRHI</name>
|
|
<description>MAC Address2 [47:32]</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_ADDR2H_MBC</name>
|
|
<description>Mask Byte Control</description>
|
|
<bitRange>[29:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_ADDR2H_SA</name>
|
|
<description>Source Address</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_ADDR2H_AE</name>
|
|
<description>Address Enable</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR2L</name>
|
|
<description>Ethernet MAC Address 2 Low</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_ADDR2L_ADDRLO</name>
|
|
<description>MAC Address2 [31:0]</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR3H</name>
|
|
<description>Ethernet MAC Address 3 High</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_ADDR3H_ADDRHI</name>
|
|
<description>MAC Address3 [47:32]</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_ADDR3H_MBC</name>
|
|
<description>Mask Byte Control</description>
|
|
<bitRange>[29:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_ADDR3H_SA</name>
|
|
<description>Source Address</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_ADDR3H_AE</name>
|
|
<description>Address Enable</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR3L</name>
|
|
<description>Ethernet MAC Address 3 Low</description>
|
|
<addressOffset>0x0000005C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_ADDR3L_ADDRLO</name>
|
|
<description>MAC Address3 [31:0]</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDOGTO</name>
|
|
<description>Ethernet MAC Watchdog Timeout</description>
|
|
<addressOffset>0x000000DC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_WDOGTO_WTO</name>
|
|
<description>Watchdog Timeout</description>
|
|
<bitRange>[13:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_WDOGTO_PWE</name>
|
|
<description>Programmable Watchdog Enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMCCTRL</name>
|
|
<description>Ethernet MAC MMC Control</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_MMCCTRL_CNTRST</name>
|
|
<description>Counters Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCCTRL_CNTSTPRO</name>
|
|
<description>Counters Stop Rollover</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCCTRL_RSTONRD</name>
|
|
<description>Reset on Read</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCCTRL_CNTFREEZ</name>
|
|
<description>MMC Counter Freeze</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCCTRL_CNTPRST</name>
|
|
<description>Counters Preset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCCTRL_CNTPRSTLVL</name>
|
|
<description>Full/Half Preset Level Value</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCCTRL_UCDBC</name>
|
|
<description>Update MMC Counters for Dropped Broadcast Frames</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMCRXRIS</name>
|
|
<description>Ethernet MAC MMC Receive Raw Interrupt Status</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_MMCRXRIS_GBF</name>
|
|
<description>MMC Receive Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCRXRIS_CRCERR</name>
|
|
<description>MMC Receive CRC Error Frame Counter Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCRXRIS_ALGNERR</name>
|
|
<description>MMC Receive Alignment Error Frame Counter Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCRXRIS_UCGF</name>
|
|
<description>MMC Receive Unicast Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMCTXRIS</name>
|
|
<description>Ethernet MAC MMC Transmit Raw Interrupt Status</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_MMCTXRIS_GBF</name>
|
|
<description>MMC Transmit Good Bad Frame Counter Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCTXRIS_SCOLLGF</name>
|
|
<description>MMC Transmit Single Collision Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCTXRIS_MCOLLGF</name>
|
|
<description>MMC Transmit Multiple Collision Good Frame Counter Interrupt Status</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCTXRIS_OCTCNT</name>
|
|
<description>Octet Counter Interrupt Status</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMCRXIM</name>
|
|
<description>Ethernet MAC MMC Receive Interrupt Mask</description>
|
|
<addressOffset>0x0000010C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_MMCRXIM_GBF</name>
|
|
<description>MMC Receive Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCRXIM_CRCERR</name>
|
|
<description>MMC Receive CRC Error Frame Counter Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCRXIM_ALGNERR</name>
|
|
<description>MMC Receive Alignment Error Frame Counter Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCRXIM_UCGF</name>
|
|
<description>MMC Receive Unicast Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMCTXIM</name>
|
|
<description>Ethernet MAC MMC Transmit Interrupt Mask</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_MMCTXIM_GBF</name>
|
|
<description>MMC Transmit Good Bad Frame Counter Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCTXIM_SCOLLGF</name>
|
|
<description>MMC Transmit Single Collision Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCTXIM_MCOLLGF</name>
|
|
<description>MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MMCTXIM_OCTCNT</name>
|
|
<description>MMC Transmit Good Octet Counter Interrupt Mask</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCNTGB</name>
|
|
<description>Ethernet MAC Transmit Frame Count for Good and Bad Frames</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TXCNTGB_TXFRMGB</name>
|
|
<description>This field indicates the number of good and bad frames transmitted, exclusive of retried frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCNTSCOL</name>
|
|
<description>Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision</description>
|
|
<addressOffset>0x0000014C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TXCNTSCOL_TXSNGLCOLG</name>
|
|
<description>This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCNTMCOL</name>
|
|
<description>Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions</description>
|
|
<addressOffset>0x00000150</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TXCNTMCOL_TXMULTCOLG</name>
|
|
<description>This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXOCTCNTG</name>
|
|
<description>Ethernet MAC Transmit Octet Count Good</description>
|
|
<addressOffset>0x00000164</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TXOCTCNTG_TXOCTG</name>
|
|
<description>This field indicates the number of bytes transmitted, exclusive of preamble, in good frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCNTGB</name>
|
|
<description>Ethernet MAC Receive Frame Count for Good and Bad Frames</description>
|
|
<addressOffset>0x00000180</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_RXCNTGB_RXFRMGB</name>
|
|
<description>This field indicates the number of received good and bad frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCNTCRCERR</name>
|
|
<description>Ethernet MAC Receive Frame Count for CRC Error Frames</description>
|
|
<addressOffset>0x00000194</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_RXCNTCRCERR_RXCRCERR</name>
|
|
<description>This field indicates the number of frames received with CRC error</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCNTALGNERR</name>
|
|
<description>Ethernet MAC Receive Frame Count for Alignment Error Frames</description>
|
|
<addressOffset>0x00000198</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_RXCNTALGNERR_RXALGNERR</name>
|
|
<description>This field indicates the number of frames received with alignment (dribble) error</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCNTGUNI</name>
|
|
<description>Ethernet MAC Receive Frame Count for Good Unicast Frames</description>
|
|
<addressOffset>0x000001C4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_RXCNTGUNI_RXUCASTG</name>
|
|
<description>This field indicates the number of received good unicast frames</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VLNINCREP</name>
|
|
<description>Ethernet MAC VLAN Tag Inclusion or Replacement</description>
|
|
<addressOffset>0x00000584</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_VLNINCREP_VLT</name>
|
|
<description>VLAN Tag for Transmit Frames</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_VLNINCREP_VLC</name>
|
|
<description>VLAN Tag Control in Transmit Frames</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_VLNINCREP_VLC_NONE</name>
|
|
<description>No VLAN tag deletion, insertion, or replacement</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_VLNINCREP_VLC_TAGDEL</name>
|
|
<description>VLAN tag deletion</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_VLNINCREP_VLC_TAGINS</name>
|
|
<description>VLAN tag insertion</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_VLNINCREP_VLC_TAGREP</name>
|
|
<description>VLAN tag replacement</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_VLNINCREP_VLP</name>
|
|
<description>VLAN Priority Control</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_VLNINCREP_CSVL</name>
|
|
<description>C-VLAN or S-VLAN</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VLANHASH</name>
|
|
<description>Ethernet MAC VLAN Hash Table</description>
|
|
<addressOffset>0x00000588</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_VLANHASH_VLHT</name>
|
|
<description>VLAN Hash Table</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMSTCTRL</name>
|
|
<description>Ethernet MAC Timestamp Control</description>
|
|
<addressOffset>0x00000700</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_TSEN</name>
|
|
<description>Timestamp Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_TSFCUPDT</name>
|
|
<description>Timestamp Fine or Coarse Update</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_TSINIT</name>
|
|
<description>Timestamp Initialize</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_TSUPDT</name>
|
|
<description>Timestamp Update</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_INTTRIG</name>
|
|
<description>Timestamp Interrupt Trigger Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_ADDREGUP</name>
|
|
<description>Addend Register Update</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_ALLF</name>
|
|
<description>Enable Timestamp For All Frames</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_DGTLBIN</name>
|
|
<description>Timestamp Digital or Binary Rollover Control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_PTPVER2</name>
|
|
<description>Enable PTP Packet Processing For Version 2 Format</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_PTPETH</name>
|
|
<description>Enable Processing of PTP Over Ethernet Frames</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_PTPIPV6</name>
|
|
<description>Enable Processing of PTP Frames Sent Over IPv6-UDP</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_PTPIPV4</name>
|
|
<description>Enable Processing of PTP Frames Sent over IPv4-UDP</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_TSEVNT</name>
|
|
<description>Enable Timestamp Snapshot for Event Messages</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_TSMAST</name>
|
|
<description>Enable Snapshot for Messages Relevant to Master</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_SELPTP</name>
|
|
<description>Select PTP packets for Taking Snapshots</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTCTRL_PTPFLTR</name>
|
|
<description>Enable MAC address for PTP Frame Filtering</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SUBSECINC</name>
|
|
<description>Ethernet MAC Sub-Second Increment</description>
|
|
<addressOffset>0x00000704</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_SUBSECINC_SSINC</name>
|
|
<description>Sub-second Increment Value</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMSEC</name>
|
|
<description>Ethernet MAC System Time - Seconds</description>
|
|
<addressOffset>0x00000708</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TIMSEC_TSS</name>
|
|
<description>Timestamp Second</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMNANO</name>
|
|
<description>Ethernet MAC System Time - Nanoseconds</description>
|
|
<addressOffset>0x0000070C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TIMNANO_TSSS</name>
|
|
<description>Timestamp Sub-Seconds</description>
|
|
<bitRange>[30:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMSECU</name>
|
|
<description>Ethernet MAC System Time - Seconds Update</description>
|
|
<addressOffset>0x00000710</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TIMSECU_TSS</name>
|
|
<description>Timestamp Second</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMNANOU</name>
|
|
<description>Ethernet MAC System Time - Nanoseconds Update</description>
|
|
<addressOffset>0x00000714</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TIMNANOU_TSSS</name>
|
|
<description>Timestamp Sub-Second</description>
|
|
<bitRange>[30:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMNANOU_ADDSUB</name>
|
|
<description>Add or subtract time</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMADD</name>
|
|
<description>Ethernet MAC Timestamp Addend</description>
|
|
<addressOffset>0x00000718</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TIMADD_TSAR</name>
|
|
<description>Timestamp Addend Register</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TARGSEC</name>
|
|
<description>Ethernet MAC Target Time Seconds</description>
|
|
<addressOffset>0x0000071C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TARGSEC_TSTR</name>
|
|
<description>Target Time Seconds Register</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TARGNANO</name>
|
|
<description>Ethernet MAC Target Time Nanoseconds</description>
|
|
<addressOffset>0x00000720</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TARGNANO_TTSLO</name>
|
|
<description>Target Timestamp Low Register</description>
|
|
<bitRange>[30:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TARGNANO_TRGTBUSY</name>
|
|
<description>Target Time Register Busy</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWORDSEC</name>
|
|
<description>Ethernet MAC System Time-Higher Word Seconds</description>
|
|
<addressOffset>0x00000724</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_HWORDSEC_TSHWR</name>
|
|
<description>Target Timestamp Higher Word Register</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMSTAT</name>
|
|
<description>Ethernet MAC Timestamp Status</description>
|
|
<addressOffset>0x00000728</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TIMSTAT_TSSOVF</name>
|
|
<description>Timestamp Seconds Overflow</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_TIMSTAT_TSTARGT</name>
|
|
<description>Timestamp Target Time Reached</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPSCTRL</name>
|
|
<description>Ethernet MAC PPS Control</description>
|
|
<addressOffset>0x0000072C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_PPSCTRL_PPSCTRL</name>
|
|
<description>EN0PPS Output Frequency Control (PPSCTRL) or Command Control (PPSCMD)</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_1HZ</name>
|
|
<description>When the PPSEN0 bit = 0x0, the EN0PPS signal is 1 pulse of the PTP reference clock.(of width clk_ptp_i) every second</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_2HZ</name>
|
|
<description>When the PPSEN0 bit = 0x0, the binary rollover is 2 Hz, and the digital rollover is 1 Hz</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_4HZ</name>
|
|
<description>When the PPSEN0 bit = 0x0, the binary rollover is 4 Hz, and the digital rollover is 2 Hz</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_8HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 8 Hz, and the digital rollover is 4 Hz,</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_16HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 16 Hz, and the digital rollover is 8 Hz</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_32HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 32 Hz, and the digital rollover is 16 Hz</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_64HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 64 Hz, and the digital rollover is 32 Hz</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_128HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 128 Hz, and the digital rollover is 64 Hz</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_256HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 256 Hz, and the digital rollover is 128 Hz</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_512HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 512 Hz, and the digital rollover is 256 Hz</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_1024HZ</name>
|
|
<description>When the PPSEN0 bit = 0x0, the binary rollover is 1.024 kHz, and the digital rollover is 512 Hz</description>
|
|
<value>0xa</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_2048HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 2.048 kHz, and the digital rollover is 1.024 kHz</description>
|
|
<value>0xb</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_4096HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 4.096 kHz, and the digital rollover is 2.048 kHz</description>
|
|
<value>0xc</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_8192HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 8.192 kHz, and the digital rollover is 4.096 kHz</description>
|
|
<value>0xd</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_16384HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 16.384 kHz, and the digital rollover is 8.092 kHz</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_PPSCTRL_32768HZ</name>
|
|
<description>When thePPSEN0 bit = 0x0, the binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PPSCTRL_PPSEN0</name>
|
|
<description>Flexible PPS Output Mode Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PPSCTRL_TRGMODS0</name>
|
|
<description>Target Time Register Mode for PPS0 Output</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_TRGMODS0_INTONLY</name>
|
|
<description>Indicates that the Target Time registers are programmed only for generating the interrupt event</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_TRGMODS0_INTPPS0</name>
|
|
<description>Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the EN0PPS output signal</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PPSCTRL_TRGMODS0_PPS0ONLY</name>
|
|
<description>Indicates that the Target Time registers are programmed only for starting or stopping the generation of the EN0PPS output signal. No interrupt is asserted</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPS0INTVL</name>
|
|
<description>Ethernet MAC PPS0 Interval</description>
|
|
<addressOffset>0x00000760</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_PPS0INTVL_PPS0INT</name>
|
|
<description>PPS0 Output Signal Interval</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPS0WIDTH</name>
|
|
<description>Ethernet MAC PPS0 Width</description>
|
|
<addressOffset>0x00000764</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_PPS0WIDTH</name>
|
|
<description>EN0PPS Output Signal Width</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMABUSMOD</name>
|
|
<description>Ethernet MAC DMA Bus Mode</description>
|
|
<addressOffset>0x00000C00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_SWR</name>
|
|
<description>DMA Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_DA</name>
|
|
<description>DMA Arbitration Scheme</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_DSL</name>
|
|
<description>Descriptor Skip Length</description>
|
|
<bitRange>[6:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_ATDS</name>
|
|
<description>Alternate Descriptor Size</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_PBL</name>
|
|
<description>Programmable Burst Length</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_PR</name>
|
|
<description>Priority Ratio</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_FB</name>
|
|
<description>Fixed Burst</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_RPBL</name>
|
|
<description>RX DMA Programmable Burst Length (PBL)</description>
|
|
<bitRange>[22:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_USP</name>
|
|
<description>Use Separate Programmable Burst Length (PBL)</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_8XPBL</name>
|
|
<description>8 x Programmable Burst Length (PBL) Mode</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_AAL</name>
|
|
<description>Address Aligned Beats</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_MB</name>
|
|
<description>Mixed Burst</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_TXPR</name>
|
|
<description>Transmit Priority</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMABUSMOD_RIB</name>
|
|
<description>Rebuild Burst</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXPOLLD</name>
|
|
<description>Ethernet MAC Transmit Poll Demand</description>
|
|
<addressOffset>0x00000C04</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TXPOLLD_TPD</name>
|
|
<description>Transmit Poll Demand</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXPOLLD</name>
|
|
<description>Ethernet MAC Receive Poll Demand</description>
|
|
<addressOffset>0x00000C08</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_RXPOLLD_RPD</name>
|
|
<description>Receive Poll Demand</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDLADDR</name>
|
|
<description>Ethernet MAC Receive Descriptor List Address</description>
|
|
<addressOffset>0x00000C0C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_RXDLADDR_STRXLIST</name>
|
|
<description>Start of Receive List</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDLADDR</name>
|
|
<description>Ethernet MAC Transmit Descriptor List Address</description>
|
|
<addressOffset>0x00000C10</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_TXDLADDR_TXDLADDR</name>
|
|
<description>Start of Transmit List Base Address</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMARIS</name>
|
|
<description>Ethernet MAC DMA Interrupt Status</description>
|
|
<addressOffset>0x00000C14</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_DMARIS_TI</name>
|
|
<description>Transmit Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_TPS</name>
|
|
<description>Transmit Process Stopped</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_TU</name>
|
|
<description>Transmit Buffer Unavailable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_TJT</name>
|
|
<description>Transmit Jabber Timeout</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_OVF</name>
|
|
<description>Receive Overflow</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_UNF</name>
|
|
<description>Transmit Underflow</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_RI</name>
|
|
<description>Receive Interrupt</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_RU</name>
|
|
<description>Receive Buffer Unavailable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_RPS</name>
|
|
<description>Receive Process Stopped</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_RWT</name>
|
|
<description>Receive Watchdog Timeout</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_ETI</name>
|
|
<description>Early Transmit Interrupt</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_FBI</name>
|
|
<description>Fatal Bus Error Interrupt</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_ERI</name>
|
|
<description>Early Receive Interrupt</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_AIS</name>
|
|
<description>Abnormal Interrupt Summary</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_NIS</name>
|
|
<description>Normal Interrupt Summary</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_RS</name>
|
|
<description>Received Process State</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_RS_STOP</name>
|
|
<description>Stopped: Reset or stop receive command issued</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_RS_RUNRXTD</name>
|
|
<description>Running: Fetching receive transfer descriptor</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_RS_RUNRXD</name>
|
|
<description>Running: Waiting for receive packet</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_RS_SUSPEND</name>
|
|
<description>Suspended: Receive descriptor unavailable</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_RS_RUNCRD</name>
|
|
<description>Running: Closing receive descriptor</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_RS_TSWS</name>
|
|
<description>Writing Timestamp</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_RS_RUNTXD</name>
|
|
<description>Running: Transferring the receive packet data from receive buffer to host memory</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_TS</name>
|
|
<description>Transmit Process State</description>
|
|
<bitRange>[22:20]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_TS_STOP</name>
|
|
<description>Stopped; Reset or Stop transmit command processed</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_TS_RUNTXTD</name>
|
|
<description>Running; Fetching transmit transfer descriptor</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_TS_STATUS</name>
|
|
<description>Running; Waiting for status</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_TS_RUNTX</name>
|
|
<description>Running; Reading data from host memory buffer and queuing it to transmit buffer (TX FIFO)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_TS_TSTAMP</name>
|
|
<description>Writing Timestamp</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_TS_SUSPEND</name>
|
|
<description>Suspended; Transmit descriptor unavailable or transmit buffer underflow</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_TS_RUNCTD</name>
|
|
<description>Running; Closing transmit descriptor</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_AE</name>
|
|
<description>Access Error</description>
|
|
<bitRange>[25:23]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_AE_RXDMAWD</name>
|
|
<description>Error during RX DMA Write Data Transfer</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_AE_TXDMARD</name>
|
|
<description>Error during TX DMA Read Data Transfer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_AE_RXDMADW</name>
|
|
<description>Error during RX DMA Descriptor Write Access</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_AE_TXDMADW</name>
|
|
<description>Error during TX DMA Descriptor Write Access</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_AE_RXDMADR</name>
|
|
<description>Error during RX DMA Descriptor Read Access</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMARIS_AE_TXDMADR</name>
|
|
<description>Error during TX DMA Descriptor Read Access</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_MMC</name>
|
|
<description>MAC MMC Interrupt</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_PMT</name>
|
|
<description>MAC PMT Interrupt Status</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMARIS_TT</name>
|
|
<description>Timestamp Trigger Interrupt Status</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAOPMODE</name>
|
|
<description>Ethernet MAC DMA Operation Mode</description>
|
|
<addressOffset>0x00000C18</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_SR</name>
|
|
<description>Start or Stop Receive</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_OSF</name>
|
|
<description>Operate on Second Frame</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_RTC</name>
|
|
<description>Receive Threshold Control</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_RTC_64</name>
|
|
<description>64 bytes</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_RTC_32</name>
|
|
<description>32 bytes</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_RTC_96</name>
|
|
<description>96 bytes</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_RTC_128</name>
|
|
<description>128 bytes</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_DGF</name>
|
|
<description>Drop Giant Frame Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_FUF</name>
|
|
<description>Forward Undersized Good Frames</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_FEF</name>
|
|
<description>Forward Error Frames</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_ST</name>
|
|
<description>Start or Stop Transmission Command</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_TTC</name>
|
|
<description>Transmit Threshold Control</description>
|
|
<bitRange>[16:14]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_TTC_64</name>
|
|
<description>64 bytes</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_TTC_128</name>
|
|
<description>128 bytes</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_TTC_192</name>
|
|
<description>192 bytes</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_TTC_256</name>
|
|
<description>256 bytes</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_TTC_40</name>
|
|
<description>40 bytes</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_TTC_32</name>
|
|
<description>32 bytes</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_TTC_24</name>
|
|
<description>24 bytes</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_DMAOPMODE_TTC_16</name>
|
|
<description>16 bytes</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_FTF</name>
|
|
<description>Flush Transmit FIFO</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_TSF</name>
|
|
<description>Transmit Store and Forward</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_DFF</name>
|
|
<description>Disable Flushing of Received Frames</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_RSF</name>
|
|
<description>Receive Store and Forward</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAOPMODE_DT</name>
|
|
<description>Disable Dropping of TCP/IP Checksum Error Frames</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAIM</name>
|
|
<description>Ethernet MAC DMA Interrupt Mask Register</description>
|
|
<addressOffset>0x00000C1C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_DMAIM_TIE</name>
|
|
<description>Transmit Interrupt Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_TSE</name>
|
|
<description>Transmit Stopped Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_TUE</name>
|
|
<description>Transmit Buffer Unvailable Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_TJE</name>
|
|
<description>Transmit Jabber Timeout Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_OVE</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_UNE</name>
|
|
<description>Underflow Interrupt Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_RIE</name>
|
|
<description>Receive Interrupt Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_RUE</name>
|
|
<description>Receive Buffer Unavailable Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_RSE</name>
|
|
<description>Receive Stopped Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_RWE</name>
|
|
<description>Receive Watchdog Timeout Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_ETE</name>
|
|
<description>Early Transmit Interrupt Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_FBE</name>
|
|
<description>Fatal Bus Error Enable</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_ERE</name>
|
|
<description>Early Receive Interrupt Enable</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_AIE</name>
|
|
<description>Abnormal Interrupt Summary Enable</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_DMAIM_NIE</name>
|
|
<description>Normal Interrupt Summary Enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MFBOC</name>
|
|
<description>Ethernet MAC Missed Frame and Buffer Overflow Counter</description>
|
|
<addressOffset>0x00000C20</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_MFBOC_MISFRMCNT</name>
|
|
<description>Missed Frame Counter</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MFBOC_MISCNTOVF</name>
|
|
<description>Overflow bit for Missed Frame Counter</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MFBOC_OVFFRMCNT</name>
|
|
<description>Overflow Frame Counter</description>
|
|
<bitRange>[27:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_MFBOC_OVFCNTOVF</name>
|
|
<description>Overflow Bit for FIFO Overflow Counter</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXINTWDT</name>
|
|
<description>Ethernet MAC Receive Interrupt Watchdog Timer</description>
|
|
<addressOffset>0x00000C24</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_RXINTWDT_RIWT</name>
|
|
<description>Receive Interrupt Watchdog Timer Count</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HOSTXDESC</name>
|
|
<description>Ethernet MAC Current Host Transmit Descriptor</description>
|
|
<addressOffset>0x00000C48</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_HOSTXDESC_CURTXDESC</name>
|
|
<description>Host Transmit Descriptor Address Pointer</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HOSRXDESC</name>
|
|
<description>Ethernet MAC Current Host Receive Descriptor</description>
|
|
<addressOffset>0x00000C4C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_HOSRXDESC_CURRXDESC</name>
|
|
<description>Host Receive Descriptor Address Pointer</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HOSTXBA</name>
|
|
<description>Ethernet MAC Current Host Transmit Buffer Address</description>
|
|
<addressOffset>0x00000C50</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_HOSTXBA_CURTXBUFA</name>
|
|
<description>Host Transmit Buffer Address Pointer</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HOSRXBA</name>
|
|
<description>Ethernet MAC Current Host Receive Buffer Address</description>
|
|
<addressOffset>0x00000C54</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_HOSRXBA_CURRXBUFA</name>
|
|
<description>Host Receive Buffer Address Pointer</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>Ethernet MAC Peripheral Property Register</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_PP_PHYTYPE</name>
|
|
<description>Ethernet PHY Type</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_PP_PHYTYPE_NONE</name>
|
|
<description>No PHY</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PP_PHYTYPE_1</name>
|
|
<description>Snowflake class PHY</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PP_MACTYPE</name>
|
|
<description>Ethernet MAC Type</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>Ethernet MAC Peripheral Configuration Register</description>
|
|
<addressOffset>0x00000FC4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_PC_PHYHOLD</name>
|
|
<description>Ethernet PHY Hold</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_ANMODE</name>
|
|
<description>Auto Negotiation Mode</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_PC_ANMODE_10HD</name>
|
|
<description>When ANEN = 0x0, the mode is 10Base-T, Half-Duplex</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PC_ANMODE_10FD</name>
|
|
<description>When ANEN = 0x0, the mode is 10Base-T, Full-Duplex</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PC_ANMODE_100HD</name>
|
|
<description>When ANEN = 0x0, the mode is 100Base-TX, Half-Duplex</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PC_ANMODE_100FD</name>
|
|
<description>When ANEN = 0x0, the mode is 100Base-TX, Full-Duplex</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_ANEN</name>
|
|
<description>Auto Negotiation Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_FASTANSEL</name>
|
|
<description>Fast Auto Negotiation Select</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_FASTANEN</name>
|
|
<description>Fast Auto Negotiation Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_EXTFD</name>
|
|
<description>Extended Full Duplex Ability</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_FASTLUPD</name>
|
|
<description>FAST Link-Up in Parallel Detect</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_FASTRXDV</name>
|
|
<description>Fast RXDV Detection</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_MDIXEN</name>
|
|
<description>MDIX Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_FASTMDIX</name>
|
|
<description>Fast Auto MDI-X</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_RBSTMDIX</name>
|
|
<description>Robust Auto MDI-X</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_MDISWAP</name>
|
|
<description>MDI Swap</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_POLSWAP</name>
|
|
<description>Polarity Swap</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_FASTLDMODE</name>
|
|
<description>Fast Link Down Mode</description>
|
|
<bitRange>[19:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_TDRRUN</name>
|
|
<description>TDR Auto Run</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_LRR</name>
|
|
<description>Link Loss Recovery</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_ISOMIILL</name>
|
|
<description>Isolate MII in Link Loss</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_RXERIDLE</name>
|
|
<description>RXER Detection During Idle</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_NIBDETDIS</name>
|
|
<description>Odd Nibble TXER Detection Disable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_DIGRESTART</name>
|
|
<description>PHY Soft Restart</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_PINTFS</name>
|
|
<description>Ethernet Interface Select</description>
|
|
<bitRange>[30:28]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMAC_PC_PINTFS_IMII</name>
|
|
<description>MII (default) Used for internal PHY or external PHY connected via MII</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMAC_PC_PINTFS_RMII</name>
|
|
<description>RMII: Used for external PHY connected via RMII</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_PC_PHYEXT</name>
|
|
<description>PHY Select</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC</name>
|
|
<description>Ethernet MAC Clock Configuration Register</description>
|
|
<addressOffset>0x00000FC8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_CC_POL</name>
|
|
<description>LED Polarity Control</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMAC_CC_PTPCEN</name>
|
|
<description>PTP Clock Reference Enable</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPHYRIS</name>
|
|
<description>Ethernet PHY Raw Interrupt Status</description>
|
|
<addressOffset>0x00000FCC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_EPHYRIS_INT</name>
|
|
<description>Ethernet PHY Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPHYIM</name>
|
|
<description>Ethernet PHY Interrupt Mask</description>
|
|
<addressOffset>0x00000FD0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_EPHYIM_INT</name>
|
|
<description>Ethernet PHY Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPHYMISC</name>
|
|
<description>Ethernet PHY Masked Interrupt Status and Clear</description>
|
|
<addressOffset>0x00000FD4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>EMAC_EPHYMISC_INT</name>
|
|
<description>Ethernet PHY Status and Clear register</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SYSEXC</name>
|
|
<description>Register map for SYSEXC peripheral</description>
|
|
<groupName>SYSEXC</groupName>
|
|
<prependToName>SYSEXC</prependToName>
|
|
<baseAddress>0x400F9000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>SYSEXC</name><value>67</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>System Exception Raw Interrupt Status</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSEXC_RIS_FPIDCRIS</name>
|
|
<description>Floating-Point Input Denormal Exception Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_RIS_FPDZCRIS</name>
|
|
<description>Floating-Point Divide By 0 Exception Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_RIS_FPIOCRIS</name>
|
|
<description>Floating-Point Invalid Operation Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_RIS_FPUFCRIS</name>
|
|
<description>Floating-Point Underflow Exception Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_RIS_FPOFCRIS</name>
|
|
<description>Floating-Point Overflow Exception Raw Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_RIS_FPIXCRIS</name>
|
|
<description>Floating-Point Inexact Exception Raw Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IM</name>
|
|
<description>System Exception Interrupt Mask</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSEXC_IM_FPIDCIM</name>
|
|
<description>Floating-Point Input Denormal Exception Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_IM_FPDZCIM</name>
|
|
<description>Floating-Point Divide By 0 Exception Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_IM_FPIOCIM</name>
|
|
<description>Floating-Point Invalid Operation Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_IM_FPUFCIM</name>
|
|
<description>Floating-Point Underflow Exception Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_IM_FPOFCIM</name>
|
|
<description>Floating-Point Overflow Exception Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_IM_FPIXCIM</name>
|
|
<description>Floating-Point Inexact Exception Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>System Exception Masked Interrupt Status</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSEXC_MIS_FPIDCMIS</name>
|
|
<description>Floating-Point Input Denormal Exception Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_MIS_FPDZCMIS</name>
|
|
<description>Floating-Point Divide By 0 Exception Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_MIS_FPIOCMIS</name>
|
|
<description>Floating-Point Invalid Operation Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_MIS_FPUFCMIS</name>
|
|
<description>Floating-Point Underflow Exception Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_MIS_FPOFCMIS</name>
|
|
<description>Floating-Point Overflow Exception Masked Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_MIS_FPIXCMIS</name>
|
|
<description>Floating-Point Inexact Exception Masked Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IC</name>
|
|
<description>System Exception Interrupt Clear</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SYSEXC_IC_FPIDCIC</name>
|
|
<description>Floating-Point Input Denormal Exception Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_IC_FPDZCIC</name>
|
|
<description>Floating-Point Divide By 0 Exception Interrupt Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_IC_FPIOCIC</name>
|
|
<description>Floating-Point Invalid Operation Interrupt Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_IC_FPUFCIC</name>
|
|
<description>Floating-Point Underflow Exception Interrupt Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_IC_FPOFCIC</name>
|
|
<description>Floating-Point Overflow Exception Interrupt Clear</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSEXC_IC_FPIXCIC</name>
|
|
<description>Floating-Point Inexact Exception Interrupt Clear</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HIB</name>
|
|
<description>Register map for HIB peripheral</description>
|
|
<groupName>HIB</groupName>
|
|
<prependToName>HIB</prependToName>
|
|
<baseAddress>0x400FC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>HIB</name><value>41</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>RTCC</name>
|
|
<description>Hibernation RTC Counter</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_RTCC</name>
|
|
<description>RTC Counter</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCM0</name>
|
|
<description>Hibernation RTC Match 0</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_RTCM0</name>
|
|
<description>RTC Match 0</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCLD</name>
|
|
<description>Hibernation RTC Load</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_RTCLD</name>
|
|
<description>RTC Load</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>Hibernation Control</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_CTL_RTCEN</name>
|
|
<description>RTC Timer Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_HIBREQ</name>
|
|
<description>Hibernation Request</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_RTCWEN</name>
|
|
<description>RTC Wake-up Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_PINWEN</name>
|
|
<description>External Wake Pin Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_CLK32EN</name>
|
|
<description>Clocking Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_VABORT</name>
|
|
<description>Power Cut Abort Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_VDD3ON</name>
|
|
<description>VDD Powered</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_BATWKEN</name>
|
|
<description>Wake on Low Battery</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_BATCHK</name>
|
|
<description>Check Battery Status</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_VBATSEL</name>
|
|
<description>Select for Low-Battery Comparator</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIB_CTL_VBATSEL_1_9V</name>
|
|
<description>1.9 Volts</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIB_CTL_VBATSEL_2_1V</name>
|
|
<description>2.1 Volts (default)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIB_CTL_VBATSEL_2_3V</name>
|
|
<description>2.3 Volts</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIB_CTL_VBATSEL_2_5V</name>
|
|
<description>2.5 Volts</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_OSCBYP</name>
|
|
<description>Oscillator Bypass</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_OSCDRV</name>
|
|
<description>Oscillator Drive Capability</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_OSCSEL</name>
|
|
<description>Oscillator Select</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_RETCLR</name>
|
|
<description>GPIO Retention/Clear</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CTL_WRC</name>
|
|
<description>Write Complete/Capable</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IM</name>
|
|
<description>Hibernation Interrupt Mask</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_IM_RTCALT0</name>
|
|
<description>RTC Alert 0 Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IM_LOWBAT</name>
|
|
<description>Low Battery Voltage Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IM_EXTW</name>
|
|
<description>External Wake-Up Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IM_WC</name>
|
|
<description>External Write Complete/Capable Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IM_PADIOWK</name>
|
|
<description>Pad I/O Wake-Up Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IM_RSTWK</name>
|
|
<description>Reset Pad I/O Wake-Up Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IM_VDDFAIL</name>
|
|
<description>VDD Fail Interrupt Mask</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>Hibernation Raw Interrupt Status</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_RIS_RTCALT0</name>
|
|
<description>RTC Alert 0 Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_RIS_LOWBAT</name>
|
|
<description>Low Battery Voltage Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_RIS_EXTW</name>
|
|
<description>External Wake-Up Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_RIS_WC</name>
|
|
<description>Write Complete/Capable Raw Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_RIS_PADIOWK</name>
|
|
<description>Pad I/O Wake-Up Raw Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_RIS_RSTWK</name>
|
|
<description>Reset Pad I/O Wake-Up Raw Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_RIS_VDDFAIL</name>
|
|
<description>VDD Fail Raw Interrupt Status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>Hibernation Masked Interrupt Status</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_MIS_RTCALT0</name>
|
|
<description>RTC Alert 0 Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_MIS_LOWBAT</name>
|
|
<description>Low Battery Voltage Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_MIS_EXTW</name>
|
|
<description>External Wake-Up Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_MIS_WC</name>
|
|
<description>Write Complete/Capable Masked Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_MIS_PADIOWK</name>
|
|
<description>Pad I/O Wake-Up Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_MIS_RSTWK</name>
|
|
<description>Reset Pad I/O Wake-Up Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_MIS_VDDFAIL</name>
|
|
<description>VDD Fail Interrupt Mask</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IC</name>
|
|
<description>Hibernation Interrupt Clear</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_IC_RTCALT0</name>
|
|
<description>RTC Alert0 Masked Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IC_LOWBAT</name>
|
|
<description>Low Battery Voltage Interrupt Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IC_EXTW</name>
|
|
<description>External Wake-Up Interrupt Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IC_WC</name>
|
|
<description>Write Complete/Capable Interrupt Clear</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IC_PADIOWK</name>
|
|
<description>Pad I/O Wake-Up Interrupt Clear</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IC_RSTWK</name>
|
|
<description>Reset Pad I/O Wake-Up Interrupt Clear</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IC_VDDFAIL</name>
|
|
<description>VDD Fail Interrupt Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCT</name>
|
|
<description>Hibernation RTC Trim</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_RTCT_TRIM</name>
|
|
<description>RTC Trim Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTCSS</name>
|
|
<description>Hibernation RTC Sub Seconds</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_RTCSS_RTCSSC</name>
|
|
<description>RTC Sub Seconds Count</description>
|
|
<bitRange>[14:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_RTCSS_RTCSSM</name>
|
|
<description>RTC Sub Seconds Match</description>
|
|
<bitRange>[30:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IO</name>
|
|
<description>Hibernation IO Configuration</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_IO_WUUNLK</name>
|
|
<description>I/O Wake Pad Configuration Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IO_WURSTEN</name>
|
|
<description>Reset Wake Source Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_IO_IOWRC</name>
|
|
<description>I/O Write Complete</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Hibernation Data</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_DATA_RTD</name>
|
|
<description>Hibernation Module NV Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALCTL</name>
|
|
<description>Hibernation Calendar Control</description>
|
|
<addressOffset>0x00000300</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_CALCTL_CALEN</name>
|
|
<description>RTC Calendar/Counter Mode Select</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CALCTL_CAL24</name>
|
|
<description>Calendar Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAL0</name>
|
|
<description>Hibernation Calendar 0</description>
|
|
<addressOffset>0x00000310</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_CAL0_SEC</name>
|
|
<description>Seconds</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CAL0_MIN</name>
|
|
<description>Minutes</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CAL0_HR</name>
|
|
<description>Hours</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CAL0_AMPM</name>
|
|
<description>AM/PM Designation</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CAL0_VALID</name>
|
|
<description>Valid Calendar Load</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAL1</name>
|
|
<description>Hibernation Calendar 1</description>
|
|
<addressOffset>0x00000314</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_CAL1_DOM</name>
|
|
<description>Day of Month</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CAL1_MON</name>
|
|
<description>Month</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CAL1_YEAR</name>
|
|
<description>Year Value</description>
|
|
<bitRange>[22:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CAL1_DOW</name>
|
|
<description>Day of Week</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CAL1_VALID</name>
|
|
<description>Valid Calendar Load</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALLD0</name>
|
|
<description>Hibernation Calendar Load 0</description>
|
|
<addressOffset>0x00000320</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_CALLD0_SEC</name>
|
|
<description>Seconds</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CALLD0_MIN</name>
|
|
<description>Minutes</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CALLD0_HR</name>
|
|
<description>Hours</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CALLD0_AMPM</name>
|
|
<description>AM/PM Designation</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALLD1</name>
|
|
<description>Hibernation Calendar Load</description>
|
|
<addressOffset>0x00000324</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_CALLD1_DOM</name>
|
|
<description>Day of Month</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CALLD1_MON</name>
|
|
<description>Month</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CALLD1_YEAR</name>
|
|
<description>Year Value</description>
|
|
<bitRange>[22:16]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CALLD1_DOW</name>
|
|
<description>Day of Week</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALM0</name>
|
|
<description>Hibernation Calendar Match 0</description>
|
|
<addressOffset>0x00000330</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_CALM0_SEC</name>
|
|
<description>Seconds</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CALM0_MIN</name>
|
|
<description>Minutes</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CALM0_HR</name>
|
|
<description>Hours</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_CALM0_AMPM</name>
|
|
<description>AM/PM Designation</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALM1</name>
|
|
<description>Hibernation Calendar Match 1</description>
|
|
<addressOffset>0x00000334</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_CALM1_DOM</name>
|
|
<description>Day of Month</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<description>Hibernation Lock</description>
|
|
<addressOffset>0x00000360</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_LOCK_HIBLOCK</name>
|
|
<description>HIbernate Lock</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPCTL</name>
|
|
<description>HIB Tamper Control</description>
|
|
<addressOffset>0x00000400</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_TPCTL_TPEN</name>
|
|
<description>Tamper Module Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPCTL_TPCLR</name>
|
|
<description>Tamper Event Clear</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPCTL_MEMCLR</name>
|
|
<description>HIB Memory Clear on Tamper Event</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIB_TPCTL_MEMCLR_NONE</name>
|
|
<description>Do not Clear HIB memory on tamper event</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIB_TPCTL_MEMCLR_LOW32</name>
|
|
<description>Clear Lower 32 Bytes of HIB memory on tamper event</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIB_TPCTL_MEMCLR_HIGH32</name>
|
|
<description>Clear upper 32 Bytes of HIB memory on tamper event</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIB_TPCTL_MEMCLR_ALL</name>
|
|
<description>Clear all HIB memory on tamper event</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPCTL_WAKE</name>
|
|
<description>Wake from Hibernate on a Tamper Event</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPSTAT</name>
|
|
<description>HIB Tamper Status</description>
|
|
<addressOffset>0x00000404</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_TPSTAT_XOSCFAIL</name>
|
|
<description>External Oscillator Failure</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPSTAT_XOSCST</name>
|
|
<description>External Oscillator Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPSTAT_STATE</name>
|
|
<description>Tamper Module Status</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIB_TPSTAT_STATE_DISABLED</name>
|
|
<description>Tamper disabled</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIB_TPSTAT_STATE_CONFIGED</name>
|
|
<description>Tamper configured</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIB_TPSTAT_STATE_ERROR</name>
|
|
<description>Tamper pin event occurred</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPIO</name>
|
|
<description>HIB Tamper I/O Control</description>
|
|
<addressOffset>0x00000410</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_TPIO_EN0</name>
|
|
<description>TMPR0 Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_LEV0</name>
|
|
<description>TMPR0 Trigger Level</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_PUEN0</name>
|
|
<description>TMPR0 Internal Weak Pull-up Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_GFLTR0</name>
|
|
<description>TMPR0 Glitch Filtering</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_EN1</name>
|
|
<description>TMPR1Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_LEV1</name>
|
|
<description>TMPR1 Trigger Level</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_PUEN1</name>
|
|
<description>TMPR1 Internal Weak Pull-up Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_GFLTR1</name>
|
|
<description>TMPR1 Glitch Filtering</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_EN2</name>
|
|
<description>TMPR2 Enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_LEV2</name>
|
|
<description>TMPR2 Trigger Level</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_PUEN2</name>
|
|
<description>TMPR2 Internal Weak Pull-up Enable</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_GFLTR2</name>
|
|
<description>TMPR2 Glitch Filtering</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_EN3</name>
|
|
<description>TMPR3 Enable</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_LEV3</name>
|
|
<description>TMPR3 Trigger Level</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_PUEN3</name>
|
|
<description>TMPR3 Internal Weak Pull-up Enable</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPIO_GFLTR3</name>
|
|
<description>TMPR3 Glitch Filtering</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPLOG0</name>
|
|
<description>HIB Tamper Log 0</description>
|
|
<addressOffset>0x000004E0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_TPLOG0_TIME</name>
|
|
<description>Tamper Log Calendar Information</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPLOG1</name>
|
|
<description>HIB Tamper Log 1</description>
|
|
<addressOffset>0x000004E4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_TPLOG1_TRIG0</name>
|
|
<description>Status of TMPR[0] Trigger</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG1_TRIG1</name>
|
|
<description>Status of TMPR[1] Trigger</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG1_TRIG2</name>
|
|
<description>Status of TMPR[2] Trigger</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG1_TRIG3</name>
|
|
<description>Status of TMPR[3] Trigger</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG1_XOSC</name>
|
|
<description>Status of external 32</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPLOG2</name>
|
|
<description>HIB Tamper Log 2</description>
|
|
<addressOffset>0x000004E8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_TPLOG2_TIME</name>
|
|
<description>Tamper Log Calendar Information</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPLOG3</name>
|
|
<description>HIB Tamper Log 3</description>
|
|
<addressOffset>0x000004EC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_TPLOG3_TRIG0</name>
|
|
<description>Status of TMPR[0] Trigger</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG3_TRIG1</name>
|
|
<description>Status of TMPR[1] Trigger</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG3_TRIG2</name>
|
|
<description>Status of TMPR[2] Trigger</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG3_TRIG3</name>
|
|
<description>Status of TMPR[3] Trigger</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG3_XOSC</name>
|
|
<description>Status of external 32</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPLOG4</name>
|
|
<description>HIB Tamper Log 4</description>
|
|
<addressOffset>0x000004F0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_TPLOG4_TIME</name>
|
|
<description>Tamper Log Calendar Information</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPLOG5</name>
|
|
<description>HIB Tamper Log 5</description>
|
|
<addressOffset>0x000004F4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_TPLOG5_TRIG0</name>
|
|
<description>Status of TMPR[0] Trigger</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG5_TRIG1</name>
|
|
<description>Status of TMPR[1] Trigger</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG5_TRIG2</name>
|
|
<description>Status of TMPR[2] Trigger</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG5_TRIG3</name>
|
|
<description>Status of TMPR[3] Trigger</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG5_XOSC</name>
|
|
<description>Status of external 32</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPLOG6</name>
|
|
<description>HIB Tamper Log 6</description>
|
|
<addressOffset>0x000004F8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_TPLOG6_TIME</name>
|
|
<description>Tamper Log Calendar Information</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPLOG7</name>
|
|
<description>HIB Tamper Log 7</description>
|
|
<addressOffset>0x000004FC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_TPLOG7_TRIG0</name>
|
|
<description>Status of TMPR[0] Trigger</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG7_TRIG1</name>
|
|
<description>Status of TMPR[1] Trigger</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG7_TRIG2</name>
|
|
<description>Status of TMPR[2] Trigger</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG7_TRIG3</name>
|
|
<description>Status of TMPR[3] Trigger</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_TPLOG7_XOSC</name>
|
|
<description>Status of external 32</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>Hibernation Peripheral Properties</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_PP_WAKENC</name>
|
|
<description>Wake Pin Presence</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HIB_PP_TAMPER</name>
|
|
<description>Tamper Pin Presence</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC</name>
|
|
<description>Hibernation Clock Control</description>
|
|
<addressOffset>0x00000FC8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>HIB_CC_SYSCLKEN</name>
|
|
<description>RTCOSC to System Clock Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLASH_CTRL</name>
|
|
<description>Register map for FLASH_CTRL peripheral</description>
|
|
<groupName>FLASH_CTRL</groupName>
|
|
<prependToName>FLASH_CTRL</prependToName>
|
|
<baseAddress>0x400FD000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1000</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>FLASH_CTRL</name><value>29</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FMA</name>
|
|
<description>Flash Memory Address</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMA_OFFSET</name>
|
|
<description>Address Offset</description>
|
|
<bitRange>[19:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMD</name>
|
|
<description>Flash Memory Data</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMD_DATA</name>
|
|
<description>Data Value</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMC</name>
|
|
<description>Flash Memory Control</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMC_WRITE</name>
|
|
<description>Write a Word into Flash Memory</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FMC_ERASE</name>
|
|
<description>Erase a Page of Flash Memory</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FMC_MERASE</name>
|
|
<description>Mass Erase Flash Memory</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FMC_COMT</name>
|
|
<description>Commit Register Value</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FMC_WRKEY</name>
|
|
<description>FLASH write key</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCRIS</name>
|
|
<description>Flash Controller Raw Interrupt Status</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FCRIS_ARIS</name>
|
|
<description>Access Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCRIS_PRIS</name>
|
|
<description>Programming Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCRIS_ERIS</name>
|
|
<description>EEPROM Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCRIS_VOLTRIS</name>
|
|
<description>Pump Voltage Raw Interrupt Status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCRIS_INVDRIS</name>
|
|
<description>Invalid Data Raw Interrupt Status</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCRIS_ERRIS</name>
|
|
<description>Erase Verify Error Raw Interrupt Status</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCRIS_PROGRIS</name>
|
|
<description>Program Verify Error Raw Interrupt Status</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCIM</name>
|
|
<description>Flash Controller Interrupt Mask</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FCIM_AMASK</name>
|
|
<description>Access Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCIM_PMASK</name>
|
|
<description>Programming Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCIM_EMASK</name>
|
|
<description>EEPROM Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCIM_VOLTMASK</name>
|
|
<description>VOLT Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCIM_INVDMASK</name>
|
|
<description>Invalid Data Interrupt Mask</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCIM_ERMASK</name>
|
|
<description>ERVER Interrupt Mask</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCIM_PROGMASK</name>
|
|
<description>PROGVER Interrupt Mask</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCMISC</name>
|
|
<description>Flash Controller Masked Interrupt Status and Clear</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FCMISC_AMISC</name>
|
|
<description>Access Masked Interrupt Status and Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCMISC_PMISC</name>
|
|
<description>Programming Masked Interrupt Status and Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCMISC_EMISC</name>
|
|
<description>EEPROM Masked Interrupt Status and Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCMISC_VOLTMISC</name>
|
|
<description>VOLT Masked Interrupt Status and Clear</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCMISC_INVDMISC</name>
|
|
<description>Invalid Data Masked Interrupt Status and Clear</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCMISC_ERMISC</name>
|
|
<description>ERVER Masked Interrupt Status and Clear</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCMISC_PROGMISC</name>
|
|
<description>PROGVER Masked Interrupt Status and Clear</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMC2</name>
|
|
<description>Flash Memory Control 2</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMC2_WRBUF</name>
|
|
<description>Buffered Flash Memory Write</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FWBVAL</name>
|
|
<description>Flash Write Buffer Valid</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FWBVAL_FWB</name>
|
|
<description>Flash Memory Write Buffer</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLPEKEY</name>
|
|
<description>Flash Program/Erase Key</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FLPEKEY_PEKEY</name>
|
|
<description>Key Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
|
|
<name>FWBN[%s]</name>
|
|
<description>Flash Write Buffer n</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FWBN_DATA</name>
|
|
<description>Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PP</name>
|
|
<description>Flash Peripheral Properties</description>
|
|
<addressOffset>0x00000FC0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_PP_SIZE</name>
|
|
<description>Flash Size</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_PP_MAINSS</name>
|
|
<description>Flash Sector Size of the physical bank</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_PP_MAINSS_1KB</name>
|
|
<description>1 KB</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_PP_MAINSS_2KB</name>
|
|
<description>2 KB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_PP_MAINSS_4KB</name>
|
|
<description>4 KB</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_PP_MAINSS_8KB</name>
|
|
<description>8 KB</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_PP_MAINSS_16KB</name>
|
|
<description>16 KB</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_PP_EESS</name>
|
|
<description>EEPROM Sector Size of the physical bank</description>
|
|
<bitRange>[22:19]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_PP_EESS_1KB</name>
|
|
<description>1 KB</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_PP_EESS_2KB</name>
|
|
<description>2 KB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_PP_EESS_4KB</name>
|
|
<description>4 KB</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_PP_EESS_8KB</name>
|
|
<description>8 KB</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_PP_DFA</name>
|
|
<description>DMA Flash Access</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_PP_FMM</name>
|
|
<description>Flash Mirror Mode</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_PP_PFC</name>
|
|
<description>Prefetch Buffer Mode</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSIZE</name>
|
|
<description>SRAM Size</description>
|
|
<addressOffset>0x00000FC4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_SSIZE_SIZE</name>
|
|
<description>SRAM Size</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Flash Configuration Register</description>
|
|
<addressOffset>0x00000FC8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_CONF_FPFOFF</name>
|
|
<description>Force Prefetch Off</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_CONF_FPFON</name>
|
|
<description>Force Prefetch On</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_CONF_CLRTV</name>
|
|
<description>Clear Valid Tags</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_CONF_SPFE</name>
|
|
<description>Single Prefetch Mode Enable</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_CONF_FMME</name>
|
|
<description>Flash Mirror Mode Enable</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROMSWMAP</name>
|
|
<description>ROM Software Map</description>
|
|
<addressOffset>0x00000FCC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_ROMSWMAP_SW0EN</name>
|
|
<description>ROM SW Region 0 Availability</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW0EN_NOTVIS</name>
|
|
<description>Software region not available to the core</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW0EN_CORE</name>
|
|
<description>Region available to core</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_ROMSWMAP_SW1EN</name>
|
|
<description>ROM SW Region 1 Availability</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW1EN_NOTVIS</name>
|
|
<description>Software region not available to the core</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW1EN_CORE</name>
|
|
<description>Region available to core</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_ROMSWMAP_SW2EN</name>
|
|
<description>ROM SW Region 2 Availability</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW2EN_NOTVIS</name>
|
|
<description>Software region not available to the core</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW2EN_CORE</name>
|
|
<description>Region available to core</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_ROMSWMAP_SW3EN</name>
|
|
<description>ROM SW Region 3 Availability</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW3EN_NOTVIS</name>
|
|
<description>Software region not available to the core</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW3EN_CORE</name>
|
|
<description>Region available to core</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_ROMSWMAP_SW4EN</name>
|
|
<description>ROM SW Region 4 Availability</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW4EN_NOTVIS</name>
|
|
<description>Software region not available to the core</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW4EN_CORE</name>
|
|
<description>Region available to core</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_ROMSWMAP_SW5EN</name>
|
|
<description>ROM SW Region 5 Availability</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW5EN_NOTVIS</name>
|
|
<description>Software region not available to the core</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW5EN_CORE</name>
|
|
<description>Region available to core</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_ROMSWMAP_SW6EN</name>
|
|
<description>ROM SW Region 6 Availability</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW6EN_NOTVIS</name>
|
|
<description>Software region not available to the core</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW6EN_CORE</name>
|
|
<description>Region available to core</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_ROMSWMAP_SW7EN</name>
|
|
<description>ROM SW Region 7 Availability</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW7EN_NOTVIS</name>
|
|
<description>Software region not available to the core</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_ROMSWMAP_SW7EN_CORE</name>
|
|
<description>Region available to core</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMASZ</name>
|
|
<description>Flash DMA Address Size</description>
|
|
<addressOffset>0x00000FD0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_DMASZ_SIZE</name>
|
|
<description>uDMA-accessible Memory Size</description>
|
|
<bitRange>[17:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAST</name>
|
|
<description>Flash DMA Starting Address</description>
|
|
<addressOffset>0x00000FD4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_DMAST_ADDR</name>
|
|
<description>Contains the starting address of the flash region accessible by uDMA if the FLASHPP register DFA bit is set</description>
|
|
<bitRange>[28:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RVP</name>
|
|
<description>Reset Vector Pointer</description>
|
|
<addressOffset>0x000010D4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_RVP_RV</name>
|
|
<description>Reset Vector Pointer Address</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BOOTCFG</name>
|
|
<description>Boot Configuration</description>
|
|
<addressOffset>0x000011D0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_BOOTCFG_DBG0</name>
|
|
<description>Debug Control 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_BOOTCFG_DBG1</name>
|
|
<description>Debug Control 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_BOOTCFG_KEY</name>
|
|
<description>KEY Select</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_BOOTCFG_EN</name>
|
|
<description>Boot GPIO Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_BOOTCFG_POL</name>
|
|
<description>Boot GPIO Polarity</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_BOOTCFG_PIN</name>
|
|
<description>Boot GPIO Pin</description>
|
|
<bitRange>[12:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PIN_0</name>
|
|
<description>Pin 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PIN_1</name>
|
|
<description>Pin 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PIN_2</name>
|
|
<description>Pin 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PIN_3</name>
|
|
<description>Pin 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PIN_4</name>
|
|
<description>Pin 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PIN_5</name>
|
|
<description>Pin 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PIN_6</name>
|
|
<description>Pin 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PIN_7</name>
|
|
<description>Pin 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_BOOTCFG_PORT</name>
|
|
<description>Boot GPIO Port</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PORT_A</name>
|
|
<description>Port A</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PORT_B</name>
|
|
<description>Port B</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PORT_C</name>
|
|
<description>Port C</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PORT_D</name>
|
|
<description>Port D</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PORT_E</name>
|
|
<description>Port E</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PORT_F</name>
|
|
<description>Port F</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PORT_G</name>
|
|
<description>Port G</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLASH_BOOTCFG_PORT_H</name>
|
|
<description>Port H</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_BOOTCFG_NW</name>
|
|
<description>Not Written</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USERREG0</name>
|
|
<description>User Register 0</description>
|
|
<addressOffset>0x000011E0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_USERREG0_DATA</name>
|
|
<description>User Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USERREG1</name>
|
|
<description>User Register 1</description>
|
|
<addressOffset>0x000011E4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_USERREG1_DATA</name>
|
|
<description>User Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USERREG2</name>
|
|
<description>User Register 2</description>
|
|
<addressOffset>0x000011E8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_USERREG2_DATA</name>
|
|
<description>User Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USERREG3</name>
|
|
<description>User Register 3</description>
|
|
<addressOffset>0x000011EC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_USERREG3_DATA</name>
|
|
<description>User Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE0</name>
|
|
<description>Flash Memory Protection Read Enable 0</description>
|
|
<addressOffset>0x00001200</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE1</name>
|
|
<description>Flash Memory Protection Read Enable 1</description>
|
|
<addressOffset>0x00001204</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE2</name>
|
|
<description>Flash Memory Protection Read Enable 2</description>
|
|
<addressOffset>0x00001208</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE3</name>
|
|
<description>Flash Memory Protection Read Enable 3</description>
|
|
<addressOffset>0x0000120C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE4</name>
|
|
<description>Flash Memory Protection Read Enable 4</description>
|
|
<addressOffset>0x00001210</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE5</name>
|
|
<description>Flash Memory Protection Read Enable 5</description>
|
|
<addressOffset>0x00001214</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE6</name>
|
|
<description>Flash Memory Protection Read Enable 6</description>
|
|
<addressOffset>0x00001218</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE7</name>
|
|
<description>Flash Memory Protection Read Enable 7</description>
|
|
<addressOffset>0x0000121C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE8</name>
|
|
<description>Flash Memory Protection Read Enable 8</description>
|
|
<addressOffset>0x00001220</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPRE8_READ_ENABLE</name>
|
|
<description>Flash Read Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE9</name>
|
|
<description>Flash Memory Protection Read Enable 9</description>
|
|
<addressOffset>0x00001224</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPRE9_READ_ENABLE</name>
|
|
<description>Flash Read Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE10</name>
|
|
<description>Flash Memory Protection Read Enable 10</description>
|
|
<addressOffset>0x00001228</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPRE10_READ_ENABLE</name>
|
|
<description>Flash Read Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE11</name>
|
|
<description>Flash Memory Protection Read Enable 11</description>
|
|
<addressOffset>0x0000122C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPRE11_READ_ENABLE</name>
|
|
<description>Flash Read Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE12</name>
|
|
<description>Flash Memory Protection Read Enable 12</description>
|
|
<addressOffset>0x00001230</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPRE12_READ_ENABLE</name>
|
|
<description>Flash Read Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE13</name>
|
|
<description>Flash Memory Protection Read Enable 13</description>
|
|
<addressOffset>0x00001234</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPRE13_READ_ENABLE</name>
|
|
<description>Flash Read Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE14</name>
|
|
<description>Flash Memory Protection Read Enable 14</description>
|
|
<addressOffset>0x00001238</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPRE14_READ_ENABLE</name>
|
|
<description>Flash Read Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE15</name>
|
|
<description>Flash Memory Protection Read Enable 15</description>
|
|
<addressOffset>0x0000123C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPRE15_READ_ENABLE</name>
|
|
<description>Flash Read Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE0</name>
|
|
<description>Flash Memory Protection Program Enable 0</description>
|
|
<addressOffset>0x00001400</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE1</name>
|
|
<description>Flash Memory Protection Program Enable 1</description>
|
|
<addressOffset>0x00001404</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE2</name>
|
|
<description>Flash Memory Protection Program Enable 2</description>
|
|
<addressOffset>0x00001408</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE3</name>
|
|
<description>Flash Memory Protection Program Enable 3</description>
|
|
<addressOffset>0x0000140C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE4</name>
|
|
<description>Flash Memory Protection Program Enable 4</description>
|
|
<addressOffset>0x00001410</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE5</name>
|
|
<description>Flash Memory Protection Program Enable 5</description>
|
|
<addressOffset>0x00001414</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE6</name>
|
|
<description>Flash Memory Protection Program Enable 6</description>
|
|
<addressOffset>0x00001418</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE7</name>
|
|
<description>Flash Memory Protection Program Enable 7</description>
|
|
<addressOffset>0x0000141C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE8</name>
|
|
<description>Flash Memory Protection Program Enable 8</description>
|
|
<addressOffset>0x00001420</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPPE8_PROG_ENABLE</name>
|
|
<description>Flash Programming Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE9</name>
|
|
<description>Flash Memory Protection Program Enable 9</description>
|
|
<addressOffset>0x00001424</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPPE9_PROG_ENABLE</name>
|
|
<description>Flash Programming Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE10</name>
|
|
<description>Flash Memory Protection Program Enable 10</description>
|
|
<addressOffset>0x00001428</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPPE10_PROG_ENABLE</name>
|
|
<description>Flash Programming Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE11</name>
|
|
<description>Flash Memory Protection Program Enable 11</description>
|
|
<addressOffset>0x0000142C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPPE11_PROG_ENABLE</name>
|
|
<description>Flash Programming Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE12</name>
|
|
<description>Flash Memory Protection Program Enable 12</description>
|
|
<addressOffset>0x00001430</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPPE12_PROG_ENABLE</name>
|
|
<description>Flash Programming Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE13</name>
|
|
<description>Flash Memory Protection Program Enable 13</description>
|
|
<addressOffset>0x00001434</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPPE13_PROG_ENABLE</name>
|
|
<description>Flash Programming Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE14</name>
|
|
<description>Flash Memory Protection Program Enable 14</description>
|
|
<addressOffset>0x00001438</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPPE14_PROG_ENABLE</name>
|
|
<description>Flash Programming Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE15</name>
|
|
<description>Flash Memory Protection Program Enable 15</description>
|
|
<addressOffset>0x0000143C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMPPE15_PROG_ENABLE</name>
|
|
<description>Flash Programming Enable</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SYSCTL</name>
|
|
<description>Register map for SYSCTL peripheral</description>
|
|
<groupName>SYSCTL</groupName>
|
|
<prependToName>SYSCTL</prependToName>
|
|
<baseAddress>0x400FE000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>SYSCTL</name><value>28</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DID0</name>
|
|
<description>Device Identification 0</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DID0_MIN</name>
|
|
<description>Minor Revision</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MIN_0</name>
|
|
<description>Initial device, or a major revision update</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MIN_1</name>
|
|
<description>First metal layer change</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MIN_2</name>
|
|
<description>Second metal layer change</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID0_MAJ</name>
|
|
<description>Major Revision</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MAJ_REVA</name>
|
|
<description>Revision A (initial device)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MAJ_REVB</name>
|
|
<description>Revision B (first base layer revision)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MAJ_REVC</name>
|
|
<description>Revision C (second base layer revision)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID0_CLASS</name>
|
|
<description>Device Class</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_CLASS_MSP432E4</name>
|
|
<description>MSP432E4 class microcontrollers</description>
|
|
<value>0xc</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID0_VER</name>
|
|
<description>DID0 Version</description>
|
|
<bitRange>[30:28]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_VER_1</name>
|
|
<description>Second version of the DID0 register format.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DID1</name>
|
|
<description>Device Identification 1</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DID1_QUAL</name>
|
|
<description>Qualification Status</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_QUAL_ES</name>
|
|
<description>Engineering Sample (unqualified)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_QUAL_PP</name>
|
|
<description>Pilot Production (unqualified)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_QUAL_FQ</name>
|
|
<description>Fully Qualified</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_ROHS</name>
|
|
<description>RoHS-Compliance</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_PKG</name>
|
|
<description>Package Type</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_PKG_QFP</name>
|
|
<description>QFP package</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_PKG_BGA</name>
|
|
<description>BGA package</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_TEMP</name>
|
|
<description>Temperature Range</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_TEMP_C</name>
|
|
<description>Commercial temperature range</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_TEMP_I</name>
|
|
<description>Industrial temperature range</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_TEMP_E</name>
|
|
<description>Extended temperature range</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_PINCNT</name>
|
|
<description>Package Pin Count</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_PINCNT_128</name>
|
|
<description>128-pin TQFP package</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_PINCNT_212</name>
|
|
<description>212-pin BGA package</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_PRTNO</name>
|
|
<description>Part Number</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_FAM</name>
|
|
<description>Family</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_VER</name>
|
|
<description>DID1 Version</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTBOCTL</name>
|
|
<description>Power-Temp Brown Out Control</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PTBOCTL_VDD_UBOR</name>
|
|
<description>VDD (VDDS) under BOR Event Action</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PTBOCTL_VDD_UBOR_NONE</name>
|
|
<description>No Action</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PTBOCTL_VDD_UBOR_SYSINT</name>
|
|
<description>System control interrupt</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PTBOCTL_VDD_UBOR_NMI</name>
|
|
<description>NMI</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PTBOCTL_VDD_UBOR_RST</name>
|
|
<description>Reset</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PTBOCTL_VDDA_UBOR</name>
|
|
<description>VDDA under BOR Event Action</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PTBOCTL_VDDA_UBOR_NONE</name>
|
|
<description>No Action</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT</name>
|
|
<description>System control interrupt</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PTBOCTL_VDDA_UBOR_NMI</name>
|
|
<description>NMI</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PTBOCTL_VDDA_UBOR_RST</name>
|
|
<description>Reset</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>Raw Interrupt Status</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RIS_BORRIS</name>
|
|
<description>Brown-Out Reset Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RIS_MOFRIS</name>
|
|
<description>Main Oscillator Failure Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RIS_PLLLRIS</name>
|
|
<description>PLL Lock Raw Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RIS_MOSCPUPRIS</name>
|
|
<description>MOSC Power Up Raw Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMC</name>
|
|
<description>Interrupt Mask Control</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_IMC_BORIM</name>
|
|
<description>Brown-Out Reset Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_IMC_MOFIM</name>
|
|
<description>Main Oscillator Failure Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_IMC_PLLLIM</name>
|
|
<description>PLL Lock Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_IMC_MOSCPUPIM</name>
|
|
<description>MOSC Power Up Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC</name>
|
|
<description>Masked Interrupt Status and Clear</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_MISC_BORMIS</name>
|
|
<description>BOR Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MISC_MOFMIS</name>
|
|
<description>Main Oscillator Failure Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MISC_PLLLMIS</name>
|
|
<description>PLL Lock Masked Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MISC_MOSCPUPMIS</name>
|
|
<description>MOSC Power Up Masked Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESC</name>
|
|
<description>Reset Cause</description>
|
|
<addressOffset>0x0000005C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RESC_EXT</name>
|
|
<description>External Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_POR</name>
|
|
<description>Power-On Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_BOR</name>
|
|
<description>Brown-Out Reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_WDT0</name>
|
|
<description>Watchdog Timer 0 Reset</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_SW</name>
|
|
<description>Software Reset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_WDT1</name>
|
|
<description>Watchdog Timer 1 Reset</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_HIB</name>
|
|
<description>HIB Reset</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_HSSR</name>
|
|
<description>HSSR Reset</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_MOSCFAIL</name>
|
|
<description>MOSC Failure Reset</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWRTC</name>
|
|
<description>Power-Temperature Cause</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PWRTC_VDD_UBOR</name>
|
|
<description>VDD Under BOR Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PWRTC_VDDA_UBOR</name>
|
|
<description>VDDA Under BOR Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMIC</name>
|
|
<description>NMI Cause Register</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_NMIC_EXTERNAL</name>
|
|
<description>External Pin NMI</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_NMIC_POWER</name>
|
|
<description>Power/Brown Out Event NMI</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_NMIC_WDT0</name>
|
|
<description>Watch Dog Timer (WDT) 0 NMI</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_NMIC_WDT1</name>
|
|
<description>Watch Dog Timer (WDT) 1 NMI</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_NMIC_TAMPER</name>
|
|
<description>Tamper Event NMI</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_NMIC_MOSCFAIL</name>
|
|
<description>MOSC Failure NMI</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOSCCTL</name>
|
|
<description>Main Oscillator Control</description>
|
|
<addressOffset>0x0000007C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_MOSCCTL_CVAL</name>
|
|
<description>Clock Validation for MOSC</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MOSCCTL_MOSCIM</name>
|
|
<description>MOSC Failure Action</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MOSCCTL_NOXTAL</name>
|
|
<description>No Crystal Connected</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MOSCCTL_PWRDN</name>
|
|
<description>Power Down</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MOSCCTL_OSCRNG</name>
|
|
<description>Oscillator Range</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSCLKCFG</name>
|
|
<description>Run and Sleep Mode Configuration Register</description>
|
|
<addressOffset>0x000000B0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RSCLKCFG_PSYSDIV</name>
|
|
<description>PLL System Clock Divisor</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RSCLKCFG_OSYSDIV</name>
|
|
<description>Oscillator System Clock Divisor</description>
|
|
<bitRange>[19:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RSCLKCFG_OSCSRC</name>
|
|
<description>Oscillator Source</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RSCLKCFG_OSCSRC_PIOSC</name>
|
|
<description>PIOSC is oscillator source</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RSCLKCFG_OSCSRC_LFIOSC</name>
|
|
<description>LFIOSC is oscillator source</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RSCLKCFG_OSCSRC_MOSC</name>
|
|
<description>MOSC is oscillator source</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RSCLKCFG_OSCSRC_RTC</name>
|
|
<description>Hibernation Module RTC Oscillator (RTCOSC)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RSCLKCFG_PLLSRC</name>
|
|
<description>PLL Source</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RSCLKCFG_PLLSRC_PIOSC</name>
|
|
<description>PIOSC is PLL input clock source</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RSCLKCFG_PLLSRC_MOSC</name>
|
|
<description>MOSC is the PLL input clock source</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RSCLKCFG_USEPLL</name>
|
|
<description>Use PLL</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RSCLKCFG_ACG</name>
|
|
<description>Auto Clock Gating</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RSCLKCFG_NEWFREQ</name>
|
|
<description>New PLLFREQ Accept</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RSCLKCFG_MEMTIMU</name>
|
|
<description>Memory Timing Register Update</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEMTIM0</name>
|
|
<description>Memory Timing Parameter Register 0 for Main Flash and EEPROM</description>
|
|
<addressOffset>0x000000C0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_MEMTIM0_FWS</name>
|
|
<description>Flash Wait State</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED0</name>
|
|
<description>Value of this reserved bit must be read as 1</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MEMTIM0_FBCE</name>
|
|
<description>Flash Bank Clock Edge</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MEMTIM0_FBCHT</name>
|
|
<description>Flash Bank Clock High Time</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_FBCHT_0_5</name>
|
|
<description>1/2 system clock period</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_FBCHT_1</name>
|
|
<description>1 system clock period</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_FBCHT_1_5</name>
|
|
<description>1.5 system clock periods</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_FBCHT_2</name>
|
|
<description>2 system clock periods</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_FBCHT_2_5</name>
|
|
<description>2.5 system clock periods</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_FBCHT_3</name>
|
|
<description>3 system clock periods</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_FBCHT_3_5</name>
|
|
<description>3.5 system clock periods</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_FBCHT_4</name>
|
|
<description>4 system clock periods</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_FBCHT_4_5</name>
|
|
<description>4.5 system clock periods</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MEMTIM0_EWS</name>
|
|
<description>EEPROM Wait States</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED1</name>
|
|
<description>Value of this reserved bit must be read as 1</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MEMTIM0_EBCE</name>
|
|
<description>EEPROM Bank Clock Edge</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MEMTIM0_EBCHT</name>
|
|
<description>EEPROM Clock High Time</description>
|
|
<bitRange>[25:22]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_EBCHT_0_5</name>
|
|
<description>1/2 system clock period</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_EBCHT_1</name>
|
|
<description>1 system clock period</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_EBCHT_1_5</name>
|
|
<description>1.5 system clock periods</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_EBCHT_2</name>
|
|
<description>2 system clock periods</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_EBCHT_2_5</name>
|
|
<description>2.5 system clock periods</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_EBCHT_3</name>
|
|
<description>3 system clock periods</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_EBCHT_3_5</name>
|
|
<description>3.5 system clock periods</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_EBCHT_4</name>
|
|
<description>4 system clock periods</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_MEMTIM0_EBCHT_4_5</name>
|
|
<description>4.5 system clock periods</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTCLKCFG</name>
|
|
<description>Alternate Clock Configuration</description>
|
|
<addressOffset>0x00000138</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_ALTCLKCFG_ALTCLK</name>
|
|
<description>Alternate Clock Source</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_ALTCLKCFG_ALTCLK_PIOSC</name>
|
|
<description>PIOSC</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC</name>
|
|
<description>Hibernation Module Real-time clock output (RTCOSC)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC</name>
|
|
<description>Low-frequency internal oscillator (LFIOSC)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSCLKCFG</name>
|
|
<description>Deep Sleep Clock Configuration Register</description>
|
|
<addressOffset>0x00000144</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DSCLKCFG_DSSYSDIV</name>
|
|
<description>Deep Sleep Clock Divisor</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DSCLKCFG_DSOSCSRC</name>
|
|
<description>Deep Sleep Oscillator Source</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC</name>
|
|
<description>PIOSC</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC</name>
|
|
<description>LFIOSC</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DSCLKCFG_DSOSCSRC_MOSC</name>
|
|
<description>MOSC</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DSCLKCFG_DSOSCSRC_RTC</name>
|
|
<description>Hibernation Module RTCOSC</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DSCLKCFG_MOSCDPD</name>
|
|
<description>MOSC Disable Power Down</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DSCLKCFG_PIOSCPD</name>
|
|
<description>PIOSC Power Down</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIVSCLK</name>
|
|
<description>Divisor and Source Clock Configuration</description>
|
|
<addressOffset>0x00000148</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DIVSCLK_DIV</name>
|
|
<description>Divisor Value</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DIVSCLK_SRC</name>
|
|
<description>Clock Source</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DIVSCLK_SRC_SYSCLK</name>
|
|
<description>System Clock</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DIVSCLK_SRC_PIOSC</name>
|
|
<description>PIOSC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DIVSCLK_SRC_MOSC</name>
|
|
<description>MOSC</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DIVSCLK_EN</name>
|
|
<description>DIVSCLK Enable</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPROP</name>
|
|
<description>System Properties</description>
|
|
<addressOffset>0x0000014C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SYSPROP_FPU</name>
|
|
<description>FPU Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIOSCCAL</name>
|
|
<description>Precision Internal Oscillator Calibration</description>
|
|
<addressOffset>0x00000150</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PIOSCCAL_UT</name>
|
|
<description>User Trim Value</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PIOSCCAL_UPDATE</name>
|
|
<description>Update Trim</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PIOSCCAL_CAL</name>
|
|
<description>Start Calibration</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PIOSCCAL_UTEN</name>
|
|
<description>Use User Trim Value</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIOSCSTAT</name>
|
|
<description>Precision Internal Oscillator Statistics</description>
|
|
<addressOffset>0x00000154</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PIOSCSTAT_CT</name>
|
|
<description>Calibration Trim Value</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PIOSCSTAT_CR</name>
|
|
<description>Calibration Result</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PIOSCSTAT_CRNONE</name>
|
|
<description>Calibration has not been attempted</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PIOSCSTAT_CRPASS</name>
|
|
<description>The last calibration operation completed to meet 1% accuracy</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PIOSCSTAT_CRFAIL</name>
|
|
<description>The last calibration operation failed to meet 1% accuracy</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PIOSCSTAT_DT</name>
|
|
<description>Default Trim Value</description>
|
|
<bitRange>[22:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLFREQ0</name>
|
|
<description>PLL Frequency 0</description>
|
|
<addressOffset>0x00000160</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PLLFREQ0_MINT</name>
|
|
<description>PLL M Integer Value</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PLLFREQ0_MFRAC</name>
|
|
<description>PLL M Fractional Value</description>
|
|
<bitRange>[19:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PLLFREQ0_PLLPWR</name>
|
|
<description>PLL Power</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLFREQ1</name>
|
|
<description>PLL Frequency 1</description>
|
|
<addressOffset>0x00000164</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PLLFREQ1_N</name>
|
|
<description>PLL N Value</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PLLFREQ1_Q</name>
|
|
<description>PLL Q Value</description>
|
|
<bitRange>[12:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLSTAT</name>
|
|
<description>PLL Status</description>
|
|
<addressOffset>0x00000168</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PLLSTAT_LOCK</name>
|
|
<description>PLL Lock</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SLPPWRCFG</name>
|
|
<description>Sleep Power Configuration</description>
|
|
<addressOffset>0x00000188</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SLPPWRCFG_SRAMPM</name>
|
|
<description>SRAM Power Modes</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_SLPPWRCFG_SRAMPM_NRM</name>
|
|
<description>Active Mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_SLPPWRCFG_SRAMPM_SBY</name>
|
|
<description>Standby Mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_SLPPWRCFG_SRAMPM_LP</name>
|
|
<description>Low Power Mode</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SLPPWRCFG_FLASHPM</name>
|
|
<description>Flash Power Modes</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_SLPPWRCFG_FLASHPM_NRM</name>
|
|
<description>Active Mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_SLPPWRCFG_FLASHPM_SLP</name>
|
|
<description>Low Power Mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSLPPWRCFG</name>
|
|
<description>Deep-Sleep Power Configuration</description>
|
|
<addressOffset>0x0000018C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DSLPPWRCFG_SRAMPM</name>
|
|
<description>SRAM Power Modes</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DSLPPWRCFG_SRAMPM_NRM</name>
|
|
<description>Active Mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DSLPPWRCFG_SRAMPM_SBY</name>
|
|
<description>Standby Mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DSLPPWRCFG_SRAMPM_LP</name>
|
|
<description>Low Power Mode</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DSLPPWRCFG_FLASHPM</name>
|
|
<description>Flash Power Modes</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DSLPPWRCFG_FLASHPM_NRM</name>
|
|
<description>Active Mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DSLPPWRCFG_FLASHPM_SLP</name>
|
|
<description>Low Power Mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DSLPPWRCFG_TSPD</name>
|
|
<description>Temperature Sense Power Down</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DSLPPWRCFG_LDOSM</name>
|
|
<description>LDO Sleep Mode</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVMSTAT</name>
|
|
<description>Non-Volatile Memory Information</description>
|
|
<addressOffset>0x000001A0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_NVMSTAT_FWB</name>
|
|
<description>32 Word Flash Write Buffer Available</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LDOSPCTL</name>
|
|
<description>LDO Sleep Power Control</description>
|
|
<addressOffset>0x000001B4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_LDOSPCTL_VLDO</name>
|
|
<description>LDO Output Voltage</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOSPCTL_VLDO_0_90V</name>
|
|
<description>0.90 V</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOSPCTL_VLDO_0_95V</name>
|
|
<description>0.95 V</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOSPCTL_VLDO_1_00V</name>
|
|
<description>1.00 V</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOSPCTL_VLDO_1_05V</name>
|
|
<description>1.05 V</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOSPCTL_VLDO_1_10V</name>
|
|
<description>1.10 V</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOSPCTL_VLDO_1_15V</name>
|
|
<description>1.15 V</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOSPCTL_VLDO_1_20V</name>
|
|
<description>1.20 V</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_LDOSPCTL_VADJEN</name>
|
|
<description>Voltage Adjust Enable</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LDODPCTL</name>
|
|
<description>LDO Deep-Sleep Power Control</description>
|
|
<addressOffset>0x000001BC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_LDODPCTL_VLDO</name>
|
|
<description>LDO Output Voltage</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDODPCTL_VLDO_0_90V</name>
|
|
<description>0.90 V</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDODPCTL_VLDO_0_95V</name>
|
|
<description>0.95 V</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDODPCTL_VLDO_1_00V</name>
|
|
<description>1.00 V</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDODPCTL_VLDO_1_05V</name>
|
|
<description>1.05 V</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDODPCTL_VLDO_1_10V</name>
|
|
<description>1.10 V</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDODPCTL_VLDO_1_15V</name>
|
|
<description>1.15 V</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDODPCTL_VLDO_1_20V</name>
|
|
<description>1.20 V</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDODPCTL_VLDO_1_25V</name>
|
|
<description>1.25 V</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDODPCTL_VLDO_1_30V</name>
|
|
<description>1.30 V</description>
|
|
<value>0x1a</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDODPCTL_VLDO_1_35V</name>
|
|
<description>1.35 V</description>
|
|
<value>0x1b</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_LDODPCTL_VADJEN</name>
|
|
<description>Voltage Adjust Enable</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESBEHAVCTL</name>
|
|
<description>Reset Behavior Control Register</description>
|
|
<addressOffset>0x000001D8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RESBEHAVCTL_EXTRES</name>
|
|
<description>External RST Pin Operation</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RESBEHAVCTL_EXTRES_SYSRST</name>
|
|
<description>External RST assertion issues a system reset. The application starts within 10 us</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RESBEHAVCTL_EXTRES_POR</name>
|
|
<description>External RST assertion issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESBEHAVCTL_BOR</name>
|
|
<description>BOR Reset operation</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RESBEHAVCTL_BOR_SYSRST</name>
|
|
<description>Brown Out Reset issues system reset. The application starts within 10 us</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RESBEHAVCTL_BOR_POR</name>
|
|
<description>Brown Out Reset issues a simulated POR sequence. The application starts less than 500 us after deassertion (Default)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESBEHAVCTL_WDOG0</name>
|
|
<description>Watchdog 0 Reset Operation</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RESBEHAVCTL_WDOG0_SYSRST</name>
|
|
<description>Watchdog 0 issues a system reset. The application starts within 10 us</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RESBEHAVCTL_WDOG0_POR</name>
|
|
<description>Watchdog 0 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESBEHAVCTL_WDOG1</name>
|
|
<description>Watchdog 1 Reset Operation</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RESBEHAVCTL_WDOG1_SYSRST</name>
|
|
<description>Watchdog 1 issues a system reset. The application starts within 10 us</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RESBEHAVCTL_WDOG1_POR</name>
|
|
<description>Watchdog 1 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HSSR</name>
|
|
<description>Hardware System Service Request</description>
|
|
<addressOffset>0x000001F4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_HSSR_CDOFF</name>
|
|
<description>Command Descriptor Pointer</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_HSSR_KEY</name>
|
|
<description>Write Key</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBPDS</name>
|
|
<description>USB Power Domain Status</description>
|
|
<addressOffset>0x00000280</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_USBPDS_PWRSTAT</name>
|
|
<description>Power Domain Status</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_USBPDS_PWRSTAT_OFF</name>
|
|
<description>OFF</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_USBPDS_PWRSTAT_ON</name>
|
|
<description>ON</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_USBPDS_MEMSTAT</name>
|
|
<description>Memory Array Power Status</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_USBPDS_MEMSTAT_OFF</name>
|
|
<description>Array OFF</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_USBPDS_MEMSTAT_RETAIN</name>
|
|
<description>SRAM Retention</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_USBPDS_MEMSTAT_ON</name>
|
|
<description>Array On</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBMPC</name>
|
|
<description>USB Memory Power Control</description>
|
|
<addressOffset>0x00000284</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_USBMPC_PWRCTL</name>
|
|
<description>Memory Array Power Control</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_USBMPC_PWRCTL_OFF</name>
|
|
<description>Array OFF</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_USBMPC_PWRCTL_RETAIN</name>
|
|
<description>SRAM Retention</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_USBMPC_PWRCTL_ON</name>
|
|
<description>Array On</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMACPDS</name>
|
|
<description>Ethernet MAC Power Domain Status</description>
|
|
<addressOffset>0x00000288</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_EMACPDS_PWRSTAT</name>
|
|
<description>Power Domain Status</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_EMACPDS_PWRSTAT_OFF</name>
|
|
<description>OFF</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_EMACPDS_PWRSTAT_ON</name>
|
|
<description>ON</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_EMACPDS_MEMSTAT</name>
|
|
<description>Memory Array Power Status</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_EMACPDS_MEMSTAT_OFF</name>
|
|
<description>Array OFF</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_EMACPDS_MEMSTAT_ON</name>
|
|
<description>Array On</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMACMPC</name>
|
|
<description>Ethernet MAC Memory Power Control</description>
|
|
<addressOffset>0x0000028C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_EMACMPC_PWRCTL</name>
|
|
<description>Memory Array Power Control</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_EMACMPC_PWRCTL_OFF</name>
|
|
<description>Array OFF</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_EMACMPC_PWRCTL_ON</name>
|
|
<description>Array On</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPWD</name>
|
|
<description>Watchdog Timer Peripheral Present</description>
|
|
<addressOffset>0x00000300</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPWD_P0</name>
|
|
<description>Watchdog Timer 0 Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPWD_P1</name>
|
|
<description>Watchdog Timer 1 Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPTIMER</name>
|
|
<description>16/32-Bit General-Purpose Timer Peripheral Present</description>
|
|
<addressOffset>0x00000304</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPTIMER_P0</name>
|
|
<description>16/32-Bit General-Purpose Timer 0 Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPTIMER_P1</name>
|
|
<description>16/32-Bit General-Purpose Timer 1 Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPTIMER_P2</name>
|
|
<description>16/32-Bit General-Purpose Timer 2 Present</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPTIMER_P3</name>
|
|
<description>16/32-Bit General-Purpose Timer 3 Present</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPTIMER_P4</name>
|
|
<description>16/32-Bit General-Purpose Timer 4 Present</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPTIMER_P5</name>
|
|
<description>16/32-Bit General-Purpose Timer 5 Present</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPTIMER_P6</name>
|
|
<description>16/32-Bit General-Purpose Timer 6 Present</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPTIMER_P7</name>
|
|
<description>16/32-Bit General-Purpose Timer 7 Present</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPGPIO</name>
|
|
<description>General-Purpose Input/Output Peripheral Present</description>
|
|
<addressOffset>0x00000308</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P0</name>
|
|
<description>GPIO Port A Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P1</name>
|
|
<description>GPIO Port B Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P2</name>
|
|
<description>GPIO Port C Present</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P3</name>
|
|
<description>GPIO Port D Present</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P4</name>
|
|
<description>GPIO Port E Present</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P5</name>
|
|
<description>GPIO Port F Present</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P6</name>
|
|
<description>GPIO Port G Present</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P7</name>
|
|
<description>GPIO Port H Present</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P8</name>
|
|
<description>GPIO Port J Present</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P9</name>
|
|
<description>GPIO Port K Present</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P10</name>
|
|
<description>GPIO Port L Present</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P11</name>
|
|
<description>GPIO Port M Present</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P12</name>
|
|
<description>GPIO Port N Present</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P13</name>
|
|
<description>GPIO Port P Present</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPGPIO_P14</name>
|
|
<description>GPIO Port Q Present</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPDMA</name>
|
|
<description>Micro Direct Memory Access Peripheral Present</description>
|
|
<addressOffset>0x0000030C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPDMA_P0</name>
|
|
<description>uDMA Module Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPEPI</name>
|
|
<description>EPI Peripheral Present</description>
|
|
<addressOffset>0x00000310</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPEPI_P0</name>
|
|
<description>EPI Module Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPHIB</name>
|
|
<description>Hibernation Peripheral Present</description>
|
|
<addressOffset>0x00000314</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPHIB_P0</name>
|
|
<description>Hibernation Module Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPUART</name>
|
|
<description>Universal Asynchronous Receiver/Transmitter Peripheral Present</description>
|
|
<addressOffset>0x00000318</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPUART_P0</name>
|
|
<description>UART Module 0 Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPUART_P1</name>
|
|
<description>UART Module 1 Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPUART_P2</name>
|
|
<description>UART Module 2 Present</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPUART_P3</name>
|
|
<description>UART Module 3 Present</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPUART_P4</name>
|
|
<description>UART Module 4 Present</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPUART_P5</name>
|
|
<description>UART Module 5 Present</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPUART_P6</name>
|
|
<description>UART Module 6 Present</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPUART_P7</name>
|
|
<description>UART Module 7 Present</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPSSI</name>
|
|
<description>Synchronous Serial Interface Peripheral Present</description>
|
|
<addressOffset>0x0000031C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPSSI_P0</name>
|
|
<description>SSI Module 0 Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPSSI_P1</name>
|
|
<description>SSI Module 1 Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPSSI_P2</name>
|
|
<description>SSI Module 2 Present</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPSSI_P3</name>
|
|
<description>SSI Module 3 Present</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPI2C</name>
|
|
<description>Inter-Integrated Circuit Peripheral Present</description>
|
|
<addressOffset>0x00000320</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPI2C_P0</name>
|
|
<description>I2C Module 0 Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPI2C_P1</name>
|
|
<description>I2C Module 1 Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPI2C_P2</name>
|
|
<description>I2C Module 2 Present</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPI2C_P3</name>
|
|
<description>I2C Module 3 Present</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPI2C_P4</name>
|
|
<description>I2C Module 4 Present</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPI2C_P5</name>
|
|
<description>I2C Module 5 Present</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPI2C_P6</name>
|
|
<description>I2C Module 6 Present</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPI2C_P7</name>
|
|
<description>I2C Module 7 Present</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPI2C_P8</name>
|
|
<description>I2C Module 8 Present</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPI2C_P9</name>
|
|
<description>I2C Module 9 Present</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPUSB</name>
|
|
<description>Universal Serial Bus Peripheral Present</description>
|
|
<addressOffset>0x00000328</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPUSB_P0</name>
|
|
<description>USB Module Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPEPHY</name>
|
|
<description>Ethernet PHY Peripheral Present</description>
|
|
<addressOffset>0x00000330</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPEPHY_P0</name>
|
|
<description>Ethernet PHY Module Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPCAN</name>
|
|
<description>Controller Area Network Peripheral Present</description>
|
|
<addressOffset>0x00000334</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPCAN_P0</name>
|
|
<description>CAN Module 0 Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPCAN_P1</name>
|
|
<description>CAN Module 1 Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPADC</name>
|
|
<description>Analog-to-Digital Converter Peripheral Present</description>
|
|
<addressOffset>0x00000338</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPADC_P0</name>
|
|
<description>ADC Module 0 Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PPADC_P1</name>
|
|
<description>ADC Module 1 Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPACMP</name>
|
|
<description>Analog Comparator Peripheral Present</description>
|
|
<addressOffset>0x0000033C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPACMP_P0</name>
|
|
<description>Analog Comparator Module Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPPWM</name>
|
|
<description>Pulse Width Modulator Peripheral Present</description>
|
|
<addressOffset>0x00000340</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPPWM_P0</name>
|
|
<description>PWM Module 0 Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPQEI</name>
|
|
<description>Quadrature Encoder Interface Peripheral Present</description>
|
|
<addressOffset>0x00000344</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPQEI_P0</name>
|
|
<description>QEI Module 0 Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPEEPROM</name>
|
|
<description>EEPROM Peripheral Present</description>
|
|
<addressOffset>0x00000358</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPEEPROM_P0</name>
|
|
<description>EEPROM Module Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPCCM</name>
|
|
<description>CRC and Cryptographic Modules Peripheral Present</description>
|
|
<addressOffset>0x00000374</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPCCM_P0</name>
|
|
<description>CRC and Cryptographic Modules Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPLCD</name>
|
|
<description>LCD Peripheral Present</description>
|
|
<addressOffset>0x00000390</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPLCD_P0</name>
|
|
<description>LCD Module Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPOWIRE</name>
|
|
<description>1-Wire Peripheral Present</description>
|
|
<addressOffset>0x00000398</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPOWIRE_P0</name>
|
|
<description>1-Wire Module Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPEMAC</name>
|
|
<description>Ethernet MAC Peripheral Present</description>
|
|
<addressOffset>0x0000039C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PPEMAC_P0</name>
|
|
<description>Ethernet Controller Module Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRWD</name>
|
|
<description>Watchdog Timer Software Reset</description>
|
|
<addressOffset>0x00000500</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRWD_R0</name>
|
|
<description>Watchdog Timer 0 Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRWD_R1</name>
|
|
<description>Watchdog Timer 1 Software Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRTIMER</name>
|
|
<description>16/32-Bit General-Purpose Timer Software Reset</description>
|
|
<addressOffset>0x00000504</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRTIMER_R0</name>
|
|
<description>16/32-Bit General-Purpose Timer 0 Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRTIMER_R1</name>
|
|
<description>16/32-Bit General-Purpose Timer 1 Software Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRTIMER_R2</name>
|
|
<description>16/32-Bit General-Purpose Timer 2 Software Reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRTIMER_R3</name>
|
|
<description>16/32-Bit General-Purpose Timer 3 Software Reset</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRTIMER_R4</name>
|
|
<description>16/32-Bit General-Purpose Timer 4 Software Reset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRTIMER_R5</name>
|
|
<description>16/32-Bit General-Purpose Timer 5 Software Reset</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRTIMER_R6</name>
|
|
<description>16/32-Bit General-Purpose Timer 6 Software Reset</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRTIMER_R7</name>
|
|
<description>16/32-Bit General-Purpose Timer 7 Software Reset</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRGPIO</name>
|
|
<description>General-Purpose Input/Output Software Reset</description>
|
|
<addressOffset>0x00000508</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R0</name>
|
|
<description>GPIO Port A Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R1</name>
|
|
<description>GPIO Port B Software Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R2</name>
|
|
<description>GPIO Port C Software Reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R3</name>
|
|
<description>GPIO Port D Software Reset</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R4</name>
|
|
<description>GPIO Port E Software Reset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R5</name>
|
|
<description>GPIO Port F Software Reset</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R6</name>
|
|
<description>GPIO Port G Software Reset</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R7</name>
|
|
<description>GPIO Port H Software Reset</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R8</name>
|
|
<description>GPIO Port J Software Reset</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R9</name>
|
|
<description>GPIO Port K Software Reset</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R10</name>
|
|
<description>GPIO Port L Software Reset</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R11</name>
|
|
<description>GPIO Port M Software Reset</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R12</name>
|
|
<description>GPIO Port N Software Reset</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R13</name>
|
|
<description>GPIO Port P Software Reset</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRGPIO_R14</name>
|
|
<description>GPIO Port Q Software Reset</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRDMA</name>
|
|
<description>Micro Direct Memory Access Software Reset</description>
|
|
<addressOffset>0x0000050C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRDMA_R0</name>
|
|
<description>uDMA Module Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SREPI</name>
|
|
<description>EPI Software Reset</description>
|
|
<addressOffset>0x00000510</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SREPI_R0</name>
|
|
<description>EPI Module Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRHIB</name>
|
|
<description>Hibernation Software Reset</description>
|
|
<addressOffset>0x00000514</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRHIB_R0</name>
|
|
<description>Hibernation Module Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRUART</name>
|
|
<description>Universal Asynchronous Receiver/Transmitter Software Reset</description>
|
|
<addressOffset>0x00000518</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRUART_R0</name>
|
|
<description>UART Module 0 Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRUART_R1</name>
|
|
<description>UART Module 1 Software Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRUART_R2</name>
|
|
<description>UART Module 2 Software Reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRUART_R3</name>
|
|
<description>UART Module 3 Software Reset</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRUART_R4</name>
|
|
<description>UART Module 4 Software Reset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRUART_R5</name>
|
|
<description>UART Module 5 Software Reset</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRUART_R6</name>
|
|
<description>UART Module 6 Software Reset</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRUART_R7</name>
|
|
<description>UART Module 7 Software Reset</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRSSI</name>
|
|
<description>Synchronous Serial Interface Software Reset</description>
|
|
<addressOffset>0x0000051C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRSSI_R0</name>
|
|
<description>SSI Module 0 Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRSSI_R1</name>
|
|
<description>SSI Module 1 Software Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRSSI_R2</name>
|
|
<description>SSI Module 2 Software Reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRSSI_R3</name>
|
|
<description>SSI Module 3 Software Reset</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRI2C</name>
|
|
<description>Inter-Integrated Circuit Software Reset</description>
|
|
<addressOffset>0x00000520</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRI2C_R0</name>
|
|
<description>I2C Module 0 Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRI2C_R1</name>
|
|
<description>I2C Module 1 Software Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRI2C_R2</name>
|
|
<description>I2C Module 2 Software Reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRI2C_R3</name>
|
|
<description>I2C Module 3 Software Reset</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRI2C_R4</name>
|
|
<description>I2C Module 4 Software Reset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRI2C_R5</name>
|
|
<description>I2C Module 5 Software Reset</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRI2C_R6</name>
|
|
<description>I2C Module 6 Software Reset</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRI2C_R7</name>
|
|
<description>I2C Module 7 Software Reset</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRI2C_R8</name>
|
|
<description>I2C Module 8 Software Reset</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRI2C_R9</name>
|
|
<description>I2C Module 9 Software Reset</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRUSB</name>
|
|
<description>Universal Serial Bus Software Reset</description>
|
|
<addressOffset>0x00000528</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRUSB_R0</name>
|
|
<description>USB Module Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SREPHY</name>
|
|
<description>Ethernet PHY Software Reset</description>
|
|
<addressOffset>0x00000530</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SREPHY_R0</name>
|
|
<description>Ethernet PHY Module Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCAN</name>
|
|
<description>Controller Area Network Software Reset</description>
|
|
<addressOffset>0x00000534</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRCAN_R0</name>
|
|
<description>CAN Module 0 Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCAN_R1</name>
|
|
<description>CAN Module 1 Software Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRADC</name>
|
|
<description>Analog-to-Digital Converter Software Reset</description>
|
|
<addressOffset>0x00000538</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRADC_R0</name>
|
|
<description>ADC Module 0 Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRADC_R1</name>
|
|
<description>ADC Module 1 Software Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRACMP</name>
|
|
<description>Analog Comparator Software Reset</description>
|
|
<addressOffset>0x0000053C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRACMP_R0</name>
|
|
<description>Analog Comparator Module 0 Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRPWM</name>
|
|
<description>Pulse Width Modulator Software Reset</description>
|
|
<addressOffset>0x00000540</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRPWM_R0</name>
|
|
<description>PWM Module 0 Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRQEI</name>
|
|
<description>Quadrature Encoder Interface Software Reset</description>
|
|
<addressOffset>0x00000544</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRQEI_R0</name>
|
|
<description>QEI Module 0 Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SREEPROM</name>
|
|
<description>EEPROM Software Reset</description>
|
|
<addressOffset>0x00000558</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SREEPROM_R0</name>
|
|
<description>EEPROM Module Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCCM</name>
|
|
<description>CRC and Cryptographic Modules Software Reset</description>
|
|
<addressOffset>0x00000574</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRCCM_R0</name>
|
|
<description>CRC and Cryptographic Modules Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SREMAC</name>
|
|
<description>Ethernet MAC Software Reset</description>
|
|
<addressOffset>0x0000059C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SREMAC_R0</name>
|
|
<description>Ethernet Controller MAC Module 0 Software Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCWD</name>
|
|
<description>Watchdog Timer Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000600</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCWD_R0</name>
|
|
<description>Watchdog Timer 0 Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCWD_R1</name>
|
|
<description>Watchdog Timer 1 Run Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCTIMER</name>
|
|
<description>16/32-Bit General-Purpose Timer Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000604</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCTIMER_R0</name>
|
|
<description>16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCTIMER_R1</name>
|
|
<description>16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCTIMER_R2</name>
|
|
<description>16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCTIMER_R3</name>
|
|
<description>16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCTIMER_R4</name>
|
|
<description>16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCTIMER_R5</name>
|
|
<description>16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCTIMER_R6</name>
|
|
<description>16/32-Bit General-Purpose Timer 6 Run Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCTIMER_R7</name>
|
|
<description>16/32-Bit General-Purpose Timer 7 Run Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCGPIO</name>
|
|
<description>General-Purpose Input/Output Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000608</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R0</name>
|
|
<description>GPIO Port A Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R1</name>
|
|
<description>GPIO Port B Run Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R2</name>
|
|
<description>GPIO Port C Run Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R3</name>
|
|
<description>GPIO Port D Run Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R4</name>
|
|
<description>GPIO Port E Run Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R5</name>
|
|
<description>GPIO Port F Run Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R6</name>
|
|
<description>GPIO Port G Run Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R7</name>
|
|
<description>GPIO Port H Run Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R8</name>
|
|
<description>GPIO Port J Run Mode Clock Gating Control</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R9</name>
|
|
<description>GPIO Port K Run Mode Clock Gating Control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R10</name>
|
|
<description>GPIO Port L Run Mode Clock Gating Control</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R11</name>
|
|
<description>GPIO Port M Run Mode Clock Gating Control</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R12</name>
|
|
<description>GPIO Port N Run Mode Clock Gating Control</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R13</name>
|
|
<description>GPIO Port P Run Mode Clock Gating Control</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCGPIO_R14</name>
|
|
<description>GPIO Port Q Run Mode Clock Gating Control</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCDMA</name>
|
|
<description>Micro Direct Memory Access Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000060C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCDMA_R0</name>
|
|
<description>uDMA Module Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCEPI</name>
|
|
<description>EPI Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000610</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCEPI_R0</name>
|
|
<description>EPI Module Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCHIB</name>
|
|
<description>Hibernation Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000614</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCHIB_R0</name>
|
|
<description>Hibernation Module Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCUART</name>
|
|
<description>Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000618</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCUART_R0</name>
|
|
<description>UART Module 0 Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCUART_R1</name>
|
|
<description>UART Module 1 Run Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCUART_R2</name>
|
|
<description>UART Module 2 Run Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCUART_R3</name>
|
|
<description>UART Module 3 Run Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCUART_R4</name>
|
|
<description>UART Module 4 Run Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCUART_R5</name>
|
|
<description>UART Module 5 Run Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCUART_R6</name>
|
|
<description>UART Module 6 Run Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCUART_R7</name>
|
|
<description>UART Module 7 Run Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCSSI</name>
|
|
<description>Synchronous Serial Interface Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000061C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCSSI_R0</name>
|
|
<description>SSI Module 0 Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCSSI_R1</name>
|
|
<description>SSI Module 1 Run Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCSSI_R2</name>
|
|
<description>SSI Module 2 Run Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCSSI_R3</name>
|
|
<description>SSI Module 3 Run Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCI2C</name>
|
|
<description>Inter-Integrated Circuit Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000620</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCI2C_R0</name>
|
|
<description>I2C Module 0 Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCI2C_R1</name>
|
|
<description>I2C Module 1 Run Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCI2C_R2</name>
|
|
<description>I2C Module 2 Run Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCI2C_R3</name>
|
|
<description>I2C Module 3 Run Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCI2C_R4</name>
|
|
<description>I2C Module 4 Run Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCI2C_R5</name>
|
|
<description>I2C Module 5 Run Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCI2C_R6</name>
|
|
<description>I2C Module 6 Run Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCI2C_R7</name>
|
|
<description>I2C Module 7 Run Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCI2C_R8</name>
|
|
<description>I2C Module 8 Run Mode Clock Gating Control</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCI2C_R9</name>
|
|
<description>I2C Module 9 Run Mode Clock Gating Control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCUSB</name>
|
|
<description>Universal Serial Bus Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000628</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCUSB_R0</name>
|
|
<description>USB Module Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCEPHY</name>
|
|
<description>Ethernet PHY Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000630</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCEPHY_R0</name>
|
|
<description>Ethernet PHY Module Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCCAN</name>
|
|
<description>Controller Area Network Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000634</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCCAN_R0</name>
|
|
<description>CAN Module 0 Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCCAN_R1</name>
|
|
<description>CAN Module 1 Run Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCADC</name>
|
|
<description>Analog-to-Digital Converter Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000638</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCADC_R0</name>
|
|
<description>ADC Module 0 Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGCADC_R1</name>
|
|
<description>ADC Module 1 Run Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCACMP</name>
|
|
<description>Analog Comparator Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000063C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCACMP_R0</name>
|
|
<description>Analog Comparator Module 0 Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCPWM</name>
|
|
<description>Pulse Width Modulator Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000640</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCPWM_R0</name>
|
|
<description>PWM Module 0 Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCQEI</name>
|
|
<description>Quadrature Encoder Interface Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000644</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCQEI_R0</name>
|
|
<description>QEI Module 0 Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCEEPROM</name>
|
|
<description>EEPROM Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000658</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCEEPROM_R0</name>
|
|
<description>EEPROM Module Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCCCM</name>
|
|
<description>CRC and Cryptographic Modules Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000674</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCCCM_R0</name>
|
|
<description>CRC and Cryptographic Modules Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGCEMAC</name>
|
|
<description>Ethernet MAC Run Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000069C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGCEMAC_R0</name>
|
|
<description>Ethernet MAC Module 0 Run Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCWD</name>
|
|
<description>Watchdog Timer Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000700</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCWD_S0</name>
|
|
<description>Watchdog Timer 0 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCWD_S1</name>
|
|
<description>Watchdog Timer 1 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCTIMER</name>
|
|
<description>16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000704</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCTIMER_S0</name>
|
|
<description>16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCTIMER_S1</name>
|
|
<description>16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCTIMER_S2</name>
|
|
<description>16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCTIMER_S3</name>
|
|
<description>16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCTIMER_S4</name>
|
|
<description>16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCTIMER_S5</name>
|
|
<description>16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCTIMER_S6</name>
|
|
<description>16/32-Bit General-Purpose Timer 6 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCTIMER_S7</name>
|
|
<description>16/32-Bit General-Purpose Timer 7 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCGPIO</name>
|
|
<description>General-Purpose Input/Output Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000708</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S0</name>
|
|
<description>GPIO Port A Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S1</name>
|
|
<description>GPIO Port B Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S2</name>
|
|
<description>GPIO Port C Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S3</name>
|
|
<description>GPIO Port D Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S4</name>
|
|
<description>GPIO Port E Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S5</name>
|
|
<description>GPIO Port F Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S6</name>
|
|
<description>GPIO Port G Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S7</name>
|
|
<description>GPIO Port H Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S8</name>
|
|
<description>GPIO Port J Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S9</name>
|
|
<description>GPIO Port K Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S10</name>
|
|
<description>GPIO Port L Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S11</name>
|
|
<description>GPIO Port M Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S12</name>
|
|
<description>GPIO Port N Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S13</name>
|
|
<description>GPIO Port P Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCGPIO_S14</name>
|
|
<description>GPIO Port Q Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCDMA</name>
|
|
<description>Micro Direct Memory Access Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000070C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCDMA_S0</name>
|
|
<description>uDMA Module Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCEPI</name>
|
|
<description>EPI Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000710</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCEPI_S0</name>
|
|
<description>EPI Module Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCHIB</name>
|
|
<description>Hibernation Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000714</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCHIB_S0</name>
|
|
<description>Hibernation Module Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCUART</name>
|
|
<description>Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000718</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCUART_S0</name>
|
|
<description>UART Module 0 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCUART_S1</name>
|
|
<description>UART Module 1 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCUART_S2</name>
|
|
<description>UART Module 2 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCUART_S3</name>
|
|
<description>UART Module 3 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCUART_S4</name>
|
|
<description>UART Module 4 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCUART_S5</name>
|
|
<description>UART Module 5 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCUART_S6</name>
|
|
<description>UART Module 6 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCUART_S7</name>
|
|
<description>UART Module 7 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCSSI</name>
|
|
<description>Synchronous Serial Interface Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000071C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCSSI_S0</name>
|
|
<description>SSI Module 0 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCSSI_S1</name>
|
|
<description>SSI Module 1 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCSSI_S2</name>
|
|
<description>SSI Module 2 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCSSI_S3</name>
|
|
<description>SSI Module 3 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCI2C</name>
|
|
<description>Inter-Integrated Circuit Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000720</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCI2C_S0</name>
|
|
<description>I2C Module 0 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCI2C_S1</name>
|
|
<description>I2C Module 1 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCI2C_S2</name>
|
|
<description>I2C Module 2 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCI2C_S3</name>
|
|
<description>I2C Module 3 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCI2C_S4</name>
|
|
<description>I2C Module 4 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCI2C_S5</name>
|
|
<description>I2C Module 5 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCI2C_S6</name>
|
|
<description>I2C Module 6 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCI2C_S7</name>
|
|
<description>I2C Module 7 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCI2C_S8</name>
|
|
<description>I2C Module 8 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCI2C_S9</name>
|
|
<description>I2C Module 9 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCUSB</name>
|
|
<description>Universal Serial Bus Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000728</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCUSB_S0</name>
|
|
<description>USB Module Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCEPHY</name>
|
|
<description>Ethernet PHY Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000730</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCEPHY_S0</name>
|
|
<description>PHY Module Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCCAN</name>
|
|
<description>Controller Area Network Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000734</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCCAN_S0</name>
|
|
<description>CAN Module 0 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCCAN_S1</name>
|
|
<description>CAN Module 1 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCADC</name>
|
|
<description>Analog-to-Digital Converter Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000738</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCADC_S0</name>
|
|
<description>ADC Module 0 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGCADC_S1</name>
|
|
<description>ADC Module 1 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCACMP</name>
|
|
<description>Analog Comparator Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000073C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCACMP_S0</name>
|
|
<description>Analog Comparator Module 0 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCPWM</name>
|
|
<description>Pulse Width Modulator Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000740</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCPWM_S0</name>
|
|
<description>PWM Module 0 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCQEI</name>
|
|
<description>Quadrature Encoder Interface Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000744</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCQEI_S0</name>
|
|
<description>QEI Module 0 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCEEPROM</name>
|
|
<description>EEPROM Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000758</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCEEPROM_S0</name>
|
|
<description>EEPROM Module Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCCCM</name>
|
|
<description>CRC and Cryptographic Modules Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000774</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCCCM_S0</name>
|
|
<description>CRC and Cryptographic Modules Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGCEMAC</name>
|
|
<description>Ethernet MAC Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000079C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGCEMAC_S0</name>
|
|
<description>Ethernet MAC Module 0 Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCWD</name>
|
|
<description>Watchdog Timer Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000800</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCWD_D0</name>
|
|
<description>Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCWD_D1</name>
|
|
<description>Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCTIMER</name>
|
|
<description>16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000804</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCTIMER_D0</name>
|
|
<description>16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCTIMER_D1</name>
|
|
<description>16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCTIMER_D2</name>
|
|
<description>16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCTIMER_D3</name>
|
|
<description>16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCTIMER_D4</name>
|
|
<description>16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCTIMER_D5</name>
|
|
<description>16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCTIMER_D6</name>
|
|
<description>16/32-Bit General-Purpose Timer 6 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCTIMER_D7</name>
|
|
<description>16/32-Bit General-Purpose Timer 7 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCGPIO</name>
|
|
<description>General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000808</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D0</name>
|
|
<description>GPIO Port A Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D1</name>
|
|
<description>GPIO Port B Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D2</name>
|
|
<description>GPIO Port C Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D3</name>
|
|
<description>GPIO Port D Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D4</name>
|
|
<description>GPIO Port E Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D5</name>
|
|
<description>GPIO Port F Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D6</name>
|
|
<description>GPIO Port G Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D7</name>
|
|
<description>GPIO Port H Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D8</name>
|
|
<description>GPIO Port J Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D9</name>
|
|
<description>GPIO Port K Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D10</name>
|
|
<description>GPIO Port L Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D11</name>
|
|
<description>GPIO Port M Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D12</name>
|
|
<description>GPIO Port N Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D13</name>
|
|
<description>GPIO Port P Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCGPIO_D14</name>
|
|
<description>GPIO Port Q Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCDMA</name>
|
|
<description>Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000080C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCDMA_D0</name>
|
|
<description>uDMA Module Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCEPI</name>
|
|
<description>EPI Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000810</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCEPI_D0</name>
|
|
<description>EPI Module Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCHIB</name>
|
|
<description>Hibernation Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000814</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCHIB_D0</name>
|
|
<description>Hibernation Module Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCUART</name>
|
|
<description>Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000818</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCUART_D0</name>
|
|
<description>UART Module 0 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCUART_D1</name>
|
|
<description>UART Module 1 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCUART_D2</name>
|
|
<description>UART Module 2 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCUART_D3</name>
|
|
<description>UART Module 3 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCUART_D4</name>
|
|
<description>UART Module 4 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCUART_D5</name>
|
|
<description>UART Module 5 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCUART_D6</name>
|
|
<description>UART Module 6 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCUART_D7</name>
|
|
<description>UART Module 7 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCSSI</name>
|
|
<description>Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000081C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCSSI_D0</name>
|
|
<description>SSI Module 0 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCSSI_D1</name>
|
|
<description>SSI Module 1 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCSSI_D2</name>
|
|
<description>SSI Module 2 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCSSI_D3</name>
|
|
<description>SSI Module 3 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCI2C</name>
|
|
<description>Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000820</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCI2C_D0</name>
|
|
<description>I2C Module 0 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCI2C_D1</name>
|
|
<description>I2C Module 1 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCI2C_D2</name>
|
|
<description>I2C Module 2 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCI2C_D3</name>
|
|
<description>I2C Module 3 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCI2C_D4</name>
|
|
<description>I2C Module 4 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCI2C_D5</name>
|
|
<description>I2C Module 5 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCI2C_D6</name>
|
|
<description>I2C Module 6 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCI2C_D7</name>
|
|
<description>I2C Module 7 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCI2C_D8</name>
|
|
<description>I2C Module 8 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCI2C_D9</name>
|
|
<description>I2C Module 9 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCUSB</name>
|
|
<description>Universal Serial Bus Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000828</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCUSB_D0</name>
|
|
<description>USB Module Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCEPHY</name>
|
|
<description>Ethernet PHY Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000830</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCEPHY_D0</name>
|
|
<description>PHY Module Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCCAN</name>
|
|
<description>Controller Area Network Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000834</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCCAN_D0</name>
|
|
<description>CAN Module 0 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCCAN_D1</name>
|
|
<description>CAN Module 1 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCADC</name>
|
|
<description>Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000838</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCADC_D0</name>
|
|
<description>ADC Module 0 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGCADC_D1</name>
|
|
<description>ADC Module 1 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCACMP</name>
|
|
<description>Analog Comparator Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000083C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCACMP_D0</name>
|
|
<description>Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCPWM</name>
|
|
<description>Pulse Width Modulator Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000840</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCPWM_D0</name>
|
|
<description>PWM Module 0 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCQEI</name>
|
|
<description>Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000844</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCQEI_D0</name>
|
|
<description>QEI Module 0 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCEEPROM</name>
|
|
<description>EEPROM Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000858</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCEEPROM_D0</name>
|
|
<description>EEPROM Module Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCCCM</name>
|
|
<description>CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x00000874</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCCCM_D0</name>
|
|
<description>CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGCEMAC</name>
|
|
<description>Ethernet MAC Deep-Sleep Mode Clock Gating Control</description>
|
|
<addressOffset>0x0000089C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGCEMAC_D0</name>
|
|
<description>Ethernet MAC Module 0 Deep-Sleep Mode Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCWD</name>
|
|
<description>Watchdog Timer Power Control</description>
|
|
<addressOffset>0x00000900</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCWD_P0</name>
|
|
<description>Watchdog Timer 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCWD_P1</name>
|
|
<description>Watchdog Timer 1 Power Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCTIMER</name>
|
|
<description>16/32-Bit General-Purpose Timer Power Control</description>
|
|
<addressOffset>0x00000904</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCTIMER_P0</name>
|
|
<description>General-Purpose Timer 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCTIMER_P1</name>
|
|
<description>General-Purpose Timer 1 Power Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCTIMER_P2</name>
|
|
<description>General-Purpose Timer 2 Power Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCTIMER_P3</name>
|
|
<description>General-Purpose Timer 3 Power Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCTIMER_P4</name>
|
|
<description>General-Purpose Timer 4 Power Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCTIMER_P5</name>
|
|
<description>General-Purpose Timer 5 Power Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCTIMER_P6</name>
|
|
<description>General-Purpose Timer 6 Power Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCTIMER_P7</name>
|
|
<description>General-Purpose Timer 7 Power Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCGPIO</name>
|
|
<description>General-Purpose Input/Output Power Control</description>
|
|
<addressOffset>0x00000908</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P0</name>
|
|
<description>GPIO Port A Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P1</name>
|
|
<description>GPIO Port B Power Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P2</name>
|
|
<description>GPIO Port C Power Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P3</name>
|
|
<description>GPIO Port D Power Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P4</name>
|
|
<description>GPIO Port E Power Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P5</name>
|
|
<description>GPIO Port F Power Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P6</name>
|
|
<description>GPIO Port G Power Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P7</name>
|
|
<description>GPIO Port H Power Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P8</name>
|
|
<description>GPIO Port J Power Control</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P9</name>
|
|
<description>GPIO Port K Power Control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P10</name>
|
|
<description>GPIO Port L Power Control</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P11</name>
|
|
<description>GPIO Port M Power Control</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P12</name>
|
|
<description>GPIO Port N Power Control</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P13</name>
|
|
<description>GPIO Port P Power Control</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCGPIO_P14</name>
|
|
<description>GPIO Port Q Power Control</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCDMA</name>
|
|
<description>Micro Direct Memory Access Power Control</description>
|
|
<addressOffset>0x0000090C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCDMA_P0</name>
|
|
<description>uDMA Module Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCEPI</name>
|
|
<description>External Peripheral Interface Power Control</description>
|
|
<addressOffset>0x00000910</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCEPI_P0</name>
|
|
<description>EPI Module Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCHIB</name>
|
|
<description>Hibernation Power Control</description>
|
|
<addressOffset>0x00000914</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCHIB_P0</name>
|
|
<description>Hibernation Module Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCUART</name>
|
|
<description>Universal Asynchronous Receiver/Transmitter Power Control</description>
|
|
<addressOffset>0x00000918</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCUART_P0</name>
|
|
<description>UART Module 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCUART_P1</name>
|
|
<description>UART Module 1 Power Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCUART_P2</name>
|
|
<description>UART Module 2 Power Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCUART_P3</name>
|
|
<description>UART Module 3 Power Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCUART_P4</name>
|
|
<description>UART Module 4 Power Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCUART_P5</name>
|
|
<description>UART Module 5 Power Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCUART_P6</name>
|
|
<description>UART Module 6 Power Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCUART_P7</name>
|
|
<description>UART Module 7 Power Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCSSI</name>
|
|
<description>Synchronous Serial Interface Power Control</description>
|
|
<addressOffset>0x0000091C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCSSI_P0</name>
|
|
<description>SSI Module 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCSSI_P1</name>
|
|
<description>SSI Module 1 Power Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCSSI_P2</name>
|
|
<description>SSI Module 2 Power Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCSSI_P3</name>
|
|
<description>SSI Module 3 Power Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCI2C</name>
|
|
<description>Inter-Integrated Circuit Power Control</description>
|
|
<addressOffset>0x00000920</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCI2C_P0</name>
|
|
<description>I2C Module 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCI2C_P1</name>
|
|
<description>I2C Module 1 Power Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCI2C_P2</name>
|
|
<description>I2C Module 2 Power Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCI2C_P3</name>
|
|
<description>I2C Module 3 Power Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCI2C_P4</name>
|
|
<description>I2C Module 4 Power Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCI2C_P5</name>
|
|
<description>I2C Module 5 Power Control</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCI2C_P6</name>
|
|
<description>I2C Module 6 Power Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCI2C_P7</name>
|
|
<description>I2C Module 7 Power Control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCI2C_P8</name>
|
|
<description>I2C Module 8 Power Control</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCI2C_P9</name>
|
|
<description>I2C Module 9 Power Control</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCUSB</name>
|
|
<description>Universal Serial Bus Power Control</description>
|
|
<addressOffset>0x00000928</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCUSB_P0</name>
|
|
<description>USB Module Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCEPHY</name>
|
|
<description>Ethernet PHY Power Control</description>
|
|
<addressOffset>0x00000930</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCEPHY_P0</name>
|
|
<description>Ethernet PHY Module Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCCAN</name>
|
|
<description>Controller Area Network Power Control</description>
|
|
<addressOffset>0x00000934</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCCAN_P0</name>
|
|
<description>CAN Module 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCCAN_P1</name>
|
|
<description>CAN Module 1 Power Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCADC</name>
|
|
<description>Analog-to-Digital Converter Power Control</description>
|
|
<addressOffset>0x00000938</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCADC_P0</name>
|
|
<description>ADC Module 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PCADC_P1</name>
|
|
<description>ADC Module 1 Power Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCACMP</name>
|
|
<description>Analog Comparator Power Control</description>
|
|
<addressOffset>0x0000093C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCACMP_P0</name>
|
|
<description>Analog Comparator Module 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCPWM</name>
|
|
<description>Pulse Width Modulator Power Control</description>
|
|
<addressOffset>0x00000940</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCPWM_P0</name>
|
|
<description>PWM Module 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCQEI</name>
|
|
<description>Quadrature Encoder Interface Power Control</description>
|
|
<addressOffset>0x00000944</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCQEI_P0</name>
|
|
<description>QEI Module 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCEEPROM</name>
|
|
<description>EEPROM Power Control</description>
|
|
<addressOffset>0x00000958</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCEEPROM_P0</name>
|
|
<description>EEPROM Module 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCCCM</name>
|
|
<description>CRC and Cryptographic Modules Power Control</description>
|
|
<addressOffset>0x00000974</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCCCM_P0</name>
|
|
<description>CRC and Cryptographic Modules Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCEMAC</name>
|
|
<description>Ethernet MAC Power Control</description>
|
|
<addressOffset>0x0000099C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PCEMAC_P0</name>
|
|
<description>Ethernet MAC Module 0 Power Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRWD</name>
|
|
<description>Watchdog Timer Peripheral Ready</description>
|
|
<addressOffset>0x00000A00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRWD_R0</name>
|
|
<description>Watchdog Timer 0 Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRWD_R1</name>
|
|
<description>Watchdog Timer 1 Peripheral Ready</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRTIMER</name>
|
|
<description>16/32-Bit General-Purpose Timer Peripheral Ready</description>
|
|
<addressOffset>0x00000A04</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRTIMER_R0</name>
|
|
<description>16/32-Bit General-Purpose Timer 0 Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRTIMER_R1</name>
|
|
<description>16/32-Bit General-Purpose Timer 1 Peripheral Ready</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRTIMER_R2</name>
|
|
<description>16/32-Bit General-Purpose Timer 2 Peripheral Ready</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRTIMER_R3</name>
|
|
<description>16/32-Bit General-Purpose Timer 3 Peripheral Ready</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRTIMER_R4</name>
|
|
<description>16/32-Bit General-Purpose Timer 4 Peripheral Ready</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRTIMER_R5</name>
|
|
<description>16/32-Bit General-Purpose Timer 5 Peripheral Ready</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRTIMER_R6</name>
|
|
<description>16/32-Bit General-Purpose Timer 6 Peripheral Ready</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRTIMER_R7</name>
|
|
<description>16/32-Bit General-Purpose Timer 7 Peripheral Ready</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRGPIO</name>
|
|
<description>General-Purpose Input/Output Peripheral Ready</description>
|
|
<addressOffset>0x00000A08</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R0</name>
|
|
<description>GPIO Port A Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R1</name>
|
|
<description>GPIO Port B Peripheral Ready</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R2</name>
|
|
<description>GPIO Port C Peripheral Ready</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R3</name>
|
|
<description>GPIO Port D Peripheral Ready</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R4</name>
|
|
<description>GPIO Port E Peripheral Ready</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R5</name>
|
|
<description>GPIO Port F Peripheral Ready</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R6</name>
|
|
<description>GPIO Port G Peripheral Ready</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R7</name>
|
|
<description>GPIO Port H Peripheral Ready</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R8</name>
|
|
<description>GPIO Port J Peripheral Ready</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R9</name>
|
|
<description>GPIO Port K Peripheral Ready</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R10</name>
|
|
<description>GPIO Port L Peripheral Ready</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R11</name>
|
|
<description>GPIO Port M Peripheral Ready</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R12</name>
|
|
<description>GPIO Port N Peripheral Ready</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R13</name>
|
|
<description>GPIO Port P Peripheral Ready</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRGPIO_R14</name>
|
|
<description>GPIO Port Q Peripheral Ready</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRDMA</name>
|
|
<description>Micro Direct Memory Access Peripheral Ready</description>
|
|
<addressOffset>0x00000A0C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRDMA_R0</name>
|
|
<description>uDMA Module Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PREPI</name>
|
|
<description>EPI Peripheral Ready</description>
|
|
<addressOffset>0x00000A10</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PREPI_R0</name>
|
|
<description>EPI Module Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRHIB</name>
|
|
<description>Hibernation Peripheral Ready</description>
|
|
<addressOffset>0x00000A14</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRHIB_R0</name>
|
|
<description>Hibernation Module Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRUART</name>
|
|
<description>Universal Asynchronous Receiver/Transmitter Peripheral Ready</description>
|
|
<addressOffset>0x00000A18</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRUART_R0</name>
|
|
<description>UART Module 0 Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRUART_R1</name>
|
|
<description>UART Module 1 Peripheral Ready</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRUART_R2</name>
|
|
<description>UART Module 2 Peripheral Ready</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRUART_R3</name>
|
|
<description>UART Module 3 Peripheral Ready</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRUART_R4</name>
|
|
<description>UART Module 4 Peripheral Ready</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRUART_R5</name>
|
|
<description>UART Module 5 Peripheral Ready</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRUART_R6</name>
|
|
<description>UART Module 6 Peripheral Ready</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRUART_R7</name>
|
|
<description>UART Module 7 Peripheral Ready</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRSSI</name>
|
|
<description>Synchronous Serial Interface Peripheral Ready</description>
|
|
<addressOffset>0x00000A1C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRSSI_R0</name>
|
|
<description>SSI Module 0 Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRSSI_R1</name>
|
|
<description>SSI Module 1 Peripheral Ready</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRSSI_R2</name>
|
|
<description>SSI Module 2 Peripheral Ready</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRSSI_R3</name>
|
|
<description>SSI Module 3 Peripheral Ready</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRI2C</name>
|
|
<description>Inter-Integrated Circuit Peripheral Ready</description>
|
|
<addressOffset>0x00000A20</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRI2C_R0</name>
|
|
<description>I2C Module 0 Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRI2C_R1</name>
|
|
<description>I2C Module 1 Peripheral Ready</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRI2C_R2</name>
|
|
<description>I2C Module 2 Peripheral Ready</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRI2C_R3</name>
|
|
<description>I2C Module 3 Peripheral Ready</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRI2C_R4</name>
|
|
<description>I2C Module 4 Peripheral Ready</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRI2C_R5</name>
|
|
<description>I2C Module 5 Peripheral Ready</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRI2C_R6</name>
|
|
<description>I2C Module 6 Peripheral Ready</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRI2C_R7</name>
|
|
<description>I2C Module 7 Peripheral Ready</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRI2C_R8</name>
|
|
<description>I2C Module 8 Peripheral Ready</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRI2C_R9</name>
|
|
<description>I2C Module 9 Peripheral Ready</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRUSB</name>
|
|
<description>Universal Serial Bus Peripheral Ready</description>
|
|
<addressOffset>0x00000A28</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRUSB_R0</name>
|
|
<description>USB Module Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PREPHY</name>
|
|
<description>Ethernet PHY Peripheral Ready</description>
|
|
<addressOffset>0x00000A30</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PREPHY_R0</name>
|
|
<description>Ethernet PHY Module Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRCAN</name>
|
|
<description>Controller Area Network Peripheral Ready</description>
|
|
<addressOffset>0x00000A34</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRCAN_R0</name>
|
|
<description>CAN Module 0 Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRCAN_R1</name>
|
|
<description>CAN Module 1 Peripheral Ready</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRADC</name>
|
|
<description>Analog-to-Digital Converter Peripheral Ready</description>
|
|
<addressOffset>0x00000A38</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRADC_R0</name>
|
|
<description>ADC Module 0 Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PRADC_R1</name>
|
|
<description>ADC Module 1 Peripheral Ready</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRACMP</name>
|
|
<description>Analog Comparator Peripheral Ready</description>
|
|
<addressOffset>0x00000A3C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRACMP_R0</name>
|
|
<description>Analog Comparator Module 0 Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRPWM</name>
|
|
<description>Pulse Width Modulator Peripheral Ready</description>
|
|
<addressOffset>0x00000A40</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRPWM_R0</name>
|
|
<description>PWM Module 0 Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRQEI</name>
|
|
<description>Quadrature Encoder Interface Peripheral Ready</description>
|
|
<addressOffset>0x00000A44</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRQEI_R0</name>
|
|
<description>QEI Module 0 Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PREEPROM</name>
|
|
<description>EEPROM Peripheral Ready</description>
|
|
<addressOffset>0x00000A58</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PREEPROM_R0</name>
|
|
<description>EEPROM Module Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRCCM</name>
|
|
<description>CRC and Cryptographic Modules Peripheral Ready</description>
|
|
<addressOffset>0x00000A74</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PRCCM_R0</name>
|
|
<description>CRC and Cryptographic Modules Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PREMAC</name>
|
|
<description>Ethernet MAC Peripheral Ready</description>
|
|
<addressOffset>0x00000A9C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PREMAC_R0</name>
|
|
<description>Ethernet MAC Module 0 Peripheral Ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UNIQUEID0</name>
|
|
<description>Unique ID 0</description>
|
|
<addressOffset>0x00000F20</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>UNIQUEID1</name>
|
|
<description>Unique ID 1</description>
|
|
<addressOffset>0x00000F24</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>UNIQUEID2</name>
|
|
<description>Unique ID 2</description>
|
|
<addressOffset>0x00000F28</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>UNIQUEID3</name>
|
|
<description>Unique ID 3</description>
|
|
<addressOffset>0x00000F2C</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UDMA</name>
|
|
<description>Register map for UDMA peripheral</description>
|
|
<groupName>UDM</groupName>
|
|
<prependToName>UDMA</prependToName>
|
|
<baseAddress>0x400FF000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt><name>UDMA</name><value>44</value></interrupt>
|
|
<interrupt><name>UDMAERR</name><value>45</value></interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>DMA Status</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_STAT_MASTEN</name>
|
|
<description>Master Enable Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_STAT_STATE</name>
|
|
<description>Control State Machine Status</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UDMA_STAT_STATE_IDLE</name>
|
|
<description>Idle</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UDMA_STAT_STATE_RD_CTRL</name>
|
|
<description>Reading channel controller data</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UDMA_STAT_STATE_RD_SRCENDP</name>
|
|
<description>Reading source end pointer</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UDMA_STAT_STATE_RD_DSTENDP</name>
|
|
<description>Reading destination end pointer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UDMA_STAT_STATE_RD_SRCDAT</name>
|
|
<description>Reading source data</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UDMA_STAT_STATE_WR_DSTDAT</name>
|
|
<description>Writing destination data</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UDMA_STAT_STATE_WAIT</name>
|
|
<description>Waiting for uDMA request to clear</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UDMA_STAT_STATE_WR_CTRL</name>
|
|
<description>Writing channel controller data</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UDMA_STAT_STATE_STALL</name>
|
|
<description>Stalled</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UDMA_STAT_STATE_DONE</name>
|
|
<description>Done</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UDMA_STAT_STATE_UNDEF</name>
|
|
<description>Undefined</description>
|
|
<value>0xa</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_STAT_DMACHANS</name>
|
|
<description>Available uDMA Channels Minus 1</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>DMA Configuration</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_CFG_MASTEN</name>
|
|
<description>Controller Master Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTLBASE</name>
|
|
<description>DMA Channel Control Base Pointer</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_CTLBASE_ADDR</name>
|
|
<description>Channel Control Base Address</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTBASE</name>
|
|
<description>DMA Alternate Channel Control Base Pointer</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_ALTBASE_ADDR</name>
|
|
<description>Alternate Channel Address Pointer</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAITSTAT</name>
|
|
<description>DMA Channel Wait-on-Request Status</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_WAITSTAT_WAITREQ</name>
|
|
<description>Channel [n] Wait Status</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWREQ</name>
|
|
<description>DMA Channel Software Request</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_SWREQ</name>
|
|
<description>Channel [n] Software Request</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USEBURSTSET</name>
|
|
<description>DMA Channel Useburst Set</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_USEBURSTSET_SET</name>
|
|
<description>Channel [n] Useburst Set</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USEBURSTCLR</name>
|
|
<description>DMA Channel Useburst Clear</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_USEBURSTCLR_CLR</name>
|
|
<description>Channel [n] Useburst Clear</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REQMASKSET</name>
|
|
<description>DMA Channel Request Mask Set</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_REQMASKSET_SET</name>
|
|
<description>Channel [n] Request Mask Set</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REQMASKCLR</name>
|
|
<description>DMA Channel Request Mask Clear</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_REQMASKCLR_CLR</name>
|
|
<description>Channel [n] Request Mask Clear</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENASET</name>
|
|
<description>DMA Channel Enable Set</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_ENASET_SET</name>
|
|
<description>Channel [n] Enable Set</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENACLR</name>
|
|
<description>DMA Channel Enable Clear</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_ENACLR_CLR</name>
|
|
<description>Clear Channel [n] Enable Clear</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTSET</name>
|
|
<description>DMA Channel Primary Alternate Set</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_ALTSET_SET</name>
|
|
<description>Channel [n] Alternate Set</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTCLR</name>
|
|
<description>DMA Channel Primary Alternate Clear</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_ALTCLR_CLR</name>
|
|
<description>Channel [n] Alternate Clear</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRIOSET</name>
|
|
<description>DMA Channel Priority Set</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_PRIOSET_SET</name>
|
|
<description>Channel [n] Priority Set</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRIOCLR</name>
|
|
<description>DMA Channel Priority Clear</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_PRIOCLR_CLR</name>
|
|
<description>Channel [n] Priority Clear</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERRCLR</name>
|
|
<description>DMA Bus Error Clear</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_ERRCLR_ERRCLR</name>
|
|
<description>uDMA Bus Error Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHMAP0</name>
|
|
<description>DMA Channel Map Select 0</description>
|
|
<addressOffset>0x00000510</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_CHMAP0_CH0SEL</name>
|
|
<description>uDMA Channel 0 Source Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP0_CH1SEL</name>
|
|
<description>uDMA Channel 1 Source Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP0_CH2SEL</name>
|
|
<description>uDMA Channel 2 Source Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP0_CH3SEL</name>
|
|
<description>uDMA Channel 3 Source Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP0_CH4SEL</name>
|
|
<description>uDMA Channel 4 Source Select</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP0_CH5SEL</name>
|
|
<description>uDMA Channel 5 Source Select</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP0_CH6SEL</name>
|
|
<description>uDMA Channel 6 Source Select</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP0_CH7SEL</name>
|
|
<description>uDMA Channel 7 Source Select</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHMAP1</name>
|
|
<description>DMA Channel Map Select 1</description>
|
|
<addressOffset>0x00000514</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_CHMAP1_CH8SEL</name>
|
|
<description>uDMA Channel 8 Source Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP1_CH9SEL</name>
|
|
<description>uDMA Channel 9 Source Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP1_CH10SEL</name>
|
|
<description>uDMA Channel 10 Source Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP1_CH11SEL</name>
|
|
<description>uDMA Channel 11 Source Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP1_CH12SEL</name>
|
|
<description>uDMA Channel 12 Source Select</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP1_CH13SEL</name>
|
|
<description>uDMA Channel 13 Source Select</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP1_CH14SEL</name>
|
|
<description>uDMA Channel 14 Source Select</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP1_CH15SEL</name>
|
|
<description>uDMA Channel 15 Source Select</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHMAP2</name>
|
|
<description>DMA Channel Map Select 2</description>
|
|
<addressOffset>0x00000518</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_CHMAP2_CH16SEL</name>
|
|
<description>uDMA Channel 16 Source Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP2_CH17SEL</name>
|
|
<description>uDMA Channel 17 Source Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP2_CH18SEL</name>
|
|
<description>uDMA Channel 18 Source Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP2_CH19SEL</name>
|
|
<description>uDMA Channel 19 Source Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP2_CH20SEL</name>
|
|
<description>uDMA Channel 20 Source Select</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP2_CH21SEL</name>
|
|
<description>uDMA Channel 21 Source Select</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP2_CH22SEL</name>
|
|
<description>uDMA Channel 22 Source Select</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP2_CH23SEL</name>
|
|
<description>uDMA Channel 23 Source Select</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHMAP3</name>
|
|
<description>DMA Channel Map Select 3</description>
|
|
<addressOffset>0x0000051C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UDMA_CHMAP3_CH24SEL</name>
|
|
<description>uDMA Channel 24 Source Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP3_CH25SEL</name>
|
|
<description>uDMA Channel 25 Source Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP3_CH26SEL</name>
|
|
<description>uDMA Channel 26 Source Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP3_CH27SEL</name>
|
|
<description>uDMA Channel 27 Source Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP3_CH28SEL</name>
|
|
<description>uDMA Channel 28 Source Select</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP3_CH29SEL</name>
|
|
<description>uDMA Channel 29 Source Select</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP3_CH30SEL</name>
|
|
<description>uDMA Channel 30 Source Select</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UDMA_CHMAP3_CH31SEL</name>
|
|
<description>uDMA Channel 31 Source Select</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CCM0</name>
|
|
<description>Register map for CCM0 peripheral</description>
|
|
<groupName>CCM</groupName>
|
|
<prependToName>CCM0</prependToName>
|
|
<baseAddress>0x44030204</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000004</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CCMCGREQ</name>
|
|
<description>Cryptographic Modules Clock Gating Request</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>Register map for CRC peripheral</description>
|
|
<groupName>CRC</groupName>
|
|
<baseAddress>0x44030400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x0000001C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>CRC Control</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_CTRL_TYPE</name>
|
|
<description>Operation Type</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_TYPE_P8055</name>
|
|
<description>Polynomial 0x8005</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_TYPE_P1021</name>
|
|
<description>Polynomial 0x1021</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_TYPE_P4C11DB7</name>
|
|
<description>Polynomial 0x4C11DB7</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_TYPE_P1EDC6F41</name>
|
|
<description>Polynomial 0x1EDC6F41</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_TYPE_TCPCHKSUM</name>
|
|
<description>TCP checksum</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRC_CTRL_ENDIAN</name>
|
|
<description>Endian Control</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_ENDIAN_SBHW</name>
|
|
<description>Configuration unchanged. (B3, B2, B1, B0)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_ENDIAN_SHW</name>
|
|
<description>Bytes are swapped in half-words but half-words are not swapped (B2, B3, B0, B1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_ENDIAN_SHWNB</name>
|
|
<description>Half-words are swapped but bytes are not swapped in half-word. (B1, B0, B3, B2)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_ENDIAN_SBSW</name>
|
|
<description>Bytes are swapped in half-words and half-words are swapped. (B0, B1, B2, B3)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRC_CTRL_BR</name>
|
|
<description>Bit reverse enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRC_CTRL_OBR</name>
|
|
<description>Output Reverse Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRC_CTRL_RESINV</name>
|
|
<description>Result Inverse Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRC_CTRL_SIZE</name>
|
|
<description>Input Data Size</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRC_CTRL_INIT</name>
|
|
<description>CRC Initialization</description>
|
|
<bitRange>[14:13]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_INIT_SEED</name>
|
|
<description>Use the CRCSEED register context as the starting value</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_INIT_0</name>
|
|
<description>Initialize to all '0s'</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_CTRL_INIT_1</name>
|
|
<description>Initialize to all '1s'</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCSEED</name>
|
|
<description>CRC SEED/Context</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_SEED_SEED</name>
|
|
<description>SEED/Context Value</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCDIN</name>
|
|
<description>CRC Data Input</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_DIN_DATAIN</name>
|
|
<description>Data Input</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCRSLTPP</name>
|
|
<description>CRC Post Processing Result</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>CRC_RSLTPP_RSLTPP</name>
|
|
<description>Post Processing Result</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SHAMD5</name>
|
|
<description>Register map for SHAMD5 peripheral</description>
|
|
<groupName>SHAMD5</groupName>
|
|
<prependToName>SHAMD5</prependToName>
|
|
<baseAddress>0x44034000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00002000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ODIGEST_A</name>
|
|
<description>SHA Outer Digest A</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_ODIGEST_A_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODIGEST_B</name>
|
|
<description>SHA Outer Digest B</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_ODIGEST_B_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODIGEST_C</name>
|
|
<description>SHA Outer Digest C</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_ODIGEST_C_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODIGEST_D</name>
|
|
<description>SHA Outer Digest D</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_ODIGEST_D_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODIGEST_E</name>
|
|
<description>SHA Outer Digest E</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_ODIGEST_E_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODIGEST_F</name>
|
|
<description>SHA Outer Digest F</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_ODIGEST_F_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODIGEST_G</name>
|
|
<description>SHA Outer Digest G</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_ODIGEST_G_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODIGEST_H</name>
|
|
<description>SHA Outer Digest H</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_ODIGEST_H_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIGEST_A</name>
|
|
<description>SHA Inner Digest A</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_IDIGEST_A_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIGEST_B</name>
|
|
<description>SHA Inner Digest B</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_IDIGEST_B_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIGEST_C</name>
|
|
<description>SHA Inner Digest C</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_IDIGEST_C_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIGEST_D</name>
|
|
<description>SHA Inner Digest D</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_IDIGEST_D_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIGEST_E</name>
|
|
<description>SHA Inner Digest E</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_IDIGEST_E_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIGEST_F</name>
|
|
<description>SHA Inner Digest F</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_IDIGEST_F_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIGEST_G</name>
|
|
<description>SHA Inner Digest G</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_IDIGEST_G_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIGEST_H</name>
|
|
<description>SHA Inner Digest H</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_IDIGEST_H_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIGEST_COUNT</name>
|
|
<description>SHA Digest Count</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DIGEST_COUNT</name>
|
|
<description>Digest Count</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>SHA Mode</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_MODE_ALGO</name>
|
|
<description>Hash Algorithm</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SHAMD5_MODE_ALGO_MD5</name>
|
|
<description>MD5</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHAMD5_MODE_ALGO_SHA1</name>
|
|
<description>SHA-1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHAMD5_MODE_ALGO_SHA224</name>
|
|
<description>SHA-224</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHAMD5_MODE_ALGO_SHA256</name>
|
|
<description>SHA-256</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_MODE_ALGO_CONSTANT</name>
|
|
<description>The initial digest register will be overwritten with the algorithm constants for the selected algorithm when hashing and the initial digest count register will be reset to 0</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_MODE_CLOSE_HASH</name>
|
|
<description>Performs the padding, the Hash/HMAC will be 'closed' at the end of the block, as per MD5/SHA-1/SHA-2 specification</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_MODE_HMAC_KEY_PROC</name>
|
|
<description>HMAC Key Processing Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_MODE_HMAC_OUTER_HASH</name>
|
|
<description>HMAC Outer Hash Processing Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LENGTH</name>
|
|
<description>SHA Length</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_LENGTH</name>
|
|
<description>Block Length/Remaining Byte Count</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_0_IN</name>
|
|
<description>SHA Data 0 Input</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_0_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_1_IN</name>
|
|
<description>SHA Data 1 Input</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_1_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_2_IN</name>
|
|
<description>SHA Data 2 Input</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_2_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_3_IN</name>
|
|
<description>SHA Data 3 Input</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_3_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_4_IN</name>
|
|
<description>SHA Data 4 Input</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_4_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_5_IN</name>
|
|
<description>SHA Data 5 Input</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_5_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_6_IN</name>
|
|
<description>SHA Data 6 Input</description>
|
|
<addressOffset>0x00000098</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_6_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_7_IN</name>
|
|
<description>SHA Data 7 Input</description>
|
|
<addressOffset>0x0000009C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_7_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_8_IN</name>
|
|
<description>SHA Data 8 Input</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_8_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_9_IN</name>
|
|
<description>SHA Data 9 Input</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_9_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_10_IN</name>
|
|
<description>SHA Data 10 Input</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_10_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_11_IN</name>
|
|
<description>SHA Data 11 Input</description>
|
|
<addressOffset>0x000000AC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_11_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_12_IN</name>
|
|
<description>SHA Data 12 Input</description>
|
|
<addressOffset>0x000000B0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_12_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_13_IN</name>
|
|
<description>SHA Data 13 Input</description>
|
|
<addressOffset>0x000000B4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_13_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_14_IN</name>
|
|
<description>SHA Data 14 Input</description>
|
|
<addressOffset>0x000000B8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_14_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_15_IN</name>
|
|
<description>SHA Data 15 Input</description>
|
|
<addressOffset>0x000000BC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DATA_15_IN_DATA</name>
|
|
<description>Digest/Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REVISION</name>
|
|
<description>SHA Revision</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_REVISION</name>
|
|
<description>Revision Number</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSCONFIG</name>
|
|
<description>SHA System Configuration</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_SYSCONFIG_SOFTRESET</name>
|
|
<description>Soft reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_SYSCONFIG_IT_EN</name>
|
|
<description>Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_SYSCONFIG_DMA_EN</name>
|
|
<description>uDMA Request Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_SYSCONFIG_SIDLE</name>
|
|
<description>Sidle mode</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SHAMD5_SYSCONFIG_SIDLE_FORCE</name>
|
|
<description>Force-idle mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_SYSCONFIG_SADVANCED</name>
|
|
<description>Advanced Mode Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSSTATUS</name>
|
|
<description>SHA System Status</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_SYSSTATUS_RESETDONE</name>
|
|
<description>Reset done status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQSTATUS</name>
|
|
<description>SHA Interrupt Status</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_IRQSTATUS_OUTPUT_READY</name>
|
|
<description>Output Ready Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_IRQSTATUS_INPUT_READY</name>
|
|
<description>Input Ready Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_IRQSTATUS_CONTEXT_READY</name>
|
|
<description>Context Ready Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQENABLE</name>
|
|
<description>SHA Interrupt Enable</description>
|
|
<addressOffset>0x0000011C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_IRQENABLE_OUTPUT_READY</name>
|
|
<description>Mask for output ready interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_IRQENABLE_INPUT_READY</name>
|
|
<description>Mask for input ready interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_IRQENABLE_CONTEXT_READY</name>
|
|
<description>Mask for context ready interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SHAMD5_DMA</name>
|
|
<description>Register map for SHAMD5 DMA peripheral</description>
|
|
<groupName>SHAMD5_DMA</groupName>
|
|
<prependToName>SHAMD5_DMA</prependToName>
|
|
<baseAddress>0x44030010</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000010</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SHAMD5_DMAIM</name>
|
|
<description>SHAMD5 DMA Interrupt Mask</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DMAIM_CIN</name>
|
|
<description>Context In DMA Done Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMAIM_COUT</name>
|
|
<description>Context Out DMA Done Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMAIM_DIN</name>
|
|
<description>Data In DMA Done Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMAIM_DOUT</name>
|
|
<description>Data Out DMA Done Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHAMD5_DMARIS</name>
|
|
<description>SHAMD5 DMA Raw Interrupt Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DMARIS_CIN</name>
|
|
<description>Context In DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMARIS_COUT</name>
|
|
<description>Context Out DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMARIS_DIN</name>
|
|
<description>Data In DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMARIS_DOUT</name>
|
|
<description>Data Out DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHAMD5_DMAMIS</name>
|
|
<description>SHAMD5 DMA Masked Interrupt Status</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DMAMIS_CIN</name>
|
|
<description>Context In DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMAMIS_COUT</name>
|
|
<description>Context Out DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMAMIS_DIN</name>
|
|
<description>Data In DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMAMIS_DOUT</name>
|
|
<description>Data Out DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHAMD5_DMAIC</name>
|
|
<description>SHAMD5 DMA Interrupt Clear</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SHAMD5_DMAIC_CIN</name>
|
|
<description>Context In DMA Done Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMAIC_COUT</name>
|
|
<description>Context Out DMA Done Interrupt Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMAIC_DIN</name>
|
|
<description>Data In DMA Done Interrupt Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SHAMD5_DMAIC_DOUT</name>
|
|
<description>Data Out DMA Done Interrupt Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AES</name>
|
|
<description>Register map for AES peripheral</description>
|
|
<groupName>AES</groupName>
|
|
<prependToName>AES</prependToName>
|
|
<baseAddress>0x44036000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00002000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>KEY2_6</name>
|
|
<description>AES Key 2_6</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY2_6_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY2_7</name>
|
|
<description>AES Key 2_7</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY2_7_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY2_4</name>
|
|
<description>AES Key 2_4</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY2_4_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY2_5</name>
|
|
<description>AES Key 2_5</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY2_5_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY2_2</name>
|
|
<description>AES Key 2_2</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY2_2_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY2_3</name>
|
|
<description>AES Key 2_3</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY2_3_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY2_0</name>
|
|
<description>AES Key 2_0</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY2_0_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY2_1</name>
|
|
<description>AES Key 2_1</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY2_1_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY1_6</name>
|
|
<description>AES Key 1_6</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY1_6_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY1_7</name>
|
|
<description>AES Key 1_7</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY1_7_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY1_4</name>
|
|
<description>AES Key 1_4</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY1_4_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY1_5</name>
|
|
<description>AES Key 1_5</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY1_5_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY1_2</name>
|
|
<description>AES Key 1_2</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY1_2_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY1_3</name>
|
|
<description>AES Key 1_3</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY1_3_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY1_0</name>
|
|
<description>AES Key 1_0</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY1_0_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY1_1</name>
|
|
<description>AES Key 1_1</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_KEY1_1_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IV_IN_0</name>
|
|
<description>AES Initialization Vector Input 0</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_IV_IN_0_DATA</name>
|
|
<description>Initialization Vector Input</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IV_IN_1</name>
|
|
<description>AES Initialization Vector Input 1</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_IV_IN_1_DATA</name>
|
|
<description>Initialization Vector Input</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IV_IN_2</name>
|
|
<description>AES Initialization Vector Input 2</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_IV_IN_2_DATA</name>
|
|
<description>Initialization Vector Input</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IV_IN_3</name>
|
|
<description>AES Initialization Vector Input 3</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_IV_IN_3_DATA</name>
|
|
<description>Initialization Vector Input</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>AES Control</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_CTRL_OUTPUT_READY</name>
|
|
<description>Output Ready Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_INPUT_READY</name>
|
|
<description>Input Ready Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_DIRECTION</name>
|
|
<description>Encryption/Decryption Selection</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_KEY_SIZE</name>
|
|
<description>Key Size</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_KEY_SIZE_128</name>
|
|
<description>Key is 128 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_KEY_SIZE_192</name>
|
|
<description>Key is 192 bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_KEY_SIZE_256</name>
|
|
<description>Key is 256 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_MODE</name>
|
|
<description>ECB/CBC Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_CTR</name>
|
|
<description>Counter Mode</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_CTR_WIDTH</name>
|
|
<description>AES-CTR Mode Counter Width</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_CTR_WIDTH_32</name>
|
|
<description>Counter is 32 bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_CTR_WIDTH_64</name>
|
|
<description>Counter is 64 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_CTR_WIDTH_96</name>
|
|
<description>Counter is 96 bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_CTR_WIDTH_128</name>
|
|
<description>Counter is 128 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_ICM</name>
|
|
<description>AES Integer Counter Mode (ICM) Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_CFB</name>
|
|
<description>Full block AES cipher feedback mode (CFB128) Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_XTS</name>
|
|
<description>AES-XTS Operation Enabled</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_XTS_NOP</name>
|
|
<description>No operation</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_XTS_TWEAKJL</name>
|
|
<description>Previous/intermediate tweak value and j loaded (value is loaded via IV, j is loaded via the AAD length register)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_XTS_K2IJL</name>
|
|
<description>Key2, n and j are loaded (n is loaded via IV, j is loaded via the AAD length register)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_XTS_K2ILJ0</name>
|
|
<description>Key2 and n are loaded; j=0 (n is loaded via IV)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_F8</name>
|
|
<description>AES f8 Mode Enable</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_F9</name>
|
|
<description>AES f9 Mode Enable</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_CBCMAC</name>
|
|
<description>AES-CBC MAC Enable</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_GCM</name>
|
|
<description>AES-GCM Mode Enable</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_GCM_NOP</name>
|
|
<description>No operation</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_GCM_HLY0ZERO</name>
|
|
<description>GHASH with H loaded and Y0-encrypted forced to zero</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_GCM_HLY0CALC</name>
|
|
<description>GHASH with H loaded and Y0-encrypted calculated internally</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_GCM_HY0CALC</name>
|
|
<description>Autonomous GHASH (both H and Y0-encrypted calculated internally)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_CCM</name>
|
|
<description>AES-CCM Mode Enable</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_CCM_L</name>
|
|
<description>L Value</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_CCM_L_2</name>
|
|
<description>width = 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_CCM_L_4</name>
|
|
<description>width = 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES_CTRL_CCM_L_8</name>
|
|
<description>width = 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_CCM_M</name>
|
|
<description>Counter with CBC-MAC (CCM)</description>
|
|
<bitRange>[24:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_SAVE_CONTEXT</name>
|
|
<description>TAG or Result IV Save</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_SVCTXTRDY</name>
|
|
<description>AES TAG/IV Block(s) Ready</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_CTRL_CTXTRDY</name>
|
|
<description>Context Data Registers Ready</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C_LENGTH_0</name>
|
|
<description>AES Crypto Data Length 0</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_C_LENGTH_0_LENGTH</name>
|
|
<description>Data Length</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C_LENGTH_1</name>
|
|
<description>AES Crypto Data Length 1</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_C_LENGTH_1_LENGTH</name>
|
|
<description>Data Length</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AUTH_LENGTH</name>
|
|
<description>AES Authentication Data Length</description>
|
|
<addressOffset>0x0000005C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_AUTH_LENGTH_AUTH</name>
|
|
<description>Authentication Data Length</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_IN_0</name>
|
|
<description>AES Data RW Plaintext/Ciphertext 0</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_DATA_IN_0_DATA</name>
|
|
<description>Secure Data RW Plaintext/Ciphertext</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_IN_1</name>
|
|
<description>AES Data RW Plaintext/Ciphertext 1</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_DATA_IN_1_DATA</name>
|
|
<description>Secure Data RW Plaintext/Ciphertext</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_IN_2</name>
|
|
<description>AES Data RW Plaintext/Ciphertext 2</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_DATA_IN_2_DATA</name>
|
|
<description>Secure Data RW Plaintext/Ciphertext</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_IN_3</name>
|
|
<description>AES Data RW Plaintext/Ciphertext 3</description>
|
|
<addressOffset>0x0000006C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_DATA_IN_3_DATA</name>
|
|
<description>Secure Data RW Plaintext/Ciphertext</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAG_OUT_0</name>
|
|
<description>AES Hash Tag Out 0</description>
|
|
<addressOffset>0x00000070</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_TAG_OUT_0_HASH</name>
|
|
<description>Hash Result</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAG_OUT_1</name>
|
|
<description>AES Hash Tag Out 1</description>
|
|
<addressOffset>0x00000074</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_TAG_OUT_1_HASH</name>
|
|
<description>Hash Result</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAG_OUT_2</name>
|
|
<description>AES Hash Tag Out 2</description>
|
|
<addressOffset>0x00000078</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_TAG_OUT_2_HASH</name>
|
|
<description>Hash Result</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAG_OUT_3</name>
|
|
<description>AES Hash Tag Out 3</description>
|
|
<addressOffset>0x0000007C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_TAG_OUT_3_HASH</name>
|
|
<description>Hash Result</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REVISION</name>
|
|
<description>AES IP Revision Identifier</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_REVISION</name>
|
|
<description>Revision number</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSCONFIG</name>
|
|
<description>AES System Configuration</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_SYSCONFIG_SOFTRESET</name>
|
|
<description>Soft reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_SYSCONFIG_DMA_REQ_DATA_IN_EN</name>
|
|
<description>DMA Request Data In Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN</name>
|
|
<description>DMA Request Data Out Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN</name>
|
|
<description>DMA Request Context In Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN</name>
|
|
<description>DMA Request Context Out Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT</name>
|
|
<description>Map Context Out on Data Out Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_SYSCONFIG_KEYENC</name>
|
|
<description>Key Encoding</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_SYSCONFIG_K3</name>
|
|
<description>K3 Select</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSSTATUS</name>
|
|
<description>AES System Status</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_SYSSTATUS_RESETDONE</name>
|
|
<description>Reset Done</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQSTATUS</name>
|
|
<description>AES Interrupt Status</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_IRQSTATUS_CONTEXT_IN</name>
|
|
<description>Context In Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_IRQSTATUS_DATA_IN</name>
|
|
<description>Data In Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_IRQSTATUS_DATA_OUT</name>
|
|
<description>Data Out Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_IRQSTATUS_CONTEXT_OUT</name>
|
|
<description>Context Output Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQENABLE</name>
|
|
<description>AES Interrupt Enable</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_IRQENABLE_CONTEXT_IN</name>
|
|
<description>Context In Interrupt Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_IRQENABLE_DATA_IN</name>
|
|
<description>Data In Interrupt Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_IRQENABLE_DATA_OUT</name>
|
|
<description>Data Out Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_IRQENABLE_CONTEXT_OUT</name>
|
|
<description>Context Out Interrupt Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRTYBITS</name>
|
|
<description>AES Dirty Bits</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_DIRTYBITS_S_ACCESS</name>
|
|
<description>AES Access Bit</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DIRTYBITS_S_DIRTY</name>
|
|
<description>AES Dirty Bit</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AES_DMA</name>
|
|
<description>Register map for AES DMA peripheral</description>
|
|
<groupName>AES_DMA</groupName>
|
|
<prependToName>AES_DMA</prependToName>
|
|
<baseAddress>0x44030020</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000010</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>AES_DMAIM</name>
|
|
<description>AES DMA Interrupt Mask</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_DMAIM_CIN</name>
|
|
<description>Context In DMA Done Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMAIM_COUT</name>
|
|
<description>Context Out DMA Done Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMAIM_DIN</name>
|
|
<description>Data In DMA Done Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMAIM_DOUT</name>
|
|
<description>Data Out DMA Done Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AES_DMARIS</name>
|
|
<description>AES DMA Raw Interrupt Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_DMARIS_CIN</name>
|
|
<description>Context In DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMARIS_COUT</name>
|
|
<description>Context Out DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMARIS_DIN</name>
|
|
<description>Data In DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMARIS_DOUT</name>
|
|
<description>Data Out DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AES_DMAMIS</name>
|
|
<description>AES DMA Masked Interrupt Status</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_DMAMIS_CIN</name>
|
|
<description>Context In DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMAMIS_COUT</name>
|
|
<description>Context Out DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMAMIS_DIN</name>
|
|
<description>Data In DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMAMIS_DOUT</name>
|
|
<description>Data Out DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AES_DMAIC</name>
|
|
<description>AES DMA Interrupt Clear</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>AES_DMAIC_CIN</name>
|
|
<description>Context In DMA Done Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMAIC_COUT</name>
|
|
<description>Context Out DMA Done Interrupt Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMAIC_DIN</name>
|
|
<description>Data In DMA Done Interrupt Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AES_DMAIC_DOUT</name>
|
|
<description>Data Out DMA Done Interrupt Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DES</name>
|
|
<description>Register map for DES peripheral</description>
|
|
<groupName>DES</groupName>
|
|
<prependToName>DES</prependToName>
|
|
<baseAddress>0x44038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00002000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>KEY3_L</name>
|
|
<description>DES Key 3 LSW for 192-Bit Key</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_KEY3_L_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY3_H</name>
|
|
<description>DES Key 3 MSW for 192-Bit Key</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_KEY3_H_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY2_L</name>
|
|
<description>DES Key 2 LSW for 128-Bit Key</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_KEY2_L_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY2_H</name>
|
|
<description>DES Key 2 MSW for 128-Bit Key</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_KEY2_H_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY1_L</name>
|
|
<description>DES Key 1 LSW for 64-Bit Key</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_KEY1_L_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY1_H</name>
|
|
<description>DES Key 1 MSW for 64-Bit Key</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_KEY1_H_KEY</name>
|
|
<description>Key Data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IV_L</name>
|
|
<description>DES Initialization Vector</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_IV_L</name>
|
|
<description>Initialization vector for CBC, CFB modes (LSW)</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IV_H</name>
|
|
<description>DES Initialization Vector</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_IV_H</name>
|
|
<description>Initialization vector for CBC, CFB modes (MSW)</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>DES Control</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_CTRL_OUTPUT_READY</name>
|
|
<description>When 1, Data decrypted/encrypted ready</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_CTRL_INPUT_READY</name>
|
|
<description>When 1, ready to encrypt/decrypt data</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_CTRL_DIRECTION</name>
|
|
<description>Select encryption/decryption 0x0: decryption is selected0x1: Encryption is selected</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_CTRL_TDES</name>
|
|
<description>Select DES or triple DES encryption/decryption</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_CTRL_MODE</name>
|
|
<description>Select CBC, ECB or CFB mode0x0: ECB mode0x1: CBC mode0x2: CFB mode0x3: reserved</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_CTRL_CONTEXT</name>
|
|
<description>If 1, this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LENGTH</name>
|
|
<description>DES Cryptographic Data Length</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_LENGTH</name>
|
|
<description>Cryptographic data length in bytes for all modes</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_L</name>
|
|
<description>DES LSW Data RW</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_DATA_L</name>
|
|
<description>Data for encryption/decryption, LSW</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_H</name>
|
|
<description>DES MSW Data RW</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_DATA_H</name>
|
|
<description>Data for encryption/decryption, MSW</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REVISION</name>
|
|
<description>DES Revision Number</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_REVISION</name>
|
|
<description>Revision number</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSCONFIG</name>
|
|
<description>DES System Configuration</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_SYSCONFIG_SOFTRESET</name>
|
|
<description>Soft reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_SYSCONFIG_SIDLE</name>
|
|
<description>Sidle mode</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DES_SYSCONFIG_SIDLE_FORCE</name>
|
|
<description>Force-idle mode</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DES_SYSCONFIG_DMA_REQ_DATA_IN_EN</name>
|
|
<description>DMA Request Data In Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN</name>
|
|
<description>DMA Request Data Out Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN</name>
|
|
<description>DMA Request Context In Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSSTATUS</name>
|
|
<description>DES System Status</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_SYSSTATUS_RESETDONE</name>
|
|
<description>Reset Done</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQSTATUS</name>
|
|
<description>DES Interrupt Status</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_IRQSTATUS_CONTEX_IN</name>
|
|
<description>This bit indicates context interrupt is active and triggers the interrupt output</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_IRQSTATUS_DATA_IN</name>
|
|
<description>This bit indicates data input interrupt is active and triggers the interrupt output</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_IRQSTATUS_DATA_OUT</name>
|
|
<description>This bit indicates data output interrupt is active and triggers the interrupt output</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQENABLE</name>
|
|
<description>DES Interrupt Enable</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_IRQENABLE_M_CONTEX_IN</name>
|
|
<description>If this bit is set to 1 the context interrupt is enabled</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_IRQENABLE_M_DATA_IN</name>
|
|
<description>If this bit is set to 1 the data input interrupt is enabled</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_IRQENABLE_M_DATA_OUT</name>
|
|
<description>If this bit is set to 1 the data output interrupt is enabled</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIRTYBITS</name>
|
|
<description>DES Dirty Bits</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_DIRTYBITS_S_ACCESS</name>
|
|
<description>This bit is set to 1 by the module if any of the DES_* registers is read</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DIRTYBITS_S_DIRTY</name>
|
|
<description>This bit is set to 1 by the module if any of the DES_* registers is written</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DES_DMA</name>
|
|
<description>Register map for DES DMA peripheral</description>
|
|
<groupName>DES_DMA</groupName>
|
|
<prependToName>DES_DMA</prependToName>
|
|
<baseAddress>0x44030030</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000010</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DES_DMAIM</name>
|
|
<description>DES DMA Interrupt Mask</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_DMAIM_CIN</name>
|
|
<description>Context In DMA Done Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMAIM_COUT</name>
|
|
<description>Context Out DMA Done Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMAIM_DIN</name>
|
|
<description>Data In DMA Done Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMAIM_DOUT</name>
|
|
<description>Data Out DMA Done Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DES_DMARIS</name>
|
|
<description>DES DMA Raw Interrupt Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_DMARIS_CIN</name>
|
|
<description>Context In DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMARIS_COUT</name>
|
|
<description>Context Out DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMARIS_DIN</name>
|
|
<description>Data In DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMARIS_DOUT</name>
|
|
<description>Data Out DMA Done Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DES_DMAMIS</name>
|
|
<description>DES DMA Masked Interrupt Status</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_DMAMIS_CIN</name>
|
|
<description>Context In DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMAMIS_COUT</name>
|
|
<description>Context Out DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMAMIS_DIN</name>
|
|
<description>Data In DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMAMIS_DOUT</name>
|
|
<description>Data Out DMA Done Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DES_DMAIC</name>
|
|
<description>DES DMA Interrupt Clear</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>DES_DMAIC_CIN</name>
|
|
<description>Context In DMA Done Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMAIC_COUT</name>
|
|
<description>Context Out DMA Done Interrupt Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMAIC_DIN</name>
|
|
<description>Data In DMA Done Interrupt Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DES_DMAIC_DOUT</name>
|
|
<description>Data Out DMA Done Interrupt Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
<vendorExtensions>
|
|
<memory>
|
|
<name>FLASH</name>
|
|
<description>FLASH Memory Map for MSP432E401Y</description>
|
|
<baseAddress>0x00000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00100000</size>
|
|
<usage>FLASH Memory</usage>
|
|
</addressBlock>
|
|
</memory>
|
|
<memory>
|
|
<name>ROM</name>
|
|
<description>ROM Memory Map for MSP432E401Y</description>
|
|
<baseAddress>0x01000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00008c00</size>
|
|
<usage>ROM Boot Loader</usage>
|
|
</addressBlock>
|
|
</memory>
|
|
<memory>
|
|
<name>SRAM</name>
|
|
<description>SRAM Memory Map for MSP432E401Y</description>
|
|
<baseAddress>0x20000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00040000</size>
|
|
<usage>SRAM</usage>
|
|
</addressBlock>
|
|
</memory>
|
|
</vendorExtensions>
|
|
</device>
|