45905 lines
1.6 MiB
45905 lines
1.6 MiB
<?xml version="1.0" encoding="utf-8"?>
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<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
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<name>SIM3U166_B</name>
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<version>1</version>
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<description>USB, 256K Flash, 32K RAM, EMIF</description>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>32</size>
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<access>read-write</access>
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<peripherals>
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<peripheral>
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<name>SARADC_0</name>
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<version>A</version>
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<description>None</description>
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<groupName>ADC</groupName>
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<baseAddress>0x4001a000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0xffc</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>SARADC0_IRQn</name>
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<value>35</value>
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</interrupt>
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<registers>
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<!--BASEPOINTER_START_1-->
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<register>
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<name>CONFIG</name>
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<description>Module Configuration</description>
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<addressOffset>0x0</addressOffset>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>SPSEL</name>
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<description>Sampling Phase Select. </description>
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<bitOffset>0</bitOffset>
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<bitWidth>4</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>PHASE0</name>
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<description>The ADC samples at SSG phase 0.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE1</name>
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<description>The ADC samples at SSG phase 1.</description>
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<value>1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE2</name>
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<description>The ADC samples at SSG phase 2.</description>
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<value>2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE3</name>
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<description>The ADC samples at SSG phase 3.</description>
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<value>3</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE4</name>
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<description>The ADC samples at SSG phase 4.</description>
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<value>4</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE5</name>
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<description>The ADC samples at SSG phase 5.</description>
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<value>5</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE6</name>
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<description>The ADC samples at SSG phase 6.</description>
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<value>6</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE7</name>
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<description>The ADC samples at SSG phase 7.</description>
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<value>7</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE8</name>
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<description>The ADC samples at SSG phase 8.</description>
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<value>8</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE9</name>
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<description>The ADC samples at SSG phase 9.</description>
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<value>9</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE10</name>
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<description>The ADC samples at SSG phase 10.</description>
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<value>10</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE11</name>
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<description>The ADC samples at SSG phase 11.</description>
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<value>11</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE12</name>
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<description>The ADC samples at SSG phase 12.</description>
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<value>12</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE13</name>
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<description>The ADC samples at SSG phase 13.</description>
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<value>13</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE14</name>
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<description>The ADC samples at SSG phase 14.</description>
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<value>14</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PHASE15</name>
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<description>The ADC samples at SSG phase 15.</description>
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<value>15</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>SPEN</name>
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<description>Sampling Phase Enable. </description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>DISABLED</name>
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<description>Disable Phase Select. The ADC will always sample on the start-of-conversion trigger selected by the SCSEL field.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ENABLED</name>
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<description>Enable Phase Select. The ADC will sample according to the phase selected by the SPSEL field.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>SSGEN</name>
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<description>Synchronous Sample Generator Enable. </description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>DISABLED</name>
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<description>Disable the SAR clock output to SSG.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ENABLED</name>
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<description>The ADC is the SSG master, and the SAR clock will be output to the SSG block.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>PACKMD</name>
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<description>Output Packing Mode. </description>
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<bitOffset>6</bitOffset>
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<bitWidth>2</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>UPPER_ONLY</name>
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<description>Data is written to the upper half-word and the lower half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>LOWER_ONLY</name>
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<description>Data is written to the lower half-word, and the upper half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled.</description>
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<value>1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>UPPER_FIRST</name>
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<description>Two data words are packed into the register with the upper half-word representing the earlier data, and the lower half-word representing the later data. If SIMCEN is set to 1, the upper half-word represents data from the master ADC (selected by SSGEN) and the lower half-word represents data from the slave ADC. The ADC write to the lower half-word will trigger the SCI interrupt, if enabled.</description>
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<value>2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>LOWER_FIRST</name>
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<description>Two data words are packed into the register with the lower half-word representing the earlier data, and the upper half-word representing the later data. If SIMCEN is set to 1, the lower half-word represents data from the master ADC (selected by SSGEN) and the upper half-word represents data from the slave ADC. The ADC write to the upper half-word will trigger the SCI interrupt, if enabled.</description>
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<value>3</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>SIMCEN</name>
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<description>Simultaneous Conversion Packing Enable. </description>
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<bitOffset>8</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>DISABLED</name>
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<description>Disable simultaneous mode conversion packing.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ENABLED</name>
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<description>Enable simultaneous mode conversion packing.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>INTLVEN</name>
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<description>Interleaved Conversion Packing Enable. </description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>DISABLED</name>
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<description>Disable interleaved mode conversion packing.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ENABLED</name>
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<description>Enable interleaved mode conversion packing.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>SCANEN</name>
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<description>Scan Mode Enable. </description>
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<bitOffset>10</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>DISABLED</name>
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<description>Disable ADC scan mode.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ENABLED</name>
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<description>Enable ADC scan mode. The ADC will scan through the defined time slots in sequence on every start of conversion.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>SCANMD</name>
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<description>Scan Mode Select. </description>
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<bitOffset>12</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>ONCE</name>
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<description>The channel sequencer will cycle through all of the specified time slots once.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>LOOP</name>
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<description>The channel sequencer will cycle through all of the specified time slots in a loop until SCANEN is cleared to 0.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>DMAEN</name>
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<description>DMA Interface Enable . </description>
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<bitOffset>14</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>DISABLED</name>
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<description>Disable the ADC module DMA interface.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ENABLED</name>
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<description>Enable the ADC module DMA interface.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>BCLKSEL</name>
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<description>Burst Mode Clock Select. </description>
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<bitOffset>15</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>LPOSC0</name>
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<description>Burst mode uses the Low Power Oscillator.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>APB</name>
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<description>Burst mode uses the APB clock.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>CLKDIV</name>
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<description>SAR Clock Divider. </description>
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<bitOffset>16</bitOffset>
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<bitWidth>11</bitWidth>
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</field>
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<field>
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<name>SCCIEN</name>
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<description>Single Conversion Complete Interrupt Enable. </description>
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<bitOffset>27</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>DISABLED</name>
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<description>Disable the ADC single data conversion complete interrupt.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ENABLED</name>
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<description>Enable the ADC single data conversion complete interrupt.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>SDIEN</name>
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<description>Scan Done Interrupt Enable. </description>
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<bitOffset>28</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>DISABLED</name>
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<description>Disable the ADC scan complete interrupt.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ENABLED</name>
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<description>Enable the ADC scan complete interrupt.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>FORIEN</name>
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<description>FIFO Overrun Interrupt Enable. </description>
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<bitOffset>29</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>DISABLED</name>
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<description>Disable the data FIFO overrun interrupt.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ENABLED</name>
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<description>Enable the data FIFO overrun interrupt.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>FURIEN</name>
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<description>FIFO Underrun Interrupt Enable. </description>
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<bitOffset>30</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>DISABLED</name>
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<description>Disable the data FIFO underrun interrupt.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ENABLED</name>
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<description>Enable the data FIFO underrun interrupt.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>CONTROL</name>
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<description>Measurement Control</description>
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<addressOffset>0x10</addressOffset>
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<resetValue>0x1008F078</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>REFGNDSEL</name>
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<description>Reference Ground Select. </description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>INTERNAL</name>
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<description>The internal device ground is used as the ground reference for ADC conversions.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>EXTERNAL</name>
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<description>The VREFGND pin is used as the ground reference for ADC conversions.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>CLKESEL</name>
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<description>Sampling Clock Edge Select. </description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>RISING</name>
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<description>Select the rising edge of the APB clock.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>FALLING</name>
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<description>Select the falling edge of the APB clock.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>BMTK</name>
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<description>Burst Mode Tracking Time. </description>
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<bitOffset>2</bitOffset>
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<bitWidth>6</bitWidth>
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</field>
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<field>
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<name>SCSEL</name>
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<description>Start-Of-Conversion Source Select. </description>
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<bitOffset>8</bitOffset>
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<bitWidth>4</bitWidth>
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<enumeratedValues>
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<enumeratedValue>
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<name>ADCNT0</name>
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<description>An ADC conversion triggers from the ADCnT0 ("On Demand" by writing 1 to ADBUSY) trigger source.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ADCNT1</name>
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<description>An ADC conversion triggers from the ADCnT1 (Timer 0 Low Overflow) trigger source.</description>
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<value>1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ADCNT2</name>
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<description>An ADC conversion triggers from the ADCnT2 (Timer 0 High Overflow) trigger source.</description>
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<value>2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ADCNT3</name>
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<description>An ADC conversion triggers from the ADCnT3 (Timer 1 Low Overflow) trigger source.</description>
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<value>3</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ADCNT4</name>
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<description>An ADC conversion triggers from the ADCnT4 (Timer 1 High Overflow) trigger source.</description>
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<value>4</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>ADCNT5</name>
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<description>An ADC conversion triggers from the ADCnT5 (EPCA0 synchronization pulse) trigger source.</description>
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<value>5</value>
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</enumeratedValue>
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<enumeratedValue>
|
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<name>ADCNT6</name>
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<description>An ADC conversion triggers from the ADCnT6 (I2C0 Timer overflow) trigger source.</description>
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<value>6</value>
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</enumeratedValue>
|
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<enumeratedValue>
|
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<name>ADCNT7</name>
|
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<description>An ADC conversion triggers from the ADCnT7 (I2C1 Timer overflow) trigger source.</description>
|
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<value>7</value>
|
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</enumeratedValue>
|
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<enumeratedValue>
|
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<name>ADCNT8</name>
|
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<description>An ADC conversion triggers from the ADCnT8 (SSG phase defined by ADSP bits) trigger source.</description>
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<value>8</value>
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</enumeratedValue>
|
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<enumeratedValue>
|
|
<name>ADCNT9</name>
|
|
<description>An ADC conversion triggers from the ADCnT9 (RESERVED) trigger source.</description>
|
|
<value>9</value>
|
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</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT10</name>
|
|
<description>An ADC conversion triggers from the ADCnT10 (RESERVED) trigger source.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT11</name>
|
|
<description>An ADC conversion triggers from the ADCnT11 (RESERVED) trigger source.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT12</name>
|
|
<description>An ADC conversion triggers from the ADCnT12 (RESERVED) trigger source.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT13</name>
|
|
<description>An ADC conversion triggers from the ADCnT13 (RESERVED) trigger source.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT14</name>
|
|
<description>An ADC conversion triggers from the ADCnT14 (RESERVED) trigger source.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT15</name>
|
|
<description>An ADC conversion triggers from the ADCnT15 (PB1.6) trigger source.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWRTIME</name>
|
|
<description>Burst Mode Power Up Time. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BURSTEN</name>
|
|
<description>Burst Mode Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable burst mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable burst mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCEN</name>
|
|
<description>ADC Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the ADC (low-power shutdown).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the ADC (active and ready for data conversions).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AD12BSSEL</name>
|
|
<description>12-Bit Mode Sample Select. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>The ADC re-samples the input before each of the four conversions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>The ADC samples once before the first conversion and converts four times.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VCMEN</name>
|
|
<description>Common Mode Buffer Enable. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the common mode buffer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the common mode buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACCMD</name>
|
|
<description>Accumulation Mode. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACCUMULATE</name>
|
|
<description>Conversions will be accumulated for the specified number of cycles in burst mode according to the channel configuration.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEAT</name>
|
|
<description>Conversions will not be accumulated in burst mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRKMD</name>
|
|
<description>ADC Tracking Mode. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal Tracking Mode: When the ADC is enabled, a conversion begins immediately following the start-of-conversion signal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DELAYED</name>
|
|
<description>Delayed Tracking Mode: When the ADC is enabled, a conversion begins 3 SAR clock cycles following the start-of-conversion signal. The ADC is allowed to track during this time.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADBUSY</name>
|
|
<description>ADC Busy. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIASSEL</name>
|
|
<description>Bias Power Select. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>Select bias current mode 0. Recommended to use modes 1, 2, or 3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>Select bias current mode 1 (SARCLK = 16 MHz).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>Select bias current mode 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>Select bias current mode 3 (SARCLK = 4 MHz).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPMDEN</name>
|
|
<description>Low Power Mode Enable. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable low power mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable low power mode (requires extended tracking time).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MREFLPEN</name>
|
|
<description>MUX and VREF Low Power Enable. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable low power mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable low power mode (SAR clock <= 4 MHz).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREFSEL</name>
|
|
<description>Voltage Reference Select. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_VREF</name>
|
|
<description>Select the internal, dedicated SARADC voltage reference as the ADC reference.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDD</name>
|
|
<description>Select the VDD pin as the ADC reference.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDO_OUT</name>
|
|
<description>Select the output of the internal LDO regulator (~1.8 V) as the ADC reference.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTERNAL_VREF</name>
|
|
<description>Select the VREF pin as the ADC reference. This option is used for either an external VREF or the on-chip VREF driving out to the VREF pin.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQ7654</name>
|
|
<description>Channel Sequencer Time Slots 4-7 Setup</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TS4CHR</name>
|
|
<description>Time Slot 4 Conversion Characteristic. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 4.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 4.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 4.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS4MUX</name>
|
|
<description>Time Slot 4 Input Channel. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (RESERVED).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (RESERVED).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB0.0).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB0.1).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB0.2).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB0.3).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.4).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB0.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB0.6).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (PB0.8).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB0.9).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (RESERVED).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (VSS).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (1.8V Output of LDO).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VDD).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS5CHR</name>
|
|
<description>Time Slot 5 Conversion Characteristic. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 5.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 5.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 5.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS5MUX</name>
|
|
<description>Time Slot 5 Input Channel. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (RESERVED).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (RESERVED).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB0.0).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB0.1).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB0.2).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB0.3).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.4).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB0.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB0.6).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (PB0.8).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB0.9).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (RESERVED).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (VSS).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (1.8V Output of LDO).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VDD).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS6CHR</name>
|
|
<description>Time Slot 6 Conversion Characteristic. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 6.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 6.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 6.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 6.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS6MUX</name>
|
|
<description>Time Slot 6 Input Channel. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (RESERVED).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (RESERVED).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB0.0).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB0.1).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB0.2).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB0.3).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.4).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB0.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB0.6).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (PB0.8).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB0.9).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (RESERVED).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (VSS).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (1.8V Output of LDO).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VDD).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS7CHR</name>
|
|
<description>Time Slot 7 Conversion Characteristic. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 7.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 7.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 7.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS7MUX</name>
|
|
<description>Time Slot 7 Input Channel. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (RESERVED).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (RESERVED).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB0.0).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB0.1).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB0.2).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB0.3).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.4).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB0.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB0.6).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (PB0.8).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB0.9).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (RESERVED).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (VSS).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (1.8V Output of LDO).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VDD).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQ3210</name>
|
|
<description>Channel Sequencer Time Slots 0-3 Setup</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TS0CHR</name>
|
|
<description>Time Slot 0 Conversion Characteristic. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 0.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 0.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS0MUX</name>
|
|
<description>Time Slot 0 Input Channel. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (RESERVED).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (RESERVED).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB0.0).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB0.1).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB0.2).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB0.3).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.4).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB0.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB0.6).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (PB0.8).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB0.9).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (RESERVED).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (VSS).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (1.8V Output of LDO).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VDD).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS1CHR</name>
|
|
<description>Time Slot 1 Conversion Characteristic. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 1.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 1.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS1MUX</name>
|
|
<description>Time Slot 1 Input Channel. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (RESERVED).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (RESERVED).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB0.0).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB0.1).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB0.2).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB0.3).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.4).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB0.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB0.6).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (PB0.8).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB0.9).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (RESERVED).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (VSS).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (1.8V Output of LDO).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VDD).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS2CHR</name>
|
|
<description>Time Slot 2 Conversion Characteristic. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 2.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS2MUX</name>
|
|
<description>Time Slot 2 Input Channel. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (RESERVED).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (RESERVED).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB0.0).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB0.1).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB0.2).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB0.3).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.4).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB0.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB0.6).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (PB0.8).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB0.9).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (RESERVED).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (VSS).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (1.8V Output of LDO).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VDD).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS3CHR</name>
|
|
<description>Time Slot 3 Conversion Characteristic. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 3.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 3.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS3MUX</name>
|
|
<description>Time Slot 3 Input Channel. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (RESERVED).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (RESERVED).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB0.0).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB0.1).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB0.2).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB0.3).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.4).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB0.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB0.6).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (PB0.8).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB0.9).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (RESERVED).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.0 Output (IVC0C0)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (VSS).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (1.8V Output of LDO).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VDD).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHAR32</name>
|
|
<description>Conversion Characteristic 2 and 3 Setup</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHR2GN</name>
|
|
<description>Conversion Characteristic 2 Gain. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNITY</name>
|
|
<description>The on-chip PGA gain is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>The on-chip PGA gain is 0.5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR2RPT</name>
|
|
<description>Conversion Characteristic 2 Repeat Counter. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACC1</name>
|
|
<description>Accumulate one sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC4</name>
|
|
<description>Accumulate four samples.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC8</name>
|
|
<description>Accumulate eight samples.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC16</name>
|
|
<description>Accumulate sixteen samples.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC32</name>
|
|
<description>Accumulate thirty-two samples (10-bit mode only).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC64</name>
|
|
<description>Accumulate sixty-four samples (10-bit mode only).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR2LS</name>
|
|
<description>Conversion Characteristic 2 Left-Shift Bits. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHR2RSEL</name>
|
|
<description>Conversion Characteristic 2 Resolution Selection. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>B10</name>
|
|
<description>Select 10-bit Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>B12</name>
|
|
<description>Select 12-bit Mode (burst mode must be enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR2WCIEN</name>
|
|
<description>Conversion Characteristic 2 Window Comparator Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable window comparison interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR3GN</name>
|
|
<description>Conversion Characteristic 3 Gain. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNITY</name>
|
|
<description>The on-chip PGA gain is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>The on-chip PGA gain is 0.5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR3RPT</name>
|
|
<description>Conversion Characteristic 3 Repeat Counter. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACC1</name>
|
|
<description>Accumulate one sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC4</name>
|
|
<description>Accumulate four samples.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC8</name>
|
|
<description>Accumulate eight samples.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC16</name>
|
|
<description>Accumulate sixteen samples.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC32</name>
|
|
<description>Accumulate thirty-two samples (10-bit mode only).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC64</name>
|
|
<description>Accumulate sixty-four samples (10-bit mode only).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR3LS</name>
|
|
<description>Conversion Characteristic 3 Left-Shift Bits. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHR3RSEL</name>
|
|
<description>Conversion Characteristic 3 Resolution Selection. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>B10</name>
|
|
<description>Select 10-bit Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>B12</name>
|
|
<description>Select 12-bit Mode (burst mode must be enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR3WCIEN</name>
|
|
<description>Conversion Characteristic 3 Window Comparator Interrupt Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable window comparison interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHAR10</name>
|
|
<description>Conversion Characteristic 0 and 1 Setup</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHR0GN</name>
|
|
<description>Conversion Characteristic 0 Gain. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNITY</name>
|
|
<description>The on-chip PGA gain is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>The on-chip PGA gain is 0.5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR0RPT</name>
|
|
<description>Conversion Characteristic 0 Repeat Counter. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACC1</name>
|
|
<description>Accumulate one sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC4</name>
|
|
<description>Accumulate four samples.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC8</name>
|
|
<description>Accumulate eight samples.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC16</name>
|
|
<description>Accumulate sixteen samples.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC32</name>
|
|
<description>Accumulate thirty-two samples (10-bit mode only).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC64</name>
|
|
<description>Accumulate sixty-four samples (10-bit mode only).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR0LS</name>
|
|
<description>Conversion Characteristic 0 Left-Shift Bits. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHR0RSEL</name>
|
|
<description>Conversion Characteristic 0 Resolution Selection. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>B10</name>
|
|
<description>Select 10-bit Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>B12</name>
|
|
<description>Select 12-bit Mode (burst mode must be enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR0WCIEN</name>
|
|
<description>Conversion Characteristic 0 Window Comparator Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable window comparison interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR1GN</name>
|
|
<description>Conversion Characteristic 1 Gain. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNITY</name>
|
|
<description>The on-chip PGA gain is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>The on-chip PGA gain is 0.5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR1RPT</name>
|
|
<description>Conversion Characteristic 1 Repeat Counter. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACC1</name>
|
|
<description>Accumulate one sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC4</name>
|
|
<description>Accumulate four samples.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC8</name>
|
|
<description>Accumulate eight samples.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC16</name>
|
|
<description>Accumulate sixteen samples.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC32</name>
|
|
<description>Accumulate thirty-two samples (10-bit mode only).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC64</name>
|
|
<description>Accumulate sixty-four samples (10-bit mode only).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR1LS</name>
|
|
<description>Conversion Characteristic 1 Left-Shift Bits. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHR1RSEL</name>
|
|
<description>Conversion Characteristic 1 Resolution Selection. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>B10</name>
|
|
<description>Select 10-bit Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>B12</name>
|
|
<description>Select 12-bit Mode (burst mode must be enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR1WCIEN</name>
|
|
<description>Conversion Characteristic 1 Window Comparator Interrupt Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable window comparison interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Output Data Word</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Output Data Word. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WCLIMITS</name>
|
|
<description>Window Comparator Limits</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WCLT</name>
|
|
<description>Less-Than Window Comparator Limit. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCGT</name>
|
|
<description>Greater-Than Window Comparator Limit. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACC</name>
|
|
<description>Accumulator Initial Value</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>Accumulator Initial Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WCI</name>
|
|
<description>Window Compare Interrupt. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A window compare interrupt has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A window compare interrupt occurred. Write: Force a window compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCCI</name>
|
|
<description>Single Conversion Complete Interrupt. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A single data conversion interrupt has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A single data conversion interrupt occurred. Write: Force a single data conversion interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDI</name>
|
|
<description>Scan Done Interrupt. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A scan done interrupt has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A scan done interrupt occurred. Write: Force a scan done interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORI</name>
|
|
<description>FIFO Overrun Interrupt. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A data FIFO overrun interrupt has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A data FIFO overrun interrupt occurred. Write: Force a data FIFO overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FURI</name>
|
|
<description>FIFO Underrun Interrupt. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A data FIFO underrun interrupt has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A data FIFO underrun interrupt occurred. Write: Force a data FIFO underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOSTATUS</name>
|
|
<description>FIFO Status</description>
|
|
<addressOffset>0xa0</addressOffset>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOLVL</name>
|
|
<description>FIFO Level. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DPSTS</name>
|
|
<description>Data Packing Status. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOWER</name>
|
|
<description>The next ADC conversion will be written to the lower half-word.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPPER</name>
|
|
<description>The next ADC conversion will be written to the upper half-word.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRDYF</name>
|
|
<description>Data Ready Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>New data is not produced yet.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>New data is ready.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SARADC_1</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>ADC</groupName>
|
|
<baseAddress>0x4001b000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SARADC1_IRQn</name>
|
|
<value>36</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPSEL</name>
|
|
<description>Sampling Phase Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PHASE0</name>
|
|
<description>The ADC samples at SSG phase 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE1</name>
|
|
<description>The ADC samples at SSG phase 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE2</name>
|
|
<description>The ADC samples at SSG phase 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE3</name>
|
|
<description>The ADC samples at SSG phase 3.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE4</name>
|
|
<description>The ADC samples at SSG phase 4.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE5</name>
|
|
<description>The ADC samples at SSG phase 5.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE6</name>
|
|
<description>The ADC samples at SSG phase 6.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE7</name>
|
|
<description>The ADC samples at SSG phase 7.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE8</name>
|
|
<description>The ADC samples at SSG phase 8.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE9</name>
|
|
<description>The ADC samples at SSG phase 9.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE10</name>
|
|
<description>The ADC samples at SSG phase 10.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE11</name>
|
|
<description>The ADC samples at SSG phase 11.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE12</name>
|
|
<description>The ADC samples at SSG phase 12.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE13</name>
|
|
<description>The ADC samples at SSG phase 13.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE14</name>
|
|
<description>The ADC samples at SSG phase 14.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHASE15</name>
|
|
<description>The ADC samples at SSG phase 15.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEN</name>
|
|
<description>Sampling Phase Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Phase Select. The ADC will always sample on the start-of-conversion trigger selected by the SCSEL field.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Phase Select. The ADC will sample according to the phase selected by the SPSEL field.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGEN</name>
|
|
<description>Synchronous Sample Generator Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the SAR clock output to SSG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The ADC is the SSG master, and the SAR clock will be output to the SSG block.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PACKMD</name>
|
|
<description>Output Packing Mode. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UPPER_ONLY</name>
|
|
<description>Data is written to the upper half-word and the lower half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOWER_ONLY</name>
|
|
<description>Data is written to the lower half-word, and the upper half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPPER_FIRST</name>
|
|
<description>Two data words are packed into the register with the upper half-word representing the earlier data, and the lower half-word representing the later data. If SIMCEN is set to 1, the upper half-word represents data from the master ADC (selected by SSGEN) and the lower half-word represents data from the slave ADC. The ADC write to the lower half-word will trigger the SCI interrupt, if enabled.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOWER_FIRST</name>
|
|
<description>Two data words are packed into the register with the lower half-word representing the earlier data, and the upper half-word representing the later data. If SIMCEN is set to 1, the lower half-word represents data from the master ADC (selected by SSGEN) and the upper half-word represents data from the slave ADC. The ADC write to the upper half-word will trigger the SCI interrupt, if enabled.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIMCEN</name>
|
|
<description>Simultaneous Conversion Packing Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable simultaneous mode conversion packing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable simultaneous mode conversion packing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTLVEN</name>
|
|
<description>Interleaved Conversion Packing Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable interleaved mode conversion packing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable interleaved mode conversion packing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCANEN</name>
|
|
<description>Scan Mode Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable ADC scan mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable ADC scan mode. The ADC will scan through the defined time slots in sequence on every start of conversion.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCANMD</name>
|
|
<description>Scan Mode Select. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONCE</name>
|
|
<description>The channel sequencer will cycle through all of the specified time slots once.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOOP</name>
|
|
<description>The channel sequencer will cycle through all of the specified time slots in a loop until SCANEN is cleared to 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Interface Enable . </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the ADC module DMA interface.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the ADC module DMA interface.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCLKSEL</name>
|
|
<description>Burst Mode Clock Select. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPOSC0</name>
|
|
<description>Burst mode uses the Low Power Oscillator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>APB</name>
|
|
<description>Burst mode uses the APB clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>SAR Clock Divider. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCCIEN</name>
|
|
<description>Single Conversion Complete Interrupt Enable. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the ADC single data conversion complete interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the ADC single data conversion complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDIEN</name>
|
|
<description>Scan Done Interrupt Enable. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the ADC scan complete interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the ADC scan complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORIEN</name>
|
|
<description>FIFO Overrun Interrupt Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the data FIFO overrun interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the data FIFO overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FURIEN</name>
|
|
<description>FIFO Underrun Interrupt Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the data FIFO underrun interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the data FIFO underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Measurement Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x1008F078</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFGNDSEL</name>
|
|
<description>Reference Ground Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTERNAL</name>
|
|
<description>The internal device ground is used as the ground reference for ADC conversions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTERNAL</name>
|
|
<description>The VREFGND pin is used as the ground reference for ADC conversions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKESEL</name>
|
|
<description>Sampling Clock Edge Select. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Select the rising edge of the APB clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Select the falling edge of the APB clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BMTK</name>
|
|
<description>Burst Mode Tracking Time. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCSEL</name>
|
|
<description>Start-Of-Conversion Source Select. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCNT0</name>
|
|
<description>An ADC conversion triggers from the ADCnT0 ("On Demand" by writing 1 to ADBUSY) trigger source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT1</name>
|
|
<description>An ADC conversion triggers from the ADCnT1 (Timer 0 Low Overflow) trigger source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT2</name>
|
|
<description>An ADC conversion triggers from the ADCnT2 (Timer 0 High Overflow) trigger source.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT3</name>
|
|
<description>An ADC conversion triggers from the ADCnT3 (Timer 1 Low Overflow) trigger source.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT4</name>
|
|
<description>An ADC conversion triggers from the ADCnT4 (Timer 1 High Overflow) trigger source.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT5</name>
|
|
<description>An ADC conversion triggers from the ADCnT5 (EPCA0 synchronization pulse) trigger source.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT6</name>
|
|
<description>An ADC conversion triggers from the ADCnT6 (I2C0 Timer overflow) trigger source.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT7</name>
|
|
<description>An ADC conversion triggers from the ADCnT7 (I2C1 Timer overflow) trigger source.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT8</name>
|
|
<description>An ADC conversion triggers from the ADCnT8 (SSG phase defined by ADSP bits) trigger source.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT9</name>
|
|
<description>An ADC conversion triggers from the ADCnT9 (RESERVED) trigger source.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT10</name>
|
|
<description>An ADC conversion triggers from the ADCnT10 (RESERVED) trigger source.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT11</name>
|
|
<description>An ADC conversion triggers from the ADCnT11 (RESERVED) trigger source.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT12</name>
|
|
<description>An ADC conversion triggers from the ADCnT12 (RESERVED) trigger source.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT13</name>
|
|
<description>An ADC conversion triggers from the ADCnT13 (RESERVED) trigger source.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT14</name>
|
|
<description>An ADC conversion triggers from the ADCnT14 (RESERVED) trigger source.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCNT15</name>
|
|
<description>An ADC conversion triggers from the ADCnT15 (PB1.7) trigger source.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWRTIME</name>
|
|
<description>Burst Mode Power Up Time. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BURSTEN</name>
|
|
<description>Burst Mode Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable burst mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable burst mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCEN</name>
|
|
<description>ADC Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the ADC (low-power shutdown).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the ADC (active and ready for data conversions).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AD12BSSEL</name>
|
|
<description>12-Bit Mode Sample Select. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>The ADC re-samples the input before each of the four conversions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>The ADC samples once before the first conversion and converts four times.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VCMEN</name>
|
|
<description>Common Mode Buffer Enable. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the common mode buffer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the common mode buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACCMD</name>
|
|
<description>Accumulation Mode. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACCUMULATE</name>
|
|
<description>Conversions will be accumulated for the specified number of cycles in burst mode according to the channel configuration.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEAT</name>
|
|
<description>Conversions will not be accumulated in burst mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRKMD</name>
|
|
<description>ADC Tracking Mode. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal Tracking Mode: When the ADC is enabled, a conversion begins immediately following the start-of-conversion signal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DELAYED</name>
|
|
<description>Delayed Tracking Mode: When the ADC is enabled, a conversion begins 3 SAR clock cycles following the start-of-conversion signal. The ADC is allowed to track during this time.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADBUSY</name>
|
|
<description>ADC Busy. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIASSEL</name>
|
|
<description>Bias Power Select. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>Select bias current mode 0. Recommended to use modes 1, 2, or 3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>Select bias current mode 1 (SARCLK = 16 MHz).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>Select bias current mode 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>Select bias current mode 3 (SARCLK = 4 MHz).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPMDEN</name>
|
|
<description>Low Power Mode Enable. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable low power mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable low power mode (requires extended tracking time).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MREFLPEN</name>
|
|
<description>MUX and VREF Low Power Enable. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable low power mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable low power mode (SAR clock <= 4 MHz).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREFSEL</name>
|
|
<description>Voltage Reference Select. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_VREF</name>
|
|
<description>Select the internal, dedicated SARADC voltage reference as the ADC reference.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDD</name>
|
|
<description>Select the VDD pin as the ADC reference.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDO_OUT</name>
|
|
<description>Select the output of the internal LDO regulator (~1.8 V) as the ADC reference.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTERNAL_VREF</name>
|
|
<description>Select the VREF pin as the ADC reference. This option is used for either an external VREF or the on-chip VREF driving out to the VREF pin.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQ7654</name>
|
|
<description>Channel Sequencer Time Slots 4-7 Setup</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TS4CHR</name>
|
|
<description>Time Slot 4 Conversion Characteristic. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 4.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 4.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 4.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS4MUX</name>
|
|
<description>Time Slot 4 Input Channel. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (PB1.11).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (PB1.10).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB1.9).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB1.8).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB1.7).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB1.6).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.10).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB1.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB1.4).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (RESERVED).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB1.3).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (PB1.2).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.1 Output (IVC0C1)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (Voltage at VREGIN / 4).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (EXTVREG0 Current Sense).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VIO).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS5CHR</name>
|
|
<description>Time Slot 5 Conversion Characteristic. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 5.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 5.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 5.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS5MUX</name>
|
|
<description>Time Slot 5 Input Channel. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (PB1.11).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (PB1.10).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB1.9).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB1.8).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB1.7).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB1.6).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.10).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB1.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB1.4).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (RESERVED).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB1.3).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (PB1.2).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.1 Output (IVC0C1)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (Voltage at VREGIN / 4).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (EXTVREG0 Current Sense).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VIO).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS6CHR</name>
|
|
<description>Time Slot 6 Conversion Characteristic. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 6.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 6.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 6.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 6.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS6MUX</name>
|
|
<description>Time Slot 6 Input Channel. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (PB1.11).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (PB1.10).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB1.9).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB1.8).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB1.7).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB1.6).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.10).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB1.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB1.4).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (RESERVED).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB1.3).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (PB1.2).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.1 Output (IVC0C1)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (Voltage at VREGIN / 4).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (EXTVREG0 Current Sense).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VIO).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS7CHR</name>
|
|
<description>Time Slot 7 Conversion Characteristic. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 7.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 7.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 7.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS7MUX</name>
|
|
<description>Time Slot 7 Input Channel. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (PB1.11).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (PB1.10).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB1.9).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB1.8).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB1.7).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB1.6).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.10).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB1.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB1.4).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (RESERVED).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB1.3).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (PB1.2).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.1 Output (IVC0C1)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (Voltage at VREGIN / 4).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (EXTVREG0 Current Sense).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VIO).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQ3210</name>
|
|
<description>Channel Sequencer Time Slots 0-3 Setup</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TS0CHR</name>
|
|
<description>Time Slot 0 Conversion Characteristic. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 0.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 0.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS0MUX</name>
|
|
<description>Time Slot 0 Input Channel. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (PB1.11).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (PB1.10).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB1.9).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB1.8).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB1.7).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB1.6).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.10).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB1.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB1.4).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (RESERVED).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB1.3).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (PB1.2).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.1 Output (IVC0C1)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (Voltage at VREGIN / 4).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (EXTVREG0 Current Sense).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VIO).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS1CHR</name>
|
|
<description>Time Slot 1 Conversion Characteristic. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 1.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 1.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS1MUX</name>
|
|
<description>Time Slot 1 Input Channel. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (PB1.11).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (PB1.10).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB1.9).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB1.8).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB1.7).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB1.6).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.10).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB1.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB1.4).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (RESERVED).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB1.3).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (PB1.2).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.1 Output (IVC0C1)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (Voltage at VREGIN / 4).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (EXTVREG0 Current Sense).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VIO).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS2CHR</name>
|
|
<description>Time Slot 2 Conversion Characteristic. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 2.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS2MUX</name>
|
|
<description>Time Slot 2 Input Channel. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (PB1.11).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (PB1.10).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB1.9).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB1.8).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB1.7).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB1.6).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.10).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB1.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB1.4).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (RESERVED).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB1.3).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (PB1.2).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.1 Output (IVC0C1)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (Voltage at VREGIN / 4).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (EXTVREG0 Current Sense).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VIO).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS3CHR</name>
|
|
<description>Time Slot 3 Conversion Characteristic. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CC0</name>
|
|
<description>Select conversion characteristic 0 for time slot 3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Select conversion characteristic 1 for time slot 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC2</name>
|
|
<description>Select conversion characteristic 2 for time slot 3.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC3</name>
|
|
<description>Select conversion characteristic 3 for time slot 3.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TS3MUX</name>
|
|
<description>Time Slot 3 Input Channel. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCN0</name>
|
|
<description>Select channel ADCn.0 (PB1.11).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN1</name>
|
|
<description>Select channel ADCn.1 (PB1.10).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN2</name>
|
|
<description>Select channel ADCn.2 (PB1.9).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN3</name>
|
|
<description>Select channel ADCn.3 (PB1.8).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN4</name>
|
|
<description>Select channel ADCn.4 (PB1.7).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN5</name>
|
|
<description>Select channel ADCn.5 (PB1.6).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN6</name>
|
|
<description>Select channel ADCn.6 (PB0.10).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN7</name>
|
|
<description>Select channel ADCn.7 (PB1.5).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN8</name>
|
|
<description>Select channel ADCn.8 (PB1.4).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN9</name>
|
|
<description>Select channel ADCn.9 (RESERVED).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN10</name>
|
|
<description>Select channel ADCn.10 (PB1.3).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN11</name>
|
|
<description>Select channel ADCn.11 (PB1.2).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN12</name>
|
|
<description>Select channel ADCn.12 (PB0.14).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN13</name>
|
|
<description>Select channel ADCn.13 (PB0.15).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN14</name>
|
|
<description>Select channel ADCn.14 (PB1.0).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN15</name>
|
|
<description>Select channel ADCn.15 (PB1.1).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN16</name>
|
|
<description>Select channel ADCn.16 (IVC0.1 Output (IVC0C1)).</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN17</name>
|
|
<description>Select channel ADCn.17 (Voltage at VREGIN / 4).</description>
|
|
<value>17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN18</name>
|
|
<description>Select channel ADCn.18 (EXTVREG0 Current Sense).</description>
|
|
<value>18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN19</name>
|
|
<description>Select channel ADCn.19 (VIO).</description>
|
|
<value>19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN20</name>
|
|
<description>Select channel ADCn.20 (Temperature Sensor Output).</description>
|
|
<value>20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN21</name>
|
|
<description>Select channel ADCn.21 (VIOHD / 4).</description>
|
|
<value>21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN22</name>
|
|
<description>Select channel ADCn.22 (RESERVED).</description>
|
|
<value>22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN23</name>
|
|
<description>Select channel ADCn.23 (RESERVED).</description>
|
|
<value>23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN24</name>
|
|
<description>Select channel ADCn.24 (RESERVED).</description>
|
|
<value>24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN25</name>
|
|
<description>Select channel ADCn.25 (RESERVED).</description>
|
|
<value>25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN26</name>
|
|
<description>Select channel ADCn.26 (RESERVED).</description>
|
|
<value>26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN27</name>
|
|
<description>Select channel ADCn.27 (RESERVED).</description>
|
|
<value>27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN28</name>
|
|
<description>Select channel ADCn.28 (RESERVED).</description>
|
|
<value>28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN29</name>
|
|
<description>Select channel ADCn.29 (RESERVED).</description>
|
|
<value>29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCN30</name>
|
|
<description>Select channel ADCn.30 (RESERVED).</description>
|
|
<value>30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>END</name>
|
|
<description>None - End the sequence.</description>
|
|
<value>31</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHAR32</name>
|
|
<description>Conversion Characteristic 2 and 3 Setup</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHR2GN</name>
|
|
<description>Conversion Characteristic 2 Gain. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNITY</name>
|
|
<description>The on-chip PGA gain is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>The on-chip PGA gain is 0.5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR2RPT</name>
|
|
<description>Conversion Characteristic 2 Repeat Counter. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACC1</name>
|
|
<description>Accumulate one sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC4</name>
|
|
<description>Accumulate four samples.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC8</name>
|
|
<description>Accumulate eight samples.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC16</name>
|
|
<description>Accumulate sixteen samples.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC32</name>
|
|
<description>Accumulate thirty-two samples (10-bit mode only).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC64</name>
|
|
<description>Accumulate sixty-four samples (10-bit mode only).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR2LS</name>
|
|
<description>Conversion Characteristic 2 Left-Shift Bits. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHR2RSEL</name>
|
|
<description>Conversion Characteristic 2 Resolution Selection. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>B10</name>
|
|
<description>Select 10-bit Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>B12</name>
|
|
<description>Select 12-bit Mode (burst mode must be enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR2WCIEN</name>
|
|
<description>Conversion Characteristic 2 Window Comparator Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable window comparison interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR3GN</name>
|
|
<description>Conversion Characteristic 3 Gain. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNITY</name>
|
|
<description>The on-chip PGA gain is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>The on-chip PGA gain is 0.5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR3RPT</name>
|
|
<description>Conversion Characteristic 3 Repeat Counter. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACC1</name>
|
|
<description>Accumulate one sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC4</name>
|
|
<description>Accumulate four samples.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC8</name>
|
|
<description>Accumulate eight samples.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC16</name>
|
|
<description>Accumulate sixteen samples.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC32</name>
|
|
<description>Accumulate thirty-two samples (10-bit mode only).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC64</name>
|
|
<description>Accumulate sixty-four samples (10-bit mode only).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR3LS</name>
|
|
<description>Conversion Characteristic 3 Left-Shift Bits. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHR3RSEL</name>
|
|
<description>Conversion Characteristic 3 Resolution Selection. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>B10</name>
|
|
<description>Select 10-bit Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>B12</name>
|
|
<description>Select 12-bit Mode (burst mode must be enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR3WCIEN</name>
|
|
<description>Conversion Characteristic 3 Window Comparator Interrupt Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable window comparison interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHAR10</name>
|
|
<description>Conversion Characteristic 0 and 1 Setup</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHR0GN</name>
|
|
<description>Conversion Characteristic 0 Gain. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNITY</name>
|
|
<description>The on-chip PGA gain is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>The on-chip PGA gain is 0.5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR0RPT</name>
|
|
<description>Conversion Characteristic 0 Repeat Counter. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACC1</name>
|
|
<description>Accumulate one sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC4</name>
|
|
<description>Accumulate four samples.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC8</name>
|
|
<description>Accumulate eight samples.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC16</name>
|
|
<description>Accumulate sixteen samples.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC32</name>
|
|
<description>Accumulate thirty-two samples (10-bit mode only).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC64</name>
|
|
<description>Accumulate sixty-four samples (10-bit mode only).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR0LS</name>
|
|
<description>Conversion Characteristic 0 Left-Shift Bits. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHR0RSEL</name>
|
|
<description>Conversion Characteristic 0 Resolution Selection. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>B10</name>
|
|
<description>Select 10-bit Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>B12</name>
|
|
<description>Select 12-bit Mode (burst mode must be enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR0WCIEN</name>
|
|
<description>Conversion Characteristic 0 Window Comparator Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable window comparison interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR1GN</name>
|
|
<description>Conversion Characteristic 1 Gain. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNITY</name>
|
|
<description>The on-chip PGA gain is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>The on-chip PGA gain is 0.5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR1RPT</name>
|
|
<description>Conversion Characteristic 1 Repeat Counter. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACC1</name>
|
|
<description>Accumulate one sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC4</name>
|
|
<description>Accumulate four samples.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC8</name>
|
|
<description>Accumulate eight samples.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC16</name>
|
|
<description>Accumulate sixteen samples.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC32</name>
|
|
<description>Accumulate thirty-two samples (10-bit mode only).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC64</name>
|
|
<description>Accumulate sixty-four samples (10-bit mode only).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR1LS</name>
|
|
<description>Conversion Characteristic 1 Left-Shift Bits. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHR1RSEL</name>
|
|
<description>Conversion Characteristic 1 Resolution Selection. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>B10</name>
|
|
<description>Select 10-bit Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>B12</name>
|
|
<description>Select 12-bit Mode (burst mode must be enabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHR1WCIEN</name>
|
|
<description>Conversion Characteristic 1 Window Comparator Interrupt Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable window comparison interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Output Data Word</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Output Data Word. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WCLIMITS</name>
|
|
<description>Window Comparator Limits</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WCLT</name>
|
|
<description>Less-Than Window Comparator Limit. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCGT</name>
|
|
<description>Greater-Than Window Comparator Limit. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACC</name>
|
|
<description>Accumulator Initial Value</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACC</name>
|
|
<description>Accumulator Initial Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WCI</name>
|
|
<description>Window Compare Interrupt. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A window compare interrupt has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A window compare interrupt occurred. Write: Force a window compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCCI</name>
|
|
<description>Single Conversion Complete Interrupt. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A single data conversion interrupt has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A single data conversion interrupt occurred. Write: Force a single data conversion interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDI</name>
|
|
<description>Scan Done Interrupt. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A scan done interrupt has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A scan done interrupt occurred. Write: Force a scan done interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORI</name>
|
|
<description>FIFO Overrun Interrupt. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A data FIFO overrun interrupt has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A data FIFO overrun interrupt occurred. Write: Force a data FIFO overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FURI</name>
|
|
<description>FIFO Underrun Interrupt. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A data FIFO underrun interrupt has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A data FIFO underrun interrupt occurred. Write: Force a data FIFO underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOSTATUS</name>
|
|
<description>FIFO Status</description>
|
|
<addressOffset>0xa0</addressOffset>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOLVL</name>
|
|
<description>FIFO Level. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DPSTS</name>
|
|
<description>Data Packing Status. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOWER</name>
|
|
<description>The next ADC conversion will be written to the lower half-word.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPPER</name>
|
|
<description>The next ADC conversion will be written to the upper half-word.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DRDYF</name>
|
|
<description>Data Ready Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>New data is not produced yet.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>New data is ready.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AES_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>AES_0</groupName>
|
|
<baseAddress>0x40027000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>AES0_IRQn</name>
|
|
<value>42</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFRSTA</name>
|
|
<description>AES Transfer Start. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start the AES operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEYCPEN</name>
|
|
<description>Key Capture Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable key capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable key capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDMD</name>
|
|
<description>Encryption/Decryption Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DECRYPT</name>
|
|
<description>AES module performs a decryption operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENCRYPT</name>
|
|
<description>AES module performs an encryption operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWMDEN</name>
|
|
<description>Software Mode Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable software mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable software mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEN</name>
|
|
<description>Bypass AES Operation Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not bypass AES operations.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Bypass AES operations.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XOREN</name>
|
|
<description>XOR Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XOR_DISABLED</name>
|
|
<description>Disable the XOR paths.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOR_INPUT</name>
|
|
<description>Enable the XOR input path, disable the XOR output path.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XOR_OUTPUT</name>
|
|
<description>Disable the XOR input path, enable the XOR output path.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HCTREN</name>
|
|
<description>Hardware Counter Mode Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable hardware counter mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable hardware counter mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HCBCEN</name>
|
|
<description>Hardware Cipher-Block Chaining Mode Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable hardware cipher-block chaining (CBC) mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable hardware cipher-block chaining (CBC) mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEYSIZE</name>
|
|
<description>Keystore Size Select. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KEY128</name>
|
|
<description>Key is composed of 128 bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KEY192</name>
|
|
<description>Key is composed of 192 bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KEY256</name>
|
|
<description>Key is composed of 256 bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERRIEN</name>
|
|
<description>Error Interrupt Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the error interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCIEN</name>
|
|
<description>Operation Complete Interrupt Enable. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the operation complete interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the operation complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>AES Debug Mode. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the AES module to halt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The AES module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>Module Soft Reset. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>AES module is not in soft reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>AES module is in soft reset and none of the module bits can be accessed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XFRSIZE</name>
|
|
<description>Number of Blocks</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFRSIZE</name>
|
|
<description>Transfer Size. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATAFIFO</name>
|
|
<description>Input/Output Data FIFO Access</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATAFIFO</name>
|
|
<description>Input/Output Data FIFO Access. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XORFIFO</name>
|
|
<description>XOR Data FIFO Access</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>XORFIFO</name>
|
|
<description>XOR Data FIFO Access. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWKEY0</name>
|
|
<description>Hardware Key Word 0</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWKEY0</name>
|
|
<description>Hardware Key Word 0. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWKEY1</name>
|
|
<description>Hardware Key Word 1</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWKEY1</name>
|
|
<description>Hardware Key Word 1. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWKEY2</name>
|
|
<description>Hardware Key Word 2</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWKEY2</name>
|
|
<description>Hardware Key Word 2. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWKEY3</name>
|
|
<description>Hardware Key Word 3</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWKEY3</name>
|
|
<description>Hardware Key Word 3. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWKEY4</name>
|
|
<description>Hardware Key Word 4</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWKEY4</name>
|
|
<description>Hardware Key Word 4. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWKEY5</name>
|
|
<description>Hardware Key Word 5</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWKEY5</name>
|
|
<description>Hardware Key Word 5. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWKEY6</name>
|
|
<description>Hardware Key Word 6</description>
|
|
<addressOffset>0xa0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWKEY6</name>
|
|
<description>Hardware Key Word 6. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWKEY7</name>
|
|
<description>Hardware Key Word 7</description>
|
|
<addressOffset>0xb0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWKEY7</name>
|
|
<description>Hardware Key Word 7. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWCTR0</name>
|
|
<description>Hardware Counter Word 0</description>
|
|
<addressOffset>0xc0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWCTR0</name>
|
|
<description>Hardware Counter Word 0. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWCTR1</name>
|
|
<description>Hardware Counter Word 1</description>
|
|
<addressOffset>0xd0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWCTR1</name>
|
|
<description>Hardware Counter Word 1. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWCTR2</name>
|
|
<description>Hardware Counter Word 2</description>
|
|
<addressOffset>0xe0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWCTR2</name>
|
|
<description>Hardware Counter Word 2. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWCTR3</name>
|
|
<description>Hardware Counter Word 3</description>
|
|
<addressOffset>0xf0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWCTR3</name>
|
|
<description>Hardware Counter Word 3. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DURF</name>
|
|
<description>Input/Output Data FIFO Underrun Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>No input/output data FIFO underrun.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>An input/output data FIFO underrun has occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DORF</name>
|
|
<description>Input/Output Data FIFO Overrun Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>No input/output data FIFO overrun.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>An input/output data FIFO overrun has occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XORF</name>
|
|
<description>XOR Data FIFO Overrun Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>No XOR data FIFO overrun.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>An XOR data FIFO overrun has occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFIFOLVL</name>
|
|
<description>Input/Output Data FIFO Level. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Input/Output data FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1WORD</name>
|
|
<description>Input/Output data FIFO contains 1 word.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2WORDS</name>
|
|
<description>Input/Output data FIFO contains 2 words.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3WORDS</name>
|
|
<description>Input/Output data FIFO contains 3 words.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>Input/Output data FIFO contains 4 words (full).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XFIFOLVL</name>
|
|
<description>XOR Data FIFO Level. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>XOR data FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1WORD</name>
|
|
<description>XOR data FIFO contains 1 word.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2WORDS</name>
|
|
<description>XOR data FIFO contains 2 words.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3WORDS</name>
|
|
<description>XOR data FIFO contains 3 words.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>XOR data FIFO contains 4 words (full).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSYF</name>
|
|
<description>Module Busy Flag. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>AES module is not busy.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>AES module is completing an operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERRI</name>
|
|
<description>Error Interrupt Flag. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>AES error interrupt has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>AES error interrupt has occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCI</name>
|
|
<description>Operation Complete Interrupt Flag. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>AES operation complete interrupt has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>AES operation complete interrupt occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRC_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>CRC_0</groupName>
|
|
<baseAddress>0x40028000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SINITEN</name>
|
|
<description>Seed Initialization Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not initialize the CRC module to the value set by the SEED bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Initialize the CRC module to the value set by the SEED bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEED</name>
|
|
<description>Seed Setting. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALL_ZEROES</name>
|
|
<description>CRC seed value is all 0's (0x00000000)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALL_ONES</name>
|
|
<description>CRC seed value is all 1's (0xFFFFFFFF).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>CRC Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable CRC operations.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable CRC operations.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLYSEL</name>
|
|
<description>Polynomial Selection. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CRC_32_04C11DB7</name>
|
|
<description>Select 32-bit polynomial: 0x04C11DB7.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_16_1021</name>
|
|
<description>Select 16-bit polynomial: 0x1021.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_16_3D65</name>
|
|
<description>Select 16-bit polynomial: 0x3D65.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC_16_8005</name>
|
|
<description>Select 16-bit polynomial: 0x8005.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BMDEN</name>
|
|
<description>Byte Mode Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable byte mode (word/byte width is determined automatically by the hardware).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable byte mode (all writes are considered as bytes).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BBREN</name>
|
|
<description>Byte-Level Bit Reversal Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>No byte-level bit reversal (input is same order as written).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Byte-level bit reversal enabled (the bits in each byte are reversed).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORDER</name>
|
|
<description>Input Processing Order. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_REORDER</name>
|
|
<description>No byte reorientation (output is same order as input).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIG_ENDIAN_16</name>
|
|
<description>Swap for 16-bit big endian order (input: B3 B2 B1 B0, output: B2 B3 B0 B1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIG_ENDIAN_32</name>
|
|
<description>Swap for 32-bit big endian order (input: B3 B2 B1 B0, output: B0 B1 B2 B3).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Input/Result Data</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Input/Result Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDATA</name>
|
|
<description>Bit-Reversed Output Data</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDATA</name>
|
|
<description>Bit-Reversed Output Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CAPSENSE_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>CAPSENSE_0</groupName>
|
|
<baseAddress>0x40023000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CAPSENSE0_IRQn</name>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000040</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSYF</name>
|
|
<description>Start and Busy Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>Read: A capacitive sensing conversion is complete or a conversion is not currently in progress. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUSY</name>
|
|
<description>Read: A capacitive sensing conversion is in progress. Write: Initiate a capacitive sensing conversion if BUSYF is selected as the start of conversion source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSEN</name>
|
|
<description>Module Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the capacitive sensing module.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the capacitive sensing module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BIASEN</name>
|
|
<description>Bias Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the bias.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the bias.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPPOL</name>
|
|
<description>Digital Comparator Polarity Select. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GT</name>
|
|
<description>The digital comparator generates an interrupt if the conversion is greater than the CSTH threshold.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LTE</name>
|
|
<description>The digital comparator generates an interrupt if the conversion is less than or equal to the CSTH threshold.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Conversion Mode Select. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>Single Conversion Mode: One conversion occurs on a single channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCAN</name>
|
|
<description>Single Scan Mode: One conversion on each channel selected by SCANEN occurs. An end-of-scan interrupt indicates all channels have been measured.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONT_SINGLE</name>
|
|
<description>Continuous Single Conversion Mode: Continuously converts on a single channel. This operation ends only if the module is disabled (CSEN = 0) or if a compare threshold event occurs (CMPI = 1).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONT_SCAN</name>
|
|
<description>Continuous Scan Mode: Continuously loops through and converts on all the channels selected by SCANEN. This operation ends only if the module is disabled (CSEN = 0) or if a compare threshold event occurs (CMPI = 1).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNVR</name>
|
|
<description>Conversion Rate. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>12BIT</name>
|
|
<description>Conversions last 12 internal CAPSENSE clocks and results are 12 bits in length.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>13BIT</name>
|
|
<description>Conversions last 13 internal CAPSENSE clocks and results are 13 bits in length.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>14BIT</name>
|
|
<description>Conversions last 14 internal CAPSENSE clocks and results are 14 bits in length.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16BIT</name>
|
|
<description>Conversions last 16 internal CAPSENSE clocks and results are 16 bits in length.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACCMD</name>
|
|
<description>Accumulator Mode Select. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACC_1</name>
|
|
<description>Accumulate 1 sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC_4</name>
|
|
<description>Accumulate 4 samples.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC_8</name>
|
|
<description>Accumulate 8 samples.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC_16</name>
|
|
<description>Accumulate 16 samples.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC_32</name>
|
|
<description>Accumulate 32 samples.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACC_64</name>
|
|
<description>Accumulate 64 samples.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCEN</name>
|
|
<description>Multiple Channel Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the multiple channel measurement feature.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the multiple channel measurement feature.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCM</name>
|
|
<description>Start of Conversion Mode Select. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CSNT0</name>
|
|
<description>The CSnT0 ("On Demand" by writing 1 to CSBUSY) trigger source starts conversions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT1</name>
|
|
<description>The CSnT1 (Timer 0 Low Overflow) trigger source starts conversions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT2</name>
|
|
<description>The CSnT2 (Timer 0 High Overflow) trigger source starts conversions.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT3</name>
|
|
<description>The CSnT3 (Timer 1 Low Overflow) trigger source starts conversions.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT4</name>
|
|
<description>The CSnT4 (Timer 1 High Overflow) trigger source starts conversions.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT5</name>
|
|
<description>The CSnT5 (I2C0 Timer Byte 1 Overflow) trigger source starts conversions.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT6</name>
|
|
<description>The CSnT6 (I2C0 Timer Byte 3 Overflow) trigger source starts conversions.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT7</name>
|
|
<description>The CSnT7 (I2C1 Timer Byte 1 Overflow) trigger source starts conversions.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT8</name>
|
|
<description>The CSnT8 (I2C1 Timer Byte 3 Overflow) trigger source starts conversions.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT9</name>
|
|
<description>The CSnT9 (RESERVED) trigger source starts conversions.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT10</name>
|
|
<description>The CSnT10 (RESERVED) trigger source starts conversions.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT11</name>
|
|
<description>The CSnT11 (RESERVED) trigger source starts conversions.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT12</name>
|
|
<description>The CSnT12 (RESERVED) trigger source starts conversions.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT13</name>
|
|
<description>The CSnT13 (RESERVED) trigger source starts conversions.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT14</name>
|
|
<description>The CSnT14 (RESERVED) trigger source starts conversions.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSNT15</name>
|
|
<description>The CSnT15 (RESERVED) trigger source starts conversions.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMMD</name>
|
|
<description>Pin Monitor Mode. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALWAYS_RETRY</name>
|
|
<description>Always retry on a pin state change.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRY_TWICE</name>
|
|
<description>Retry up to twice on consecutive bit cycles.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETRY_FOUR_TIMES</name>
|
|
<description>Retry up to four times on consecutive bit cycles.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_RETRY</name>
|
|
<description>Ignore monitored signal state change.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMEF</name>
|
|
<description>Pin Monitor Event Flag. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A retry did not occur due to a pin monitor event during the last conversion.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A retry occurred due to a pin monitor event during the last conversion.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPEN</name>
|
|
<description>Threshold Comparator Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the threshold comparator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the threshold comparator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDIEN</name>
|
|
<description>Conversion Done Interrupt Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the single conversion done interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the single conversion done interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOSIEN</name>
|
|
<description>End-of-Scan Interrupt Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the single scan end-of-scan interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the single scan end-of-scan interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPI</name>
|
|
<description>Threshold Comparator Interrupt Flag. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The capacitive sensing result did not cause a compare threshold interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The capacitive sensing result caused a compare threshold interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDI</name>
|
|
<description>Conversion Done Interrupt Flag. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: The CAPSENSEn module has not completed a data conversion since the last time CDI was cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: The CAPSENSEn module completed a data conversion. Write: Force a conversion complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOSI</name>
|
|
<description>End-of-Scan Interrupt Flag. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The CAPSENSEn module has not completed a scan since the last time EOSI was cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The CAPSENSEn module completed a scan.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Measurement Mode</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000007</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CGSEL</name>
|
|
<description>Capacitance Gain Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRSEL</name>
|
|
<description>Double Reset Select. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAMPSEL</name>
|
|
<description>Ramp Selection. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IASEL</name>
|
|
<description>Output Current Select. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTSEL</name>
|
|
<description>Discharge Time Select. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPFSEL</name>
|
|
<description>Low Pass Filter Select. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Measurement Data</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Capacitive Sensing Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCAN</name>
|
|
<description>Channel Scan Enable</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCANEN</name>
|
|
<description>Channel Scan Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSTH</name>
|
|
<description>Compare Threshold</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTH</name>
|
|
<description>Compare Threshold. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MUX</name>
|
|
<description>Mux Channel Select</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSMX</name>
|
|
<description>Mux Channel Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CSN0</name>
|
|
<description>Select CSn.0 (RESERVED).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN1</name>
|
|
<description>Select CSn.1 (PB0.0).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN2</name>
|
|
<description>Select CSn.2 (PB0.1).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN3</name>
|
|
<description>Select CSn.3 (PB0.2).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN4</name>
|
|
<description>Select CSn.4 (PB0.3).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN5</name>
|
|
<description>Select CSn.5 (PB0.4).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN6</name>
|
|
<description>Select CSn.6 (PB0.5).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN7</name>
|
|
<description>Select CSn.7 (PB0.6).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN8</name>
|
|
<description>Select CSn.8 (PB1.2).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN9</name>
|
|
<description>Select CSn.9 (PB1.3).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN10</name>
|
|
<description>Select CSn.10 (PB1.6).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN11</name>
|
|
<description>Select CSn.11 (PB1.7).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN12</name>
|
|
<description>Select CSn.12 (PB1.8).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN13</name>
|
|
<description>Select CSn.13 (PB1.9).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN14</name>
|
|
<description>Select CSn.14 (PB1.10).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSN15</name>
|
|
<description>Select CSn.15 (PB.11).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSDISC</name>
|
|
<description>Channel Disconnect. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONNECT</name>
|
|
<description>Connect the capacitive sensing circuit to the selected channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCONNECT</name>
|
|
<description>Disconnect the capacitive sensing input channel.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CLKCTRL_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>CLKCTRL_0</groupName>
|
|
<baseAddress>0x4002d000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x10000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AHBSEL</name>
|
|
<description>AHB Clock Source Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPOSC0</name>
|
|
<description>AHB clock source is the Low-Power Oscillator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFOSC0</name>
|
|
<description>AHB clock source is the Low-Frequency Oscillator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC0OSC</name>
|
|
<description>AHB clock source is the RTC Oscillator.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTOSC0</name>
|
|
<description>AHB clock source is the External Oscillator.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB0OSC</name>
|
|
<description>AHB clock source is the USB Oscillator.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0OSC</name>
|
|
<description>AHB clock source is the PLL.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPOSC0_DIV</name>
|
|
<description>AHB clock source is a divided version of the Low-Power Oscillator.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AHBDIV</name>
|
|
<description>AHB Clock Divider. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>AHB clock divided by 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>AHB clock divided by 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>AHB clock divided by 4.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>AHB clock divided by 8.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>AHB clock divided by 16.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>AHB clock divided by 32.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>AHB clock divided by 64.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>AHB clock divided by 128.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>APBDIV</name>
|
|
<description>APB Clock Divider. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>APB clock is the same as the AHB clock (divided by 1).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>APB clock is the AHB clock divided by 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTESEL</name>
|
|
<description>External Clock Edge Select. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BOTH_EDGES</name>
|
|
<description>External clock generated by both rising and falling edges of the external oscillator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_ONLY</name>
|
|
<description>External clock generated by only rising edges of the external oscillator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OBUSYF</name>
|
|
<description>Oscillators Busy Flag. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>AHB and APB oscillators are not busy.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>AHB and APB oscillators are busy and the AHBSEL, AHBDIV, and APBDIV fields should not be modified.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBCLKG</name>
|
|
<description>AHB Clock Gate</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000005</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAMCEN</name>
|
|
<description>RAM Clock Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the AHB clock to the RAM.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the AHB clock to the RAM (default).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMACEN</name>
|
|
<description>DMA Controller Clock Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the AHB clock to the DMA Controller (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the AHB clock to the DMA Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASHCEN</name>
|
|
<description>Flash Clock Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the AHB clock to the Flash.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the AHB clock to the Flash (default).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMIF0CEN</name>
|
|
<description>EMIF Clock Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the AHB clock to the External Memory Interface (EMIF) (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the AHB clock to the External Memory Interface (EMIF).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB0BCEN</name>
|
|
<description>USB0 Buffer Clock Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the AHB clock to the USB0 Buffer (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the AHB clock to the USB0 Buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBCLKG0</name>
|
|
<description>APB Clock Gate 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PLL0CEN</name>
|
|
<description>PLL Module Clock Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the PLL0 registers (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the PLL0 registers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB0CEN</name>
|
|
<description>Port Bank Module Clock Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the Port Bank Modules (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the Port Bank Modules.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART0CEN</name>
|
|
<description>USART0 Module Clock Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the USART0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the USART0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART1CEN</name>
|
|
<description>USART1 Module Clock Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the USART1 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the USART1 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0CEN</name>
|
|
<description>UART0 Module Clock Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the UART0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the UART0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART1CEN</name>
|
|
<description>UART1 Module Clock Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the UART1 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the UART1 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI0CEN</name>
|
|
<description>SPI0 Module Clock Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the SPI0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the SPI0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI1CEN</name>
|
|
<description>SPI1 Module Clock Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the SPI1 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the SPI1 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI2CEN</name>
|
|
<description>SPI2 Module Clock Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the SPI2 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the SPI2 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C0CEN</name>
|
|
<description>I2C0 Module Clock Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the I2C0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the I2C0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C1CEN</name>
|
|
<description>I2C1 Module Clock Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the I2C1 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the I2C1 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPCA0CEN</name>
|
|
<description>EPCA0 Module Clock Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the EPCA0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the EPCA0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCA0CEN</name>
|
|
<description>PCA0 Module Clock Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the PCA0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the PCA0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCA1CEN</name>
|
|
<description>PCA1 Module Clock Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the PCA1 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the PCA1 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSG0CEN</name>
|
|
<description>SSG0 Module Clock Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the SSG0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the SSG0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER0CEN</name>
|
|
<description>TIMER0 Module Clock Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the TIMER0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the TIMER0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER1CEN</name>
|
|
<description>TIMER1 Module Clock Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the TIMER1 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the TIMER1 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0CEN</name>
|
|
<description>SARADC0 Module Clock Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the SARADC0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the SARADC0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1CEN</name>
|
|
<description>SARADC1 Module Clock Enable. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the SARADC1 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the SARADC1 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0CEN</name>
|
|
<description>Comparator 0 Module Clock Enable. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the Comparator 0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the Comparator 0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1CEN</name>
|
|
<description>Comparator 1 Module Clock Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the Comparator 1 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the Comparator 1 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CS0CEN</name>
|
|
<description>Capacitive Sensing (CAPSENSE0) Module Clock Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the CAPSENSE0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the CAPSENSE0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AES0CEN</name>
|
|
<description>AES0 Module Clock Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the AES0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the AES0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRC0CEN</name>
|
|
<description>CRC0 Module Clock Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the CRC0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the CRC0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDAC0CEN</name>
|
|
<description>IDAC0 Module Clock Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the IDAC0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the IDAC0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDAC1CEN</name>
|
|
<description>IDAC1 Module Clock Enable. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the IDAC1 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the IDAC1 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPT0CEN</name>
|
|
<description>Low Power Timer (LPTIMER0) Module Clock Enable. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the LPTIMER0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the LPTIMER0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2S0CEN</name>
|
|
<description>I2S0 Module Clock Enable. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the I2S0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the I2S0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB0CEN</name>
|
|
<description>USB0 Module Clock Enable. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the USB0 Module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the USB0 Module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EVREGCEN</name>
|
|
<description>External Regulator Clock Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the External Regulator Module (EXTVREG0) (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the External Regulator Module (EXTVREG0).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLCTRLCEN</name>
|
|
<description>Flash Controller Clock Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the Flash Controller Module (FLASHCTRL0) (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the Flash Controller Module (FLASHCTRL0).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBCLKG1</name>
|
|
<description>APB Clock Gate 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MISC0CEN</name>
|
|
<description>Miscellaneous 0 Clock Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, LPOSC0, EXTVREG0, IVC0 and RTC0 modules (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, LPOSC0, EXTVREG0, IVC0 and RTC0 modules.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MISC1CEN</name>
|
|
<description>Miscellaneous 1 Clock Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar (DMAXBAR0) modules.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar (DMAXBAR0) modules (default).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MISC2CEN</name>
|
|
<description>Miscellaneous 2 Clock Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the APB clock to the OSCVLDF flag in the EXTOSC module (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the APB clock to the OSCVLDF flag in the EXTOSC module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PM3CN</name>
|
|
<description>Power Mode 3 Clock Control</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM3CSEL</name>
|
|
<description>Power Mode 3 Fast-Wake Clock Source. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPOSC0</name>
|
|
<description>Power Mode 3 clock source is the Low-Power Oscillator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFOSC0</name>
|
|
<description>Power Mode 3 clock source is the Low-Frequency Oscillator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC0OSC</name>
|
|
<description>Power Mode 3 clock source is the RTC Oscillator.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTOSC0</name>
|
|
<description>Power Mode 3 clock source is the External Oscillator.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB0OSC</name>
|
|
<description>Power Mode 3 clock source is the USB Oscillator.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0OSC</name>
|
|
<description>Power Mode 3 clock source is the PLL.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPOSC0_DIV</name>
|
|
<description>Power Mode 3 clock source is a divided version of the Low-Power Oscillator.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PM3CEN</name>
|
|
<description>Power Mode 3 Fast-Wake Clock Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the core clock when in Power Mode 3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The core clock is enabled and runs off the clock selected by PM3CSEL in Power Mode 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CMP_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Comparator</groupName>
|
|
<baseAddress>0x4001f000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMP0_IRQn</name>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPFI</name>
|
|
<description>Falling Edge Interrupt Flag. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>No comparator falling edge has occurred since this flag was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A comparator falling edge occurred since last flag was cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPRI</name>
|
|
<description>Rising Edge Interrupt Flag. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>No comparator rising edge has occurred since this flag was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A comparator rising edge occurred since last flag was cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPOUT</name>
|
|
<description>Output State. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POS_LT_NEG</name>
|
|
<description>Voltage on CP+ < CP-.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POS_GT_NEG</name>
|
|
<description>Voltage on CP+ > CP-.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPEN</name>
|
|
<description>Comparator Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the comparator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the comparator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Input and Module Mode</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000800</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NMUX</name>
|
|
<description>Negative Input Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPNN0</name>
|
|
<description>Select CMPnN.0 (PB2.2).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN1</name>
|
|
<description>Select CMPnN.1 (PB3.1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN2</name>
|
|
<description>Select CMPnN.2 (PB3.3).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN3</name>
|
|
<description>Select CMPnN.3 (PB3.5).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN4</name>
|
|
<description>Select CMPnN.4 (PB3.7).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN5</name>
|
|
<description>Select CMPnN.5 (PB3.9).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN6</name>
|
|
<description>Select CMPnN.6 (RESERVED).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN7</name>
|
|
<description>Select CMPnN.7 (RESERVED).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN8</name>
|
|
<description>Select CMPnN.8 (VDD).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN9</name>
|
|
<description>Select CMPnN.9 (VREF).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN10</name>
|
|
<description>Select CMPnN.10 (RESERVED).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN11</name>
|
|
<description>Select CMPnN.11 (RESERVED).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN12</name>
|
|
<description>Select CMPnN.12 (RESERVED).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN13</name>
|
|
<description>Select CMPnN.13 (RESERVED).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN14</name>
|
|
<description>Select CMPnN.14 (RESERVED).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN15</name>
|
|
<description>Select CMPnN.15 (RESERVED).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMUX</name>
|
|
<description>Positive Input Select. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPNP0</name>
|
|
<description>Select CMPnP.0 (PB2.3).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP1</name>
|
|
<description>Select CMPnP.1 (PB3.0).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP2</name>
|
|
<description>Select CMPnP.2 (PB3.2).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP3</name>
|
|
<description>Select CMPnP.3 (PB3.4).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP4</name>
|
|
<description>Select CMPnP.4 (PB3.6).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP5</name>
|
|
<description>Select CMPnP.5 (PB.3.8).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP6</name>
|
|
<description>Select CMPnP.6 (RESERVED).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP7</name>
|
|
<description>Select CMPnP.7 (RESERVED).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP8</name>
|
|
<description>Select CMPnP.8 (Voltage at VREGIN / 4).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP9</name>
|
|
<description>Select CMPnP.9 (EXTVREG0 Current Sense).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP10</name>
|
|
<description>Select CMPnP.10 (1.8V Output of LDO).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP11</name>
|
|
<description>Select CMPnP.11 (VDDOSC Supply).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP12</name>
|
|
<description>Select CMPnP.12 (VREF).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP13</name>
|
|
<description>Select CMPnP.13 (VIO).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP14</name>
|
|
<description>Select CMPnP.14 (Voltage at VIOHD / 4).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP15</name>
|
|
<description>Select CMPnP.15 (RESERVED).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INMUX</name>
|
|
<description>Input MUX Select. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIRECT</name>
|
|
<description>Connects the NMUX signal to CP- and the PMUX signal to CP+.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPP_VSS</name>
|
|
<description>Connects VSS to CP- and the PMUX signal to CP+.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPP_DAC</name>
|
|
<description>Connects the NMUX signal to CP-, the PMUX signal to the Comparator DAC voltage reference, and the DAC output to CP+.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPN_DAC</name>
|
|
<description>Connects the PMUX signal to CP+, the NMUX signal to the Comparator DAC voltage reference, and the DAC output to CP-.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPMD</name>
|
|
<description>Comparator Mode. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>Mode 0 (fastest response time, highest power consumption).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>Mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>Mode 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>Mode 3 (slowest response time, lowest power consumption).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIEN</name>
|
|
<description>Falling Edge Interrupt Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the comparator falling edge interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the comparator falling edge interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIEN</name>
|
|
<description>Rising Edge Interrupt Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the comparator rising edge interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the comparator rising edge interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACLVL</name>
|
|
<description>Comparator DAC Output Level. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NWPUEN</name>
|
|
<description>Negative Input Weak Pullup Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the negative input weak pull up.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the negative input weak pull up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWPUEN</name>
|
|
<description>Positive Input Weak Pullup Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the positive input weak pull up.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the positive input weak pull up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPHYN</name>
|
|
<description>Negative Hysteresis Control. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative hysteresis.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEG_5_MV</name>
|
|
<description>Set negative hysteresis to 5 mV.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEG_10_MV</name>
|
|
<description>Set negative hysteresis to 10 mV.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEG_20_MV</name>
|
|
<description>Set negative hysteresis to 20 mV.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPHYP</name>
|
|
<description>Positive Hysteresis Control. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive hysteresis.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POS_5_MV</name>
|
|
<description>Set positive hysteresis to 5 mV.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POS_10_MV</name>
|
|
<description>Set positive hysteresis to 10 mV.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POS_20_MV</name>
|
|
<description>Set positive hysteresis to 20 mV.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVEN</name>
|
|
<description>Invert Comparator Output Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the comparator output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the comparator output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CMP_1</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Comparator</groupName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMP1_IRQn</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPFI</name>
|
|
<description>Falling Edge Interrupt Flag. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>No comparator falling edge has occurred since this flag was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A comparator falling edge occurred since last flag was cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPRI</name>
|
|
<description>Rising Edge Interrupt Flag. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>No comparator rising edge has occurred since this flag was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A comparator rising edge occurred since last flag was cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPOUT</name>
|
|
<description>Output State. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POS_LT_NEG</name>
|
|
<description>Voltage on CP+ < CP-.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POS_GT_NEG</name>
|
|
<description>Voltage on CP+ > CP-.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPEN</name>
|
|
<description>Comparator Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the comparator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the comparator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Input and Module Mode</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000800</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NMUX</name>
|
|
<description>Negative Input Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPNN0</name>
|
|
<description>Select CMPnN.0 (PB2.2).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN1</name>
|
|
<description>Select CMPnN.1 (PB3.1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN2</name>
|
|
<description>Select CMPnN.2 (PB3.3).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN3</name>
|
|
<description>Select CMPnN.3 (PB3.5).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN4</name>
|
|
<description>Select CMPnN.4 (PB3.7).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN5</name>
|
|
<description>Select CMPnN.5 (PB3.9).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN6</name>
|
|
<description>Select CMPnN.6 (RESERVED).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN7</name>
|
|
<description>Select CMPnN.7 (RESERVED).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN8</name>
|
|
<description>Select CMPnN.8 (VDD).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN9</name>
|
|
<description>Select CMPnN.9 (VREF).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN10</name>
|
|
<description>Select CMPnN.10 (RESERVED).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN11</name>
|
|
<description>Select CMPnN.11 (RESERVED).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN12</name>
|
|
<description>Select CMPnN.12 (RESERVED).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN13</name>
|
|
<description>Select CMPnN.13 (RESERVED).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN14</name>
|
|
<description>Select CMPnN.14 (RESERVED).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNN15</name>
|
|
<description>Select CMPnN.15 (RESERVED).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMUX</name>
|
|
<description>Positive Input Select. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPNP0</name>
|
|
<description>Select CMPnP.0 (PB2.3).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP1</name>
|
|
<description>Select CMPnP.1 (PB3.0).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP2</name>
|
|
<description>Select CMPnP.2 (PB3.2).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP3</name>
|
|
<description>Select CMPnP.3 (PB3.4).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP4</name>
|
|
<description>Select CMPnP.4 (PB3.6).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP5</name>
|
|
<description>Select CMPnP.5 (PB3.8).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP6</name>
|
|
<description>Select CMPnP.6 (RESERVED).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP7</name>
|
|
<description>Select CMPnP.7 (RESERVED).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP8</name>
|
|
<description>Select CMPnP.8 (Voltage at VREGIN / 4).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP9</name>
|
|
<description>Select CMPnP.9 (EXTVREG0 Current Sense).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP10</name>
|
|
<description>Select CMPnP.10 (1.8V Output of LDO).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP11</name>
|
|
<description>Select CMPnP.11 (VDDOSC Supply).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP12</name>
|
|
<description>Select CMPnP.12 (VREF).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP13</name>
|
|
<description>Select CMPnP.13 (VIO).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP14</name>
|
|
<description>Select CMPnP.14 (Voltage at VIOHD / 4).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPNP15</name>
|
|
<description>Select CMPnP.15 (RESERVED).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INMUX</name>
|
|
<description>Input MUX Select. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIRECT</name>
|
|
<description>Connects the NMUX signal to CP- and the PMUX signal to CP+.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPP_VSS</name>
|
|
<description>Connects VSS to CP- and the PMUX signal to CP+.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPP_DAC</name>
|
|
<description>Connects the NMUX signal to CP-, the PMUX signal to the Comparator DAC voltage reference, and the DAC output to CP+.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPN_DAC</name>
|
|
<description>Connects the PMUX signal to CP+, the NMUX signal to the Comparator DAC voltage reference, and the DAC output to CP-.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPMD</name>
|
|
<description>Comparator Mode. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>Mode 0 (fastest response time, highest power consumption).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>Mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>Mode 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>Mode 3 (slowest response time, lowest power consumption).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIEN</name>
|
|
<description>Falling Edge Interrupt Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the comparator falling edge interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the comparator falling edge interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIEN</name>
|
|
<description>Rising Edge Interrupt Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the comparator rising edge interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the comparator rising edge interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACLVL</name>
|
|
<description>Comparator DAC Output Level. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NWPUEN</name>
|
|
<description>Negative Input Weak Pullup Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the negative input weak pull up.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the negative input weak pull up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWPUEN</name>
|
|
<description>Positive Input Weak Pullup Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the positive input weak pull up.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the positive input weak pull up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPHYN</name>
|
|
<description>Negative Hysteresis Control. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative hysteresis.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEG_5_MV</name>
|
|
<description>Set negative hysteresis to 5 mV.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEG_10_MV</name>
|
|
<description>Set negative hysteresis to 10 mV.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEG_20_MV</name>
|
|
<description>Set negative hysteresis to 20 mV.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPHYP</name>
|
|
<description>Positive Hysteresis Control. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive hysteresis.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POS_5_MV</name>
|
|
<description>Set positive hysteresis to 5 mV.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POS_10_MV</name>
|
|
<description>Set positive hysteresis to 10 mV.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POS_20_MV</name>
|
|
<description>Set positive hysteresis to 20 mV.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVEN</name>
|
|
<description>Invert Comparator Output Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the comparator output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the comparator output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMACTRL_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>DMA</groupName>
|
|
<baseAddress>0x40036000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Controller Status</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x000F0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAENSTS</name>
|
|
<description>DMA Enable Status. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>DMA controller is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>DMA controller is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATE</name>
|
|
<description>State Machine State. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>Idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READING_CHANNEL_CONFIG</name>
|
|
<description>Reading channel controller data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READING_SOURCE_POINTER</name>
|
|
<description>Reading source data end pointer.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READING_DEST_POINTER</name>
|
|
<description>Reading destination data end pointer.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READING_SOURCE_DATA</name>
|
|
<description>Reading source data.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_DEST_DATA</name>
|
|
<description>Writing destination data.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING_DMA_REQ_CLEAR</name>
|
|
<description>Waiting for a DMA request to clear.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_CHANNEL_CONFIG</name>
|
|
<description>Writing channel controller data.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STALLED</name>
|
|
<description>Stalled.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DONE</name>
|
|
<description>Done.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCATTER_GATHER_TRANSITION</name>
|
|
<description>Peripheral scatter-gather transition.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NUMCHAN</name>
|
|
<description>Number of Supported DMA Channels. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Controller Configuration</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the DMA controller.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the DMA controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASEPTR</name>
|
|
<description>Base Pointer</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BASEPTR</name>
|
|
<description>Control Base Pointer. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ABASEPTR</name>
|
|
<description>Alternate Base Pointer</description>
|
|
<addressOffset>0xc</addressOffset>
|
|
<resetValue>0x00000100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ABASEPTR</name>
|
|
<description>Alternate Control Base Pointer. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHSTATUS</name>
|
|
<description>Channel Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Status. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 0 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 0 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Status. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 1 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 1 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 Status. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 2 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 2 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 Status. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 3 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 3 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 Status. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 4 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 4 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 Status. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 5 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 5 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 Status. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 6 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 6 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 Status. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 7 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 7 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 Status. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 8 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 8 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 Status. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 9 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 9 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 Status. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 10 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 10 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 Status. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 11 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 11 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 Status. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 12 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 12 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 Status. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 13 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 13 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 Status. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 14 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 14 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 Status. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_WAITING</name>
|
|
<description>DMA Channel 15 is not waiting for a data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITING</name>
|
|
<description>DMA Channel 15 is waiting for a data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHSWRCN</name>
|
|
<description>Channel Software Request Control</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Software Request. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 0 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 0 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Software Request. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 1 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 1 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 Software Request. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 2 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 2 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 Software Request. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 3 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 3 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 Software Request. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 4 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 4 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 Software Request. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 5 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 5 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 Software Request. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 6 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 6 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 Software Request. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 7 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 7 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 Software Request. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 8 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 8 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 Software Request. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 9 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 9 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 Software Request. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 10 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 10 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 Software Request. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 11 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 11 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 Software Request. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 12 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 12 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 Software Request. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 13 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 13 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 Software Request. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 14 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 14 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 Software Request. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 15 does not generate a software data request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE_SW_REQ</name>
|
|
<description>DMA Channel 15 generates a software data request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHREQMSET</name>
|
|
<description>Channel Request Mask Set</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Request Mask Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 0 peripheral data requests enabled. 1: DMA Channel 0 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 0 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Request Mask Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 1 peripheral data requests enabled. 1: DMA Channel 1 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 1 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 Request Mask Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 2 peripheral data requests enabled. 1: DMA Channel 2 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 2 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 Request Mask Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 3 peripheral data requests enabled. 1: DMA Channel 3 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 3 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 Request Mask Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 4 peripheral data requests enabled. 1: DMA Channel 4 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 4 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 Request Mask Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 5 peripheral data requests enabled. 1: DMA Channel 5 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 5 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 Request Mask Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 6 peripheral data requests enabled. 1: DMA Channel 6 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 6 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 Request Mask Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 7 peripheral data requests enabled. 1: DMA Channel 7 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 7 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 Request Mask Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 8 peripheral data requests enabled. 1: DMA Channel 8 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 8 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 Request Mask Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 9 peripheral data requests enabled. 1: DMA Channel 9 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 9 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 Request Mask Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 10 peripheral data requests enabled. 1: DMA Channel 10 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 10 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 Request Mask Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 11 peripheral data requests enabled. 1: DMA Channel 11 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 11 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 Request Mask Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 12 peripheral data requests enabled. 1: DMA Channel 12 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 12 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 Request Mask Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 13 peripheral data requests enabled. 1: DMA Channel 13 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 13 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 Request Mask Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 14 peripheral data requests enabled. 1: DMA Channel 14 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 14 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 Request Mask Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 15 peripheral data requests enabled. 1: DMA Channel 15 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 15 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHREQMCLR</name>
|
|
<description>Channel Request Mask Clear</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Request Mask Disable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 0 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Request Mask Disable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 1 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 Request Mask Disable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 2 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 Request Mask Disable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 3 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 Request Mask Disable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 4 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 Request Mask Disable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 5 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 Request Mask Disable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 6 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 Request Mask Disable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 7 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 Request Mask Disable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 8 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 Request Mask Disable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 9 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 Request Mask Disable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 10 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 Request Mask Disable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 11 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 Request Mask Disable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 12 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 Request Mask Disable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 13 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 Request Mask Disable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 14 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 Request Mask Disable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Enable DMA Channel 15 peripheral data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHENSET</name>
|
|
<description>Channel Enable Set</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 0 disabled. 1: DMA Channel 0 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 1 disabled. 1: DMA Channel 1 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 2 disabled. 1: DMA Channel 2 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 3 disabled. 1: DMA Channel 3 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 4 disabled. 1: DMA Channel 4 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 5 disabled. 1: DMA Channel 5 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 6 disabled. 1: DMA Channel 6 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 6.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 7 disabled. 1: DMA Channel 7 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 8 disabled. 1: DMA Channel 8 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 8.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 9 disabled. 1: DMA Channel 9 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 9.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 10 disabled. 1: DMA Channel 10 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 10.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 11 disabled. 1: DMA Channel 11 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 11.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 12 disabled. 1: DMA Channel 12 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 12.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 13 disabled. 1: DMA Channel 13 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 13.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 14 disabled. 1: DMA Channel 14 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 14.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 15 disabled. 1: DMA Channel 15 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 15.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHENCLR</name>
|
|
<description>Channel Enable Clear</description>
|
|
<addressOffset>0x2c</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Disable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Disable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 Disable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 Disable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 Disable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 Disable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 Disable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 6.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 Disable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 Disable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 8.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 Disable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 9.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 Disable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 10.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 Disable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 11.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 Disable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 12.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 Disable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 13.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 Disable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 14.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 Disable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA Channel 15.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHALTSET</name>
|
|
<description>Channel Alternate Select Set</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Alternate Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 0 is using primary data structure. 1: DMA Channel 0 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Alternate Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 1 is using primary data structure. 1: DMA Channel 1 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 Alternate Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 2 is using primary data structure. 1: DMA Channel 2 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 Alternate Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 3 is using primary data structure. 1: DMA Channel 3 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 Alternate Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 4 is using primary data structure. 1: DMA Channel 4 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 Alternate Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 5 is using primary data structure. 1: DMA Channel 5 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 Alternate Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 6 is using primary data structure. 1: DMA Channel 6 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 6.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 Alternate Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 7 is using primary data structure. 1: DMA Channel 7 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 Alternate Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 8 is using primary data structure. 1: DMA Channel 8 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 8.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 Alternate Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 9 is using primary data structure. 1: DMA Channel 9 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 9.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 Alternate Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 10 is using primary data structure. 1: DMA Channel 10 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 10.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 Alternate Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 11 is using primary data structure. 1: DMA Channel 11 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 11.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 Alternate Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 12 is using primary data structure. 1: DMA Channel 12 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 12.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 Alternate Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 13 is using primary data structure. 1: DMA Channel 13 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 13.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 Alternate Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 14 is using primary data structure. 1: DMA Channel 14 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 14.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 Alternate Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 15 is using primary data structure. 1: DMA Channel 15 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 15.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHALTCLR</name>
|
|
<description>Channel Alternate Select Clear</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Alternate Disable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Alternate Disable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 Alternate Disable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 Alternate Disable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 Alternate Disable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 Alternate Disable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 Alternate Disable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 6.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 Alternate Disable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 Alternate Disable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 8.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 Alternate Disable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 9.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 Alternate Disable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 10.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 Alternate Disable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 11.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 Alternate Disable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 12.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 Alternate Disable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 13.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 Alternate Disable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 14.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 Alternate Disable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the primary data structure for DMA Channel 15.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHHPSET</name>
|
|
<description>Channel High Priority Set</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 High Priority Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 0 is using the default priority level. 1: DMA Channel 0 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 High Priority Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 1 is using the default priority level. 1: DMA Channel 1 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 High Priority Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 2 is using the default priority level. 1: DMA Channel 2 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 High Priority Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 3 is using the default priority level. 1: DMA Channel 3 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 High Priority Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 4 is using the default priority level. 1: DMA Channel 4 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 High Priority Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 5 is using the default priority level. 1: DMA Channel 5 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 High Priority Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 6 is using the default priority level. 1: DMA Channel 6 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 6.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 High Priority Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 7 is using the default priority level. 1: DMA Channel 7 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 High Priority Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 8 is using the default priority level. 1: DMA Channel 8 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 8.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 High Priority Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 9 is using the default priority level. 1: DMA Channel 9 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 9.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 High Priority Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 10 is using the default priority level. 1: DMA Channel 10 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 10.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 High Priority Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 11 is using the default priority level. 1: DMA Channel 11 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 11.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 High Priority Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 12 is using the default priority level. 1: DMA Channel 12 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 12.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 High Priority Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 13 is using the default priority level. 1: DMA Channel 13 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 13.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 High Priority Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 14 is using the default priority level. 1: DMA Channel 14 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 14.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 High Priority Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: 0: DMA Channel 15 is using the default priority level. 1: DMA Channel 15 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 15.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHHPCLR</name>
|
|
<description>Channel High Priority Clear</description>
|
|
<addressOffset>0x3c</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 High Priority Disable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 High Priority Disable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 High Priority Disable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 High Priority Disable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 High Priority Disable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 High Priority Disable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 High Priority Disable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 6.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 High Priority Disable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 High Priority Disable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 8.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 High Priority Disable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 9.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 High Priority Disable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 10.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 High Priority Disable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 11.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 High Priority Disable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 12.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 High Priority Disable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 13.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 High Priority Disable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 14.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 High Priority Disable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the high default level for DMA Channel 15.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BERRCLR</name>
|
|
<description>Bus Error Clear</description>
|
|
<addressOffset>0x4c</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>DMA Bus Error Clear. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Read: 0: DMA error did not occur. 1: DMA error occurred since the last time ERROR was cleared. Write: 0: No effect. 1: Clear the DMA error flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMAXBAR_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>DMA</groupName>
|
|
<baseAddress>0x40037000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMACH0_IRQn</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH1_IRQn</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH2_IRQn</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH3_IRQn</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH4_IRQn</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH5_IRQn</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH6_IRQn</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH7_IRQn</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH8_IRQn</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH9_IRQn</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH10_IRQn</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH11_IRQn</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH12_IRQn</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH13_IRQn</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH14_IRQn</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMACH15_IRQn</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>DMAXBAR0</name>
|
|
<description>Channel 0-7 Trigger Select</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0SEL</name>
|
|
<description>DMA Channel 0 Peripheral Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP4_OUT</name>
|
|
<description>Service USB0 EP4 OUT data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI1_RX</name>
|
|
<description>Service SPI1 RX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_RX</name>
|
|
<description>Service USART0 RX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0_TX</name>
|
|
<description>Service I2C0 TX data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0L</name>
|
|
<description>Service TIMER0L overflow data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0H</name>
|
|
<description>Service TIMER0H overflow data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1L</name>
|
|
<description>Service TIMER1L overflow data requests.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1H</name>
|
|
<description>Service TIMER1H overflow data requests.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1SEL</name>
|
|
<description>DMA Channel 1 Peripheral Select. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP3_OUT</name>
|
|
<description>Service USB0 EP3 OUT data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI0_RX</name>
|
|
<description>Service SPI0 RX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1_RX</name>
|
|
<description>Service USART1 RX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0_RX</name>
|
|
<description>Service I2C0 RX data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDAC1</name>
|
|
<description>Service IDAC1 data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0_CONTROL</name>
|
|
<description>Service EPCA0 control data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0L</name>
|
|
<description>Service TIMER0L overflow data requests.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1L</name>
|
|
<description>Service TIMER1L overflow data requests.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1H</name>
|
|
<description>Service TIMER1H overflow data requests.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2SEL</name>
|
|
<description>DMA Channel 2 Peripheral Select. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP2_OUT</name>
|
|
<description>Service USB0 EP2 OUT data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI0_TX</name>
|
|
<description>Service SPI0 TX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_TX</name>
|
|
<description>Service USART0 TX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SARADC0</name>
|
|
<description>Service SARADC0 data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDAC1</name>
|
|
<description>Service IDAC1 data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_TX</name>
|
|
<description>Service I2S0 TX data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0_CONTROL</name>
|
|
<description>Service EPCA0 control data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3SEL</name>
|
|
<description>DMA Channel 3 Peripheral Select. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP1_OUT</name>
|
|
<description>Service USB0 EP1 OUT data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SARADC1</name>
|
|
<description>Service SARADC1 data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDAC0</name>
|
|
<description>Service IDAC0 data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_TX</name>
|
|
<description>Service I2S0 TX data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0_CAPTURE</name>
|
|
<description>Service EPCA0 capture data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1H</name>
|
|
<description>Service TIMER1H overflow data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4SEL</name>
|
|
<description>DMA Channel 4 Peripheral Select. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP4_IN</name>
|
|
<description>Service USB0 EP4 IN data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI1_TX</name>
|
|
<description>Service SPI1 TX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_TX</name>
|
|
<description>Service USART0 TX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SARADC0</name>
|
|
<description>Service SARADC0 data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_RX</name>
|
|
<description>Service I2S0 RX data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0_CAPTURE</name>
|
|
<description>Service EPCA0 capture data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0H</name>
|
|
<description>Service TIMER0H overflow data requests.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5SEL</name>
|
|
<description>DMA Channel 5 Peripheral Select. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP3_IN</name>
|
|
<description>Service USB0 EP3 IN data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES0_TX</name>
|
|
<description>Service AES0 TX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1_TX</name>
|
|
<description>Service USART1 TX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SARADC0</name>
|
|
<description>Service SARADC0 data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_RX</name>
|
|
<description>Service I2S0 RX data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6SEL</name>
|
|
<description>DMA Channel 6 Peripheral Select. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP2_IN</name>
|
|
<description>Service USB0 EP2 IN data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES0_RX</name>
|
|
<description>Service AES0 RX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_RX</name>
|
|
<description>Service USART0 RX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0_RX</name>
|
|
<description>Service I2C0 RX data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDAC0</name>
|
|
<description>Service IDAC0 data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0H</name>
|
|
<description>Service TIMER0H overflow data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7SEL</name>
|
|
<description>DMA Channel 7 Peripheral Select. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP1_IN</name>
|
|
<description>Service USB0 EP1 IN data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES0_XOR</name>
|
|
<description>Service AES0 XOR data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI1_TX</name>
|
|
<description>Service SPI1 TX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_TX</name>
|
|
<description>Service USART0 TX data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0L</name>
|
|
<description>Service TIMER0L overflow data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1L</name>
|
|
<description>Service TIMER1L overflow data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1H</name>
|
|
<description>Service TIMER1H overflow data requests.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAXBAR1</name>
|
|
<description>Channel 8-15 Trigger Select</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH8SEL</name>
|
|
<description>DMA Channel 8 Peripheral Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP4_OUT</name>
|
|
<description>Service USB0 EP4 OUT data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1_RX</name>
|
|
<description>Service USART1 RX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI1_RX</name>
|
|
<description>Service SPI1 RX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_RX</name>
|
|
<description>Service USART0 RX data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0_CAPTURE</name>
|
|
<description>Service EPCA0 capture data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9SEL</name>
|
|
<description>DMA Channel 9 Peripheral Select. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP3_OUT</name>
|
|
<description>Service USB0 EP3 OUT data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1_TX</name>
|
|
<description>Service USART1 TX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0_TX</name>
|
|
<description>Service I2C0 TX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0_CAPTURE</name>
|
|
<description>Service EPCA0 capture data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0H</name>
|
|
<description>Service TIMER0H overflow data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10SEL</name>
|
|
<description>DMA Channel 10 Peripheral Select. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP2_OUT</name>
|
|
<description>Service USB0 EP2 OUT data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES0_TX</name>
|
|
<description>Service AES0 TX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SARADC1</name>
|
|
<description>Service SARADC1 data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_RX</name>
|
|
<description>Service I2S0 RX data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1H</name>
|
|
<description>Service TIMER1H overflow data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11SEL</name>
|
|
<description>DMA Channel 11 Peripheral Select. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP1_OUT</name>
|
|
<description>Service USB0 EP1 OUT data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES0_RX</name>
|
|
<description>Service AES0 RX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1_RX</name>
|
|
<description>Service USART1 RX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_RX</name>
|
|
<description>Service USART0 RX data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0_RX</name>
|
|
<description>Service I2C0 RX data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_RX</name>
|
|
<description>Service I2S0 RX data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0H</name>
|
|
<description>Service TIMER0H overflow data requests.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12SEL</name>
|
|
<description>DMA Channel 12 Peripheral Select. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP4_IN</name>
|
|
<description>Service USB0 EP4 IN data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES0_XOR</name>
|
|
<description>Service AES0 XOR data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1_TX</name>
|
|
<description>Service USART1 TX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI1_TX</name>
|
|
<description>Service SPI1 TX data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDAC1</name>
|
|
<description>Service IDAC1 data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_TX</name>
|
|
<description>Service I2S0 TX data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0L</name>
|
|
<description>Service TIMER0L overflow data requests.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1L</name>
|
|
<description>Service TIMER1L overflow data requests.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1H</name>
|
|
<description>Service TIMER1H overflow data requests.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13SEL</name>
|
|
<description>DMA Channel 13 Peripheral Select. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP3_IN</name>
|
|
<description>Service USB0 EP3 IN data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI0_RX</name>
|
|
<description>Service SPI0 RX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_RX</name>
|
|
<description>Service USART0 RX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDAC1</name>
|
|
<description>Service IDAC1 data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_TX</name>
|
|
<description>Service I2S0 TX data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0H</name>
|
|
<description>Service TIMER0H overflow data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14SEL</name>
|
|
<description>DMA Channel 14 Peripheral Select. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP2_IN</name>
|
|
<description>Service USB0 EP2 IN data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI0_TX</name>
|
|
<description>Service SPI0 TX data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_TX</name>
|
|
<description>Service USART0 TX data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDAC0</name>
|
|
<description>Service IDAC0 data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0_CONTROL</name>
|
|
<description>Service EPCA0 control data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0L</name>
|
|
<description>Service TIMER0L overflow data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1L</name>
|
|
<description>Service TIMER1L overflow data requests.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15SEL</name>
|
|
<description>DMA Channel 15 Peripheral Select. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB0_EP1_IN</name>
|
|
<description>Service USB0 EP1 IN data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SARADC1</name>
|
|
<description>Service SARADC1 data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDAC0</name>
|
|
<description>Service IDAC0 data requests.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0_CONTROL</name>
|
|
<description>Service EPCA0 control data requests.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_RISE</name>
|
|
<description>Service DMAXT0 (PB1.4) rising edge data requests.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T0_FALL</name>
|
|
<description>Service DMAXT0 (PB1.4) falling edge data requests.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_RISE</name>
|
|
<description>Service DMAXT1 (PB1.5) rising edge data requests.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA0T1_FALL</name>
|
|
<description>Service DMAXT1 (PB1.5) falling edge data requests.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0H</name>
|
|
<description>Service TIMER0H overflow data requests.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1H</name>
|
|
<description>Service TIMER1H overflow data requests.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DEVICEID_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>DEVICEID_0</groupName>
|
|
<baseAddress>0x400490c0</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>DEVICEID0</name>
|
|
<description>Device ID Word 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REVID</name>
|
|
<description>Revision ID. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REVA</name>
|
|
<description>Revision A.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEVICEID0</name>
|
|
<description>Device ID 0. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>28</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICEID1</name>
|
|
<description>Device ID Word 1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICEID1</name>
|
|
<description>Device ID 1. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICEID2</name>
|
|
<description>Device ID Word 2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICEID2</name>
|
|
<description>Device ID 2. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICEID3</name>
|
|
<description>Device ID Word 3</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICEID3</name>
|
|
<description>Device ID 3. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EMIF_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>EMIF_0</groupName>
|
|
<baseAddress>0x40026000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IF0EN</name>
|
|
<description>Interface 0 Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable interface 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable interface 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IF1EN</name>
|
|
<description>Interface 1 Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable interface 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable interface 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFFSTEN</name>
|
|
<description>OFF Output State Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>EMIF will not enter the off state after 4 idle cycles.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>EMIF will enter the off state after 4 idle cycles.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSTS</name>
|
|
<description>EMIF OFF Status. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ON</name>
|
|
<description>The EMIF bus is active.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>The EMIF is in the off bus state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLESTS</name>
|
|
<description>EMIF IDLE Status. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_IDLE</name>
|
|
<description>The EMIF has not been idle for four cycles.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>The EMIF has been idle for four four cycles.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_2-->
|
|
<register>
|
|
<name>CONFIG_0</name>
|
|
<description>Interface Configuration</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSWIDTH</name>
|
|
<description>Interface Bus Data Width. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>8BIT</name>
|
|
<description>The data bus is 8-bits wide.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16BIT</name>
|
|
<description>The data bus is 16-bits wide.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUXMD</name>
|
|
<description>Interface Mux Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONMUXED</name>
|
|
<description>The interface operates in non-multiplexed mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MUXED</name>
|
|
<description>The interface operates in multiplexed mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASEN</name>
|
|
<description>Interface Automatic Address Shift Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The address is not automatically shifted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The address is automatically shifted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROEN</name>
|
|
<description>Interface Read Only Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The interface supports reads and writes.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The interface supports only reads.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDHINH</name>
|
|
<description>Write Data Hold State Inhibit. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Enable the write data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Inhibit the write data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DELAYOE</name>
|
|
<description>Output Enable Delay. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The output enable signal (/OE) is not delayed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The output enable signal (/OE) is delayed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KLREN</name>
|
|
<description>Keep Last Read Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The bus is driven to the idle state between active requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The bus drives the last value read on the interface between active requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFRT_0</name>
|
|
<description>Interface Read Timing</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RASET</name>
|
|
<description>Interface Read Address Setup Delay . </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAHOLD</name>
|
|
<description>Interface Read Address Hold Delay. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDHOLD</name>
|
|
<description>Interface Read Data Hold Delay. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDWAIT</name>
|
|
<description>Interface Read Data Wait Delay. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFWT_0</name>
|
|
<description>Interface Write Timing</description>
|
|
<addressOffset>0xa0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WASET</name>
|
|
<description>Interface Write Address Setup Delay . </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAHOLD</name>
|
|
<description>Interface Write Address Hold Delay. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDHOLD</name>
|
|
<description>Interface Write Data Hold Delay. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDWAIT</name>
|
|
<description>Interface Write Data Wait Delay. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFRCST_0</name>
|
|
<description>Interface Read Control States</description>
|
|
<addressOffset>0xb0</addressOffset>
|
|
<resetValue>0x00000FBB</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSRAS</name>
|
|
<description>Chip Select Read Address Setup State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the read address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the read address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSRAH</name>
|
|
<description>Chip Select Read Address Hold State. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the read address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the read address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSRDW</name>
|
|
<description>Chip Select Read Data Wait State. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the read data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the read data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSRDH</name>
|
|
<description>Chip Select Read Data Hold State. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the read data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the read data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OERAS</name>
|
|
<description>Output Enable Read Address Setup State. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the read address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the read address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OERAH</name>
|
|
<description>Output Enable Read Address Hold State. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the read address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the read address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OERDW</name>
|
|
<description>Output Enable Read Data Wait State. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the read data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the read data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OERDH</name>
|
|
<description>Output Enable Read Data Hold State. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the read data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the read data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRRAS</name>
|
|
<description>Write Signal Read Address Setup State. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the read address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the read address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRRAH</name>
|
|
<description>Write Signal Read Address Hold State. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the read address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the read address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRRDW</name>
|
|
<description>Write Signal Read Data Wait State. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the read data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the read data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRRDH</name>
|
|
<description>Write Signal Read Data Hold State. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the read data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the read data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERAS</name>
|
|
<description>Address Latch Enable Read Address Setup State. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the read address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the read address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERAH</name>
|
|
<description>Address Latch Enable Read Address Hold State. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the read address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the read address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERDW</name>
|
|
<description>Address Latch Enable Read Data Wait State. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the read data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the read data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERDH</name>
|
|
<description>Address Latch Enable Read Data Hold State. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the read data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the read data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFWCST_0</name>
|
|
<description>Interface Write Control States</description>
|
|
<addressOffset>0xc0</addressOffset>
|
|
<resetValue>0x00000BFB</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSWAS</name>
|
|
<description>Chip Select Write Address Setup State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the write address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the write address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSWAH</name>
|
|
<description>Chip Select Write Address Hold State. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the write address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the write address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSWDW</name>
|
|
<description>Chip Select Write Data Wait State. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the write data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the write data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSWDH</name>
|
|
<description>Chip Select Write Data Hold State. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the write data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the write data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OEWAS</name>
|
|
<description>Output Enable Write Address Setup State. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the write address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the write address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OEWAH</name>
|
|
<description>Output Enable Write Address Hold State. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the write address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the write address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OEWDW</name>
|
|
<description>Output Enable Write Data Wait State. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the write data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the write data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OEWDH</name>
|
|
<description>Output Enable Write Data Hold State. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the write data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the write data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRWAS</name>
|
|
<description>Write Signal Write Address Setup State. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the write address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the write address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRWAH</name>
|
|
<description>Write Signal Write Address Hold State. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the write address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the write address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRWDW</name>
|
|
<description>Write Signal Write Data Wait State. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the write data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the write data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRWDH</name>
|
|
<description>Write Signal Write Data Hold State. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the write data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the write data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALEWAS</name>
|
|
<description>Address Latch Enable Write Address Setup State. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the write address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the write address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALEWAH</name>
|
|
<description>Address Latch Enable Write Address Hold State. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the write address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the write address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALEWDW</name>
|
|
<description>Address Latch Enable Write Data Wait State. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the write data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the write data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALEWDH</name>
|
|
<description>Address Latch Enable Write Data Hold State. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the write data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the write data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_3-->
|
|
<register>
|
|
<name>CONFIG_1</name>
|
|
<description>Interface Configuration</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSWIDTH</name>
|
|
<description>Interface Bus Data Width. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>8BIT</name>
|
|
<description>The data bus is 8-bits wide.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16BIT</name>
|
|
<description>The data bus is 16-bits wide.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUXMD</name>
|
|
<description>Interface Mux Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONMUXED</name>
|
|
<description>The interface operates in non-multiplexed mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MUXED</name>
|
|
<description>The interface operates in multiplexed mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASEN</name>
|
|
<description>Interface Automatic Address Shift Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The address is not automatically shifted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The address is automatically shifted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROEN</name>
|
|
<description>Interface Read Only Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The interface supports reads and writes.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The interface supports only reads.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDHINH</name>
|
|
<description>Write Data Hold State Inhibit. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Enable the write data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Inhibit the write data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DELAYOE</name>
|
|
<description>Output Enable Delay. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The output enable signal (/OE) is not delayed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The output enable signal (/OE) is delayed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KLREN</name>
|
|
<description>Keep Last Read Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The bus is driven to the idle state between active requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The bus drives the last value read on the interface between active requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFRT_1</name>
|
|
<description>Interface Read Timing</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RASET</name>
|
|
<description>Interface Read Address Setup Delay . </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAHOLD</name>
|
|
<description>Interface Read Address Hold Delay. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDHOLD</name>
|
|
<description>Interface Read Data Hold Delay. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDWAIT</name>
|
|
<description>Interface Read Data Wait Delay. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFWT_1</name>
|
|
<description>Interface Write Timing</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WASET</name>
|
|
<description>Interface Write Address Setup Delay . </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAHOLD</name>
|
|
<description>Interface Write Address Hold Delay. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDHOLD</name>
|
|
<description>Interface Write Data Hold Delay. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDWAIT</name>
|
|
<description>Interface Write Data Wait Delay. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFRCST_1</name>
|
|
<description>Interface Read Control States</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<resetValue>0x00000FBB</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSRAS</name>
|
|
<description>Chip Select Read Address Setup State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the read address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the read address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSRAH</name>
|
|
<description>Chip Select Read Address Hold State. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the read address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the read address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSRDW</name>
|
|
<description>Chip Select Read Data Wait State. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the read data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the read data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSRDH</name>
|
|
<description>Chip Select Read Data Hold State. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the read data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the read data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OERAS</name>
|
|
<description>Output Enable Read Address Setup State. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the read address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the read address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OERAH</name>
|
|
<description>Output Enable Read Address Hold State. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the read address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the read address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OERDW</name>
|
|
<description>Output Enable Read Data Wait State. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the read data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the read data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OERDH</name>
|
|
<description>Output Enable Read Data Hold State. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the read data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the read data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRRAS</name>
|
|
<description>Write Signal Read Address Setup State. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the read address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the read address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRRAH</name>
|
|
<description>Write Signal Read Address Hold State. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the read address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the read address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRRDW</name>
|
|
<description>Write Signal Read Data Wait State. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the read data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the read data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRRDH</name>
|
|
<description>Write Signal Read Data Hold State. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the read data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the read data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERAS</name>
|
|
<description>Address Latch Enable Read Address Setup State. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the read address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the read address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERAH</name>
|
|
<description>Address Latch Enable Read Address Hold State. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the read address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the read address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERDW</name>
|
|
<description>Address Latch Enable Read Data Wait State. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the read data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the read data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALERDH</name>
|
|
<description>Address Latch Enable Read Data Hold State. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the read data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the read data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFWCST_1</name>
|
|
<description>Interface Write Control States</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<resetValue>0x00000BFB</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSWAS</name>
|
|
<description>Chip Select Write Address Setup State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the write address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the write address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSWAH</name>
|
|
<description>Chip Select Write Address Hold State. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the write address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the write address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSWDW</name>
|
|
<description>Chip Select Write Data Wait State. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the write data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the write data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSWDH</name>
|
|
<description>Chip Select Write Data Hold State. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set chip select (CSx) to low during the write data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set chip select (CSx) to high during the write data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OEWAS</name>
|
|
<description>Output Enable Write Address Setup State. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the write address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the write address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OEWAH</name>
|
|
<description>Output Enable Write Address Hold State. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the write address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the write address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OEWDW</name>
|
|
<description>Output Enable Write Data Wait State. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the write data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the write data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OEWDH</name>
|
|
<description>Output Enable Write Data Hold State. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set output enable (/OE) to low during the write data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set output enable (/OE) to high during the write data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRWAS</name>
|
|
<description>Write Signal Write Address Setup State. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the write address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the write address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRWAH</name>
|
|
<description>Write Signal Write Address Hold State. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the write address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the write address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRWDW</name>
|
|
<description>Write Signal Write Data Wait State. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the write data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the write data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRWDH</name>
|
|
<description>Write Signal Write Data Hold State. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set write signal (/WR) to low during the write data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set write signal (/WR) to high during the write data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALEWAS</name>
|
|
<description>Address Latch Enable Write Address Setup State. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the write address setup state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the write address setup state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALEWAH</name>
|
|
<description>Address Latch Enable Write Address Hold State. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the write address hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the write address hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALEWDW</name>
|
|
<description>Address Latch Enable Write Data Wait State. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the write data wait state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the write data wait state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALEWDH</name>
|
|
<description>Address Latch Enable Write Data Hold State. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set address latch enable (ALEm) to low during the write data hold state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set address latch enable (ALEm) to high during the write data hold state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EPCA_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>EPCA_0</groupName>
|
|
<baseAddress>0x4000e000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EPCA0_IRQn</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Module Operating Mode</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<resetValue>0x01FF0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Input Clock Divider. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Input Clock (F<subscript>CLKIN</subscript>) Select. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>APB</name>
|
|
<description>Set the APB as the input clock (FCLKIN).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HL_ECI</name>
|
|
<description>Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTOSCN</name>
|
|
<description>Set the external oscillator module output (EXTOSCn) divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECI</name>
|
|
<description>Set ECI transitions divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HDOSEL</name>
|
|
<description>High Drive Port Bank Output Select. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>THREE_DIFF</name>
|
|
<description>Select three differential outputs from Channels 3, 4, and 5 for the High Drive pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO_DIFF</name>
|
|
<description>Select the differential outputs from Channels 4 and 5 and non-differential outputs from Channels 2 and 3 for the High Drive pins.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_DIFF</name>
|
|
<description>Select the differential output from Channel 5 and non-differential outputs from Channels 1-4 for the High Drive pins.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_DIFF</name>
|
|
<description>Select the non-differential channel outputs (Channels 0-5) for the High Drive pins.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEND</name>
|
|
<description>DMA Write End Index. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LIMIT</name>
|
|
<description>Set the last register in a DMA write transfer to LIMITUPD.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>Set the last register in a DMA write transfer to Channel 0 CCAPVUPD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>Set the last register in a DMA write transfer to Channel 1 CCAPVUPD.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>Set the last register in a DMA write transfer to Channel 2 CCAPVUPD.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>Set the last register in a DMA write transfer to Channel 3 CCAPVUPD.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH4</name>
|
|
<description>Set the last register in a DMA write transfer to Channel 4 CCAPVUPD.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH5</name>
|
|
<description>Set the last register in a DMA write transfer to Channel 5 CCAPVUPD.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Empty slot.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPTR</name>
|
|
<description>DMA Write Transfer Pointer. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LIMIT</name>
|
|
<description>The DMA channel will write to LIMITUPD next.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>The DMA channel will write to Channel 0 CCAPVUPD next.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>The DMA channel will write to Channel 1 CCAPVUPD next.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>The DMA channel will write to Channel 2 CCAPVUPD next.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>The DMA channel will write to Channel 3 CCAPVUPD next.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH4</name>
|
|
<description>The DMA channel will write to Channel 4 CCAPVUPD next.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH5</name>
|
|
<description>The DMA channel will write to Channel 5 CCAPVUPD next.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Empty slot.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSTART</name>
|
|
<description>DMA Target Start Index. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LIMIT</name>
|
|
<description>Set the first register in a DMA write transfer to LIMITUPD.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>Set the first register in a DMA write transfer to Channel 0 CCAPVUPD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>Set the first register in a DMA write transfer to Channel 1 CCAPVUPD.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>Set the first register in a DMA write transfer to Channel 2 CCAPVUPD.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>Set the first register in a DMA write transfer to Channel 3 CCAPVUPD.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH4</name>
|
|
<description>Set the first register in a DMA write transfer to Channel 4 CCAPVUPD.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH5</name>
|
|
<description>Set the first register in a DMA write transfer to Channel 5 CCAPVUPD.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Empty slot.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBUSYF</name>
|
|
<description>DMA Busy Flag. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>The DMA channel is not servicing an EPCA control transfer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUSY</name>
|
|
<description>The DMA channel is busy servicing an EPCA control transfer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STDOSEL</name>
|
|
<description>Standard Port Bank Output Select. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_DIFF</name>
|
|
<description>Select the non-differential channel outputs (Channels 0-5) for the standard PB pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_DIFF</name>
|
|
<description>Select the differential output from Channel 2 and non-differential outputs from Channels 0, 1, 3, and 4 for the standard PB pins.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO_DIFF</name>
|
|
<description>Select the differential outputs from Channels 1 and 2 and non-differential outputs from Channels 0 and 3 for the standard PB pins.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THREE_DIFF</name>
|
|
<description>Select three differential outputs from Channels 0, 1, and 2 for the standard PB pins.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVFIEN</name>
|
|
<description>EPCA Counter Overflow/Limit Interrupt Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the EPCA counter overflow/limit event interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the EPCA counter overflow/limit event interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVFDEN</name>
|
|
<description>EPCA Counter Overflow/Limit DMA Request Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a EPCA counter overflow/limit event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a EPCA counter overflow/limit event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVFSEN</name>
|
|
<description>EPCA Counter Overflow/Limit Synchronization Signal Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a EPCA counter overflow/limit event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a EPCA counter overflow/limit event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALTIEN</name>
|
|
<description>EPCA Halt Input Interrupt Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not generate an interrupt if the EPCA halt input is high.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Generate an interrupt if the EPCA halt input is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOUPD</name>
|
|
<description>Internal Register Update Inhibit. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The EPCA registers will automatically load any new update values after an overflow/limit event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>The EPCA registers will not load any new update values after an overflow/limit event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLEBEN</name>
|
|
<description>Idle Bypass Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The EPCA module will stop running when the core halts (idle).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The EPCA module will continue normal operation when the core halts (idle).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>EPCA Debug Mode. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will stop the EPCA counter/timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The EPCA will continue to operate while the core is halted in debug mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALTEN</name>
|
|
<description>Halt Input Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The Halt input (PB_HDKill) does not affect the EPCA counter/timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An assertion of the Halt input (PB_HDKill) will stop the EPCA counter/timer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STSEL</name>
|
|
<description>Synchronous Input Trigger Select. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPCANT0</name>
|
|
<description>Select input trigger 0, EPCAnT0 (Comparator 0 Output).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCANT1</name>
|
|
<description>Select input trigger 1, EPCAnT1 (Comparator 1 Output).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCANT2</name>
|
|
<description>Select input trigger 2, EPCAnT2 (Timer 0 High Overflow ).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCANT3</name>
|
|
<description>Select input trigger 3, EPCAnT3 (Timer 1 High Overflow).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STESEL</name>
|
|
<description>Synchronous Input Trigger Edge Select. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>A high-to-low transition (falling edge) on EPCAnTx will start the counter/timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>A low-to-high transition (rising edge) on EPCAnTx will start the counter/timer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STEN</name>
|
|
<description>Synchronous Input Trigger Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the input trigger (EPCAnTx). The EPCA counter/timer will continue to run if the RUN bit is set regardless of the value on the input trigger.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the input trigger (EPCAnTx). If RUN is set to 1, the EPCA counter/timer will start running when the selected input trigger (STSEL) meets the criteria set by STESEL. It will not stop running if the criteria is no longer met.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVST</name>
|
|
<description>Clock Divider Output State. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_HIGH</name>
|
|
<description>The clock divider is currently in the first half-cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_LOW</name>
|
|
<description>The clock divider is currently in the second half-cycle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Current Clock Divider Count. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0x1a0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>C0CCI</name>
|
|
<description>Channel 0 Capture/Compare Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Channel 0 match or capture event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Channel 0 match or capture event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C1CCI</name>
|
|
<description>Channel 1 Capture/Compare Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Channel 1 match or capture event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Channel 1 match or capture event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C2CCI</name>
|
|
<description>Channel 2 Capture/Compare Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Channel 2 match or capture event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Channel 2 match or capture event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C3CCI</name>
|
|
<description>Channel 3 Capture/Compare Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Channel 3 match or capture event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Channel 3 match or capture event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C4CCI</name>
|
|
<description>Channel 4 Capture/Compare Interrupt Flag. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Channel 4 match or capture event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Channel 4 match or capture event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C5CCI</name>
|
|
<description>Channel 5 Capture/Compare Interrupt Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Channel 5 match or capture event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Channel 5 match or capture event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Counter/Timer Run. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the EPCA Counter/Timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start the EPCA Counter/Timer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVFI</name>
|
|
<description>Counter/Timer Overflow/Limit Interrupt Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>An EPCA Counter/Timer overflow/limit event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>An EPCA Counter/Timer overflow/limit event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UPDCF</name>
|
|
<description>Register Update Complete Flag. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>An EPCA register update completed or is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>An EPCA register update has not completed and is still pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALTI</name>
|
|
<description>Halt Input Interrupt Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The Halt input (PB_HDKill) was not asserted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The Halt input (PB_HDKill) was asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C0IOVFI</name>
|
|
<description>Channel 0 Intermediate Overflow Interrupt Flag. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Channel 0 did not count past the channel n-bit mode limit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Channel 0 counted past the channel n-bit mode limit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C1IOVFI</name>
|
|
<description>Channel 1 Intermediate Overflow Interrupt Flag. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Channel 1 did not count past the channel n-bit mode limit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Channel 1 counted past the channel n-bit mode limit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C2IOVFI</name>
|
|
<description>Channel 2 Intermediate Overflow Interrupt Flag. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Channel 2 did not count past the channel n-bit mode limit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Channel 2 counted past the channel n-bit mode limit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C3IOVFI</name>
|
|
<description>Channel 3 Intermediate Overflow Interrupt Flag. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Channel 3 did not count past the channel n-bit mode limit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Channel 3 counted past the channel n-bit mode limit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C4IOVFI</name>
|
|
<description>Channel 4 Intermediate Overflow Interrupt Flag. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Channel 4 did not count past the channel n-bit mode limit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Channel 4 counted past the channel n-bit mode limit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C5IOVFI</name>
|
|
<description>Channel 5 Intermediate Overflow Interrupt Flag. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Channel 5 did not count past the channel n-bit mode limit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Channel 5 counted past the channel n-bit mode limit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNTER</name>
|
|
<description>Module Counter/Timer</description>
|
|
<addressOffset>0x1b0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNTER</name>
|
|
<description>Counter/Timer. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LIMIT</name>
|
|
<description>Module Upper Limit</description>
|
|
<addressOffset>0x1c0</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LIMIT</name>
|
|
<description>Upper Limit. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LIMITUPD</name>
|
|
<description>Module Upper Limit Update Value</description>
|
|
<addressOffset>0x1d0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LIMITUPD</name>
|
|
<description>Module Upper Limit Update Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTIME</name>
|
|
<description>Phase Delay Time</description>
|
|
<addressOffset>0x1e0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTIMEX</name>
|
|
<description>X Phase Delay Time. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTIMEY</name>
|
|
<description>Y Phase Delay Time. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTARGET</name>
|
|
<description>DMA Transfer Target</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTARGET</name>
|
|
<description>DMA Transfer Target. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_2-->
|
|
<register>
|
|
<name>MODE_0</name>
|
|
<description>Channel Capture/Compare Mode</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COSEL</name>
|
|
<description>Channel Output Function Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT</name>
|
|
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT</name>
|
|
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMD</name>
|
|
<description>PWM N-Bit Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIFGEN</name>
|
|
<description>Differential Signal Generator Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Channel Operating Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE_PWM</name>
|
|
<description>Configure the channel for edge-aligned PWM mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_PWM</name>
|
|
<description>Configure the channel for center-aligned PWM mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HF_SQUARE_WAVE</name>
|
|
<description>Configure the channel for high-frequency/square-wave mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CAPTURE</name>
|
|
<description>Configure the channel for timer/capture mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>N_BIT_PWM</name>
|
|
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL_0</name>
|
|
<description>Channel Capture/Compare Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUTST</name>
|
|
<description>Channel Output State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The channel output state is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The channel output state is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCAPEN</name>
|
|
<description>Positive Edge Input Capture Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable positive-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNCAPEN</name>
|
|
<description>Negative Edge Input Capture Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable negative-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUPDCF</name>
|
|
<description>Channel Register Update Complete Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A EPCA channel register update completed or is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A EPCA channel register update has not completed and is still pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>YPHST</name>
|
|
<description>Differential Y Phase State. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the Y Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the Y Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVEPH</name>
|
|
<description>Active Channel Select. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>YACTIVE</name>
|
|
<description>The Y Phase is active and X Phase is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XACTIVE</name>
|
|
<description>The X Phase is active and Y Phase is inactive.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XPHST</name>
|
|
<description>Differential X Phase State. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the X Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the X Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIEN</name>
|
|
<description>Capture/Compare Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel capture/compare interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel capture/compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCDEN</name>
|
|
<description>Capture/Compare DMA Request Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCSEN</name>
|
|
<description>Capture/Compare Synchronization Signal Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFIEN</name>
|
|
<description>Intermediate Overflow Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel intermediate overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel intermediate overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFDEN</name>
|
|
<description>Intermediate Overflow DMA Request Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFSEN</name>
|
|
<description>Intermediate Overflow Synchronization Signal Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPV_0</name>
|
|
<description>Channel Compare Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPV</name>
|
|
<description>Channel Compare Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPVUPD_0</name>
|
|
<description>Channel Compare Update Value</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPVUPD</name>
|
|
<description>Channel Compare Update Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_3-->
|
|
<register>
|
|
<name>MODE_1</name>
|
|
<description>Channel Capture/Compare Mode</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COSEL</name>
|
|
<description>Channel Output Function Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT</name>
|
|
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT</name>
|
|
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMD</name>
|
|
<description>PWM N-Bit Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIFGEN</name>
|
|
<description>Differential Signal Generator Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Channel Operating Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE_PWM</name>
|
|
<description>Configure the channel for edge-aligned PWM mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_PWM</name>
|
|
<description>Configure the channel for center-aligned PWM mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HF_SQUARE_WAVE</name>
|
|
<description>Configure the channel for high-frequency/square-wave mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CAPTURE</name>
|
|
<description>Configure the channel for timer/capture mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>N_BIT_PWM</name>
|
|
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL_1</name>
|
|
<description>Channel Capture/Compare Control</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUTST</name>
|
|
<description>Channel Output State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The channel output state is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The channel output state is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCAPEN</name>
|
|
<description>Positive Edge Input Capture Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable positive-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNCAPEN</name>
|
|
<description>Negative Edge Input Capture Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable negative-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUPDCF</name>
|
|
<description>Channel Register Update Complete Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A EPCA channel register update completed or is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A EPCA channel register update has not completed and is still pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>YPHST</name>
|
|
<description>Differential Y Phase State. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the Y Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the Y Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVEPH</name>
|
|
<description>Active Channel Select. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>YACTIVE</name>
|
|
<description>The Y Phase is active and X Phase is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XACTIVE</name>
|
|
<description>The X Phase is active and Y Phase is inactive.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XPHST</name>
|
|
<description>Differential X Phase State. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the X Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the X Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIEN</name>
|
|
<description>Capture/Compare Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel capture/compare interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel capture/compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCDEN</name>
|
|
<description>Capture/Compare DMA Request Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCSEN</name>
|
|
<description>Capture/Compare Synchronization Signal Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFIEN</name>
|
|
<description>Intermediate Overflow Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel intermediate overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel intermediate overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFDEN</name>
|
|
<description>Intermediate Overflow DMA Request Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFSEN</name>
|
|
<description>Intermediate Overflow Synchronization Signal Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPV_1</name>
|
|
<description>Channel Compare Value</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPV</name>
|
|
<description>Channel Compare Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPVUPD_1</name>
|
|
<description>Channel Compare Update Value</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPVUPD</name>
|
|
<description>Channel Compare Update Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_4-->
|
|
<register>
|
|
<name>MODE_2</name>
|
|
<description>Channel Capture/Compare Mode</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COSEL</name>
|
|
<description>Channel Output Function Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT</name>
|
|
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT</name>
|
|
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMD</name>
|
|
<description>PWM N-Bit Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIFGEN</name>
|
|
<description>Differential Signal Generator Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Channel Operating Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE_PWM</name>
|
|
<description>Configure the channel for edge-aligned PWM mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_PWM</name>
|
|
<description>Configure the channel for center-aligned PWM mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HF_SQUARE_WAVE</name>
|
|
<description>Configure the channel for high-frequency/square-wave mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CAPTURE</name>
|
|
<description>Configure the channel for timer/capture mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>N_BIT_PWM</name>
|
|
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL_2</name>
|
|
<description>Channel Capture/Compare Control</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUTST</name>
|
|
<description>Channel Output State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The channel output state is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The channel output state is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCAPEN</name>
|
|
<description>Positive Edge Input Capture Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable positive-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNCAPEN</name>
|
|
<description>Negative Edge Input Capture Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable negative-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUPDCF</name>
|
|
<description>Channel Register Update Complete Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A EPCA channel register update completed or is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A EPCA channel register update has not completed and is still pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>YPHST</name>
|
|
<description>Differential Y Phase State. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the Y Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the Y Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVEPH</name>
|
|
<description>Active Channel Select. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>YACTIVE</name>
|
|
<description>The Y Phase is active and X Phase is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XACTIVE</name>
|
|
<description>The X Phase is active and Y Phase is inactive.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XPHST</name>
|
|
<description>Differential X Phase State. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the X Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the X Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIEN</name>
|
|
<description>Capture/Compare Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel capture/compare interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel capture/compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCDEN</name>
|
|
<description>Capture/Compare DMA Request Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCSEN</name>
|
|
<description>Capture/Compare Synchronization Signal Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFIEN</name>
|
|
<description>Intermediate Overflow Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel intermediate overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel intermediate overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFDEN</name>
|
|
<description>Intermediate Overflow DMA Request Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFSEN</name>
|
|
<description>Intermediate Overflow Synchronization Signal Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPV_2</name>
|
|
<description>Channel Compare Value</description>
|
|
<addressOffset>0xa0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPV</name>
|
|
<description>Channel Compare Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPVUPD_2</name>
|
|
<description>Channel Compare Update Value</description>
|
|
<addressOffset>0xb0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPVUPD</name>
|
|
<description>Channel Compare Update Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_5-->
|
|
<register>
|
|
<name>MODE_3</name>
|
|
<description>Channel Capture/Compare Mode</description>
|
|
<addressOffset>0xc0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COSEL</name>
|
|
<description>Channel Output Function Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT</name>
|
|
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT</name>
|
|
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMD</name>
|
|
<description>PWM N-Bit Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIFGEN</name>
|
|
<description>Differential Signal Generator Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Channel Operating Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE_PWM</name>
|
|
<description>Configure the channel for edge-aligned PWM mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_PWM</name>
|
|
<description>Configure the channel for center-aligned PWM mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HF_SQUARE_WAVE</name>
|
|
<description>Configure the channel for high-frequency/square-wave mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CAPTURE</name>
|
|
<description>Configure the channel for timer/capture mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>N_BIT_PWM</name>
|
|
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL_3</name>
|
|
<description>Channel Capture/Compare Control</description>
|
|
<addressOffset>0xd0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUTST</name>
|
|
<description>Channel Output State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The channel output state is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The channel output state is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCAPEN</name>
|
|
<description>Positive Edge Input Capture Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable positive-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNCAPEN</name>
|
|
<description>Negative Edge Input Capture Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable negative-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUPDCF</name>
|
|
<description>Channel Register Update Complete Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A EPCA channel register update completed or is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A EPCA channel register update has not completed and is still pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>YPHST</name>
|
|
<description>Differential Y Phase State. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the Y Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the Y Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVEPH</name>
|
|
<description>Active Channel Select. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>YACTIVE</name>
|
|
<description>The Y Phase is active and X Phase is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XACTIVE</name>
|
|
<description>The X Phase is active and Y Phase is inactive.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XPHST</name>
|
|
<description>Differential X Phase State. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the X Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the X Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIEN</name>
|
|
<description>Capture/Compare Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel capture/compare interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel capture/compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCDEN</name>
|
|
<description>Capture/Compare DMA Request Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCSEN</name>
|
|
<description>Capture/Compare Synchronization Signal Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFIEN</name>
|
|
<description>Intermediate Overflow Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel intermediate overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel intermediate overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFDEN</name>
|
|
<description>Intermediate Overflow DMA Request Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFSEN</name>
|
|
<description>Intermediate Overflow Synchronization Signal Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPV_3</name>
|
|
<description>Channel Compare Value</description>
|
|
<addressOffset>0xe0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPV</name>
|
|
<description>Channel Compare Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPVUPD_3</name>
|
|
<description>Channel Compare Update Value</description>
|
|
<addressOffset>0xf0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPVUPD</name>
|
|
<description>Channel Compare Update Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_6-->
|
|
<register>
|
|
<name>MODE_4</name>
|
|
<description>Channel Capture/Compare Mode</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COSEL</name>
|
|
<description>Channel Output Function Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT</name>
|
|
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT</name>
|
|
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMD</name>
|
|
<description>PWM N-Bit Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIFGEN</name>
|
|
<description>Differential Signal Generator Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Channel Operating Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE_PWM</name>
|
|
<description>Configure the channel for edge-aligned PWM mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_PWM</name>
|
|
<description>Configure the channel for center-aligned PWM mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HF_SQUARE_WAVE</name>
|
|
<description>Configure the channel for high-frequency/square-wave mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CAPTURE</name>
|
|
<description>Configure the channel for timer/capture mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>N_BIT_PWM</name>
|
|
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL_4</name>
|
|
<description>Channel Capture/Compare Control</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUTST</name>
|
|
<description>Channel Output State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The channel output state is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The channel output state is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCAPEN</name>
|
|
<description>Positive Edge Input Capture Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable positive-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNCAPEN</name>
|
|
<description>Negative Edge Input Capture Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable negative-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUPDCF</name>
|
|
<description>Channel Register Update Complete Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A EPCA channel register update completed or is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A EPCA channel register update has not completed and is still pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>YPHST</name>
|
|
<description>Differential Y Phase State. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the Y Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the Y Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVEPH</name>
|
|
<description>Active Channel Select. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>YACTIVE</name>
|
|
<description>The Y Phase is active and X Phase is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XACTIVE</name>
|
|
<description>The X Phase is active and Y Phase is inactive.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XPHST</name>
|
|
<description>Differential X Phase State. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the X Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the X Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIEN</name>
|
|
<description>Capture/Compare Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel capture/compare interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel capture/compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCDEN</name>
|
|
<description>Capture/Compare DMA Request Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCSEN</name>
|
|
<description>Capture/Compare Synchronization Signal Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFIEN</name>
|
|
<description>Intermediate Overflow Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel intermediate overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel intermediate overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFDEN</name>
|
|
<description>Intermediate Overflow DMA Request Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFSEN</name>
|
|
<description>Intermediate Overflow Synchronization Signal Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPV_4</name>
|
|
<description>Channel Compare Value</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPV</name>
|
|
<description>Channel Compare Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPVUPD_4</name>
|
|
<description>Channel Compare Update Value</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPVUPD</name>
|
|
<description>Channel Compare Update Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_7-->
|
|
<register>
|
|
<name>MODE_5</name>
|
|
<description>Channel Capture/Compare Mode</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COSEL</name>
|
|
<description>Channel Output Function Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT</name>
|
|
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT</name>
|
|
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMD</name>
|
|
<description>PWM N-Bit Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIFGEN</name>
|
|
<description>Differential Signal Generator Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Channel Operating Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE_PWM</name>
|
|
<description>Configure the channel for edge-aligned PWM mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_PWM</name>
|
|
<description>Configure the channel for center-aligned PWM mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HF_SQUARE_WAVE</name>
|
|
<description>Configure the channel for high-frequency/square-wave mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CAPTURE</name>
|
|
<description>Configure the channel for timer/capture mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>N_BIT_PWM</name>
|
|
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL_5</name>
|
|
<description>Channel Capture/Compare Control</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUTST</name>
|
|
<description>Channel Output State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The channel output state is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The channel output state is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCAPEN</name>
|
|
<description>Positive Edge Input Capture Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable positive-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNCAPEN</name>
|
|
<description>Negative Edge Input Capture Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable negative-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUPDCF</name>
|
|
<description>Channel Register Update Complete Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A EPCA channel register update completed or is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A EPCA channel register update has not completed and is still pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>YPHST</name>
|
|
<description>Differential Y Phase State. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the Y Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the Y Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVEPH</name>
|
|
<description>Active Channel Select. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>YACTIVE</name>
|
|
<description>The Y Phase is active and X Phase is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XACTIVE</name>
|
|
<description>The X Phase is active and Y Phase is inactive.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XPHST</name>
|
|
<description>Differential X Phase State. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Set the X Phase output state to low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Set the X Phase output state to high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIEN</name>
|
|
<description>Capture/Compare Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel capture/compare interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel capture/compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCDEN</name>
|
|
<description>Capture/Compare DMA Request Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCSEN</name>
|
|
<description>Capture/Compare Synchronization Signal Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFIEN</name>
|
|
<description>Intermediate Overflow Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel intermediate overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel intermediate overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFDEN</name>
|
|
<description>Intermediate Overflow DMA Request Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFSEN</name>
|
|
<description>Intermediate Overflow Synchronization Signal Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPV_5</name>
|
|
<description>Channel Compare Value</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPV</name>
|
|
<description>Channel Compare Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPVUPD_5</name>
|
|
<description>Channel Compare Update Value</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPVUPD</name>
|
|
<description>Channel Compare Update Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLASHCTRL_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>FLASHCTRL_0</groupName>
|
|
<baseAddress>0x4002e000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Controller Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000720</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPMD</name>
|
|
<description>Flash Speed Mode. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>Read and write the Flash at speed mode 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>Read and write the Flash at speed mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>Read and write the Flash at speed mode 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>Read and write the Flash at speed mode 3.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDSEN</name>
|
|
<description>Read Store Mode Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable read store mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable read store mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPFEN</name>
|
|
<description>Data Prefetch Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Data accesses are excluded from the prefetch buffer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Data accesses are included in the prefetch buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFINH</name>
|
|
<description>Prefetch Inhibit. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Any reads from Flash are prefetched until the prefetch buffer is full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Inhibit the prefetch engine.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQWEN</name>
|
|
<description>Flash Write Sequence Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable sequential write mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable sequential write mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERASEEN</name>
|
|
<description>Flash Page Erase Enable. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Writes to the WRDATA field will initiate a write to Flash at the address in the WRADDR field.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Writes to the WRDATA field will initiate an erase of the Flash page containing the address in the WRADDR field.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUFSTS</name>
|
|
<description>Flash Buffer Status. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>The Flash controller write data buffer is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>The Flash controller write data buffer is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSYF</name>
|
|
<description>Flash Operation Busy Flag. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The Flash interface is not busy.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The Flash interface is busy with an operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRADDR</name>
|
|
<description>Flash Write Address</description>
|
|
<addressOffset>0xa0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WRADDR</name>
|
|
<description>Flash Write Address. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRDATA</name>
|
|
<description>Flash Write Data</description>
|
|
<addressOffset>0xb0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WRDATA</name>
|
|
<description>Flash Write Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY</name>
|
|
<description>Flash Modification Key</description>
|
|
<addressOffset>0xc0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Flash Key. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MULTI_LOCK</name>
|
|
<value>90</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INITIAL_UNLOCK</name>
|
|
<value>165</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SINGLE_UNLOCK</name>
|
|
<value>241</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTI_UNLOCK</name>
|
|
<value>242</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCONTROL</name>
|
|
<description>Flash Timing Control</description>
|
|
<addressOffset>0xd0</addressOffset>
|
|
<resetValue>0x0003005C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLRTMD</name>
|
|
<description>Flash Read Timing Mode. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLOW</name>
|
|
<description>Configure the Flash read controller for AHB clocks below 20 MHz.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Configure the Flash read controller for AHB clocks above 20 MHz.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>I2C</groupName>
|
|
<baseAddress>0x40009000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C0_IRQn</name>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x10000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSYF</name>
|
|
<description>Busy Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A transaction is not currently taking place.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A transaction is currently taking place.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Acknowledge. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: ACK has not been received. Write: Do not send an ACK.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: ACK received. Write: Send an ACK.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBLF</name>
|
|
<description>Arbitration Lost Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Arbitration lost error has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Arbitration lost error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKRQF</name>
|
|
<description>Acknowledge Request Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>ACK has not been requested.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>ACK requested.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STO</name>
|
|
<description>Stop. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stop is not pending and a stop / repeat start has not been detected. Write: Clear the STO bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Stop or stop / repeat start detected. This bit must be cleared by firmware. Write: Generate a stop.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STA</name>
|
|
<description>Start. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A start is not pending and a repeat start has not been detected. Write: Clear the STA bit. </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Start or repeat start detected. This bit must be cleared by firmware. Write: Generate a start or repeat start. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXMDF</name>
|
|
<description>Transmit Mode Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RECEIVE</name>
|
|
<description>Module is in receiver mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSMIT</name>
|
|
<description>Module is in transmitter mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSMDF</name>
|
|
<description>Master/Slave Mode Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLAVE</name>
|
|
<description>Module is operating in Slave mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER</name>
|
|
<description>Module is operating in Master mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOI</name>
|
|
<description>Stop Interrupt Flag. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stop interrupt has not occurred. Write: Clear the stop interrupt flag (STOI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Stop interrupt detected. In Slave mode, a stop has been detected on the bus. In Master mode, a stop has been generated. Write: Force a stop interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKI</name>
|
|
<description>Acknowledge Interrupt Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An acknowledge interrupt has not occurred. Write: Clear the acknowledge interrupt (ACKI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An acknowledge interrupt occurred. Write: Force an acknowledge interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXI</name>
|
|
<description>Receive Done Interrupt Flag. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A receive done interrupt has not occurred. Write: Clear the receive done interrupt (RXI). </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Receive done interrupt occurred. Write: Force a receive done interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXI</name>
|
|
<description>Transmit Done Interrupt Flag. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A transmit done interrupt has not occurred. Write: Clear the transmit done interrupt (TXI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Transmit done interrupt detected. If the transmit is forced to abort by a NACK response, the acknowledge interrupt (ACKI) will also be set. Write: Force a transmit done interrupt. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STAI</name>
|
|
<description>Start Interrupt Flag. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: Start interrupt has not occurred. Write: Clear the start interrupt (STAI). </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Start or repeat start interrupt occurred. In Slave mode, a start or repeat start is detected. In Master mode, a start or repeat start has been generated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBLI</name>
|
|
<description>Arbitration Lost Interrupt Flag. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An arbitration lost interrupt has not occurred. Write: Clear the arbitration lost interrupt (ARBLI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Arbitration lost interrupt detected. Write: Force an arbitration lost interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T0I</name>
|
|
<description>I2C Timer Byte 0 Interrupt Flag. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A I2C Timer Byte 0 interrupt has not occurred. Write: Clear the I2C Timer Byte 0 interrupt (T0I).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: I2C Timer Byte 0 overflow interrupt detected. Write: Force a I2C Timer Byte 0 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T1I</name>
|
|
<description>I2C Timer Byte 1 Interrupt Flag. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: No interrupt occurred. Write: Clear the I2C Timer Byte 1 interrupt (T1I).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: I2C Timer Byte 1 overflow interrupt is detected. Write: Force a I2C Timer Byte 1 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T2I</name>
|
|
<description>I2C Timer Byte 2 Interrupt Flag. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A I2C Timer Byte 2 interrupt has not occurred. Write: Clear the I2C Timer Byte 2 interrupt (T2I).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: I2C Timer Byte 2 overflow interrupt detected. Write: Force a I2C Timer Byte 2 interrupt. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T3I</name>
|
|
<description>I2C Timer Byte 3 Interrupt Flag. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A I2C Timer Byte 3 interrupt or SCL low timeout has not occurred. Write: Clear the I2C Timer Byte 3 interrupt (T3I).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: I2C Timer Byte 3 overflow or SCL low timeout interrupt detected. Write: Force a I2C Timer Byte 3 interrupt. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXARM</name>
|
|
<description>Receive Arm. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable data and address reception.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the module to perform a receive operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXARM</name>
|
|
<description>Transmit Arm. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable data and address transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the module to perform a transmit operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVAF</name>
|
|
<description>Slave Address Type Flag. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLAVE_ADDRESS</name>
|
|
<description>Slave address detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERAL_CALL</name>
|
|
<description>General Call address detected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATXRXEN</name>
|
|
<description>Auto Transmit or Receive Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not automatically switch to transmit or receive mode after a Start.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>If automatic hardware acknowledge mode is enabled (HACKEN = 1), automatically switch to transmit or receive mode after a Start.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMD</name>
|
|
<description>Filter Mode. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the input filter.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the input filter.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>I2C Debug Mode. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The I2C module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the I2C module to halt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMINH</name>
|
|
<description>Slave Mode Inhibit. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Enable Slave modes.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Inhibit Slave modes. The module will not respond to a Master on the bus.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HACKEN</name>
|
|
<description>Auto Acknowledge Enable . </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable automatic hardware acknowledge.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable automatic hardware acknowledge.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVAMD</name>
|
|
<description>Slave Address Mode. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>7BIT</name>
|
|
<description>Slave addresses are 7 bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10BIT</name>
|
|
<description>Slave addresses are 10 bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBACKEN</name>
|
|
<description>Last Byte Acknowledge Enable. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>NACK after the last byte is received.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>ACK after the last byte is received.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCEN</name>
|
|
<description>General Call Address Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable General Call address decoding.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable General Call address decoding.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>Module Soft Reset. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>I2C module is not in soft reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>I2C module is in soft reset and firmware cannot access all bits in the module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2CEN</name>
|
|
<description>I2C Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2C module.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2C module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCALER</name>
|
|
<description>I2C Clock Scaler. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOIEN</name>
|
|
<description>Stop Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the stop interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the stop interrupt (STOI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKIEN</name>
|
|
<description>Acknowledge Interrupt Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the acknowledge interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the acknowledge interrupt (ACKI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIEN</name>
|
|
<description>Receive Done Interrupt Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive done interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive done interrupt (RXI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXIEN</name>
|
|
<description>Transmit Done Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit done interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit done interrupt (TXI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STAIEN</name>
|
|
<description>Start Interrupt Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the start interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the start interrupt (STAI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBLIEN</name>
|
|
<description>Arbitration Lost Interrupt Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the arbitration lost interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the arbitration lost interrupt (ARBLI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T0IEN</name>
|
|
<description>I2C Timer Byte 0 Interrupt Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2C Timer Byte 0 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2C Timer Byte 0 interrupt (T0I).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T1IEN</name>
|
|
<description>I2C Timer Byte 1 Interrupt Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2C Timer Byte 1 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2C Timer Byte 1 interrupt (T1I).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T2IEN</name>
|
|
<description>I2C Timer Byte 2 Interrupt Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2C Timer Byte 2 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2C Timer Byte 2 interrupt (T2I).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T3IEN</name>
|
|
<description>I2C Timer Byte 3 Interrupt Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2C Timer Byte 3 and SCL low timeout interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2C Timer Byte 3 and SCL low timeout interrupt (T3I).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Transfer Byte Count. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BP</name>
|
|
<description>Transfer Byte Pointer. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>T0RUN</name>
|
|
<description>I2C Timer Byte 0 Run. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop Timer Byte 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start Timer Byte 0 running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T1RUN</name>
|
|
<description>I2C Timer Byte 1 Run. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop Timer Byte 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start Timer Byte 1 running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T2RUN</name>
|
|
<description>I2C Timer Byte 2 Run. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop Timer Byte 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start Timer Byte 2 running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T3RUN</name>
|
|
<description>I2C Timer Byte 3 Run. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop Timer Byte 3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start Timer Byte 3 running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMD</name>
|
|
<description>I2C Timer Mode. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>I2C Timer Mode 0: Operate the I2C timer as a single 32-bit timer : Timer Bytes [3 : 2 : 1 : 0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>I2C Timer Mode 1: Operate the I2C timer as two 16-bit timers : Timer Bytes [3 : 2] and Timer Bytes [1 : 0].</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>I2C Timer Mode 2: Operate the I2C timer as four independent 8-bit timers : Timer Byte 3, Timer Byte 2, Timer Byte 1, and Timer Byte 0.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>I2C Timer Mode 3: Operate the I2C timer as one 16-bit and two 8-bit timers : Timer Bytes [3 : 2], Timer Byte 1, and Timer Byte 0.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMEREN</name>
|
|
<description>I2C Timer Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable I2C Timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable I2C Timer for general purpose use. This setting should not be used when the I2C module is enabled (I2CEN = 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SADDRESS</name>
|
|
<description>Slave Address</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Slave Address. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMASK</name>
|
|
<description>Slave Address Mask</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Slave Address Mask. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Data Buffer Access</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMER</name>
|
|
<description>Timer Data</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>T0</name>
|
|
<description>Timer Byte 0. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T1</name>
|
|
<description>Timer Byte 1. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T2</name>
|
|
<description>Timer Byte 2. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T3</name>
|
|
<description>Timer Byte 3. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMERRL</name>
|
|
<description>Timer Reload Values</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>T0RL</name>
|
|
<description>Timer Byte 0 Reload Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T1RL</name>
|
|
<description>Timer Byte 1 Reload Value. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T2RL</name>
|
|
<description>Timer Byte 2 Reload Value. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T3RL</name>
|
|
<description>Timer Byte 3 Reload Value. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCONFIG</name>
|
|
<description>SCL Signal Configuration</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Data Setup Time Extension. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HOLD</name>
|
|
<description>Data Hold Time Extension. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCLL</name>
|
|
<description>SCL Low Time Extension. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCLLTIMER</name>
|
|
<description>SCL Low Timer Bits [3:0]. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2CDMA</name>
|
|
<description>DMA Configuration</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMALEN</name>
|
|
<description>DMA Transfer Length. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Mode Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable I2C DMA data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable I2C DMA data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C_1</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>I2C</groupName>
|
|
<baseAddress>0x4000a000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C1_IRQn</name>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x10000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSYF</name>
|
|
<description>Busy Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A transaction is not currently taking place.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A transaction is currently taking place.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Acknowledge. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: ACK has not been received. Write: Do not send an ACK.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: ACK received. Write: Send an ACK.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBLF</name>
|
|
<description>Arbitration Lost Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Arbitration lost error has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Arbitration lost error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKRQF</name>
|
|
<description>Acknowledge Request Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>ACK has not been requested.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>ACK requested.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STO</name>
|
|
<description>Stop. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stop is not pending and a stop / repeat start has not been detected. Write: Clear the STO bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Stop or stop / repeat start detected. This bit must be cleared by firmware. Write: Generate a stop.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STA</name>
|
|
<description>Start. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A start is not pending and a repeat start has not been detected. Write: Clear the STA bit. </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Start or repeat start detected. This bit must be cleared by firmware. Write: Generate a start or repeat start. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXMDF</name>
|
|
<description>Transmit Mode Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RECEIVE</name>
|
|
<description>Module is in receiver mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRANSMIT</name>
|
|
<description>Module is in transmitter mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSMDF</name>
|
|
<description>Master/Slave Mode Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLAVE</name>
|
|
<description>Module is operating in Slave mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER</name>
|
|
<description>Module is operating in Master mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOI</name>
|
|
<description>Stop Interrupt Flag. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stop interrupt has not occurred. Write: Clear the stop interrupt flag (STOI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Stop interrupt detected. In Slave mode, a stop has been detected on the bus. In Master mode, a stop has been generated. Write: Force a stop interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKI</name>
|
|
<description>Acknowledge Interrupt Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An acknowledge interrupt has not occurred. Write: Clear the acknowledge interrupt (ACKI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An acknowledge interrupt occurred. Write: Force an acknowledge interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXI</name>
|
|
<description>Receive Done Interrupt Flag. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A receive done interrupt has not occurred. Write: Clear the receive done interrupt (RXI). </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Receive done interrupt occurred. Write: Force a receive done interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXI</name>
|
|
<description>Transmit Done Interrupt Flag. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A transmit done interrupt has not occurred. Write: Clear the transmit done interrupt (TXI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Transmit done interrupt detected. If the transmit is forced to abort by a NACK response, the acknowledge interrupt (ACKI) will also be set. Write: Force a transmit done interrupt. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STAI</name>
|
|
<description>Start Interrupt Flag. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: Start interrupt has not occurred. Write: Clear the start interrupt (STAI). </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Start or repeat start interrupt occurred. In Slave mode, a start or repeat start is detected. In Master mode, a start or repeat start has been generated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBLI</name>
|
|
<description>Arbitration Lost Interrupt Flag. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An arbitration lost interrupt has not occurred. Write: Clear the arbitration lost interrupt (ARBLI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Arbitration lost interrupt detected. Write: Force an arbitration lost interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T0I</name>
|
|
<description>I2C Timer Byte 0 Interrupt Flag. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A I2C Timer Byte 0 interrupt has not occurred. Write: Clear the I2C Timer Byte 0 interrupt (T0I).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: I2C Timer Byte 0 overflow interrupt detected. Write: Force a I2C Timer Byte 0 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T1I</name>
|
|
<description>I2C Timer Byte 1 Interrupt Flag. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: No interrupt occurred. Write: Clear the I2C Timer Byte 1 interrupt (T1I).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: I2C Timer Byte 1 overflow interrupt is detected. Write: Force a I2C Timer Byte 1 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T2I</name>
|
|
<description>I2C Timer Byte 2 Interrupt Flag. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A I2C Timer Byte 2 interrupt has not occurred. Write: Clear the I2C Timer Byte 2 interrupt (T2I).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: I2C Timer Byte 2 overflow interrupt detected. Write: Force a I2C Timer Byte 2 interrupt. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T3I</name>
|
|
<description>I2C Timer Byte 3 Interrupt Flag. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A I2C Timer Byte 3 interrupt or SCL low timeout has not occurred. Write: Clear the I2C Timer Byte 3 interrupt (T3I).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: I2C Timer Byte 3 overflow or SCL low timeout interrupt detected. Write: Force a I2C Timer Byte 3 interrupt. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXARM</name>
|
|
<description>Receive Arm. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable data and address reception.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the module to perform a receive operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXARM</name>
|
|
<description>Transmit Arm. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable data and address transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the module to perform a transmit operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVAF</name>
|
|
<description>Slave Address Type Flag. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLAVE_ADDRESS</name>
|
|
<description>Slave address detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERAL_CALL</name>
|
|
<description>General Call address detected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATXRXEN</name>
|
|
<description>Auto Transmit or Receive Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not automatically switch to transmit or receive mode after a Start.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>If automatic hardware acknowledge mode is enabled (HACKEN = 1), automatically switch to transmit or receive mode after a Start.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FMD</name>
|
|
<description>Filter Mode. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the input filter.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the input filter.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>I2C Debug Mode. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The I2C module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the I2C module to halt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMINH</name>
|
|
<description>Slave Mode Inhibit. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Enable Slave modes.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Inhibit Slave modes. The module will not respond to a Master on the bus.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HACKEN</name>
|
|
<description>Auto Acknowledge Enable . </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable automatic hardware acknowledge.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable automatic hardware acknowledge.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVAMD</name>
|
|
<description>Slave Address Mode. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>7BIT</name>
|
|
<description>Slave addresses are 7 bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10BIT</name>
|
|
<description>Slave addresses are 10 bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBACKEN</name>
|
|
<description>Last Byte Acknowledge Enable. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>NACK after the last byte is received.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>ACK after the last byte is received.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCEN</name>
|
|
<description>General Call Address Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable General Call address decoding.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable General Call address decoding.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>Module Soft Reset. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>I2C module is not in soft reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>I2C module is in soft reset and firmware cannot access all bits in the module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2CEN</name>
|
|
<description>I2C Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2C module.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2C module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCALER</name>
|
|
<description>I2C Clock Scaler. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOIEN</name>
|
|
<description>Stop Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the stop interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the stop interrupt (STOI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKIEN</name>
|
|
<description>Acknowledge Interrupt Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the acknowledge interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the acknowledge interrupt (ACKI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIEN</name>
|
|
<description>Receive Done Interrupt Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive done interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive done interrupt (RXI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXIEN</name>
|
|
<description>Transmit Done Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit done interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit done interrupt (TXI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STAIEN</name>
|
|
<description>Start Interrupt Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the start interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the start interrupt (STAI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARBLIEN</name>
|
|
<description>Arbitration Lost Interrupt Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the arbitration lost interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the arbitration lost interrupt (ARBLI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T0IEN</name>
|
|
<description>I2C Timer Byte 0 Interrupt Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2C Timer Byte 0 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2C Timer Byte 0 interrupt (T0I).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T1IEN</name>
|
|
<description>I2C Timer Byte 1 Interrupt Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2C Timer Byte 1 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2C Timer Byte 1 interrupt (T1I).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T2IEN</name>
|
|
<description>I2C Timer Byte 2 Interrupt Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2C Timer Byte 2 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2C Timer Byte 2 interrupt (T2I).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T3IEN</name>
|
|
<description>I2C Timer Byte 3 Interrupt Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2C Timer Byte 3 and SCL low timeout interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2C Timer Byte 3 and SCL low timeout interrupt (T3I).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Transfer Byte Count. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BP</name>
|
|
<description>Transfer Byte Pointer. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>T0RUN</name>
|
|
<description>I2C Timer Byte 0 Run. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop Timer Byte 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start Timer Byte 0 running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T1RUN</name>
|
|
<description>I2C Timer Byte 1 Run. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop Timer Byte 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start Timer Byte 1 running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T2RUN</name>
|
|
<description>I2C Timer Byte 2 Run. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop Timer Byte 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start Timer Byte 2 running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>T3RUN</name>
|
|
<description>I2C Timer Byte 3 Run. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop Timer Byte 3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start Timer Byte 3 running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMD</name>
|
|
<description>I2C Timer Mode. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>I2C Timer Mode 0: Operate the I2C timer as a single 32-bit timer : Timer Bytes [3 : 2 : 1 : 0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>I2C Timer Mode 1: Operate the I2C timer as two 16-bit timers : Timer Bytes [3 : 2] and Timer Bytes [1 : 0].</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>I2C Timer Mode 2: Operate the I2C timer as four independent 8-bit timers : Timer Byte 3, Timer Byte 2, Timer Byte 1, and Timer Byte 0.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>I2C Timer Mode 3: Operate the I2C timer as one 16-bit and two 8-bit timers : Timer Bytes [3 : 2], Timer Byte 1, and Timer Byte 0.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMEREN</name>
|
|
<description>I2C Timer Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable I2C Timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable I2C Timer for general purpose use. This setting should not be used when the I2C module is enabled (I2CEN = 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SADDRESS</name>
|
|
<description>Slave Address</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Slave Address. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMASK</name>
|
|
<description>Slave Address Mask</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Slave Address Mask. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Data Buffer Access</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMER</name>
|
|
<description>Timer Data</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>T0</name>
|
|
<description>Timer Byte 0. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T1</name>
|
|
<description>Timer Byte 1. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T2</name>
|
|
<description>Timer Byte 2. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T3</name>
|
|
<description>Timer Byte 3. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMERRL</name>
|
|
<description>Timer Reload Values</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>T0RL</name>
|
|
<description>Timer Byte 0 Reload Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T1RL</name>
|
|
<description>Timer Byte 1 Reload Value. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T2RL</name>
|
|
<description>Timer Byte 2 Reload Value. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T3RL</name>
|
|
<description>Timer Byte 3 Reload Value. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCONFIG</name>
|
|
<description>SCL Signal Configuration</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Data Setup Time Extension. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HOLD</name>
|
|
<description>Data Hold Time Extension. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCLL</name>
|
|
<description>SCL Low Time Extension. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCLLTIMER</name>
|
|
<description>SCL Low Timer Bits [3:0]. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2S_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>I2S_0</groupName>
|
|
<baseAddress>0x4003a000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2S0RX_IRQn</name>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2S0TX_IRQn</name>
|
|
<value>41</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>TXCONTROL</name>
|
|
<description>Transmit Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x02000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FSGEN</name>
|
|
<description>DFS Generator Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the internal DFS generator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the internal DFS generator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSSEN</name>
|
|
<description>DFS Synchronize Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The internal DFS generator starts immediately when FSGEN is set to 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Synchronize the rising edge of the internally generated WS signal from the DFS generator to the rising edge of the external WS input signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDIS</name>
|
|
<description>Transmit Delay Disable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The first data bit is sent on the second or later rising edge of SCK after WS changes.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>The first data bit is sent on the first rising edge of SCK after WS changes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSDEL</name>
|
|
<description>Transmit Initial Phase Delay. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSSRCSEL</name>
|
|
<description>Transmit Frame Sync Source Select. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FSIN_EXT</name>
|
|
<description>The word select or frame sync is input from the WS pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FSIN_INT</name>
|
|
<description>The word select or frame sync is input from the internal DFS generator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILLSEL</name>
|
|
<description>Transmit Data Fill Select. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZEROS</name>
|
|
<description>Send zeros during unused bit cycles.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONES</name>
|
|
<description>Send ones during unused bit cycles.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIGN</name>
|
|
<description>Send the sign bit of the current sample (MSB-first format) or last sample (LSB-first format) during unused bit cycles.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANDOM</name>
|
|
<description>Send pseudo-random data generated by an 8-bit LFSR during unused bit cycles.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>JSEL</name>
|
|
<description>Transmit Data Justification Select. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LEFT</name>
|
|
<description>Use left-justified or I2S-style formats.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RIGHT</name>
|
|
<description>Use right-justified format.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSINVEN</name>
|
|
<description>Transmit WS Inversion Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Don't invert the WS signal. Use this setting for I2S format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the WS signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLKINVEN</name>
|
|
<description>Transmit SCK Inversion Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the transmitter bit clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the transmitter bit clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORDER</name>
|
|
<description>Transmit Order. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LEFT_RIGHT</name>
|
|
<description>Left sample transmitted first, right sample transmitted second. Use this setting for I2S format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RIGHT_LEFT</name>
|
|
<description>Right sample transmitted first, left sample transmitted second.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBSEL</name>
|
|
<description>Transmit Mono Bit-Width Select. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>8BITS</name>
|
|
<description>8 bits are sent per mono sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9BITS</name>
|
|
<description>9 bits are sent per mono sample.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16BITS</name>
|
|
<description>16 bits are sent per mono sample.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>24BITS</name>
|
|
<description>24 bits are sent per mono sample.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32BITS</name>
|
|
<description>32 bits are sent per mono sample.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2S transmitter.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2S transmitter.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMODE</name>
|
|
<description>Transmit Mode</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CYCLE</name>
|
|
<description>Transmit Clock Cycle Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Transmit Start Control. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTS</name>
|
|
<description>Transmit Drive Select. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDIS</name>
|
|
<description>Transmit Drive Early Disable. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Drive the output during every cycle of the transmitter's assigned slot(s), including the last clock cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Drive the output for every cycle of the transmitter's assigned slot(s), except for the last clock cycle of the last slot.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIMD</name>
|
|
<description>Transmit Drive Inactive Mode. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZERO</name>
|
|
<description>Drive zero on the data output pin during non-active slots.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_Z</name>
|
|
<description>Don't drive the data output pin. The data output pin is tristated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMEN</name>
|
|
<description>Transmit Time Division Multiplexing Enable. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the time division multiplexing (TDM) feature.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the time division multiplexing (TDM) feature.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSDUTY</name>
|
|
<description>Frame Sync Duty Cycle</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FSLOW</name>
|
|
<description>Frame Sync Low Time. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSHIGH</name>
|
|
<description>Frame Sync High Time. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCONTROL</name>
|
|
<description>Receive Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00010000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FSDEL</name>
|
|
<description>Receive Initial Phase Delay. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JSEL</name>
|
|
<description>Receive Data Justification. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LEFT</name>
|
|
<description>Use left-justified or I2S-style formats.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RIGHT</name>
|
|
<description>Use right-justified format.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDIS</name>
|
|
<description>Receive Delay Disable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The first data bit is captured on the second or later rising edge of SCK after WS changes.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>The first data bit is captured by the receiver on the first rising edge of SCK after WS changes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSINVEN</name>
|
|
<description>Receive WS Inversion Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Don't invert the WS signal. Use this setting for I2S format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the WS signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCLKINVEN</name>
|
|
<description>Receive SCK Inversion Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the receiver bit clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the receiver bit clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORDER</name>
|
|
<description>Receive Order. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LEFT_RIGHT</name>
|
|
<description>Left sample received first, right sample received second. Use this setting for I2S format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RIGHT_LEFT</name>
|
|
<description>Right sample received first, left sample received second.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBSEL</name>
|
|
<description>Receive Mono Bit-Width Select. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>8BITS</name>
|
|
<description>8 bits are received per mono sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9BITS</name>
|
|
<description>9 bits are received per mono sample.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16BITS</name>
|
|
<description>16 bits are received per mono sample.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>24BITS</name>
|
|
<description>24 bits are received per mono sample.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32BITS</name>
|
|
<description>32 bits are received per mono sample.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSSRCSEL</name>
|
|
<description>Receive Frame Sync Source Select. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FSIN_EXT</name>
|
|
<description>The word select or frame sync is input from the WS pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FSIN_INT</name>
|
|
<description>The word select or frame sync is input from the internal DFS generator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receive Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2S receiver.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2S receiver.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXMODE</name>
|
|
<description>Receive Mode</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CYCLE</name>
|
|
<description>Receive Clock Cycle Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Receive Start Control. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTS</name>
|
|
<description>Receive Drive Select. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDMEN</name>
|
|
<description>Receive Time Division Multiplexing Enable. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the time division multiplexing (TDM) feature.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the time division multiplexing (TDM) feature.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKCONTROL</name>
|
|
<description>Clock Control</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTDIV</name>
|
|
<description>Clock Divider Integer Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRACDIV</name>
|
|
<description>Clock Divider Fractional Value. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUTYMD</name>
|
|
<description>Duty Cycle Adjustment Mode. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MORE</name>
|
|
<description>When the division is fractional, the clock high time will be greater than 50% (by half of the source clock period).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESS</name>
|
|
<description>When the division is fractional, the clock low time will be greater than 50% (by half of the source clock period).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKUPD</name>
|
|
<description>Clock Divider Update. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Update the clock divider with new values of INTDIV, FRACDIV, and DIVEN.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVEN</name>
|
|
<description>Clock Divider Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the clock divider.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the clock divider.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCLKSEL</name>
|
|
<description>Transmit Clock Select. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTERNAL</name>
|
|
<description>The I2S transmitter is clocked from the internal clock divider.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTERNAL</name>
|
|
<description>The I2S transmitter is clocked from the SCK pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXCLKSEL</name>
|
|
<description>Receive Clock Select. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTERNAL</name>
|
|
<description>The I2S receiver is clocked from the internal clock divider.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTERNAL</name>
|
|
<description>The I2S receiver is clocked from the SCK pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>I2S Module Reset. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Reset the I2S module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXCLKEN</name>
|
|
<description>Receive Clock Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2S receiver clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2S receiver clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCLKEN</name>
|
|
<description>Transmit Clock Enable. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the I2S transmitter clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the I2S transmitter clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXSCLKMD</name>
|
|
<description>Receive SCK Mode. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCK_OUTPUT</name>
|
|
<description>The I2S receiver SCK signal is an output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK_INPUT</name>
|
|
<description>The I2S receiver SCK signal is an input.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXSCLKMD</name>
|
|
<description>Transmit SCK Mode. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCK_OUTPUT</name>
|
|
<description>The I2S transmitter SCK signal is an output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK_INPUT</name>
|
|
<description>The I2S transmitter SCK signal is an input.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFIFO</name>
|
|
<description>Transmit Data FIFO</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Transmit Data FIFO. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFO</name>
|
|
<description>Receive Data FIFO</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Receive Data FIFO. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOSTATUS</name>
|
|
<description>FIFO Status</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXFIFONUM</name>
|
|
<description>Transmit FIFO Status. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFONUM</name>
|
|
<description>Receive FIFO Status. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOCONTROL</name>
|
|
<description>FIFO Control</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXFIFOWM</name>
|
|
<description>Transmit FIFO Low Watermark. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFOWM</name>
|
|
<description>Receive FIFO High Watermark. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOFL</name>
|
|
<description>Transmit FIFO Flush. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the I2S transmitter FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFOFL</name>
|
|
<description>Receive FIFO Flush. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the I2S receiver FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCONTROL</name>
|
|
<description>Interrupt Control</description>
|
|
<addressOffset>0xa0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXUFIEN</name>
|
|
<description>Transmit Underflow Interrupt Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit underflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit underflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXOFIEN</name>
|
|
<description>Receive Overflow Interrupt Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXLWMIEN</name>
|
|
<description>Transmit FIFO Low Watermark Interrupt Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit FIFO low watermark interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit FIFO low watermark interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXHWMIEN</name>
|
|
<description>Receive FIFO High Watermark Interrupt Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive FIFO high watermark interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive FIFO high watermark interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0xb0</addressOffset>
|
|
<resetValue>0x0000002C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXUFI</name>
|
|
<description>Transmit Underflow Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A transmit underflow has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A transmit underflow occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXOFI</name>
|
|
<description>Receive Overflow Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A receive overflow has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A receive overflow occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXLWMI</name>
|
|
<description>Transmit FIFO Low Watermark Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Transmit FIFO level is above the low watermark.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Transmit FIFO level is at or below the low watermark.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXHWMI</name>
|
|
<description>Receive FIFO High Watermark Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Receive FIFO level is below the high watermark.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Receive FIFO level is at or above the high watermark.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDBUSYF</name>
|
|
<description>Clock Divider Busy Flag. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_BUSY</name>
|
|
<description>The divider is not busy and an update is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUSY</name>
|
|
<description>The divider is busy and an update is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CDSTS</name>
|
|
<description>Clock Divider Counter Status. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUNNING</name>
|
|
<description>Divided clock output is running.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALTED</name>
|
|
<description>Divided clock output is halted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCLKSELRF</name>
|
|
<description>Transmit Clock Select Ready Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The transmit clock is not synchronized.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The transmit clock is synchronized and the transmitter is ready to send data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXCLKSELRF</name>
|
|
<description>Receive Clock Select Ready Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The receive clock is not synchronized.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The receive clock is synchronized and the receiver is ready to accept data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCLKENRF</name>
|
|
<description>Transmit Clock Enable Ready Flag. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The transmit clock is not synchronized.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The transmit clock is synchronized and the transmitter is ready to send data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXCLKENRF</name>
|
|
<description>Receive Clock Enable Ready Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The receive clock is not synchronized.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The receive clock is synchronized and the receiver is ready to accept data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACONTROL</name>
|
|
<description>DMA Control</description>
|
|
<addressOffset>0xc0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDMAEN</name>
|
|
<description>Transmit DMA Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable transmitter DMA data requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable transmitter DMA data requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDMAEN</name>
|
|
<description>Receive DMA Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable receiver DMA data transfer requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable receiver DMA data transfer requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDMABMD</name>
|
|
<description>Transmit DMA Burst Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE_WORD</name>
|
|
<description>The transmitter transmits one word at a time. Whenever there is any room in the transmit FIFO, a single word burst DMA data request is generated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR_WORDS</name>
|
|
<description>The transmitter transmits four words at a time. Whenever the FIFO depth drops below five, a DMA burst request is generated for four words.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDMABMD</name>
|
|
<description>Receive DMA Burst Mode. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE_WORD</name>
|
|
<description>The receiver receives one word at a time. Whenever there is at least one word in the receive FIFO, a single word burst DMA request is generated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR_WORDS</name>
|
|
<description>The receiver receives four words at a time. Whenever the FIFO depth rises above three, a DMA burst request is generated for four words.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGCONTROL</name>
|
|
<description>Debug Control</description>
|
|
<addressOffset>0xd0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDBGHEN</name>
|
|
<description>I2S Transmit DMA Debug Halt Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Transmit DMA requests continue while the core is debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Transmit DMA requests stop while the core is debug mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDBGHEN</name>
|
|
<description>I2S Receive DMA Debug Halt Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Receive DMA requests continue while the core is debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Receive DMA requests stop while the core is debug mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDBGMD</name>
|
|
<description>I2S Transmit Debug Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The clock to the I2S transmitter is active in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>The clock to the I2S transmitter is not active in debug mode. The clock divider keeps running and the clock will be disabled when two samples are ready to be sent by the transmitter.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDBGMD</name>
|
|
<description>I2S Receive Debug Mode. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The clock to the I2S receiver is active in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>The clock to the I2S receiver is not active in debug mode. The clock divider keeps running and the clock will be disabled when two samples are captured in the receiver.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IDAC_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>IDAC</groupName>
|
|
<baseAddress>0x40031000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>IDAC0_IRQn</name>
|
|
<value>48</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000007</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUPDT</name>
|
|
<description>Output Update Trigger. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DACNT8</name>
|
|
<description>The IDAC output updates using the DACnT8 (Timer 0 Low Overflow) trigger source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT9</name>
|
|
<description>The IDAC output updates using the DACnT9 (Timer 1 High Overflow) trigger source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT10</name>
|
|
<description>The IDAC output updates using the DACnT10 (Timer 1 Low Overflow) trigger source.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT11</name>
|
|
<description>The IDAC output updates using the DACnT11 (Timer 1 High Overflow) trigger source.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT12</name>
|
|
<description>The IDAC output updates on the rising edge of the trigger source selected by ETRIG.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT13</name>
|
|
<description>The IDAC output updates on the falling edge of the trigger source selected by ETRIG.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT14</name>
|
|
<description>The IDAC output updates on any edge of the trigger source selected by ETRIG.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT15</name>
|
|
<description>The IDAC output updates on write to DATA register (On Demand).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ETRIG</name>
|
|
<description>Edge Trigger Source Select. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DACNT0</name>
|
|
<description>Select DACnT0 (PB3.2) as the IDAC external trigger source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT1</name>
|
|
<description>Select DACnT1 (PB3.3) as the IDAC external trigger source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT2</name>
|
|
<description>Select DACnT2 (PB3.5) as the IDAC external trigger source.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT3</name>
|
|
<description>Select DACnT3 (PB3.6) as the IDAC external trigger source.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT4</name>
|
|
<description>Select DACnT4 (PB3.7) as the IDAC external trigger source.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT5</name>
|
|
<description>Select DACnT5 (PB3.8) as the IDAC external trigger source.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT6</name>
|
|
<description>Select DACnT6 (PB3.9) as the IDAC external trigger source.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT7</name>
|
|
<description>Select DACnT7 (SSG0 EX2) as the IDAC external trigger source.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTMD</name>
|
|
<description>Output Mode. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0P5_MA</name>
|
|
<description>The full-scale output current is 0.5 mA.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_MA</name>
|
|
<description>The full-scale output current is 1 mA.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_MA</name>
|
|
<description>The full-scale output current is 2 mA.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INFMT</name>
|
|
<description>Data Input Format. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1_10_BIT</name>
|
|
<description>Writes are interpreted as one 10-bit sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_10_BIT</name>
|
|
<description>Writes are interpreted as two 10-bit samples.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_8_BIT</name>
|
|
<description>Writes are interpreted as four 8-bit samples.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMARUN</name>
|
|
<description>DMA Run. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Read: No DMA operations are occurring or the DMA is done. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: A DMA operation is currently in progress. Write: Start a DMA operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>JSEL</name>
|
|
<description>Data Justification Select. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RIGHT</name>
|
|
<description>Data is right-justified.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEFT</name>
|
|
<description>Data is left-justified.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUFRESET</name>
|
|
<description>Data Buffer Reset. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Initiate a data buffer reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGINH</name>
|
|
<description>Trigger Source Inhibit. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The selected trigger source will cause the IDAC output to update.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>The selected trigger source will not update the IDAC output, except for On-Demand DATA writes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRAPEN</name>
|
|
<description>Wrap Mode Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The IDAC will not wrap when it reaches the end of the data buffer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The IDAC will cycle through the data buffer contents.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIEN</name>
|
|
<description>FIFO Overrun Interrupt Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the FIFO overrun interrupt (ORI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the FIFO overrun interrupt (ORI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>URIEN</name>
|
|
<description>FIFO Underrun Interrupt Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the FIFO underrun interrupt (URI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the FIFO underrun interrupt (URI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WEIEN</name>
|
|
<description>FIFO Went Empty Interrupt Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the FIFO went empty interrupt (WEI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the FIFO went empty interrupt (WEI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>IDAC Debug Mode. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The IDAC module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the IDAC module to halt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOADEN</name>
|
|
<description>Load Resistor Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the internal load resistor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the internal load resistor.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDACEN</name>
|
|
<description>IDAC Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the IDAC.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the IDAC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Output Data</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Output Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUFSTATUS</name>
|
|
<description>FIFO Buffer Status</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>FIFO Level. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>The data FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1WORD</name>
|
|
<description>The data FIFO contains one word.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2WORDS</name>
|
|
<description>The data FIFO contains two words.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3WORDS</name>
|
|
<description>The data FIFO contains three words.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4WORDS</name>
|
|
<description>The data FIFO is full and contains four words.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORI</name>
|
|
<description>FIFO Overrun Interrupt Flag. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A FIFO overrun has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A FIFO overrun occurred. Write: Force a FIFO overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>URI</name>
|
|
<description>FIFO Underrun Interrupt Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A FIFO underrun has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A FIFO underrun occurred. Write: Force a FIFO underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WEI</name>
|
|
<description>FIFO Went Empty Interrupt Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A FIFO went empty condition has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: The FIFO is empty. Write: Force a FIFO went empty interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUFFER10</name>
|
|
<description>FIFO Buffer Entries 0 and 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUFFER0</name>
|
|
<description>FIFO Buffer Entry 0. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFFER1</name>
|
|
<description>FIFO Buffer Entry 1. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUFFER32</name>
|
|
<description>FIFO Buffer Entries 2 and 3</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUFFER2</name>
|
|
<description>FIFO Buffer Entry 2. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFFER3</name>
|
|
<description>FIFO Buffer Entry 3. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GAINADJ</name>
|
|
<description>Output Current Gain Adjust</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x0000000D</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GAINADJ</name>
|
|
<description>Output Current Gain Adjust. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IDAC_1</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>IDAC</groupName>
|
|
<baseAddress>0x40032000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>IDAC1_IRQn</name>
|
|
<value>49</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000007</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUPDT</name>
|
|
<description>Output Update Trigger. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DACNT8</name>
|
|
<description>The IDAC output updates using the DACnT8 (Timer 0 Low Overflow) trigger source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT9</name>
|
|
<description>The IDAC output updates using the DACnT9 (Timer 1 High Overflow) trigger source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT10</name>
|
|
<description>The IDAC output updates using the DACnT10 (Timer 1 Low Overflow) trigger source.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT11</name>
|
|
<description>The IDAC output updates using the DACnT11 (Timer 1 High Overflow) trigger source.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT12</name>
|
|
<description>The IDAC output updates on the rising edge of the trigger source selected by ETRIG.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT13</name>
|
|
<description>The IDAC output updates on the falling edge of the trigger source selected by ETRIG.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT14</name>
|
|
<description>The IDAC output updates on any edge of the trigger source selected by ETRIG.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT15</name>
|
|
<description>The IDAC output updates on write to DATA register (On Demand).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ETRIG</name>
|
|
<description>Edge Trigger Source Select. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DACNT0</name>
|
|
<description>Select DACnT0 (PB3.2) as the IDAC external trigger source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT1</name>
|
|
<description>Select DACnT1 (PB3.3) as the IDAC external trigger source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT2</name>
|
|
<description>Select DACnT2 (PB3.5) as the IDAC external trigger source.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT3</name>
|
|
<description>Select DACnT3 (PB3.6) as the IDAC external trigger source.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT4</name>
|
|
<description>Select DACnT4 (PB3.7) as the IDAC external trigger source.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT5</name>
|
|
<description>Select DACnT5 (PB3.8) as the IDAC external trigger source.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT6</name>
|
|
<description>Select DACnT6 (PB3.9) as the IDAC external trigger source.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACNT7</name>
|
|
<description>Select DACnT7 (SSG0 EX3) as the IDAC external trigger source.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTMD</name>
|
|
<description>Output Mode. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0P5_MA</name>
|
|
<description>The full-scale output current is 0.5 mA.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_MA</name>
|
|
<description>The full-scale output current is 1 mA.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_MA</name>
|
|
<description>The full-scale output current is 2 mA.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INFMT</name>
|
|
<description>Data Input Format. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1_10_BIT</name>
|
|
<description>Writes are interpreted as one 10-bit sample.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_10_BIT</name>
|
|
<description>Writes are interpreted as two 10-bit samples.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_8_BIT</name>
|
|
<description>Writes are interpreted as four 8-bit samples.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMARUN</name>
|
|
<description>DMA Run. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Read: No DMA operations are occurring or the DMA is done. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Read: A DMA operation is currently in progress. Write: Start a DMA operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>JSEL</name>
|
|
<description>Data Justification Select. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RIGHT</name>
|
|
<description>Data is right-justified.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEFT</name>
|
|
<description>Data is left-justified.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUFRESET</name>
|
|
<description>Data Buffer Reset. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Initiate a data buffer reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGINH</name>
|
|
<description>Trigger Source Inhibit. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The selected trigger source will cause the IDAC output to update.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>The selected trigger source will not update the IDAC output, except for On-Demand DATA writes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRAPEN</name>
|
|
<description>Wrap Mode Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The IDAC will not wrap when it reaches the end of the data buffer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The IDAC will cycle through the data buffer contents.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIEN</name>
|
|
<description>FIFO Overrun Interrupt Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the FIFO overrun interrupt (ORI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the FIFO overrun interrupt (ORI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>URIEN</name>
|
|
<description>FIFO Underrun Interrupt Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the FIFO underrun interrupt (URI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the FIFO underrun interrupt (URI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WEIEN</name>
|
|
<description>FIFO Went Empty Interrupt Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the FIFO went empty interrupt (WEI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the FIFO went empty interrupt (WEI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>IDAC Debug Mode. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The IDAC module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the IDAC module to halt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOADEN</name>
|
|
<description>Load Resistor Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the internal load resistor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the internal load resistor.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDACEN</name>
|
|
<description>IDAC Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the IDAC.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the IDAC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Output Data</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Output Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUFSTATUS</name>
|
|
<description>FIFO Buffer Status</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>FIFO Level. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>The data FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1WORD</name>
|
|
<description>The data FIFO contains one word.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2WORDS</name>
|
|
<description>The data FIFO contains two words.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3WORDS</name>
|
|
<description>The data FIFO contains three words.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4WORDS</name>
|
|
<description>The data FIFO is full and contains four words.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORI</name>
|
|
<description>FIFO Overrun Interrupt Flag. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A FIFO overrun has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A FIFO overrun occurred. Write: Force a FIFO overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>URI</name>
|
|
<description>FIFO Underrun Interrupt Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A FIFO underrun has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A FIFO underrun occurred. Write: Force a FIFO underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WEI</name>
|
|
<description>FIFO Went Empty Interrupt Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A FIFO went empty condition has not occurred. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: The FIFO is empty. Write: Force a FIFO went empty interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUFFER10</name>
|
|
<description>FIFO Buffer Entries 0 and 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUFFER0</name>
|
|
<description>FIFO Buffer Entry 0. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFFER1</name>
|
|
<description>FIFO Buffer Entry 1. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUFFER32</name>
|
|
<description>FIFO Buffer Entries 2 and 3</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUFFER2</name>
|
|
<description>FIFO Buffer Entry 2. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFFER3</name>
|
|
<description>FIFO Buffer Entry 3. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GAINADJ</name>
|
|
<description>Output Current Gain Adjust</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x0000000D</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GAINADJ</name>
|
|
<description>Output Current Gain Adjust. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IVC_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>IVC_0</groupName>
|
|
<baseAddress>0x40044000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IN0RANGE</name>
|
|
<description>Input 0 Range. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>6_MA</name>
|
|
<description>Input range is 0-6 mA.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_MA</name>
|
|
<description>Input range is 0-5 mA.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_MA</name>
|
|
<description>Input range is 0-4 mA.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_MA</name>
|
|
<description>Input range is 0-3 mA.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_MA</name>
|
|
<description>Input range is 0-2 mA.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_MA</name>
|
|
<description>Input range is 0-1 mA.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN1RANGE</name>
|
|
<description>Input 1 Range. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>6_MA</name>
|
|
<description>Input range is 0-6 mA.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_MA</name>
|
|
<description>Input range is 0-5 mA.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_MA</name>
|
|
<description>Input range is 0-4 mA.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_MA</name>
|
|
<description>Input range is 0-3 mA.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_MA</name>
|
|
<description>Input range is 0-2 mA.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_MA</name>
|
|
<description>Input range is 0-1 mA.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C0EN</name>
|
|
<description>Converter 0 Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable IVC channel 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable IVC channel 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C1EN</name>
|
|
<description>Converter 1 Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable IVC channel 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable IVC channel 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LOCK_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>LOCK_0</groupName>
|
|
<baseAddress>0x40049000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>KEY</name>
|
|
<description>Security Key</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Peripheral Lock Mask Key. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>PERIPHLOCK registers are locked and no valid values have been written to KEY.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERMEDIATE</name>
|
|
<description>PERIPHLOCK registers are locked and the first valid value (0xA5) has been written to KEY.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>PERIPHLOCK registers are unlocked. Any subsequent writes to KEY will lock the interface.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERIPHLOCK0</name>
|
|
<description>Peripheral Lock Control 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USARTL</name>
|
|
<description>USART/UART Module Lock Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the USART0, USART1, UART0, and UART1 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the USART0, USART1, UART0, and UART1 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIL</name>
|
|
<description>SPI Module Lock Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the SPI0, SPI1, and SPI2 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the SPI0, SPI1, and SPI2 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2CL</name>
|
|
<description>I2C Module Lock Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the I2C0 and I2C1 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the I2C0 and I2C1 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCAL</name>
|
|
<description>PCA Module Lock Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the EPCA0, PCA0, and PCA1 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the EPCA0, PCA0, and PCA1 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMERL</name>
|
|
<description>Timer Module Lock Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the TIMER0 and TIMER1 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the TIMER0 and TIMER1 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBL</name>
|
|
<description>USB Module Lock Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the USB0 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the USB0 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SARADCL</name>
|
|
<description>SARADC Module Lock Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the SARADC0 and SARADC1 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the SARADC0 and SARADC1 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSGL</name>
|
|
<description>SSG Module Lock Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the SSG0 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the SSG0 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPL</name>
|
|
<description>Comparator Module Lock Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the Comparator 0 and Comparator 1 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the Comparator 0 and Comparator 1 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSL</name>
|
|
<description>Capacitive Sensing Module Lock Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the Capacitive Sensing (CAPSENSE0) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the Capacitive Sensing (CAPSENSE0) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMIFL</name>
|
|
<description>EMIF Module Lock Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the External Memory Interface (EMIF0) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the External Memory Interface (EMIF0) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AESL</name>
|
|
<description>AES Module Lock Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the AES0 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the AES0 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRCL</name>
|
|
<description>CRC Module Lock Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the CRC0 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the CRC0 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCL</name>
|
|
<description>RTC Module Lock Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the RTC0 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the RTC0 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKRSTL</name>
|
|
<description>Clock Control and Reset Sources Lock Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the Clock Control (CLKCTRL) and Reset Sources (RSTSRC) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the Clock Control (CLKCTRL) and Reset Sources (RSTSRC) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VMONL</name>
|
|
<description>Voltage Supply Monitor Module Lock Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the Voltage Supply Monitor (VMON0) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the Voltage Supply Monitor (VMON0) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDACL</name>
|
|
<description>IDAC Module Lock Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the IDAC0 and IDAC1 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the IDAC0 and IDAC1 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMACTRLL</name>
|
|
<description>DMA Controller Module Lock Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the DMA Controller (DMACTRL0) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the DMA Controller (DMACTRL0) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAXBARL</name>
|
|
<description>DMA Crossbar Module Lock Enable. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the DMA Crossbar (DMAXBAR0) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the DMA Crossbar (DMAXBAR0) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPTL</name>
|
|
<description>Low Power Timer Module Lock Enable. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the Low Power Timer (LPTIMER0) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the Low Power Timer (LPTIMER0) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREFL</name>
|
|
<description>Voltage Reference Module Lock Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the Voltage Reference (VREF0) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the Voltage Reference (VREF0) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2SL</name>
|
|
<description>I2S Module Lock Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the I2S0 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the I2S0 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLL</name>
|
|
<description>PLL Module Lock Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the PLL0 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the PLL0 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTOSCL</name>
|
|
<description>External Oscillator Module Lock Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the External Oscillator (EXTOSC0) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the External Oscillator (EXTOSC0) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREGL</name>
|
|
<description>Voltage Regulator Module Lock Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the Voltage Regulator (VREG0) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the Voltage Regulator (VREG0) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPOSCL</name>
|
|
<description>Low Power Oscillator Lock Enable. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the Low Power Oscillator (LPOSC0) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the Low Power Oscillator (LPOSC0) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EVREGL</name>
|
|
<description>External Regulator Module Lock Enable. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the External Regulator (EXTVREG0) Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the External Regulator (EXTVREG0) Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IVCL</name>
|
|
<description>IVC Module Lock Enable. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the IVC0 Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the IVC0 Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERIPHLOCK1</name>
|
|
<description>Peripheral Lock Control 1</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMUL</name>
|
|
<description>PMU Module Lock Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Unlock the PMU Module registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Lock the PMU Module registers (bits can still be read).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPTIMER_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>LPTIMER_0</groupName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPTIMER0_IRQn</name>
|
|
<value>50</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Count Mode. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FREE</name>
|
|
<description>The timer is free running mode on the RTCn module clock (RTCnOSC or LFOSCn).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>The timer is incremented on the rising edges of the selected external trigger (LPTnTx).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>The timer is incremented on the falling edges of the selected external trigger (LPTnTx).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANY_EDGE</name>
|
|
<description>The timer is incremented on both edges of the selected external trigger (LPTnTx).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTSEL</name>
|
|
<description>External Trigger Source Select. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPTNT0</name>
|
|
<description>Select external trigger LPTnT0 (PB3.2).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT1</name>
|
|
<description>Select external trigger LPTnT1 (PB3.8).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT2</name>
|
|
<description>Select external trigger LPTnT2 (PB3.9).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT3</name>
|
|
<description>Select external trigger LPTnT3 (Comparator 0 Output).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT4</name>
|
|
<description>Select external trigger LPTnT4 (RESERVED).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT5</name>
|
|
<description>Select external trigger LPTnT5 (RESERVED).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT6</name>
|
|
<description>Select external trigger LPTnT6 (RESERVED).</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT7</name>
|
|
<description>Select external trigger LPTnT7 (RESERVED).</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT8</name>
|
|
<description>Select external trigger LPTnT8 (RESERVED).</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT9</name>
|
|
<description>Select external trigger LPTnT9 (RESERVED).</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT10</name>
|
|
<description>Select external trigger LPTnT10 (RESERVED).</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT11</name>
|
|
<description>Select external trigger LPTnT11 (RESERVED).</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT12</name>
|
|
<description>Select external trigger LPTnT12 (RESERVED).</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT13</name>
|
|
<description>Select external trigger LPTnT13 (RESERVED).</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT14</name>
|
|
<description>Select external trigger LPTnT14 (RESERVED).</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTNT15</name>
|
|
<description>Select external trigger LPTnT15 (RESERVED).</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRSET</name>
|
|
<description>Timer Set. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Writing a 1 to TMRSET initiates a copy of the value from the DATA register into the internal timer register. This field is automatically cleared by hardware when the copy is complete and does not need to be cleared by software.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRCAP</name>
|
|
<description>Timer Capture. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Writing a 1 to TMRCAP initiates a read of internal timer register into the DATA register. This field is automatically cleared by hardware when the operation completes and does not need to be cleared by software.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPSET</name>
|
|
<description>Timer Comparator Set. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Writing a 1 to CMPSET initiates a copy of the value in DATA into the internal timer comparator register. This field is automatically cleared by hardware when the copy is complete and does not need to be cleared by software.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPCAP</name>
|
|
<description>Timer Comparator Capture. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Writing a 1 to CMPCAP initiates a read of the internal comparator register into the DATA register. This field is automatically cleared by hardware when the operation completes and does not need to be cleared by software.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVFIEN</name>
|
|
<description>Timer Overflow Interrupt Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the timer overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the timer overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPIEN</name>
|
|
<description>Timer Compare Event Interrupt Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the timer compare event interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the timer compare event interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVFTMD</name>
|
|
<description>Timer Overflow Toggle Mode. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Timer overflows do not toggle the Low Power Timer output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Timer overflows toggle the Low Power Timer output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPTMD</name>
|
|
<description>Timer Compare Event Toggle Mode . </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Timer compare events do not toggle the Low Power Timer output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Timer compare events toggle the Low Power Timer output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPRSTEN</name>
|
|
<description>Timer Compare Event Reset Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Timer compare events do not reset the timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Timer compare events reset the timer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>Low Power Timer Debug Mode. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The Low Power Timer module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the Low Power Timer module to halt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Timer Run Control and Compare Threshold Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the timer and disable the compare threshold.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start the timer running and enable the compare threshold.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Timer and Comparator Data</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Timer and Comparator Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVFI</name>
|
|
<description>Timer Overflow Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A timer overflow has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A timer overflow occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPI</name>
|
|
<description>Timer Compare Event Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A timer compare event has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A timer compare event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PLL_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Oscillators</groupName>
|
|
<baseAddress>0x4003b000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PLL_IRQn</name>
|
|
<value>51</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>DIVIDER</name>
|
|
<description>Reference Divider Setting</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M</name>
|
|
<description>M Divider Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>N</name>
|
|
<description>N Divider Value. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000800</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LLMTF</name>
|
|
<description>CAL Saturation (Low) Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>DCO period is not saturated low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>DCO period is saturated low.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HLMTF</name>
|
|
<description>CAL Saturation (High) Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>DCO period is not saturated high.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>DCO period is saturated high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LCKI</name>
|
|
<description>Phase-Lock and Frequency-Lock Locked Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>DCO is disabled or not locked.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>DCO is enabled and locked.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LMTIEN</name>
|
|
<description>Limit Interrupt Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Saturation (high and low) interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Saturation (high and low) interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LCKIEN</name>
|
|
<description>Locked Interrupt Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The PLL locking does not cause an interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An interrupt is generated if LCKI matches the state selected by LCKPOL.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LCKPOL</name>
|
|
<description>Lock Interrupt Polarity. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_LOW</name>
|
|
<description>The lock state PLL interrupt will occur when LCKI is 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_HIGH</name>
|
|
<description>The lock state PLL interrupt will occur when LCKI is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Reference Clock Selection Control. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC0OSC</name>
|
|
<description>PLL reference clock (FREF) is the RTC0 oscillator (RTC0OSC).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPOSC0DIV</name>
|
|
<description>PLL reference clock (FREF) is the divided Low Power Oscillator (LPOSC0).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTOSC0</name>
|
|
<description>PLL reference clock (FREF) is the external oscillator output (EXTOSC0).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USBOSC0</name>
|
|
<description>PLL reference clock (FREF) is the USB0 oscillator (USB0OSC).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCKTH</name>
|
|
<description>Lock Threshold Control. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>DCO Output Updates Stall. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>In phase-lock and frequency-lock modes, spectrum spreading, and dithering operate normally, if enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>In phase-lock and frequency-lock modes, spectrum spreading, and dithering are prevented from updating the output of the DCO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DITHEN</name>
|
|
<description>Dithering Enable. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Automatic DCO output dithering disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Automatic DCO output dithering enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGSEL</name>
|
|
<description>Edge Lock Select. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Lock DCO output frequency to the falling edge of the reference frequency.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Lock DCO output frequency to the rising edge of the reference frequency.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTMD</name>
|
|
<description>PLL Output Mode. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>DCO output is off.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCO</name>
|
|
<description>DCO output is in Free-Running DCO mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLL</name>
|
|
<description>DCO output is in frequency-lock mode (reference source required).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL</name>
|
|
<description>DCO output is in phase-lock mode (reference source required).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSPR</name>
|
|
<description>Spectrum Spreading Control</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSAMP</name>
|
|
<description>Spectrum Spreading Amplitude. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Spectrum Spreading.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETTING1</name>
|
|
<description>Spectrum Spreading set to approximately +/- 0.1% of TDCO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETTING2</name>
|
|
<description>Spectrum Spreading set to approximately +/- 0.2% of TDCO.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETTING3</name>
|
|
<description>Spectrum Spreading set to approximately +/- 0.4% of TDCO.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETTING4</name>
|
|
<description>Spectrum Spreading set to approximately +/- 0.8% of TDCO.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETTING5</name>
|
|
<description>Spectrum Spreading set to approximately +/- 1.6% of TDCO.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSUINV</name>
|
|
<description>Spectrum Spreading Update Interval. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALCONFIG</name>
|
|
<description>Calibration Configuration</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DITHER</name>
|
|
<description>DCO Dither Setting. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>DCO Calibration Value. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RANGE</name>
|
|
<description>DCO Range. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RANGE0</name>
|
|
<description>DCO operates from 23 to 37 MHz.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE1</name>
|
|
<description>DCO operates from 33 to 54 MHz.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE2</name>
|
|
<description>DCO operates from 45 to 71 MHz.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE3</name>
|
|
<description>DCO operates from 53 to 80 MHz.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE4</name>
|
|
<description>DCO operates from 73 to 80 MHz.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EXTOSC_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Oscillators</groupName>
|
|
<baseAddress>0x4003c000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Oscillator Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FREQCN</name>
|
|
<description>Frequency Control. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RANGE0</name>
|
|
<description>Set the external oscillator to range 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE1</name>
|
|
<description>Set the external oscillator to range 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE2</name>
|
|
<description>Set the external oscillator to range 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE3</name>
|
|
<description>Set the external oscillator to range 3.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE4</name>
|
|
<description>Set the external oscillator to range 4.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE5</name>
|
|
<description>Set the external oscillator to range 5.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE6</name>
|
|
<description>Set the external oscillator to range 6.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RANGE7</name>
|
|
<description>Set the external oscillator to range 7.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCVLDF</name>
|
|
<description>Oscillator Valid Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The external oscillator is unused or not yet stable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The external oscillator is running and stable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCMD</name>
|
|
<description>Oscillator Mode. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>External oscillator off.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMOS</name>
|
|
<description>External CMOS clock mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMOSDIV2</name>
|
|
<description>External CMOS with divide by 2 stage.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RC</name>
|
|
<description>RC oscillator mode with divide by 2 stage.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>C</name>
|
|
<description>C oscillator mode with divide by 2 stage.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTAL</name>
|
|
<description>Crystal oscillator mode.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALDIV2</name>
|
|
<description>Crystal oscillator mode with divide by 2 stage.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPOSC_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Oscillators</groupName>
|
|
<baseAddress>0x40041000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>OSCVAL</name>
|
|
<description>Low Power Oscillator Output Value</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OSCVAL</name>
|
|
<description>Low Power Oscillator Output Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PCA_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>PCA</groupName>
|
|
<baseAddress>0x4000f000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PCA0_IRQn</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Module Operating Mode</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Input Clock Divisor. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Input Clock (F<subscript>CLKIN</subscript>) Select. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>APB</name>
|
|
<description>Set the APB as the input clock (FCLKIN).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HL_ECI</name>
|
|
<description>Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTOSCN</name>
|
|
<description>Set the external oscillator module output (EXTOSCn) divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECI</name>
|
|
<description>Set ECI transitions divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVFIEN</name>
|
|
<description>PCA Counter Overflow/Limit Interrupt Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the PCA counter overflow/limit event interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the PCA counter overflow/limit event interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>PCA Debug Mode. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the PCA to halt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The PCA will continue to operate while the core is halted in debug mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVST</name>
|
|
<description>Clock Divider Output State. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_HIGH</name>
|
|
<description>The clock divider is currently in the first half-cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_LOW</name>
|
|
<description>The clock divider is currently in the second half-cycle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Current Clock Divider Count. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0x1a0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>C0CCI</name>
|
|
<description>Channel 0 Capture/Compare Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Channel 0 match or capture event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Channel 0 match or capture event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C1CCI</name>
|
|
<description>Channel 1 Capture/Compare Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Channel 1 match or capture event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Channel 1 match or capture event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Counter/Timer Run. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the PCA Counter/Timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start the PCA Counter/Timer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVFI</name>
|
|
<description>Counter/Timer Overflow/Limit Interrupt Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A PCA Counter/Timer overflow/limit event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A PCA Counter/Timer overflow/limit event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C0IOVFI</name>
|
|
<description>Channel 0 Intermediate Overflow Interrupt Flag. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Channel 0 did not count past the channel n-bit mode limit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Channel 0 counted past the channel n-bit mode limit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C1IOVFI</name>
|
|
<description>Channel 1 Intermediate Overflow Interrupt Flag. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Channel 1 did not count past the channel n-bit mode limit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Channel 1 counted past the channel n-bit mode limit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNTER</name>
|
|
<description>Module Counter/Timer</description>
|
|
<addressOffset>0x1b0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNTER</name>
|
|
<description>Counter/Timer. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LIMIT</name>
|
|
<description>Module Counter/Timer Upper Limit</description>
|
|
<addressOffset>0x1c0</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LIMIT</name>
|
|
<description>Upper Limit. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_2-->
|
|
<register>
|
|
<name>MODE_0</name>
|
|
<description>Channel Capture/Compare Mode</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COSEL</name>
|
|
<description>Channel Output Function Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT</name>
|
|
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT</name>
|
|
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMD</name>
|
|
<description>PWM N-Bit Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Channel Operating Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE_PWM</name>
|
|
<description>Configure the channel for edge-aligned PWM mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_PWM</name>
|
|
<description>Configure the channel for center-aligned PWM mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HF_SQUARE_WAVE</name>
|
|
<description>Configure the channel for high-frequency/square-wave mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CAPTURE</name>
|
|
<description>Configure the channel for timer/capture mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>N_BIT_PWM</name>
|
|
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL_0</name>
|
|
<description>Channel Capture/Compare Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUTST</name>
|
|
<description>Channel Output State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The channel output state is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The channel output state is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCAPEN</name>
|
|
<description>Positive Edge Input Capture Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable positive-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNCAPEN</name>
|
|
<description>Negative Edge Input Capture Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable negative-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUPDCF</name>
|
|
<description>Channel Register Update Complete Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A PCA channel register update completed or is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A PCA channel register update has not completed and is still pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIEN</name>
|
|
<description>Capture/Compare Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel capture/compare interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel capture/compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFIEN</name>
|
|
<description>Intermediate Overflow Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel intermediate overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel intermediate overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPV_0</name>
|
|
<description>Channel Compare Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPV</name>
|
|
<description>Channel Compare Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPVUPD_0</name>
|
|
<description>Channel Compare Update Value</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPVUPD</name>
|
|
<description>Channel Compare Update Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_3-->
|
|
<register>
|
|
<name>MODE_1</name>
|
|
<description>Channel Capture/Compare Mode</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COSEL</name>
|
|
<description>Channel Output Function Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT</name>
|
|
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT</name>
|
|
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMD</name>
|
|
<description>PWM N-Bit Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Channel Operating Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE_PWM</name>
|
|
<description>Configure the channel for edge-aligned PWM mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_PWM</name>
|
|
<description>Configure the channel for center-aligned PWM mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HF_SQUARE_WAVE</name>
|
|
<description>Configure the channel for high-frequency/square-wave mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CAPTURE</name>
|
|
<description>Configure the channel for timer/capture mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>N_BIT_PWM</name>
|
|
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL_1</name>
|
|
<description>Channel Capture/Compare Control</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUTST</name>
|
|
<description>Channel Output State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The channel output state is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The channel output state is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCAPEN</name>
|
|
<description>Positive Edge Input Capture Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable positive-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNCAPEN</name>
|
|
<description>Negative Edge Input Capture Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable negative-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUPDCF</name>
|
|
<description>Channel Register Update Complete Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A PCA channel register update completed or is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A PCA channel register update has not completed and is still pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIEN</name>
|
|
<description>Capture/Compare Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel capture/compare interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel capture/compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFIEN</name>
|
|
<description>Intermediate Overflow Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel intermediate overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel intermediate overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPV_1</name>
|
|
<description>Channel Compare Value</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPV</name>
|
|
<description>Channel Compare Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPVUPD_1</name>
|
|
<description>Channel Compare Update Value</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPVUPD</name>
|
|
<description>Channel Compare Update Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PCA_1</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>PCA</groupName>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PCA1_IRQn</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Module Operating Mode</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Input Clock Divisor. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Input Clock (F<subscript>CLKIN</subscript>) Select. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>APB</name>
|
|
<description>Set the APB as the input clock (FCLKIN).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HL_ECI</name>
|
|
<description>Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTOSCN</name>
|
|
<description>Set the external oscillator module output (EXTOSCn) divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECI</name>
|
|
<description>Set ECI transitions divided by 2 as the input clock (FCLKIN).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVFIEN</name>
|
|
<description>PCA Counter Overflow/Limit Interrupt Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the PCA counter overflow/limit event interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the PCA counter overflow/limit event interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>PCA Debug Mode. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the PCA to halt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The PCA will continue to operate while the core is halted in debug mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVST</name>
|
|
<description>Clock Divider Output State. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_HIGH</name>
|
|
<description>The clock divider is currently in the first half-cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_LOW</name>
|
|
<description>The clock divider is currently in the second half-cycle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Current Clock Divider Count. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0x1a0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>C0CCI</name>
|
|
<description>Channel 0 Capture/Compare Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Channel 0 match or capture event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Channel 0 match or capture event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C1CCI</name>
|
|
<description>Channel 1 Capture/Compare Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Channel 1 match or capture event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Channel 1 match or capture event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Counter/Timer Run. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the PCA Counter/Timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start the PCA Counter/Timer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVFI</name>
|
|
<description>Counter/Timer Overflow/Limit Interrupt Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A PCA Counter/Timer overflow/limit event did not occur.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A PCA Counter/Timer overflow/limit event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C0IOVFI</name>
|
|
<description>Channel 0 Intermediate Overflow Interrupt Flag. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Channel 0 did not count past the channel n-bit mode limit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Channel 0 counted past the channel n-bit mode limit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>C1IOVFI</name>
|
|
<description>Channel 1 Intermediate Overflow Interrupt Flag. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Channel 1 did not count past the channel n-bit mode limit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Channel 1 counted past the channel n-bit mode limit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNTER</name>
|
|
<description>Module Counter/Timer</description>
|
|
<addressOffset>0x1b0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNTER</name>
|
|
<description>Counter/Timer. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LIMIT</name>
|
|
<description>Module Counter/Timer Upper Limit</description>
|
|
<addressOffset>0x1c0</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LIMIT</name>
|
|
<description>Upper Limit. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_2-->
|
|
<register>
|
|
<name>MODE_0</name>
|
|
<description>Channel Capture/Compare Mode</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COSEL</name>
|
|
<description>Channel Output Function Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT</name>
|
|
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT</name>
|
|
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMD</name>
|
|
<description>PWM N-Bit Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Channel Operating Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE_PWM</name>
|
|
<description>Configure the channel for edge-aligned PWM mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_PWM</name>
|
|
<description>Configure the channel for center-aligned PWM mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HF_SQUARE_WAVE</name>
|
|
<description>Configure the channel for high-frequency/square-wave mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CAPTURE</name>
|
|
<description>Configure the channel for timer/capture mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>N_BIT_PWM</name>
|
|
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL_0</name>
|
|
<description>Channel Capture/Compare Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUTST</name>
|
|
<description>Channel Output State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The channel output state is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The channel output state is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCAPEN</name>
|
|
<description>Positive Edge Input Capture Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable positive-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNCAPEN</name>
|
|
<description>Negative Edge Input Capture Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable negative-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUPDCF</name>
|
|
<description>Channel Register Update Complete Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A PCA channel register update completed or is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A PCA channel register update has not completed and is still pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIEN</name>
|
|
<description>Capture/Compare Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel capture/compare interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel capture/compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFIEN</name>
|
|
<description>Intermediate Overflow Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel intermediate overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel intermediate overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPV_0</name>
|
|
<description>Channel Compare Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPV</name>
|
|
<description>Channel Compare Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPVUPD_0</name>
|
|
<description>Channel Compare Update Value</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPVUPD</name>
|
|
<description>Channel Compare Update Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_3-->
|
|
<register>
|
|
<name>MODE_1</name>
|
|
<description>Channel Capture/Compare Mode</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COSEL</name>
|
|
<description>Channel Output Function Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT</name>
|
|
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT</name>
|
|
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMMD</name>
|
|
<description>PWM N-Bit Mode. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Channel Operating Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE_PWM</name>
|
|
<description>Configure the channel for edge-aligned PWM mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_PWM</name>
|
|
<description>Configure the channel for center-aligned PWM mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HF_SQUARE_WAVE</name>
|
|
<description>Configure the channel for high-frequency/square-wave mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CAPTURE</name>
|
|
<description>Configure the channel for timer/capture mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>N_BIT_PWM</name>
|
|
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL_1</name>
|
|
<description>Channel Capture/Compare Control</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUTST</name>
|
|
<description>Channel Output State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The channel output state is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The channel output state is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPCAPEN</name>
|
|
<description>Positive Edge Input Capture Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable positive-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable positive-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNCAPEN</name>
|
|
<description>Negative Edge Input Capture Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable negative-edge input capture.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable negative-edge input capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUPDCF</name>
|
|
<description>Channel Register Update Complete Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A PCA channel register update completed or is not pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A PCA channel register update has not completed and is still pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIEN</name>
|
|
<description>Capture/Compare Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel capture/compare interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel capture/compare interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIOVFIEN</name>
|
|
<description>Intermediate Overflow Interrupt Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the channel intermediate overflow interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the channel intermediate overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPV_1</name>
|
|
<description>Channel Compare Value</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPV</name>
|
|
<description>Channel Compare Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCAPVUPD_1</name>
|
|
<description>Channel Compare Update Value</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCAPVUPD</name>
|
|
<description>Channel Compare Update Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMU_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>PMU_0</groupName>
|
|
<baseAddress>0x40048000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKECLR</name>
|
|
<description>Wakeup Source Clear. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear all wakeup sources.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PERILPEN</name>
|
|
<description>Peripheral Low Power Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the peripheral low power state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the peripheral low power state. The peripherals will not be accessible in this state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINLPEN</name>
|
|
<description>Pin Low Power Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the pin low power state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the pin low power state. The pins will not be accessible in this state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWAKEEN</name>
|
|
<description>Pin Wake Match Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Pin Wake.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Pin Wake.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMUASLPEN</name>
|
|
<description>PMU Asleep Pin Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the PMU Asleep pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the PMU Asleep pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTC0FREN</name>
|
|
<description>RTC0 Fail RTC0/LPTIMER0 Reset Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>An RTC0 fail event does not cause the RTC0 and LPTIMER0 modules to reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An RTC0 fail event causes the RTC0 and LPTIMER0 modules to reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC0AREN</name>
|
|
<description>RTC0 Alarm RTC0/LPTIMER0 Reset Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>An RTC0 alarm event does not cause the RTC0 and LPTIMER0 modules to reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An RTC0 alarm event causes the RTC0 and LPTIMER0 modules to reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0REN</name>
|
|
<description>Comparator 0 RTC0/LPTIMER0 Reset Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>A Comparator 0 event does not cause the RTC0 and LPTIMER0 modules to reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A Comparator 0 event causes the RTC0 and LPTIMER0 modules to reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWAKEREN</name>
|
|
<description>Pin Wake RTC0/LPTIMER0 Reset Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>A Pin Wake event does not cause the RTC0 and LPTIMER0 modules to reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A Pin Wake event causes the RTC0 and LPTIMER0 modules to reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPT0REN</name>
|
|
<description>Low Power Timer RTC0/LPTIMER0 Reset Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>An LPTIMER0 event does not cause the RTC0 and LPTIMER0 modules to reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An LPTIMER0 event causes the RTC0 and LPTIMER0 modules to reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000006</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM9EF</name>
|
|
<description>Power Mode 9 Exited Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The device has not exited Power Mode 9.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The device has exited Power Mode 9. This bit must be cleared by firmware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWAKEF</name>
|
|
<description>Pin Wake Status Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Pin Wake event has occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Pin Wake event has not occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORF</name>
|
|
<description>Power-On Reset Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A power-on reset did not occur since the last time PORF was cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A power-on reset occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAKEEN</name>
|
|
<description>Wake Source Enable</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTC0FWEN</name>
|
|
<description>RTC0 Fail Wake Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>An RTC0 fail event does not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An RTC0 fail event awakens the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC0AWEN</name>
|
|
<description>RTC0 Alarm Wake Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>An RTC0 alarm event does not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An RTC0 alarm event awakens the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0WEN</name>
|
|
<description>Comparator 0 Wake Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>A Comparator 0 event does not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A Comparator 0 event awakens the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWAKEWEN</name>
|
|
<description>Pin Wake Wake Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>A Pin Wake event does not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A Pin Wake event awakens the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPT0WEN</name>
|
|
<description>Low Power Timer Wake Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>An LPTIMER0 event does not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An LPTIMER0 event awakens the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTWEN</name>
|
|
<description>Reset Pin Wake Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>A /RESET Pin event does not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A /RESET Pin event awakens the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAKESTATUS</name>
|
|
<description>Wake Source Status</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTC0FWF</name>
|
|
<description>RTC0 Fail Wake Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>An RTC0 fail event did not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>An RTC0 fail event woke the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC0AWF</name>
|
|
<description>RTC0 Alarm Wake Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>An RTC0 alarm event did not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>An RTC0 alarm event woke the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0WF</name>
|
|
<description>Comparator 0 Wake Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Comparator 0 event did not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Comparator 0 event woke the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWAKEWF</name>
|
|
<description>Pin Wake Wake Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Pin Wake event did not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Pin Wake event woke the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPT0WF</name>
|
|
<description>Low Power Timer Wake Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>An LPTIMER0 event did not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>An LPTIMER0 event woke the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTWF</name>
|
|
<description>Reset Pin Wake Flag. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A /RESET Pin event did not wake the device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A /RESET Pin event woke the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWEN</name>
|
|
<description>Pin Wake Pin Enable</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PW0EN</name>
|
|
<description>WAKE.0 Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.0 (PB1.6) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.0 (PB1.6) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW1EN</name>
|
|
<description>WAKE.1 Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.1 (PB1.7) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.1 (PB1.7) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW2EN</name>
|
|
<description>WAKE.2 Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.2 (PB1.8) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.2 (PB1.8) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW3EN</name>
|
|
<description>WAKE.3 Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.3 (PB1.9) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.3 (PB1.9) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW4EN</name>
|
|
<description>WAKE.4 Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.4 (PB1.10) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.4 (PB1.10) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW5EN</name>
|
|
<description>WAKE.5 Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.5 (PB1.11) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.5 (PB1.11) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW6EN</name>
|
|
<description>WAKE.6 Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.6 (PB1.12) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.6 (PB1.12) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW7EN</name>
|
|
<description>WAKE.7 Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.7 (RESERVED) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.7 (RESERVED) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW8EN</name>
|
|
<description>WAKE.8 Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.8 (PB3.2) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.8 (PB3.2) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW9EN</name>
|
|
<description>WAKE.9 Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.9 (PB3.3) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.9 (PB3.3) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW10EN</name>
|
|
<description>WAKE.10 Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.10 (PB3.4) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.10 (PB3.4) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW11EN</name>
|
|
<description>WAKE.11 Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.11 (PB3.5) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.11 (PB3.5) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW12EN</name>
|
|
<description>WAKE.12 Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.12 (PB3.6) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.12 (PB3.6) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW13EN</name>
|
|
<description>WAKE.13 Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.13 (PB3.7) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.13 (PB3.7) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW14EN</name>
|
|
<description>WAKE.14 Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.14 (PB3.8) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.14 (PB3.8) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW15EN</name>
|
|
<description>WAKE.15 Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>WAKE.15 (PB3.9) is not used in the Pin Wake comparison.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>WAKE.15 (PB3.9) is used in the Pin Wake comparison.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWPOL</name>
|
|
<description>Pin Wake Pin Polarity Select</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PW0POL</name>
|
|
<description>WAKE.0 Polarity Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.0 (PB1.6) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.0 (PB1.6) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW1POL</name>
|
|
<description>WAKE.1 Polarity Select. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.1 (PB1.7) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.1 (PB1.7) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW2POL</name>
|
|
<description>WAKE.2 Polarity Select. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.2 (PB1.8) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.2 (PB1.8) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW3POL</name>
|
|
<description>WAKE.3 Polarity Select. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.3 (PB1.9) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.3 (PB1.9) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW4POL</name>
|
|
<description>WAKE.4 Polarity Select. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.4 (PB1.10) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.4 (PB1.10) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW5POL</name>
|
|
<description>WAKE.5 Polarity Select. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.5 (PB1.11) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.5 (PB1.11) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW6POL</name>
|
|
<description>WAKE.6 Polarity Select. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.6 (PB1.12) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.6 (PB1.12) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW7POL</name>
|
|
<description>WAKE.7 Polarity Select. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.7 (RESERVED) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.7 (RESERVED) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW8POL</name>
|
|
<description>WAKE.8 Polarity Select. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.8 (PB3.2) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.8 (PB3.2) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW9POL</name>
|
|
<description>WAKE.9 Polarity Select. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.9 (PB3.3) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.9 (PB3.3) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW10POL</name>
|
|
<description>WAKE.10 Polarity Select. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.10 (PB3.4) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.10 (PB3.4) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW11POL</name>
|
|
<description>WAKE.11 Polarity Select. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.11 (PB3.5) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.11 (PB3.5) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW12POL</name>
|
|
<description>WAKE.12 Polarity Select. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.12 (PB3.6) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.12 (PB3.6) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW13POL</name>
|
|
<description>WAKE.13 Polarity Select. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.13 (PB3.7) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.13 (PB3.7) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW14POL</name>
|
|
<description>WAKE.14 Polarity Select. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.14 (PB3.8) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.14 (PB3.8) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PW15POL</name>
|
|
<description>WAKE.15 Polarity Select. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The WAKE.15 (PB3.9) comparison value is logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The WAKE.15 (PB3.9) comparison value is logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PBCFG_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>PBCFG_0</groupName>
|
|
<baseAddress>0x4002a000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PBEXT0_IRQn</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PBEXT1_IRQn</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PMATCH_IRQn</name>
|
|
<value>45</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL0</name>
|
|
<description>Global Port Control 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT0SEL</name>
|
|
<description>External Interrupt 0 Pin Selection. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT0_0</name>
|
|
<description>Select INT0.0 (PB2.0)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_1</name>
|
|
<description>Select INT0.1 (PB2.1)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_2</name>
|
|
<description>Select INT0.2 (PB2.2)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_3</name>
|
|
<description>Select INT0.3 (PB2.3)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_4</name>
|
|
<description>Select INT0.4 (PB3.3)</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_5</name>
|
|
<description>Select INT0.5 (PB3.4)</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_6</name>
|
|
<description>Select INT0.6 (PB3.5)</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_7</name>
|
|
<description>Select INT0.7 (PB3.6)</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_8</name>
|
|
<description>Select INT0.8 (PB3.7)</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_9</name>
|
|
<description>Select INT0.9 (PB3.8)</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_10</name>
|
|
<description>Select INT0.10 (PB3.9)</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_11</name>
|
|
<description>Select INT0.11 (RESERVED)</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_12</name>
|
|
<description>Select INT0.12 (RESERVED)</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_13</name>
|
|
<description>Select INT0.13 (RESERVED)</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_14</name>
|
|
<description>Select INT0.14 (RESERVED)</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_15</name>
|
|
<description>Select INT0.15 (RESERVED)</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT0POL</name>
|
|
<description>External Interrupt 0 Polarity. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A low value or falling edge on the selected pin will cause interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A high value or rising edge on the selected pin will cause interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT0MD</name>
|
|
<description>External Interrupt 0 Mode. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Interrupt based on level sensitivity.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Interrupt based on edge sensitivity.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT0EN</name>
|
|
<description>External Interrupt 0 Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable external interrupt 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable external interrupt 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT1SEL</name>
|
|
<description>External Interrupt 1 Pin Selection. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT1_0</name>
|
|
<description>Select INT1.0 (PB2.0)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_1</name>
|
|
<description>Select INT1.1 (PB2.1)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_2</name>
|
|
<description>Select INT1.2 (PB2.2)</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_3</name>
|
|
<description>Select INT1.3 (PB2.3)</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_4</name>
|
|
<description>Select INT1.4 (PB3.3)</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_5</name>
|
|
<description>Select INT1.5 (PB3.4)</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_6</name>
|
|
<description>Select INT1.6 (PB3.5)</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_7</name>
|
|
<description>Select INT1.7 (PB3.6)</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_8</name>
|
|
<description>Select INT1.8 (PB3.7)</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_9</name>
|
|
<description>Select INT1.9 (PB3.8)</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_10</name>
|
|
<description>Select INT1.10 (PB3.9)</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_11</name>
|
|
<description>Select INT1.11 (RESERVED)</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_12</name>
|
|
<description>Select INT1.12 (RESERVED)</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_13</name>
|
|
<description>Select INT1.13 (RESERVED)</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_14</name>
|
|
<description>Select INT1.14 (RESERVED)</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_15</name>
|
|
<description>Select INT1.15 (RESERVED)</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT1POL</name>
|
|
<description>External Interrupt 1 Polarity. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>A low value or falling edge on the selected pin will cause interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>A high value or rising edge on the selected pin will cause interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT1MD</name>
|
|
<description>External Interrupt 1 Mode. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Interrupt based on level sensitivity.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>Interrupt based on edge sensitivity.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT1EN</name>
|
|
<description>External Interrupt 1 Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable external interrupt 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable external interrupt 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PGTIMER</name>
|
|
<description>Pulse Generator Timer. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGDONEF</name>
|
|
<description>Pulse Generator Timer Done Flag. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Firmware has written to the PBPGPHASE register, but the Pulse Generator timer has not expired.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The Pulse Generator cycle finished since the last time PBPGPHASE was written.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL1</name>
|
|
<description>Global Port Control 1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>JTAGEN</name>
|
|
<description>JTAG Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>JTAG functionality is not pinned out.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>JTAG functionality is pinned out.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ETMEN</name>
|
|
<description>ETM Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>ETM not pinned out.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>ETM is enabled and pinned out.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMIFBE0BEN</name>
|
|
<description>EMIF <overline>BE0</overline> Pin Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the EMIF /BE0 pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the /BE0 pin if EMIFEN is also set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMIFCS1EN</name>
|
|
<description>EMIF CS1 Pin Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the EMIF CS1 pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the CS1 pin if EMIFEN is also set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMIFEN</name>
|
|
<description>EMIF Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the EMIF pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>EMIF is enabled and pinned out.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMIFWIDTH</name>
|
|
<description>EMIF Width. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_8</name>
|
|
<description>EMIF Address[7:0]</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_9</name>
|
|
<description>EMIF Address[8:0], PB2.8 = A[8]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_10</name>
|
|
<description>EMIF Address[9:0], PB2.7 = A[9]</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_11</name>
|
|
<description>EMIF Address[10:0], PB2.6 = A[10]</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_12</name>
|
|
<description>EMIF Address[11:0], PB2.5 = A[11]</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_13</name>
|
|
<description>EMIF Address[12:0], PB2.4 = A[12]</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_14</name>
|
|
<description>EMIF Address[13:0], PB2.3 = A[13]</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_15</name>
|
|
<description>EMIF Address[14:0], PB2.2 = A[14]</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_16</name>
|
|
<description>EMIF Address[15:0], PB2.1 = A[15]</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_17</name>
|
|
<description>EMIF Address[16:0], PB2.0 = A[16]</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_18</name>
|
|
<description>EMIF Address[17:0], PB1.15 = A[17]</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_19</name>
|
|
<description>EMIF Address[18:0], PB1.14 = A[18]</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_20</name>
|
|
<description>EMIF Address[19:0], PB1.13 = A[19]</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_21</name>
|
|
<description>EMIF Address[20:0], PB1.12 = A[20]</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_22</name>
|
|
<description>EMIF Address[21:0], PB1.11 = A[21]</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_23</name>
|
|
<description>EMIF Address[22:0], PB1.10 = A[22]</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWIDTH_24</name>
|
|
<description>EMIF Address[23:0], PB1.10 = A[23]</description>
|
|
<value>16</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATMD</name>
|
|
<description>Match Mode. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PINMATCH</name>
|
|
<description>Port Match registers used to provide interrupt / wake sources.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPSENSE_TX</name>
|
|
<description>Port Match registers used to monitor output pin activity for Capacitive Sensing measurements.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPSENSE_RX</name>
|
|
<description>Port Match registers used to monitor input pin activity for Capacitive Sensing measurements.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EVREGRMD</name>
|
|
<description>External Regulator Reset Mode. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESET_ON_ANY</name>
|
|
<description>The pins used by the external regulator will default to digital inputs with weak pull-up enabled on any reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_ON_POR</name>
|
|
<description>The pins used by the external regulator will default to digital inputs with weak pull-up enabled only on Power-On Reset. Their configured mode will be preserved through all other resets.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Port Bank Configuration Lock. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Port Bank Configuration and Control registers are unlocked.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>The following registers are locked from write access: CONTROL1, XBAR0L, XBAR0H, XBAR1, and all PBSKIP registers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XBAR0L</name>
|
|
<description>Crossbar 0 Control (Low)</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USART0EN</name>
|
|
<description>USART0 Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable USART0 RX and TX on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable USART0 RX and TX on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART0FCEN</name>
|
|
<description>USART0 Flow Control Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable USART0 flow control on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable USART0 flow control on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART0CEN</name>
|
|
<description>USART0 Clock Signal Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable USART0 clock on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable USART0 clock on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI0EN</name>
|
|
<description>SPI0 Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable SPI0 SCK, MISO, and MOSI on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable SPI0 SCK, MISO, and MOSI on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI0NSSEN</name>
|
|
<description>SPI0 NSS Pin Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable SPI0 NSS on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable SPI0 NSS on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART1EN</name>
|
|
<description>USART1 Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable USART1 RX and TX on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable USART1 RX and TX on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART1FCEN</name>
|
|
<description>USART1 Flow Control Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable USART1 flow control on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable USART1 flow control on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART1CEN</name>
|
|
<description>USART1 Clock Signal Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable USART1 clock on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable USART1 clock on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPCA0EN</name>
|
|
<description>EPCA0 Channel Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Disable all EPCA0 channels on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STD_CEX0</name>
|
|
<description>Enable EPCA0 STD_CEX0 on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STD_CEX0_1</name>
|
|
<description>Enable EPCA0 STD_CEX0 and STD_CEX1 on Crossbar 0.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STD_CEX0_2</name>
|
|
<description>Enable EPCA0 STD_CEX0, STD_CEX1, and STD_CEX2 on Crossbar 0.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STD_CEX0_3</name>
|
|
<description>Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, and STD_CEX3 on Crossbar 0.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STD_CEX0_4</name>
|
|
<description>Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3, and STD_CEX4 on Crossbar 0.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STD_CEX0_5</name>
|
|
<description>Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3, STD_CEX4, and STD_CEX5 on Crossbar 0.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCA0EN</name>
|
|
<description>PCA0 Channel Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Disable all PCA0 channels on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEX0</name>
|
|
<description>Enable PCA0 CEX0 on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEX0_1</name>
|
|
<description>Enable PCA0 CEX0 and CEX1 on Crossbar 0.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCA1EN</name>
|
|
<description>PCA1 Channel Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Disable all PCA1 channels on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEX0</name>
|
|
<description>Enable PCA1 CEX0 on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CEX0_1</name>
|
|
<description>Enable PCA1 CEX0 and CEX1 on Crossbar 0.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EECI0EN</name>
|
|
<description>EPCA0 ECI Enable. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable EPCA0 ECI on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable EPCA0 ECI on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECI0EN</name>
|
|
<description>PCA0 ECI Enable. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable PCA0 ECI on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable PCA0 ECI on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECI1EN</name>
|
|
<description>PCA1 ECI Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable PCA1 ECI on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable PCA1 ECI on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2S0TXEN</name>
|
|
<description>I2S0 TX Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable I2S0 TX on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable I2S0 TX on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C0EN</name>
|
|
<description>I2C0 Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable I2C0 SDA and SCL on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable I2C0 SDA and SCL on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0SEN</name>
|
|
<description>Comparator 0 Synchronous Output (CMP0S) Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0AEN</name>
|
|
<description>Comparator 0 Asynchronous Output (CMP0A) Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1SEN</name>
|
|
<description>Comparator 1 Synchronous Output (CMP1S) Enable. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1AEN</name>
|
|
<description>Comparator 1 Asynchronous Output (CMP1A) Enable. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMR0CTEN</name>
|
|
<description>TIMER0 T0CT Enable. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable TIMER0 CT on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable TIMER0 CT on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMR0EXEN</name>
|
|
<description>TIMER0 T0EX Enable. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable TIMER0 EX on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable TIMER0 EX on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMR1CTEN</name>
|
|
<description>TIMER1 T1CT Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable TIMER1 CT on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable TIMER1 CT on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMR1EXEN</name>
|
|
<description>TIMER1 T1EX Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable TIMER1 EX on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable TIMER1 EX on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XBAR0H</name>
|
|
<description>Crossbar 0 Control (High)</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UART0EN</name>
|
|
<description>UART0 Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable UART0 RX and TX on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable UART0 RX and TX on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0FCEN</name>
|
|
<description>UART0 Flow Control Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable UART0 flow control on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable UART0 flow control on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART1EN</name>
|
|
<description>UART1 Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable UART1 RX and TX on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable UART1 RX and TX on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI1EN</name>
|
|
<description>SPI1 Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable SPI1 SCK, MISO, and MOSI on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable SPI1 SCK, MISO, and MOSI on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI1NSSEN</name>
|
|
<description>SPI1 NSS Pin Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable SPI1 NSS on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable SPI1 NSS on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI2EN</name>
|
|
<description>SPI2 Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable SPI2 SCK, MISO, and MOSI on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable SPI2 SCK, MISO, and MOSI on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI2NSSEN</name>
|
|
<description>SPI2 NSS Pin Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable SPI2 NSS on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable SPI2 NSS on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AHBEN</name>
|
|
<description>AHB Clock Output Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the AHB Clock / 16 output on Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the AHB Clock / 16 output on Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XBAR0EN</name>
|
|
<description>Crossbar 0 Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Crossbar 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Crossbar 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XBAR1</name>
|
|
<description>Crossbar 1 Control</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSG0EN</name>
|
|
<description>SSG0 Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Disable all SSG0 channels on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EX0</name>
|
|
<description>Enable SSG0 EX0 on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EX0_1</name>
|
|
<description>Enable SSG0 EX0 and EX1 on Crossbar 1.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EX0_3</name>
|
|
<description>Enable SSG0 EX0, EX1, EX2, and EX3 on Crossbar 1.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0SEN</name>
|
|
<description>Comparator 0 Synchronous Output (CMP0S) Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1SEN</name>
|
|
<description>Comparator 1 Synchronous Output (CMP1S) Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI1EN</name>
|
|
<description>SPI1 Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable SPI1 SCK, MISO, and MOSI on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable SPI1 SCK, MISO, and MOSI on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI1NSSEN</name>
|
|
<description>SPI1 NSS Pin Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable SPI1 NSS on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable SPI1 NSS on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC0EN</name>
|
|
<description>RTC0 Output Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable RTC0 Output on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable RTC0 Output on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI2EN</name>
|
|
<description>SPI2 Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable SPI2 SCK, MISO, and MOSI on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable SPI2 SCK, MISO, and MOSI on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPI2NSSEN</name>
|
|
<description>SPI2 NSS Pin Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable SPI2 NSS on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable SPI2 NSS on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART1EN</name>
|
|
<description>USART1 Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable USART1 RX and TX on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable USART1 RX and TX on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART1FCEN</name>
|
|
<description>USART1 Flow Control Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable USART1 flow control on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable USART1 flow control on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USART1CEN</name>
|
|
<description>USART1 Clock Signal Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable USART1 clock on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable USART1 clock on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0EN</name>
|
|
<description>UART0 Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable UART0 RX and TX on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable UART0 RX and TX on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART0FCEN</name>
|
|
<description>UART0 Flow Control Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable UART0 flow control on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable UART0 flow control on Crossbar1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2S0TXEN</name>
|
|
<description>I2S0 TX Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable I2S0 TX on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable I2S0 TX on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C0EN</name>
|
|
<description>I2C0 Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable I2C0 SDA and SCL on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable I2C0 SDA and SCL on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART1EN</name>
|
|
<description>UART1 Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable UART1 RX and TX on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable UART1 RX and TX on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2S0RXEN</name>
|
|
<description>I2S0 RX Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable I2S0 RX on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable I2S0 RX on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPT0OEN</name>
|
|
<description>LPTIMER0 Output Enable. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable LPTIMER0 Output on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable LPTIMER0 Output on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C1EN</name>
|
|
<description>I2C1 Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable I2C1 SDA and SCL on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable I2C1 SDA and SCL on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KILLHDEN</name>
|
|
<description>High Drive Kill Pin Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the PB High Drive Kill Pin on Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the PB High Drive Kill Pin on Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XBAR1EN</name>
|
|
<description>Crossbar 1 Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Crossbar 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Crossbar 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBKEY</name>
|
|
<description>Global Port Key</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Port Bank 2, 3, and 4 Key. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Port Bank 2, 3, and 4 registers are locked and no valid values have been written to PBKEY.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERMEDIATE</name>
|
|
<description>Port Bank 2, 3, and 4 registers are locked and the first valid value (0xA5) has been written to PBKEY.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Port Bank 2, 3, and 4 registers are unlocked. Any subsequent writes to the Port Bank 2, 3, or 4 registers or PBKEY will lock the interface.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PBHD_4</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>PBHD_4</groupName>
|
|
<baseAddress>0x4002a3c0</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>PB</name>
|
|
<description>Output Latch</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x0000003F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB</name>
|
|
<description>Output Latch. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBPIN</name>
|
|
<description>Pin Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBPIN</name>
|
|
<description>Pin Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBMDSEL</name>
|
|
<description>Mode Select</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x0000003F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBMDSEL</name>
|
|
<description>Mode Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBDEN</name>
|
|
<description>Driver Enable</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBNDEN</name>
|
|
<description>Port Bank N-Channel Driver Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBPDEN</name>
|
|
<description>Port Bank P-Channel Driver Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBDRV</name>
|
|
<description>Drive Strength</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBDRV</name>
|
|
<description>Drive Strength. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBPUEN</name>
|
|
<description>Port Bank Weak Pull-up Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable weak pull-ups for this port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable weak pull-ups for this port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBLVMD</name>
|
|
<description>Port Low Voltage Mode. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Port configured for normal mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Port configured for low power mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBSLEW</name>
|
|
<description>Port Slew Control. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FASTEST</name>
|
|
<description>Select the fastest transition speed for this port bank.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FASTER</name>
|
|
<description>Select the faster transition speed for this port bank.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLOWER</name>
|
|
<description>Select the slower transition speed for this port bank.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLOWEST</name>
|
|
<description>Select the slowest transition speed for this port bank.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBBIASEN</name>
|
|
<description>Port Bias Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the biasing to the port pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the biasing to the port pins.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBDRVEN</name>
|
|
<description>Port Drive Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the port drivers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the port drivers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBVTRKEN</name>
|
|
<description>Port Voltage Supply Tracking Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable VIOHD tracking.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable VIOHD tracking.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBILIMIT</name>
|
|
<description>Current Limit</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBILEN</name>
|
|
<description>Current Limit Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NILIMIT</name>
|
|
<description>N-Channel Current Limit. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>Set sink limit to mode 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>Set sink limit to mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>Set sink limit to mode 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>Set sink limit to mode 3.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE4</name>
|
|
<description>Set sink limit to mode 4.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE5</name>
|
|
<description>Set sink limit to mode 5.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE6</name>
|
|
<description>Set sink limit to mode 6.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE7</name>
|
|
<description>Set sink limit to mode 7.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE8</name>
|
|
<description>Set sink limit to mode 8.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE9</name>
|
|
<description>Set sink limit to mode 9.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE10</name>
|
|
<description>Set sink limit to mode 10.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE11</name>
|
|
<description>Set sink limit to mode 11.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE12</name>
|
|
<description>Set sink limit to mode 12.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE13</name>
|
|
<description>Set sink limit to mode 13.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE14</name>
|
|
<description>Set sink limit to mode 14.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE15</name>
|
|
<description>Set sink limit to mode 15.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PILIMIT</name>
|
|
<description>P-Channel Current Limit. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>Set source limit to mode 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>Set source limit to mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>Set source limit to mode 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>Set source limit to mode 3.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE4</name>
|
|
<description>Set source limit to mode 4.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE5</name>
|
|
<description>Set source limit to mode 5.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE6</name>
|
|
<description>Set source limit to mode 6.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE7</name>
|
|
<description>Set source limit to mode 7.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE8</name>
|
|
<description>Set source limit to mode 8.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE9</name>
|
|
<description>Set source limit to mode 9.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE10</name>
|
|
<description>Set source limit to mode 10.</description>
|
|
<value>10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE11</name>
|
|
<description>Set source limit to mode 11.</description>
|
|
<value>11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE12</name>
|
|
<description>Set source limit to mode 12.</description>
|
|
<value>12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE13</name>
|
|
<description>Set source limit to mode 13.</description>
|
|
<value>13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE14</name>
|
|
<description>Set source limit to mode 14.</description>
|
|
<value>14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE15</name>
|
|
<description>Set source limit to mode 15.</description>
|
|
<value>15</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBFSEL</name>
|
|
<description>Function Select</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB0SEL</name>
|
|
<description>Port Bank n.0 Function Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO</name>
|
|
<description>Pin configured for GPIO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMLS</name>
|
|
<description>Pin configured for Port Mapped Level Shift.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0</name>
|
|
<description>Pin configured for EPCA0 output.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB1SEL</name>
|
|
<description>Port Bank n.1 Function Select. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO</name>
|
|
<description>Pin configured for GPIO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMLS</name>
|
|
<description>Pin configured for Port Mapped Level Shift.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0</name>
|
|
<description>Pin configured for EPCA0 output.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB2SEL</name>
|
|
<description>Port Bank n.2 Function Select. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO</name>
|
|
<description>Pin configured for GPIO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMLS</name>
|
|
<description>Pin configured for Port Mapped Level Shift.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0</name>
|
|
<description>Pin configured for EPCA0 output.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1</name>
|
|
<description>Pin configured for UART1 TX.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB3SEL</name>
|
|
<description>Port Bank n.3 Function Select. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO</name>
|
|
<description>Pin configured for GPIO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMLS</name>
|
|
<description>Pin configured for Port Mapped Level Shift.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0</name>
|
|
<description>Pin configured for EPCA0 output.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1</name>
|
|
<description>Pin configured for UART1 RX.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB4SEL</name>
|
|
<description>Port Bank n.4 Function Select. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO</name>
|
|
<description>Pin configured for GPIO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMLS</name>
|
|
<description>Pin configured for Port Mapped Level Shift.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0</name>
|
|
<description>Pin configured for EPCA0 output.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1</name>
|
|
<description>Pin configured for UART1 RTS.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB5SEL</name>
|
|
<description>Port Bank n.5 Function Select. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO</name>
|
|
<description>Pin configured for GPIO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMLS</name>
|
|
<description>Pin configured for Port Mapped Level Shift.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPCA0</name>
|
|
<description>Pin configured for EPCA0 output.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1</name>
|
|
<description>Pin configured for UART1 CTS.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTIMER0</name>
|
|
<description>Pin configured for LPTIMER0 toggle output.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBSS</name>
|
|
<description>Safe State Control</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB0SSSEL</name>
|
|
<description>Port Bank n.0 Safe State Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIZ</name>
|
|
<description>Place PBn.0 in a High Impedance state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Drive PBn.0 High.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Drive PBn.0 Low.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Ignore the safe state signal (weak pull-ups disabled).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB1SSSEL</name>
|
|
<description>Port Bank n.1 Safe State Select. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIZ</name>
|
|
<description>Place PBn.1 in a High Impedance state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Drive PBn.1 High.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Drive PBn.1 Low.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Ignore the safe state signal (weak pull-ups disabled).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB2SSSEL</name>
|
|
<description>Port Bank n.2 Safe State Select. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIZ</name>
|
|
<description>Place PBn.2 in a High Impedance state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Drive PBn.2 High.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Drive PBn.2 Low.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Ignore the safe state signal (weak pull-ups disabled).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB3SSSEL</name>
|
|
<description>Port Bank n.3 Safe State Select. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIZ</name>
|
|
<description>Place PBn.3 in a High Impedance state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Drive PBn.3 High.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Drive PBn.3 Low.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Ignore the safe state signal (weak pull-ups disabled).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB4SSSEL</name>
|
|
<description>Port Bank n.4 Safe State Select. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIZ</name>
|
|
<description>Place PBn.4 in a High Impedance state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Drive PBn.4 High.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Drive PBn.4 Low.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Ignore the safe state signal (weak pull-ups disabled).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB5SSSEL</name>
|
|
<description>Port Bank n.5 Safe State Select. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIZ</name>
|
|
<description>Place PBn.5 in a High Impedance state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Drive PBn.5 High.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Drive PBn.5 Low.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Ignore the safe state signal (weak pull-ups disabled).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSMDEN</name>
|
|
<description>Enter Safe State Mode. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Safe State.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enter Safe State. Each PBn.x pin will enter the states defined by PBxSSSEL.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBSSSMD</name>
|
|
<description>Safe State Signal Mode. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DEGLITCH</name>
|
|
<description>Enable deglitching on the kill signal input. The kill signal must be asserted for two APB clocks to be recognized.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IMMEDIATE</name>
|
|
<description>Disable deglitching on the kill signal input. The kill signal will take immediate effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBLOCK</name>
|
|
<description>Lock Control</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<resetValue>0x0000003F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBLOCK</name>
|
|
<description>Port Bank Lock. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PBSTD_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Port_Standard</groupName>
|
|
<baseAddress>0x4002a0a0</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>PB</name>
|
|
<description>Output Latch</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB</name>
|
|
<description>Output Latch. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBPIN</name>
|
|
<description>Pin Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBPIN</name>
|
|
<description>Pin Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBMDSEL</name>
|
|
<description>Mode Select</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBMDSEL</name>
|
|
<description>Mode Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBSKIPEN</name>
|
|
<description>Crossbar Pin Skip Enable</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBSKIPEN</name>
|
|
<description>Crossbar Pin Skip Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBOUTMD</name>
|
|
<description>Output Mode</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBOUTMD</name>
|
|
<description>Output Mode. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBDRV</name>
|
|
<description>Drive Strength</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00010000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBDRV</name>
|
|
<description>Drive Strength. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBPUEN</name>
|
|
<description>Port Bank Weak Pull-up Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable weak pull-ups for this port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable weak pull-ups for this port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PM</name>
|
|
<description>Port Match Value</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Port Match Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMEN</name>
|
|
<description>Port Match Enable</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMEN</name>
|
|
<description>Port Match Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PBSTD_1</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Port_Standard</groupName>
|
|
<baseAddress>0x4002a140</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>PB</name>
|
|
<description>Output Latch</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB</name>
|
|
<description>Output Latch. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBPIN</name>
|
|
<description>Pin Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBPIN</name>
|
|
<description>Pin Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBMDSEL</name>
|
|
<description>Mode Select</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBMDSEL</name>
|
|
<description>Mode Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBSKIPEN</name>
|
|
<description>Crossbar Pin Skip Enable</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBSKIPEN</name>
|
|
<description>Crossbar Pin Skip Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBOUTMD</name>
|
|
<description>Output Mode</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBOUTMD</name>
|
|
<description>Output Mode. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBDRV</name>
|
|
<description>Drive Strength</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00010000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBDRV</name>
|
|
<description>Drive Strength. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBPUEN</name>
|
|
<description>Port Bank Weak Pull-up Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable weak pull-ups for this port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable weak pull-ups for this port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PM</name>
|
|
<description>Port Match Value</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Port Match Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMEN</name>
|
|
<description>Port Match Enable</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMEN</name>
|
|
<description>Port Match Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PBSTD_2</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Port_Standard</groupName>
|
|
<baseAddress>0x4002a1e0</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>PB</name>
|
|
<description>Output Latch</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB</name>
|
|
<description>Output Latch. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBPIN</name>
|
|
<description>Pin Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBPIN</name>
|
|
<description>Pin Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBMDSEL</name>
|
|
<description>Mode Select</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBMDSEL</name>
|
|
<description>Mode Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBSKIPEN</name>
|
|
<description>Crossbar Pin Skip Enable</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBSKIPEN</name>
|
|
<description>Crossbar Pin Skip Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBOUTMD</name>
|
|
<description>Output Mode</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBOUTMD</name>
|
|
<description>Output Mode. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBDRV</name>
|
|
<description>Drive Strength</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00010000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBDRV</name>
|
|
<description>Drive Strength. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBPUEN</name>
|
|
<description>Port Bank Weak Pull-up Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable weak pull-ups for this port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable weak pull-ups for this port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PM</name>
|
|
<description>Port Match Value</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Port Match Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMEN</name>
|
|
<description>Port Match Enable</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMEN</name>
|
|
<description>Port Match Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBLOCK</name>
|
|
<description>Lock Control</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBLOCK</name>
|
|
<description>Port Bank Lock. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBPGEN</name>
|
|
<description>Pulse Generator Pin Enable</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBPGEN</name>
|
|
<description>Pulse Generator Pin Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBPGPHASE</name>
|
|
<description>Pulse Generator Phase</description>
|
|
<addressOffset>0xa0</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBPGPH0</name>
|
|
<description>Pulse Generator Phase 0. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBPGPH1</name>
|
|
<description>Pulse Generator Phase 1. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PBSTD_3</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Port_Standard</groupName>
|
|
<baseAddress>0x4002a320</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>PB</name>
|
|
<description>Output Latch</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PB</name>
|
|
<description>Output Latch. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBPIN</name>
|
|
<description>Pin Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBPIN</name>
|
|
<description>Pin Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBMDSEL</name>
|
|
<description>Mode Select</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBMDSEL</name>
|
|
<description>Mode Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBSKIPEN</name>
|
|
<description>Crossbar Pin Skip Enable</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBSKIPEN</name>
|
|
<description>Crossbar Pin Skip Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBOUTMD</name>
|
|
<description>Output Mode</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBOUTMD</name>
|
|
<description>Output Mode. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBDRV</name>
|
|
<description>Drive Strength</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00010000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBDRV</name>
|
|
<description>Drive Strength. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBPUEN</name>
|
|
<description>Port Bank Weak Pull-up Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable weak pull-ups for this port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable weak pull-ups for this port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PM</name>
|
|
<description>Port Match Value</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Port Match Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMEN</name>
|
|
<description>Port Match Enable</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMEN</name>
|
|
<description>Port Match Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBLOCK</name>
|
|
<description>Lock Control</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBLOCK</name>
|
|
<description>Port Bank Lock. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>RTC_0</groupName>
|
|
<baseAddress>0x40029000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTCALRM_IRQn</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>RTCFAIL_IRQn</name>
|
|
<value>44</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>RTC Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ALM0AREN</name>
|
|
<description>Alarm 0 Automatic Reset Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Alarm 0 automatic reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Alarm 0 automatic reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>RTC Timer Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the RTC timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start the RTC timer running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCLKEN</name>
|
|
<description>Missing Clock Detector Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the missing clock detector.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the missing clock detector. If the missing clock detector triggers, it will generate an RTC Fail event.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASEN</name>
|
|
<description>Automatic Crystal Load Capacitance Stepping Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable automatic load capacitance stepping.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable automatic load capacitance stepping.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCLC</name>
|
|
<description>Load Capacitance Value. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BDEN</name>
|
|
<description>Bias Doubler Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the bias doubler, saving power.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the bias doubler, allowing for faster oscillator start up time.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRYSEN</name>
|
|
<description>Crystal Oscillator Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the crystal oscillator circuitry.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the crystal oscillator circuitry.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AGCEN</name>
|
|
<description>Automatic Gain Control Enable. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable automatic gain control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable automatic gain control, saving power.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALM0EN</name>
|
|
<description>Alarm 0 Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable RTC Alarm 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable RTC Alarm 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALM1EN</name>
|
|
<description>Alarm 1 Enable. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable RTC Alarm 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable RTC Alarm 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALM2EN</name>
|
|
<description>Alarm 2 Enable. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable RTC Alarm 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable RTC Alarm 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCOEN</name>
|
|
<description>RTC0 External Output Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the external RTCnOSC output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the external RTCnOSC output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>RTC Timer Clock Select. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTCNOSC</name>
|
|
<description>Select the RTC clock (RTCnOSC) as the RTC Timer clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFOSCN</name>
|
|
<description>Select the Low Frequency Oscillator (LFOSCn) clock as the RTC Timer clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTCEN</name>
|
|
<description>RTC Oscillator and Timer Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the RTC Oscillator and Timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the RTC Oscillator and Timer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>RTC Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ALM0I</name>
|
|
<description>Alarm 0 Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Alarm 0 event has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Alarm 0 event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALM1I</name>
|
|
<description>Alarm 1 Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Alarm 1 event has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Alarm 1 event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALM2I</name>
|
|
<description>Alarm 2 Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Alarm 2 event has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Alarm 2 event occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRCAP</name>
|
|
<description>RTC Timer Capture. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>RTC timer capture operation is complete.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Start the RTC timer capture.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMRSET</name>
|
|
<description>RTC Timer Set. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>RTC timer set operation is complete.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Start the RTC timer set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKVF</name>
|
|
<description>RTC External Oscillator Valid Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>External oscillator is not valid.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>External oscillator is valid.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCFI</name>
|
|
<description>RTC Oscillator Fail Interrupt Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Oscillator is running.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Oscillator has failed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSMDEN</name>
|
|
<description>RTC High Speed Mode Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable high speed mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable high speed mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LRDYF</name>
|
|
<description>RTC Load Capacitance Ready Flag. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The load capacitance is currently stepping.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The load capacitance has reached its programmed value.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALARM0</name>
|
|
<description>RTC Alarm 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ALARM0</name>
|
|
<description>RTC Alarm 0. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALARM1</name>
|
|
<description>RTC Alarm 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ALARM1</name>
|
|
<description>RTC Alarm 1. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALARM2</name>
|
|
<description>RTC Alarm 2</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ALARM2</name>
|
|
<description>RTC Alarm 2. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETCAP</name>
|
|
<description>RTC Timer Set/Capture Value</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETCAP</name>
|
|
<description>RTC Timer Set/Capture Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LFOCONTROL</name>
|
|
<description>LFOSC Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LFOSCEN</name>
|
|
<description>Low Frequency Oscillator Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Low Frequency Oscillator (LFOSCn).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Low Frequency Oscillator (LFOSCn).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LFOSCADJ</name>
|
|
<description>LFOSC Output Frequency Adjust</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LFOSCADJ</name>
|
|
<description>LFOSC Output Frequency Adjust. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RSTSRC_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>RSTSRC_0</groupName>
|
|
<baseAddress>0x4002d060</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>RESETEN</name>
|
|
<description>System Reset Source Enable</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x0000082F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VMONREN</name>
|
|
<description>Voltage Supply Monitor VDD Reset Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Voltage Supply Monitor VDD event as a reset source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Voltage Supply Monitor VDD event as a reset source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCDREN</name>
|
|
<description>Missing Clock Detector Reset Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Missing Clock Detector event as a reset source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Missing Clock Detector event as a reset source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTREN</name>
|
|
<description>Watchdog Timer Reset Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Watchdog Timer event as a reset source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Watchdog Timer event as a reset source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWREN</name>
|
|
<description>Software Reset. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not generate a Software Reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Generate a Software Reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0REN</name>
|
|
<description>Comparator 0 Reset Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Comparator 0 event as a reset source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Comparator 0 event as a reset source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1REN</name>
|
|
<description>Comparator 1 Reset Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Comparator 1 event as a reset source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Comparator 1 event as a reset source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB0REN</name>
|
|
<description>USB0 Reset Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the USB0 reset event as a reset source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the USB0 reset event as a reset source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC0REN</name>
|
|
<description>RTC0 Reset Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the RTC0 event as a reset source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the RTC0 event as a reset source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEREN</name>
|
|
<description>PMU Wakeup Reset Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the PMU Wakeup event as a reset source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESETFLAG</name>
|
|
<description>System Reset Flags</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINRF</name>
|
|
<description>Pin Reset Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A /RESET pin event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A /RESET pin event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PORRF</name>
|
|
<description>Power-On Reset Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Power-On Reset event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Power-On Reset event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VMONRF</name>
|
|
<description>Voltage Supply Monitor VDD Reset Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Voltage Supply Monitor VDD Reset event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Voltage Supply Monitor VDD Reset event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CORERF</name>
|
|
<description>Core Reset Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Core Reset event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Core Reset event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCDRF</name>
|
|
<description>Missing Clock Detector Reset Flag. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Missing Clock Detector event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Missing Clock Detector event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTRF</name>
|
|
<description>Watchdog Timer Reset Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Watchdog Timer event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Watchdog Timer event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRF</name>
|
|
<description>Software Reset Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Software Reset event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Software Reset event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP0RF</name>
|
|
<description>Comparator 0 Reset Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Comparator 0 event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Comparator 0 event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMP1RF</name>
|
|
<description>Comparator 1 Reset Flag. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A Comparator 1 event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A Comparator 1 event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB0RF</name>
|
|
<description>USB0 Reset Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A USB0 Reset event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A USB0 Reset event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC0RF</name>
|
|
<description>RTC0 Reset Flag. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>An RTC0 event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>An RTC0 event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKERF</name>
|
|
<description>PMU Wakeup Reset Flag. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A PMU Wakeup event did not cause the last system reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A PMU Wakeup event caused the last system reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Configuration Options</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMSEL</name>
|
|
<description>Power Mode Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PM9_DIS</name>
|
|
<description>Power Mode < PM9.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PM9_EN</name>
|
|
<description>Power Mode = PM9.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0x40004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI0_IRQn</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Input/Output Data</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Input/Output Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00004084</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRQI</name>
|
|
<description>Receive FIFO Read Request Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The RX FIFO has fewer bytes than the level defined by RFTH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The RX FIFO has equal or more bytes than the level defined by RFTH.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFORI</name>
|
|
<description>Receive FIFO Overrun Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A receive FIFO overrun has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFRQI</name>
|
|
<description>Transmit FIFO Write Request Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The TX FIFO has fewer bytes than the level defined by TFTH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The TX FIFO has equal or more bytes than the level defined by TFTH.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFORI</name>
|
|
<description>Transmit FIFO Overrun Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A transmit FIFO overrun has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVSELI</name>
|
|
<description>Slave Selected Interrupt Flag. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The slave select signal (NSS) is not active.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The slave select signal (NSS) is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDFI</name>
|
|
<description>Mode Fault Interrupt Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A master mode collision is not detected. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A master mode collision occurred. Write: Force a mode fault interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>URI</name>
|
|
<description>Underrun Interrupt Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A data transfer is still in progress. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SREI</name>
|
|
<description>Shift Register Empty Interrupt Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>There is data still present in the transmit FIFO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFILI</name>
|
|
<description>Illegal Receive FIFO Access Interrupt Flag. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFILI</name>
|
|
<description>Illegal Transmit FIFO Access Interrupt Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSSSTS</name>
|
|
<description>NSS Instantaneous Pin Status. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>NSS is currently a logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>NSS is currently a logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSYF</name>
|
|
<description>SPI Busy. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The SPI is not busy and a transfer is not in progress.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The SPI is currently busy and a transfer is in progress.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFCNT</name>
|
|
<description>Receive FIFO Counter. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFCNT</name>
|
|
<description>Transmit FIFO Counter. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>SPI Debug Mode. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The SPI module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the SPI module to halt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRQIEN</name>
|
|
<description>Receive FIFO Read Request Interrupt Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive FIFO request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive FIFO request interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFORIEN</name>
|
|
<description>Receive FIFO Overrun Interrupt Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive FIFO overrun interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive FIFO overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFRQIEN</name>
|
|
<description>Transmit FIFO Write Request Interrupt Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit FIFO data request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit FIFO data request interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFORIEN</name>
|
|
<description>Transmit FIFO Overrun Interrupt Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit FIFO overrun interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit FIFO overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVSELIEN</name>
|
|
<description>Slave Selected Interrupt Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the slave select interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the slave select interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDFIEN</name>
|
|
<description>Mode Fault Interrupt Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the mode fault interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the mode fault interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>URIEN</name>
|
|
<description>Underrun Interrupt Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the underrun interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SREIEN</name>
|
|
<description>Shift Register Empty Interrupt Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the shift register empty interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the shift register empty interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIEN</name>
|
|
<description>SPI Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the SPI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the SPI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTEN</name>
|
|
<description>Master Mode Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Operate in slave mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Operate in master mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKPOL</name>
|
|
<description>SPI Clock Polarity. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The SCK line is low in the idle state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The SCK line is high in the idle state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKPHA</name>
|
|
<description>SPI Clock Phase. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CENTER</name>
|
|
<description>The first edge of SCK is the sample edge (center of data bit).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>The first edge of SCK is the shift edge (edge of data bit).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSSPOL</name>
|
|
<description>Slave Select Polarity Select. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>NSS is active low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>NSS is active high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDIRSEL</name>
|
|
<description>Data Direction Select. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MSB_FIRST</name>
|
|
<description>Data will be shifted MSB first.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSB_FIRST</name>
|
|
<description>Data will be shifted LSB first.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSSMD</name>
|
|
<description>Slave Select Mode. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>3_WIRE_MASTER_SLAVE</name>
|
|
<description>3-wire Slave or 3-wire Master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_WIRE_SLAVE</name>
|
|
<description>4-wire slave (NSS input). This setting can also be used for multi-master configurations.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_WIRE_MASTER_NSS_LOW</name>
|
|
<description>4-wire master with NSS low (NSS output).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_WIRE_MASTER_NSS_HIGH</name>
|
|
<description>4-wire master with NSS high (NSS output).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFTH</name>
|
|
<description>Receive FIFO Threshold. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A DMA / RFRQ request asserts when >= 1 FIFO slot is filled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A DMA / RFRQ request asserts when >= 2 FIFO slots are filled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A DMA / RFRQ request asserts when >= 4 FIFO slots are filled.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>A DMA / RFRQ request asserts when all FIFO slots are filled.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFTH</name>
|
|
<description>Transmit FIFO Threshold. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A DMA / TFRQ request asserts when >= 1 FIFO slot is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A DMA / TFRQ request asserts when >= 2 FIFO slots are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A DMA / TFRQ request asserts when >= 4 FIFO slots are empty.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>A DMA / TFRQ request asserts when all FIFO slots are empty.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Data Size. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA requests. </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable DMA requests when the transmit buffer is empty or the receive buffer is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFIFOFL</name>
|
|
<description>Receive FIFO Flush. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the receive FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFIFOFL</name>
|
|
<description>Transmit FIFO Flush. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the transmit FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>Module Soft Reset. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>SPI module is not in soft reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKRATE</name>
|
|
<description>Module Clock Rate Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Divider. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSTATUS</name>
|
|
<description>FIFO Status</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRPTR</name>
|
|
<description>Receive FIFO Read Pointer. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFWPTR</name>
|
|
<description>Receive FIFO Write Pointer. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFRPTR</name>
|
|
<description>Transmit FIFO Read Pointer. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFWPTR</name>
|
|
<description>Transmit FIFO Write Pointer. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI_1</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0x40005000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI1_IRQn</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Input/Output Data</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Input/Output Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00004084</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRQI</name>
|
|
<description>Receive FIFO Read Request Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The RX FIFO has fewer bytes than the level defined by RFTH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The RX FIFO has equal or more bytes than the level defined by RFTH.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFORI</name>
|
|
<description>Receive FIFO Overrun Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A receive FIFO overrun has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFRQI</name>
|
|
<description>Transmit FIFO Write Request Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The TX FIFO has fewer bytes than the level defined by TFTH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The TX FIFO has equal or more bytes than the level defined by TFTH.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFORI</name>
|
|
<description>Transmit FIFO Overrun Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A transmit FIFO overrun has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVSELI</name>
|
|
<description>Slave Selected Interrupt Flag. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The slave select signal (NSS) is not active.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The slave select signal (NSS) is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDFI</name>
|
|
<description>Mode Fault Interrupt Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A master mode collision is not detected. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A master mode collision occurred. Write: Force a mode fault interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>URI</name>
|
|
<description>Underrun Interrupt Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A data transfer is still in progress. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SREI</name>
|
|
<description>Shift Register Empty Interrupt Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>There is data still present in the transmit FIFO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFILI</name>
|
|
<description>Illegal Receive FIFO Access Interrupt Flag. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFILI</name>
|
|
<description>Illegal Transmit FIFO Access Interrupt Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSSSTS</name>
|
|
<description>NSS Instantaneous Pin Status. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>NSS is currently a logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>NSS is currently a logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSYF</name>
|
|
<description>SPI Busy. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The SPI is not busy and a transfer is not in progress.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The SPI is currently busy and a transfer is in progress.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFCNT</name>
|
|
<description>Receive FIFO Counter. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFCNT</name>
|
|
<description>Transmit FIFO Counter. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>SPI Debug Mode. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The SPI module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the SPI module to halt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRQIEN</name>
|
|
<description>Receive FIFO Read Request Interrupt Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive FIFO request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive FIFO request interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFORIEN</name>
|
|
<description>Receive FIFO Overrun Interrupt Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive FIFO overrun interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive FIFO overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFRQIEN</name>
|
|
<description>Transmit FIFO Write Request Interrupt Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit FIFO data request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit FIFO data request interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFORIEN</name>
|
|
<description>Transmit FIFO Overrun Interrupt Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit FIFO overrun interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit FIFO overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVSELIEN</name>
|
|
<description>Slave Selected Interrupt Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the slave select interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the slave select interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDFIEN</name>
|
|
<description>Mode Fault Interrupt Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the mode fault interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the mode fault interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>URIEN</name>
|
|
<description>Underrun Interrupt Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the underrun interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SREIEN</name>
|
|
<description>Shift Register Empty Interrupt Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the shift register empty interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the shift register empty interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIEN</name>
|
|
<description>SPI Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the SPI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the SPI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTEN</name>
|
|
<description>Master Mode Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Operate in slave mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Operate in master mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKPOL</name>
|
|
<description>SPI Clock Polarity. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The SCK line is low in the idle state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The SCK line is high in the idle state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKPHA</name>
|
|
<description>SPI Clock Phase. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CENTER</name>
|
|
<description>The first edge of SCK is the sample edge (center of data bit).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>The first edge of SCK is the shift edge (edge of data bit).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSSPOL</name>
|
|
<description>Slave Select Polarity Select. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>NSS is active low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>NSS is active high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDIRSEL</name>
|
|
<description>Data Direction Select. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MSB_FIRST</name>
|
|
<description>Data will be shifted MSB first.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSB_FIRST</name>
|
|
<description>Data will be shifted LSB first.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSSMD</name>
|
|
<description>Slave Select Mode. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>3_WIRE_MASTER_SLAVE</name>
|
|
<description>3-wire Slave or 3-wire Master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_WIRE_SLAVE</name>
|
|
<description>4-wire slave (NSS input). This setting can also be used for multi-master configurations.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_WIRE_MASTER_NSS_LOW</name>
|
|
<description>4-wire master with NSS low (NSS output).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_WIRE_MASTER_NSS_HIGH</name>
|
|
<description>4-wire master with NSS high (NSS output).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFTH</name>
|
|
<description>Receive FIFO Threshold. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A DMA / RFRQ request asserts when >= 1 FIFO slot is filled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A DMA / RFRQ request asserts when >= 2 FIFO slots are filled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A DMA / RFRQ request asserts when >= 4 FIFO slots are filled.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>A DMA / RFRQ request asserts when all FIFO slots are filled.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFTH</name>
|
|
<description>Transmit FIFO Threshold. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A DMA / TFRQ request asserts when >= 1 FIFO slot is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A DMA / TFRQ request asserts when >= 2 FIFO slots are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A DMA / TFRQ request asserts when >= 4 FIFO slots are empty.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>A DMA / TFRQ request asserts when all FIFO slots are empty.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Data Size. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA requests. </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable DMA requests when the transmit buffer is empty or the receive buffer is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFIFOFL</name>
|
|
<description>Receive FIFO Flush. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the receive FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFIFOFL</name>
|
|
<description>Transmit FIFO Flush. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the transmit FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>Module Soft Reset. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>SPI module is not in soft reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKRATE</name>
|
|
<description>Module Clock Rate Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Divider. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSTATUS</name>
|
|
<description>FIFO Status</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRPTR</name>
|
|
<description>Receive FIFO Read Pointer. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFWPTR</name>
|
|
<description>Receive FIFO Write Pointer. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFRPTR</name>
|
|
<description>Transmit FIFO Read Pointer. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFWPTR</name>
|
|
<description>Transmit FIFO Write Pointer. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI_2</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0x40006000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI2_IRQn</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Input/Output Data</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Input/Output Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00004084</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRQI</name>
|
|
<description>Receive FIFO Read Request Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The RX FIFO has fewer bytes than the level defined by RFTH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The RX FIFO has equal or more bytes than the level defined by RFTH.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFORI</name>
|
|
<description>Receive FIFO Overrun Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A receive FIFO overrun has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFRQI</name>
|
|
<description>Transmit FIFO Write Request Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The TX FIFO has fewer bytes than the level defined by TFTH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The TX FIFO has equal or more bytes than the level defined by TFTH.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFORI</name>
|
|
<description>Transmit FIFO Overrun Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A transmit FIFO overrun has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVSELI</name>
|
|
<description>Slave Selected Interrupt Flag. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The slave select signal (NSS) is not active.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The slave select signal (NSS) is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDFI</name>
|
|
<description>Mode Fault Interrupt Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A master mode collision is not detected. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A master mode collision occurred. Write: Force a mode fault interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>URI</name>
|
|
<description>Underrun Interrupt Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A data transfer is still in progress. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SREI</name>
|
|
<description>Shift Register Empty Interrupt Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>There is data still present in the transmit FIFO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFILI</name>
|
|
<description>Illegal Receive FIFO Access Interrupt Flag. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFILI</name>
|
|
<description>Illegal Transmit FIFO Access Interrupt Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSSSTS</name>
|
|
<description>NSS Instantaneous Pin Status. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>NSS is currently a logic low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>NSS is currently a logic high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSYF</name>
|
|
<description>SPI Busy. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The SPI is not busy and a transfer is not in progress.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The SPI is currently busy and a transfer is in progress.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFCNT</name>
|
|
<description>Receive FIFO Counter. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFCNT</name>
|
|
<description>Transmit FIFO Counter. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>SPI Debug Mode. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The SPI module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the SPI module to halt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRQIEN</name>
|
|
<description>Receive FIFO Read Request Interrupt Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive FIFO request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive FIFO request interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFORIEN</name>
|
|
<description>Receive FIFO Overrun Interrupt Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive FIFO overrun interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive FIFO overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFRQIEN</name>
|
|
<description>Transmit FIFO Write Request Interrupt Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit FIFO data request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit FIFO data request interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFORIEN</name>
|
|
<description>Transmit FIFO Overrun Interrupt Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit FIFO overrun interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit FIFO overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLVSELIEN</name>
|
|
<description>Slave Selected Interrupt Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the slave select interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the slave select interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDFIEN</name>
|
|
<description>Mode Fault Interrupt Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the mode fault interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the mode fault interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>URIEN</name>
|
|
<description>Underrun Interrupt Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the underrun interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SREIEN</name>
|
|
<description>Shift Register Empty Interrupt Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the shift register empty interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the shift register empty interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIEN</name>
|
|
<description>SPI Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the SPI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the SPI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTEN</name>
|
|
<description>Master Mode Enable. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Operate in slave mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Operate in master mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKPOL</name>
|
|
<description>SPI Clock Polarity. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The SCK line is low in the idle state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The SCK line is high in the idle state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKPHA</name>
|
|
<description>SPI Clock Phase. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CENTER</name>
|
|
<description>The first edge of SCK is the sample edge (center of data bit).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE</name>
|
|
<description>The first edge of SCK is the shift edge (edge of data bit).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSSPOL</name>
|
|
<description>Slave Select Polarity Select. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>NSS is active low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>NSS is active high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDIRSEL</name>
|
|
<description>Data Direction Select. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MSB_FIRST</name>
|
|
<description>Data will be shifted MSB first.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSB_FIRST</name>
|
|
<description>Data will be shifted LSB first.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSSMD</name>
|
|
<description>Slave Select Mode. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>3_WIRE_MASTER_SLAVE</name>
|
|
<description>3-wire Slave or 3-wire Master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_WIRE_SLAVE</name>
|
|
<description>4-wire slave (NSS input). This setting can also be used for multi-master configurations.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_WIRE_MASTER_NSS_LOW</name>
|
|
<description>4-wire master with NSS low (NSS output).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_WIRE_MASTER_NSS_HIGH</name>
|
|
<description>4-wire master with NSS high (NSS output).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFTH</name>
|
|
<description>Receive FIFO Threshold. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A DMA / RFRQ request asserts when >= 1 FIFO slot is filled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A DMA / RFRQ request asserts when >= 2 FIFO slots are filled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A DMA / RFRQ request asserts when >= 4 FIFO slots are filled.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>A DMA / RFRQ request asserts when all FIFO slots are filled.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFTH</name>
|
|
<description>Transmit FIFO Threshold. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A DMA / TFRQ request asserts when >= 1 FIFO slot is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A DMA / TFRQ request asserts when >= 2 FIFO slots are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A DMA / TFRQ request asserts when >= 4 FIFO slots are empty.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>A DMA / TFRQ request asserts when all FIFO slots are empty.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Data Size. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable DMA requests. </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable DMA requests when the transmit buffer is empty or the receive buffer is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFIFOFL</name>
|
|
<description>Receive FIFO Flush. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the receive FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFIFOFL</name>
|
|
<description>Transmit FIFO Flush. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the transmit FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>Module Soft Reset. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>SPI module is not in soft reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKRATE</name>
|
|
<description>Module Clock Rate Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Divider. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSTATUS</name>
|
|
<description>FIFO Status</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRPTR</name>
|
|
<description>Receive FIFO Read Pointer. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFWPTR</name>
|
|
<description>Receive FIFO Write Pointer. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFRPTR</name>
|
|
<description>Transmit FIFO Read Pointer. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFWPTR</name>
|
|
<description>Transmit FIFO Write Pointer. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SSG_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>SSG_0</groupName>
|
|
<baseAddress>0x4001e000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Pulse Generator Counter. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSEL</name>
|
|
<description>Speed Select. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>The SSG module runs at normal speed, where each pulse and phase cycle consists of 16 ADC clocks.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE</name>
|
|
<description>The SSG module runs at double speed, where each pulse and phase cycle consists of 8 ADC clocks.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHGFREN</name>
|
|
<description>Phase Generator Free-Run Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The Phase Generator runs only when pulse generation occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The Phase Generator runs when an ADC is enabled, regardless of the Pulse Generator settings.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUGFREN</name>
|
|
<description>Pulse Generator Free-Run Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The COUNT field determines the number of pulses generated by the Pulse Generator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The Pulse Generator always generates pulses regardless of COUNT unless all outputs are disabled (EX0EN, EX1EN, EX2EN, and EX3EN are all 0).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EX0INVEN</name>
|
|
<description>Output 0 Invert Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Do not invert the Pulse Generator output on EX0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERT</name>
|
|
<description>Invert the Pulse Generator output on EX0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EX1INVEN</name>
|
|
<description>Output 1 Invert Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Do not invert the Pulse Generator output on EX1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERT</name>
|
|
<description>Invert the Pulse Generator output on EX1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EX2INVEN</name>
|
|
<description>Output 2 Invert Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Do not invert the Pulse Generator output on EX2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERT</name>
|
|
<description>Invert the Pulse Generator output on EX2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EX3INVEN</name>
|
|
<description>Output 3 Invert Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Do not invert the Pulse Generator output on EX3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERT</name>
|
|
<description>Invert the Pulse Generator output on EX3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EX0EN</name>
|
|
<description>Output 0 Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the EX0 Pulse Generator output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the EX0 Pulse Generator output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EX1EN</name>
|
|
<description>Output 1 Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the EX1 Pulse Generator output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the EX1 Pulse Generator output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EX2EN</name>
|
|
<description>Output 2 Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the EX2 Pulse Generator output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the EX2 Pulse Generator output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EX3EN</name>
|
|
<description>Output 3 Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the EX3 Pulse Generator output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the EX3 Pulse Generator output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>SSG Module Status. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>The SSG module is idle and the Pulse Generator is not operating.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>The SSG module is active and the Pulse Generator is counting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Timer</groupName>
|
|
<baseAddress>0x40014000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER0L_IRQn</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIMER0H_IRQn</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>High and Low Timer Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCLK</name>
|
|
<description>Low Clock Source. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>APB</name>
|
|
<description>Select the APB clock as the timer source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTOSCN</name>
|
|
<description>Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLKDIV</name>
|
|
<description>Select the dedicated 8-bit prescaler as the timer source.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT_FALLING_EDGE</name>
|
|
<description>Select falling edges of the CT signal as the timer clock source.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LMSTREN</name>
|
|
<description>Low Run Master Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>MSTRUN does not need to be set for the low timer to run.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>MSTRUN must be set for the low timer to run.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLITEN</name>
|
|
<description>Split Mode Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The timer operates as a single 32-bit timer controlled by the high timer fields.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The timer operates as two independent 16-bit timers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LEXIEN</name>
|
|
<description>Low Timer Extra Interrupt Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The state of the LEXI flag does not affect the low timer interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A low timer interrupt request is generated if LEXI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOVFIEN</name>
|
|
<description>Low Timer Overflow Interrupt Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The state of LOVFI does not affect the low timer interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A low timer interrupt request is generated if LOVFI = 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LMD</name>
|
|
<description>Low Timer Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTO_RELOAD</name>
|
|
<description>The low timer is in Auto-Reload Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP_DOWN</name>
|
|
<description>The low timer is in Up/Down Count Mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL_CAPTURE</name>
|
|
<description>The low timer is in Falling Edge Capture Mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE_CAPTURE</name>
|
|
<description>The low timer is in Rising Edge Capture Mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_CAPTURE</name>
|
|
<description>The low timer is in Low Time Capture Mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_CAPTURE</name>
|
|
<description>The low timer is in High Time Capture Mode.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC_CAPTURE</name>
|
|
<description>The low timer is in Duty Cycle Capture Mode.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOT</name>
|
|
<description>The low timer is in Oneshot Mode.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSTATE</name>
|
|
<description>Low Multi Purpose State Indicator. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LRUN</name>
|
|
<description>Run Control Low. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the low timer if split mode is enabled (SPLITEN = 1).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>The low timer runs if split mode is enabled (SPLITEN = 1) and (LMSTREN = 0 or MSTRUN = 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LEXI</name>
|
|
<description>Low Timer Extra Interrupt Flag. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A low timer extra interrupt is not pending. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Indicates the low 16-bit timer has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by hardware in all modes except Auto-Reload and Toggle. This flag is not set by hardware when split mode is disabled (SPLITEN = 0). Write: Force a low timer extra interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOVFI</name>
|
|
<description>Low Timer Overflow Interrupt. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A low timer overflow interrupt is not pending. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: The low 16-bit timer has wrapped or reloaded after reaching all 1's. This bit is set by the module regardless of the state of SPLITEN and can be set in all modes. Write: Force a low timer overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HCLK</name>
|
|
<description>High Clock Source. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>APB</name>
|
|
<description>Select the APB clock as the timer source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTOSCN</name>
|
|
<description>Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLKDIV</name>
|
|
<description>Select the dedicated 8-bit prescaler as the timer source.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT_FALLING_EDGE</name>
|
|
<description>Select falling edges of the CT signal as the timer clock source.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTRUN</name>
|
|
<description>Master Run Control. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Disable the master run control for all timers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Enable the master run control for all timers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HMSTREN</name>
|
|
<description>High Master Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>MSTRUN does not need to be set for the high timer to run.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>MSTRUN must be set for the high timer to run.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>Timer Debug Mode. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The Timer will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the Timer to halt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HEXIEN</name>
|
|
<description>High Timer Extra Interrupt Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The state of the HEXI flag does not affect the high timer interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A high timer interrupt request is generated if HEXI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HOVFIEN</name>
|
|
<description>High Timer Overflow Interrupt Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The state of HOVFI does not affect the high timer interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A high timer interrupt request is generated if HOVFI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HMD</name>
|
|
<description>High Timer Mode. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTO_RELOAD</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Auto-Reload Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP_DOWN</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Up/Down Count Mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL_CAPTURE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Falling Edge Capture Mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE_CAPTURE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Rising Edge Capture Mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_CAPTURE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Low Time Capture Mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_CAPTURE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in High Time Capture Mode.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC_CAPTURE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Duty Cycle Capture Mode.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOT</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Oneshot Mode.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Toggle Output Mode.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in PWM Mode.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSTATE</name>
|
|
<description>High Multi Purpose State Indicator. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRUN</name>
|
|
<description>High Run Control. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the high timer or entire 32-bit timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>The high timer runs if HMSTREN = 0 or MSTRUN = 1. The full 32-bit timer runs if split mode is disabled and (HMSTREN = 0 or MSTRUN = 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HEXI</name>
|
|
<description>High Timer Extra Interrupt Flag. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A high timer extra interrupt is not pending. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Indicates the high 16-bit timer (or 32-bit timer if SPLITEN = 0) has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by the timer module in all modes except Auto-Reload and Toggle. Write: Force a high timer extra interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HOVFI</name>
|
|
<description>High Timer Overflow Interrupt Flag. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A high timer overflow interrupt is not pending. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: If split mode is enabled (SPLITEN = 1), this value indicates the high 16-bit timer has wrapped or reloaded after reaching all 1's. If split mode is disabled (SPLITEN = 0), this value indicates the 32-bit timer has wrapped or reloaded after reaching all 1's. The timer module can set this bit in all modes. Write: Force a high timer overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Module Clock Divider Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIVRL</name>
|
|
<description>Clock Divider Reload Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIVCT</name>
|
|
<description>Clock Divider Counter. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>Timer Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCOUNT</name>
|
|
<description>Low Timer Count. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HCOUNT</name>
|
|
<description>High Timer Count. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPTURE</name>
|
|
<description>Timer Capture/Reload Value</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCCR</name>
|
|
<description>Low Timer Capture/Reload. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HCCR</name>
|
|
<description>High Timer Capture/Reload. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER_1</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Timer</groupName>
|
|
<baseAddress>0x40015000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER1L_IRQn</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIMER1H_IRQn</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>High and Low Timer Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCLK</name>
|
|
<description>Low Clock Source. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>APB</name>
|
|
<description>Select the APB clock as the timer source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTOSCN</name>
|
|
<description>Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLKDIV</name>
|
|
<description>Select the dedicated 8-bit prescaler as the timer source.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT_FALLING_EDGE</name>
|
|
<description>Select falling edges of the CT signal as the timer clock source.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LMSTREN</name>
|
|
<description>Low Run Master Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>MSTRUN does not need to be set for the low timer to run.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>MSTRUN must be set for the low timer to run.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLITEN</name>
|
|
<description>Split Mode Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The timer operates as a single 32-bit timer controlled by the high timer fields.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The timer operates as two independent 16-bit timers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LEXIEN</name>
|
|
<description>Low Timer Extra Interrupt Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The state of the LEXI flag does not affect the low timer interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A low timer interrupt request is generated if LEXI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOVFIEN</name>
|
|
<description>Low Timer Overflow Interrupt Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The state of LOVFI does not affect the low timer interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A low timer interrupt request is generated if LOVFI = 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LMD</name>
|
|
<description>Low Timer Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTO_RELOAD</name>
|
|
<description>The low timer is in Auto-Reload Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP_DOWN</name>
|
|
<description>The low timer is in Up/Down Count Mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL_CAPTURE</name>
|
|
<description>The low timer is in Falling Edge Capture Mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE_CAPTURE</name>
|
|
<description>The low timer is in Rising Edge Capture Mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_CAPTURE</name>
|
|
<description>The low timer is in Low Time Capture Mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_CAPTURE</name>
|
|
<description>The low timer is in High Time Capture Mode.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC_CAPTURE</name>
|
|
<description>The low timer is in Duty Cycle Capture Mode.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOT</name>
|
|
<description>The low timer is in Oneshot Mode.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSTATE</name>
|
|
<description>Low Multi Purpose State Indicator. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LRUN</name>
|
|
<description>Run Control Low. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the low timer if split mode is enabled (SPLITEN = 1).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>The low timer runs if split mode is enabled (SPLITEN = 1) and (LMSTREN = 0 or MSTRUN = 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LEXI</name>
|
|
<description>Low Timer Extra Interrupt Flag. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A low timer extra interrupt is not pending. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Indicates the low 16-bit timer has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by hardware in all modes except Auto-Reload and Toggle. This flag is not set by hardware when split mode is disabled (SPLITEN = 0). Write: Force a low timer extra interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOVFI</name>
|
|
<description>Low Timer Overflow Interrupt. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A low timer overflow interrupt is not pending. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: The low 16-bit timer has wrapped or reloaded after reaching all 1's. This bit is set by the module regardless of the state of SPLITEN and can be set in all modes. Write: Force a low timer overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HCLK</name>
|
|
<description>High Clock Source. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>APB</name>
|
|
<description>Select the APB clock as the timer source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTOSCN</name>
|
|
<description>Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CLKDIV</name>
|
|
<description>Select the dedicated 8-bit prescaler as the timer source.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT_FALLING_EDGE</name>
|
|
<description>Select falling edges of the CT signal as the timer clock source.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTRUN</name>
|
|
<description>Master Run Control. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Disable the master run control for all timers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Enable the master run control for all timers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HMSTREN</name>
|
|
<description>High Master Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>MSTRUN does not need to be set for the high timer to run.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>MSTRUN must be set for the high timer to run.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>Timer Debug Mode. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The Timer will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the Timer to halt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HEXIEN</name>
|
|
<description>High Timer Extra Interrupt Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The state of the HEXI flag does not affect the high timer interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A high timer interrupt request is generated if HEXI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HOVFIEN</name>
|
|
<description>High Timer Overflow Interrupt Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The state of HOVFI does not affect the high timer interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A high timer interrupt request is generated if HOVFI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HMD</name>
|
|
<description>High Timer Mode. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTO_RELOAD</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Auto-Reload Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP_DOWN</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Up/Down Count Mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL_CAPTURE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Falling Edge Capture Mode.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE_CAPTURE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Rising Edge Capture Mode.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_CAPTURE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Low Time Capture Mode.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_CAPTURE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in High Time Capture Mode.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC_CAPTURE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Duty Cycle Capture Mode.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOT</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Oneshot Mode.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in Toggle Output Mode.</description>
|
|
<value>8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>The high 16-bit timer or entire 32-bit timer is in PWM Mode.</description>
|
|
<value>9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSTATE</name>
|
|
<description>High Multi Purpose State Indicator. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRUN</name>
|
|
<description>High Run Control. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop the high timer or entire 32-bit timer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>The high timer runs if HMSTREN = 0 or MSTRUN = 1. The full 32-bit timer runs if split mode is disabled and (HMSTREN = 0 or MSTRUN = 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HEXI</name>
|
|
<description>High Timer Extra Interrupt Flag. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A high timer extra interrupt is not pending. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Indicates the high 16-bit timer (or 32-bit timer if SPLITEN = 0) has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by the timer module in all modes except Auto-Reload and Toggle. Write: Force a high timer extra interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HOVFI</name>
|
|
<description>High Timer Overflow Interrupt Flag. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A high timer overflow interrupt is not pending. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: If split mode is enabled (SPLITEN = 1), this value indicates the high 16-bit timer has wrapped or reloaded after reaching all 1's. If split mode is disabled (SPLITEN = 0), this value indicates the 32-bit timer has wrapped or reloaded after reaching all 1's. The timer module can set this bit in all modes. Write: Force a high timer overflow interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Module Clock Divider Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIVRL</name>
|
|
<description>Clock Divider Reload Value. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIVCT</name>
|
|
<description>Clock Divider Counter. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>Timer Value</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCOUNT</name>
|
|
<description>Low Timer Count. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HCOUNT</name>
|
|
<description>High Timer Count. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPTURE</name>
|
|
<description>Timer Capture/Reload Value</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCCR</name>
|
|
<description>Low Timer Capture/Reload. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HCCR</name>
|
|
<description>High Timer Capture/Reload. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>UART</groupName>
|
|
<baseAddress>0x40002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART0_IRQn</name>
|
|
<value>46</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x030D030D</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTRTEN</name>
|
|
<description>Receiver Start Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect a start bit during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect a start bit during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPAREN</name>
|
|
<description>Receiver Parity Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect a parity bit during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect a parity bit during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTPEN</name>
|
|
<description>Receiver Stop Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect stop bits during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect stop bits during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTPMD</name>
|
|
<description>Receiver Stop Mode. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0P5_STOP</name>
|
|
<description>0.5 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_STOP</name>
|
|
<description>1 stop bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P5_STOP</name>
|
|
<description>1.5 stop bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP</name>
|
|
<description>2 stop bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPARMD</name>
|
|
<description>Receiver Parity Mode. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Set (Parity = 1).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Clear (Parity = 0).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDATLN</name>
|
|
<description>Receiver Data Length. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>5_BITS</name>
|
|
<description>5 bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BITS</name>
|
|
<description>6 bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BITS</name>
|
|
<description>7 bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BITS</name>
|
|
<description>8 bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_STORED</name>
|
|
<description>9 bits. The 9th bit is stored in the FIFO (normal mode).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_MATCH</name>
|
|
<description>9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSCEN</name>
|
|
<description>Receiver Smartcard Parity Response Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver does not send a Smartcard parity error response.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver sends a Smartcard Parity response.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIRDAEN</name>
|
|
<description>Receiver IrDA Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver does not operate in IrDA mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver operates in IrDA mode. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RINVEN</name>
|
|
<description>Receiver Invert Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the RX pin signals (the RX idle state is high).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the RX pin signals (the RX idle state is low).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTRTEN</name>
|
|
<description>Transmitter Start Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not generate a start bit during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Generate a start bit during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPAREN</name>
|
|
<description>Transmitter Parity Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a parity bit during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a parity bit during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTPEN</name>
|
|
<description>Transmitter Stop Enable. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send stop bits during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send stop bits during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTPMD</name>
|
|
<description>Transmitter Stop Mode. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0P5_STOP</name>
|
|
<description>0.5 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_STOP</name>
|
|
<description>1 stop bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P5_STOP</name>
|
|
<description>1.5 stop bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP</name>
|
|
<description>2 stop bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPARMD</name>
|
|
<description>Transmitter Parity Mode. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Set (Parity = 1).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Clear (Parity = 0).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDATLN</name>
|
|
<description>Transmitter Data Length. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>5_BITS</name>
|
|
<description>5 bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BITS</name>
|
|
<description>6 bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BITS</name>
|
|
<description>7 bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BITS</name>
|
|
<description>8 bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_FIFO</name>
|
|
<description>9 bits. The 9th bit is taken from the FIFO data (normal mode).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_TBIT</name>
|
|
<description>9 bits. The 9th bit is set by the value of TBIT (fixed mode).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSCEN</name>
|
|
<description>Transmitter Smartcard Parity Response Enable. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The transmitter does not check for a Smartcard parity error response.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The transmitter checks for a Smartcard parity error response.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIRDAEN</name>
|
|
<description>Transmitter IrDA Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable IrDA transmit mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable IrDA transmit mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TINVEN</name>
|
|
<description>Transmitter Invert Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the TX pin signals (the TX idle state is high).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the TX pin signals (the TX idle state is low).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Module Mode Select</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00600000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>UART Debug Mode. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The UART module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the UART module to halt. Any active transmissions and receptions will complete first.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBMD</name>
|
|
<description>Loop Back Mode. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Loop back is disabled and the TX and RX signals are connected to the corresponding external pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RX_ONLY</name>
|
|
<description>Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TX_ONLY</name>
|
|
<description>Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DUPLEXMD</name>
|
|
<description>Duplex Mode. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL_DUPLEX</name>
|
|
<description>Full-duplex mode. The transmitter and receiver can operate simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF_DUPLEX</name>
|
|
<description>Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITSEN</name>
|
|
<description>Idle TX Tristate Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The TX pin is tristated when idle. If ISTCLK is cleared to 0 and the transmitter is configured in synchronous master mode, the UCLK pin will also be tristated when idle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLOWCN</name>
|
|
<description>Flow Control</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00020001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTS</name>
|
|
<description>RTS State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>RTS pin (before optional inversion) is driven low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>RTS pin (before optional inversion) is driven high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RX</name>
|
|
<description>RX Pin Status. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>RX pin (after optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>RX pin (after optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSINVEN</name>
|
|
<description>RTS Invert Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The UART does not invert the RTS signal before driving the pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The UART inverts the RTS signal driving the pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSTH</name>
|
|
<description>RTS Threshold Control. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_BYTE_FREE</name>
|
|
<description>RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>RTS Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>CTS State. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Indicates the CTS pin state (after optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Indicates the CTS pin state (after optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>TX State. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The TX pin (before optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The TX pin (before optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSINVEN</name>
|
|
<description>CTS Invert Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The UART does not invert CTS.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The UART inverts CTS.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTS Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The CTS pin state does not affect transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Transmissions will begin only if the CTS pin (after optional inversion) is low.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIRDAPW</name>
|
|
<description>Transmit IrDA Pulse Width. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1_16TH</name>
|
|
<description>The IrDA pulse width is 1/16th of a bit period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_8TH</name>
|
|
<description>The IrDA pulse width is 1/8th of a bit period.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_16TH</name>
|
|
<description>The IrDA pulse width is 3/16th of a bit period.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_4TH</name>
|
|
<description>The IrDA pulse width is 1/4th of a bit period.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRMERI</name>
|
|
<description>Receive Frame Error Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A frame error occurred. Write: Force a frame error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPARERI</name>
|
|
<description>Receive Parity Error Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROREI</name>
|
|
<description>Receive Overrun Error Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDREQI</name>
|
|
<description>Receive Data Request Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Fewer than RFTH FIFO slots are filled with data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>At least RFTH FIFO slots are filled with data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RERIEN</name>
|
|
<description>Receive Error Interrupt Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive error interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive error interrupt. A receive error interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDREQIEN</name>
|
|
<description>Receive Data Request Interrupt Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the read data request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATMD</name>
|
|
<description>Match Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Disable the match function.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCE</name>
|
|
<description>(MCE) Data whose last data bit equals RBIT is accepted and stored. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAME</name>
|
|
<description>(Frame) A framing error is asserted if the last received bit matches RBIT.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STORE</name>
|
|
<description>(Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RABDEN</name>
|
|
<description>Receiver Auto-Baud Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable receiver auto-baud.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable receiver auto-baud.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RBUSYF</name>
|
|
<description>Receiver Busy Flag. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The UART receiver is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The UART receiver is receiving data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RBIT</name>
|
|
<description>Last Receive Bit. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROSEN</name>
|
|
<description>Receiver One-Shot Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable one-shot receive mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable one-shot receive mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RINH</name>
|
|
<description>Receiver Inhibit. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The receiver operates normally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REN</name>
|
|
<description>Receiver Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receiver. The receiver can receive one data transaction only if ROSEN is set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receiver.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSCERI</name>
|
|
<description>Smartcard Parity Error Interrupt Flag. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDREQI</name>
|
|
<description>Transmit Data Request Interrupt Flag. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The transmitter is not requesting more FIFO data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The transmitter is requesting more FIFO data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTI</name>
|
|
<description>Transmit Complete Interrupt Flag. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTTH</name>
|
|
<description>Transmit Complete Threshold. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET_ON_TX</name>
|
|
<description>A transmit is completed (TCPTI = 1) at the end of each transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_ON_EMPTY</name>
|
|
<description>A transmit is completed (TCPTI = 1) only at the end of a transmission when no more data is available to transmit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TERIEN</name>
|
|
<description>Transmit Error Interrupt Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit error interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDREQIEN</name>
|
|
<description>Transmit Data Request Interrupt Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit data request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTIEN</name>
|
|
<description>Transmit Complete Interrupt Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit complete interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TBUSYF</name>
|
|
<description>Transmitter Busy Flag. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The UART transmitter is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The UART transmitter is active and transmitting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TBIT</name>
|
|
<description>Last Transmit Bit. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TINH</name>
|
|
<description>Transmit Inhibit. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The transmitter operates normally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Transmissions are inhibited. The transmitter will stall after any current transmission is complete.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transmitter Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPDELAY</name>
|
|
<description>Inter-Packet Delay</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPDELAY</name>
|
|
<description>Inter-Packet Delay. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUDRATE</name>
|
|
<description>Transmit and Receive Baud Rate</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBAUD</name>
|
|
<description>Receiver Baud Rate Control. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBAUD</name>
|
|
<description>Transmitter Baud Rate Control. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOCN</name>
|
|
<description>FIFO Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCNT</name>
|
|
<description>Receive FIFO Count. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFTH</name>
|
|
<description>Receive FIFO Threshold. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A read data request interrupt (RDREQI) is asserted when >= 1 FIFO slot is full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A read data request interrupt (RDREQI) is asserted when >= 2 FIFO slots are full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A read data request interrupt (RDREQI) is asserted when >= 4 FIFO slots are full.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFIFOFL</name>
|
|
<description>Receive FIFO Flush. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the contents of the receive FIFO and any data in the receive shift register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFERI</name>
|
|
<description>Receive FIFO Error Interrupt Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A receive FIFO error has not occurred since RFERI was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A receive FIFO error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRFULLF</name>
|
|
<description>Receive Shift Register Full . </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The receive data shift register is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The receive data shift register is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCNT</name>
|
|
<description>Transmit FIFO Count. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFTH</name>
|
|
<description>Transmit FIFO Threshold. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO slot is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO slots are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A transmit data request interrupt (TDREQI) is asserted when >= 4 FIFO slots are empty.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFIFOFL</name>
|
|
<description>Transmit FIFO Flush. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFERI</name>
|
|
<description>Transmit FIFO Error Interrupt Flag. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A transmit FIFO error has not occurred since TFERI was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A transmit FIFO error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSRFULLF</name>
|
|
<description>Transmit Shift Register Full Flag. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The transmit shift register is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The transmit shift register is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>FIFO Input/Output Data</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>FIFO Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART_1</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>UART</groupName>
|
|
<baseAddress>0x40003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART1_IRQn</name>
|
|
<value>47</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x030D030D</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTRTEN</name>
|
|
<description>Receiver Start Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect a start bit during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect a start bit during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPAREN</name>
|
|
<description>Receiver Parity Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect a parity bit during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect a parity bit during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTPEN</name>
|
|
<description>Receiver Stop Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect stop bits during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect stop bits during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTPMD</name>
|
|
<description>Receiver Stop Mode. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0P5_STOP</name>
|
|
<description>0.5 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_STOP</name>
|
|
<description>1 stop bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P5_STOP</name>
|
|
<description>1.5 stop bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP</name>
|
|
<description>2 stop bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPARMD</name>
|
|
<description>Receiver Parity Mode. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Set (Parity = 1).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Clear (Parity = 0).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDATLN</name>
|
|
<description>Receiver Data Length. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>5_BITS</name>
|
|
<description>5 bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BITS</name>
|
|
<description>6 bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BITS</name>
|
|
<description>7 bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BITS</name>
|
|
<description>8 bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_STORED</name>
|
|
<description>9 bits. The 9th bit is stored in the FIFO (normal mode).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_MATCH</name>
|
|
<description>9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSCEN</name>
|
|
<description>Receiver Smartcard Parity Response Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver does not send a Smartcard parity error response.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver sends a Smartcard Parity response.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIRDAEN</name>
|
|
<description>Receiver IrDA Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver does not operate in IrDA mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver operates in IrDA mode. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RINVEN</name>
|
|
<description>Receiver Invert Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the RX pin signals (the RX idle state is high).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the RX pin signals (the RX idle state is low).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTRTEN</name>
|
|
<description>Transmitter Start Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not generate a start bit during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Generate a start bit during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPAREN</name>
|
|
<description>Transmitter Parity Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a parity bit during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a parity bit during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTPEN</name>
|
|
<description>Transmitter Stop Enable. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send stop bits during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send stop bits during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTPMD</name>
|
|
<description>Transmitter Stop Mode. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0P5_STOP</name>
|
|
<description>0.5 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_STOP</name>
|
|
<description>1 stop bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P5_STOP</name>
|
|
<description>1.5 stop bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP</name>
|
|
<description>2 stop bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPARMD</name>
|
|
<description>Transmitter Parity Mode. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Set (Parity = 1).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Clear (Parity = 0).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDATLN</name>
|
|
<description>Transmitter Data Length. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>5_BITS</name>
|
|
<description>5 bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BITS</name>
|
|
<description>6 bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BITS</name>
|
|
<description>7 bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BITS</name>
|
|
<description>8 bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_FIFO</name>
|
|
<description>9 bits. The 9th bit is taken from the FIFO data (normal mode).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_TBIT</name>
|
|
<description>9 bits. The 9th bit is set by the value of TBIT (fixed mode).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSCEN</name>
|
|
<description>Transmitter Smartcard Parity Response Enable. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The transmitter does not check for a Smartcard parity error response.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The transmitter checks for a Smartcard parity error response.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIRDAEN</name>
|
|
<description>Transmitter IrDA Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable IrDA transmit mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable IrDA transmit mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TINVEN</name>
|
|
<description>Transmitter Invert Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the TX pin signals (the TX idle state is high).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the TX pin signals (the TX idle state is low).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Module Mode Select</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00600000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>UART Debug Mode. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The UART module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the UART module to halt. Any active transmissions and receptions will complete first.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBMD</name>
|
|
<description>Loop Back Mode. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Loop back is disabled and the TX and RX signals are connected to the corresponding external pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RX_ONLY</name>
|
|
<description>Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TX_ONLY</name>
|
|
<description>Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DUPLEXMD</name>
|
|
<description>Duplex Mode. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL_DUPLEX</name>
|
|
<description>Full-duplex mode. The transmitter and receiver can operate simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF_DUPLEX</name>
|
|
<description>Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITSEN</name>
|
|
<description>Idle TX Tristate Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The TX pin is tristated when idle. If ISTCLK is cleared to 0 and the transmitter is configured in synchronous master mode, the UCLK pin will also be tristated when idle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLOWCN</name>
|
|
<description>Flow Control</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00020001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTS</name>
|
|
<description>RTS State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>RTS pin (before optional inversion) is driven low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>RTS pin (before optional inversion) is driven high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RX</name>
|
|
<description>RX Pin Status. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>RX pin (after optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>RX pin (after optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSINVEN</name>
|
|
<description>RTS Invert Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The UART does not invert the RTS signal before driving the pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The UART inverts the RTS signal driving the pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSTH</name>
|
|
<description>RTS Threshold Control. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_BYTE_FREE</name>
|
|
<description>RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>RTS Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>CTS State. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Indicates the CTS pin state (after optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Indicates the CTS pin state (after optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>TX State. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The TX pin (before optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The TX pin (before optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSINVEN</name>
|
|
<description>CTS Invert Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The UART does not invert CTS.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The UART inverts CTS.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTS Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The CTS pin state does not affect transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Transmissions will begin only if the CTS pin (after optional inversion) is low.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIRDAPW</name>
|
|
<description>Transmit IrDA Pulse Width. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1_16TH</name>
|
|
<description>The IrDA pulse width is 1/16th of a bit period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_8TH</name>
|
|
<description>The IrDA pulse width is 1/8th of a bit period.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_16TH</name>
|
|
<description>The IrDA pulse width is 3/16th of a bit period.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_4TH</name>
|
|
<description>The IrDA pulse width is 1/4th of a bit period.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRMERI</name>
|
|
<description>Receive Frame Error Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A frame error occurred. Write: Force a frame error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPARERI</name>
|
|
<description>Receive Parity Error Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROREI</name>
|
|
<description>Receive Overrun Error Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDREQI</name>
|
|
<description>Receive Data Request Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Fewer than RFTH FIFO slots are filled with data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>At least RFTH FIFO slots are filled with data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RERIEN</name>
|
|
<description>Receive Error Interrupt Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive error interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive error interrupt. A receive error interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDREQIEN</name>
|
|
<description>Receive Data Request Interrupt Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the read data request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATMD</name>
|
|
<description>Match Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Disable the match function.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCE</name>
|
|
<description>(MCE) Data whose last data bit equals RBIT is accepted and stored. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAME</name>
|
|
<description>(Frame) A framing error is asserted if the last received bit matches RBIT.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STORE</name>
|
|
<description>(Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RABDEN</name>
|
|
<description>Receiver Auto-Baud Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable receiver auto-baud.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable receiver auto-baud.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RBUSYF</name>
|
|
<description>Receiver Busy Flag. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The UART receiver is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The UART receiver is receiving data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RBIT</name>
|
|
<description>Last Receive Bit. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROSEN</name>
|
|
<description>Receiver One-Shot Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable one-shot receive mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable one-shot receive mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RINH</name>
|
|
<description>Receiver Inhibit. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The receiver operates normally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REN</name>
|
|
<description>Receiver Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receiver. The receiver can receive one data transaction only if ROSEN is set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receiver.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSCERI</name>
|
|
<description>Smartcard Parity Error Interrupt Flag. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDREQI</name>
|
|
<description>Transmit Data Request Interrupt Flag. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The transmitter is not requesting more FIFO data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The transmitter is requesting more FIFO data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTI</name>
|
|
<description>Transmit Complete Interrupt Flag. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTTH</name>
|
|
<description>Transmit Complete Threshold. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET_ON_TX</name>
|
|
<description>A transmit is completed (TCPTI = 1) at the end of each transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_ON_EMPTY</name>
|
|
<description>A transmit is completed (TCPTI = 1) only at the end of a transmission when no more data is available to transmit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TERIEN</name>
|
|
<description>Transmit Error Interrupt Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit error interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDREQIEN</name>
|
|
<description>Transmit Data Request Interrupt Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit data request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTIEN</name>
|
|
<description>Transmit Complete Interrupt Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit complete interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TBUSYF</name>
|
|
<description>Transmitter Busy Flag. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The UART transmitter is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The UART transmitter is active and transmitting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TBIT</name>
|
|
<description>Last Transmit Bit. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TINH</name>
|
|
<description>Transmit Inhibit. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The transmitter operates normally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Transmissions are inhibited. The transmitter will stall after any current transmission is complete.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transmitter Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPDELAY</name>
|
|
<description>Inter-Packet Delay</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPDELAY</name>
|
|
<description>Inter-Packet Delay. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUDRATE</name>
|
|
<description>Transmit and Receive Baud Rate</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBAUD</name>
|
|
<description>Receiver Baud Rate Control. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBAUD</name>
|
|
<description>Transmitter Baud Rate Control. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOCN</name>
|
|
<description>FIFO Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCNT</name>
|
|
<description>Receive FIFO Count. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFTH</name>
|
|
<description>Receive FIFO Threshold. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A read data request interrupt (RDREQI) is asserted when >= 1 FIFO slot is full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A read data request interrupt (RDREQI) is asserted when >= 2 FIFO slots are full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A read data request interrupt (RDREQI) is asserted when >= 4 FIFO slots are full.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFIFOFL</name>
|
|
<description>Receive FIFO Flush. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the contents of the receive FIFO and any data in the receive shift register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFERI</name>
|
|
<description>Receive FIFO Error Interrupt Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A receive FIFO error has not occurred since RFERI was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A receive FIFO error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRFULLF</name>
|
|
<description>Receive Shift Register Full . </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The receive data shift register is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The receive data shift register is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCNT</name>
|
|
<description>Transmit FIFO Count. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFTH</name>
|
|
<description>Transmit FIFO Threshold. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO slot is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO slots are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A transmit data request interrupt (TDREQI) is asserted when >= 4 FIFO slots are empty.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFIFOFL</name>
|
|
<description>Transmit FIFO Flush. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFERI</name>
|
|
<description>Transmit FIFO Error Interrupt Flag. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A transmit FIFO error has not occurred since TFERI was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A transmit FIFO error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSRFULLF</name>
|
|
<description>Transmit Shift Register Full Flag. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The transmit shift register is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The transmit shift register is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>FIFO Input/Output Data</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>FIFO Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USART_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART0_IRQn</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x030D030D</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTRTEN</name>
|
|
<description>Receiver Start Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect a start bit during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect a start bit during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPAREN</name>
|
|
<description>Receiver Parity Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect a parity bit during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect a parity bit during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTPEN</name>
|
|
<description>Receiver Stop Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect stop bits during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect stop bits during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTPMD</name>
|
|
<description>Receiver Stop Mode. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0P5_STOP</name>
|
|
<description>0.5 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_STOP</name>
|
|
<description>1 stop bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P5_STOP</name>
|
|
<description>1.5 stop bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP</name>
|
|
<description>2 stop bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPARMD</name>
|
|
<description>Receiver Parity Mode. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Set (Parity = 1).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Clear (Parity = 0).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDATLN</name>
|
|
<description>Receiver Data Length. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>5_BITS</name>
|
|
<description>5 bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BITS</name>
|
|
<description>6 bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BITS</name>
|
|
<description>7 bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BITS</name>
|
|
<description>8 bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_STORED</name>
|
|
<description>9 bits. The 9th bit is stored in the FIFO (normal mode).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_MATCH</name>
|
|
<description>9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSCEN</name>
|
|
<description>Receiver Smartcard Parity Response Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver does not send a Smartcard parity error response.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver sends a Smartcard parity response.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIRDAEN</name>
|
|
<description>Receiver IrDA Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver does not operate in IrDA mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver operates in IrDA mode. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RINVEN</name>
|
|
<description>Receiver Invert Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the RX pin signals (the RX idle state is high).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the RX pin signals (the RX idle state is low).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSYNCEN</name>
|
|
<description>Receiver Synchronous Mode Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver operates in asynchronous mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver operates in synchronous mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTRTEN</name>
|
|
<description>Transmitter Start Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not generate a start bit during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Generate a start bit during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPAREN</name>
|
|
<description>Transmitter Parity Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a parity bit during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a parity bit during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTPEN</name>
|
|
<description>Transmitter Stop Enable. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send stop bits during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send stop bits during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTPMD</name>
|
|
<description>Transmitter Stop Mode. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0P5_STOP</name>
|
|
<description>0.5 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_STOP</name>
|
|
<description>1 stop bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P5_STOP</name>
|
|
<description>1.5 stop bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP</name>
|
|
<description>2 stop bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPARMD</name>
|
|
<description>Transmitter Parity Mode. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Set (Parity = 1).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Clear (Parity = 0).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDATLN</name>
|
|
<description>Transmitter Data Length. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>5_BITS</name>
|
|
<description>5 bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BITS</name>
|
|
<description>6 bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BITS</name>
|
|
<description>7 bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BITS</name>
|
|
<description>8 bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_FIFO</name>
|
|
<description>9 bits. The 9th bit is taken from the FIFO data (normal mode).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_TBIT</name>
|
|
<description>9 bits. The 9th bit is set by the value of TBIT (fixed mode).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSCEN</name>
|
|
<description>Transmitter Smartcard Parity Response Enable. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The transmitter does not check for a Smartcard parity error response.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The transmitter checks for a Smartcard parity error response.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIRDAEN</name>
|
|
<description>Transmitter IrDA Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable IrDA transmit mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable IrDA transmit mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TINVEN</name>
|
|
<description>Transmitter Invert Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the TX pin signals (the TX idle state is high).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the TX pin signals (the TX idle state is low).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSYNCEN</name>
|
|
<description>Transmitter Synchronous Mode Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The transmitter operates in asynchronous mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The transmitter operates in synchronous mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Module Mode Select</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00600000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>USART Debug Mode. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The USART module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the USART module to halt. Any active transmissions and receptions will complete first.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBMD</name>
|
|
<description>Loop Back Mode. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Loop back is disabled and the TX and RX signals are connected to the corresponding external pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXONLY</name>
|
|
<description>Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXONLY</name>
|
|
<description>Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STPSTCLK</name>
|
|
<description>Stop State Clock Control. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>When the USART is a clock master, the clock is not generated during stop bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>When the USART is a clock master, the clock is generated during stop bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STRTSTCLK</name>
|
|
<description>Start State Clock Control. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>When the USART is a clock master, the clock is held idle during a start bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>When the USART is a clock master, the clock is generated during a start bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISTCLK</name>
|
|
<description>Idle Clock Control. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>When the USART is a clock master and CLKESEL is not equal to CLKIDLE, the clock is held idle between transmissions. When the USART is a clock master and CLKESEL equals CLKIDEL, the clock will still be generated between transmissions. When the USART is a clock slave, the USART will begin transmissions without waiting for the next clock edge.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>When the USART is a clock master, the clock is generated between transmissions or receptions. When the USART is a clock slave, the USART will wait until the next clock edge before transmitting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DUPLEXMD</name>
|
|
<description>Duplex Mode. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL_DUPLEX</name>
|
|
<description>Full-duplex mode. The transmitter and receiver can operate simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF_DUPLEX</name>
|
|
<description>Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKIDLE</name>
|
|
<description>Clock Idle State. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE_LOW</name>
|
|
<description>The synchronous clock is low when idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLE_HIGH</name>
|
|
<description>The synchronous clock is high when idle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKESEL</name>
|
|
<description>Clock Edge Select. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>The clock falls in the middle of each bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>The clock rises in the middle of each bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITSEN</name>
|
|
<description>Idle TX/UCLK Tristate Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The TX pin is tristated when idle. If ISTCLK is cleared to 0 and the transmitter is configured in synchronous master mode, the UCLK pin will also be tristated when idle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPMD</name>
|
|
<description>Operational Mode. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLAVE</name>
|
|
<description>The USART operates as a slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER</name>
|
|
<description>The USART operates as a master.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLOWCN</name>
|
|
<description>Flow Control</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00020001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTS</name>
|
|
<description>RTS State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>RTS pin (before optional inversion) is driven low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>RTS pin (before optional inversion) is driven high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RX</name>
|
|
<description>RX Pin Status. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>RX pin (after optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>RX pin (after optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSINVEN</name>
|
|
<description>RTS Invert Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The USART does not invert the RTS signal before driving the pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The USART inverts the RTS signal driving the pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSTH</name>
|
|
<description>RTS Threshold Control. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_BYTE_FREE</name>
|
|
<description>RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>RTS Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>CTS State. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Indicates the CTS pin state (after optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Indicates the CTS pin state (after optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>TX State. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The TX pin (before optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The TX pin (before optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCLK</name>
|
|
<description>UCLK State. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The UCLK pin is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The UCLK pin is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSINVEN</name>
|
|
<description>CTS Invert Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The USART does not invert CTS.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The USART inverts CTS.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTS Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The CTS pin state does not affect transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Transmissions will begin only if the CTS pin (after optional inversion) is low.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIRDAPW</name>
|
|
<description>Transmit IrDA Pulse Width. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1_16TH</name>
|
|
<description>The IrDA pulse width is 1/16th of a bit period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_8TH</name>
|
|
<description>The IrDA pulse width is 1/8th of a bit period.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_16TH</name>
|
|
<description>The IrDA pulse width is 3/16th of a bit period.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_4TH</name>
|
|
<description>The IrDA pulse width is 1/4th of a bit period.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRMERI</name>
|
|
<description>Receive Frame Error Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A frame error occurred. Write: Force a frame error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPARERI</name>
|
|
<description>Receive Parity Error Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROREI</name>
|
|
<description>Receive Overrun Error Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDREQI</name>
|
|
<description>Receive Data Request Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Fewer than RFTH FIFO slots are filled with data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>At least RFTH FIFO slots are filled with data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RERIEN</name>
|
|
<description>Receive Error Interrupt Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive error interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive error interrupt. A receive error interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDREQIEN</name>
|
|
<description>Receive Data Request Interrupt Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the read data request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATMD</name>
|
|
<description>Match Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Disable the match function.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCE</name>
|
|
<description>(MCE) Data whose last data bit equals RBIT is accepted and stored. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAME</name>
|
|
<description>(Frame) A framing error is asserted if the last received bit matches RBIT.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STORE</name>
|
|
<description>(Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RABDEN</name>
|
|
<description>Receiver Auto-Baud Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable receiver auto-baud.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable receiver auto-baud.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RBUSYF</name>
|
|
<description>Receiver Busy Flag. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The USART receiver is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The USART receiver is receiving data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RBIT</name>
|
|
<description>Last Receive Bit. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROSEN</name>
|
|
<description>Receiver One-Shot Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable one-shot receive mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable one-shot receive mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RINH</name>
|
|
<description>Receiver Inhibit. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The receiver operates normally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REN</name>
|
|
<description>Receiver Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receiver. The receiver can receive one data transaction only if ROSEN is set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receiver.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSCERI</name>
|
|
<description>Smartcard Parity Error Interrupt Flag. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TUREI</name>
|
|
<description>Transmit Underrun Error Interrupt Flag. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A transmitter underrun has not occurred since TUREI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A transmitter underrun occurred. Write: Force a transmitter underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDREQI</name>
|
|
<description>Transmit Data Request Interrupt Flag. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The transmitter is not requesting more FIFO data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The transmitter is requesting more FIFO data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTI</name>
|
|
<description>Transmit Complete Interrupt Flag. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTTH</name>
|
|
<description>Transmit Complete Threshold. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET_ON_TX</name>
|
|
<description>A transmit is completed (TCPTI = 1) at the end of each transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_ON_EMPTY</name>
|
|
<description>A transmit is completed (TCPTI = 1) only at the end of a transmission when no more data is available to transmit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TERIEN</name>
|
|
<description>Transmit Error Interrupt Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit error interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDREQIEN</name>
|
|
<description>Transmit Data Request Interrupt Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit data request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTIEN</name>
|
|
<description>Transmit Complete Interrupt Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit complete interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TBUSYF</name>
|
|
<description>Transmitter Busy Flag. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The USART transmitter is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The USART transmitter is active and transmitting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TBIT</name>
|
|
<description>Last Transmit Bit. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TINH</name>
|
|
<description>Transmit Inhibit. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The transmitter operates normally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Transmissions are inhibited. The transmitter will stall after any current transmission is complete.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transmitter Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPDELAY</name>
|
|
<description>Inter-Packet Delay</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPDELAY</name>
|
|
<description>Inter-Packet Delay. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUDRATE</name>
|
|
<description>Transmit and Receive Baud Rate</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBAUD</name>
|
|
<description>Receiver Baud Rate Control. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBAUD</name>
|
|
<description>Transmitter Baud Rate Control. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOCN</name>
|
|
<description>FIFO Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCNT</name>
|
|
<description>Receive FIFO Count. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFTH</name>
|
|
<description>Receive FIFO Threshold. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A DMA request or read data request interrupt (RDREQI) is asserted when >= 1 FIFO slot is full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A DMA request or read data request interrupt (RDREQI) is asserted when >= 2 FIFO slots are full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A DMA request or read data request interrupt (RDREQ) is asserted when >= 4 FIFO slots are full.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMAEN</name>
|
|
<description>Receiver DMA Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable receive FIFO DMA requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable receive FIFO DMA requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFIFOFL</name>
|
|
<description>Receive FIFO Flush. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the contents of the receive FIFO and any data in the receive shift register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFERI</name>
|
|
<description>Receive FIFO Error Interrupt Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A receive FIFO error has not occurred since RFERI was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A receive FIFO error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRFULLF</name>
|
|
<description>Receive Shift Register Full Flag. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The receive data shift register is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The receive data shift register is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCNT</name>
|
|
<description>Transmit FIFO Count. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFTH</name>
|
|
<description>Transmit FIFO Threshold. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO slot is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO slots are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A DMA request or transmit data request interrupt (TDREQ) is asserted when >= 4 FIFO slots are empty.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAEN</name>
|
|
<description>Transmitter DMA Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable transmit FIFO DMA requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable transmit FIFO DMA requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFIFOFL</name>
|
|
<description>Transmit FIFO Flush. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFERI</name>
|
|
<description>Transmit FIFO Error Interrupt Flag. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A transmit FIFO error has not occurred since TFERI was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A transmit FIFO error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSRFULLF</name>
|
|
<description>Transmit Shift Register Full Flag. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The transmit shift register is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The transmit shift register is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>FIFO Input/Output Data</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>FIFO Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USART_1</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART1_IRQn</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x030D030D</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTRTEN</name>
|
|
<description>Receiver Start Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect a start bit during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect a start bit during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPAREN</name>
|
|
<description>Receiver Parity Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect a parity bit during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect a parity bit during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTPEN</name>
|
|
<description>Receiver Stop Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not expect stop bits during receptions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Expect stop bits during receptions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTPMD</name>
|
|
<description>Receiver Stop Mode. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0P5_STOP</name>
|
|
<description>0.5 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_STOP</name>
|
|
<description>1 stop bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P5_STOP</name>
|
|
<description>1.5 stop bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP</name>
|
|
<description>2 stop bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPARMD</name>
|
|
<description>Receiver Parity Mode. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Set (Parity = 1).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Clear (Parity = 0).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDATLN</name>
|
|
<description>Receiver Data Length. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>5_BITS</name>
|
|
<description>5 bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BITS</name>
|
|
<description>6 bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BITS</name>
|
|
<description>7 bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BITS</name>
|
|
<description>8 bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_STORED</name>
|
|
<description>9 bits. The 9th bit is stored in the FIFO (normal mode).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_MATCH</name>
|
|
<description>9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSCEN</name>
|
|
<description>Receiver Smartcard Parity Response Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver does not send a Smartcard parity error response.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver sends a Smartcard parity response.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIRDAEN</name>
|
|
<description>Receiver IrDA Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver does not operate in IrDA mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver operates in IrDA mode. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RINVEN</name>
|
|
<description>Receiver Invert Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the RX pin signals (the RX idle state is high).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the RX pin signals (the RX idle state is low).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSYNCEN</name>
|
|
<description>Receiver Synchronous Mode Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver operates in asynchronous mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver operates in synchronous mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTRTEN</name>
|
|
<description>Transmitter Start Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not generate a start bit during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Generate a start bit during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPAREN</name>
|
|
<description>Transmitter Parity Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send a parity bit during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send a parity bit during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTPEN</name>
|
|
<description>Transmitter Stop Enable. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not send stop bits during transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Send stop bits during transmissions.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTPMD</name>
|
|
<description>Transmitter Stop Mode. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0P5_STOP</name>
|
|
<description>0.5 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_STOP</name>
|
|
<description>1 stop bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P5_STOP</name>
|
|
<description>1.5 stop bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP</name>
|
|
<description>2 stop bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPARMD</name>
|
|
<description>Transmitter Parity Mode. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd Parity.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even Parity.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MARK</name>
|
|
<description>Set (Parity = 1).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPACE</name>
|
|
<description>Clear (Parity = 0).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDATLN</name>
|
|
<description>Transmitter Data Length. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>5_BITS</name>
|
|
<description>5 bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BITS</name>
|
|
<description>6 bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BITS</name>
|
|
<description>7 bits.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BITS</name>
|
|
<description>8 bits.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_FIFO</name>
|
|
<description>9 bits. The 9th bit is taken from the FIFO data (normal mode).</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_TBIT</name>
|
|
<description>9 bits. The 9th bit is set by the value of TBIT (fixed mode).</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSCEN</name>
|
|
<description>Transmitter Smartcard Parity Response Enable. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The transmitter does not check for a Smartcard parity error response.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The transmitter checks for a Smartcard parity error response.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIRDAEN</name>
|
|
<description>Transmitter IrDA Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable IrDA transmit mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable IrDA transmit mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TINVEN</name>
|
|
<description>Transmitter Invert Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not invert the TX pin signals (the TX idle state is high).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Invert the TX pin signals (the TX idle state is low).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSYNCEN</name>
|
|
<description>Transmitter Synchronous Mode Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The transmitter operates in asynchronous mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The transmitter operates in synchronous mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Module Mode Select</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00600000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>USART Debug Mode. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The USART module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the USART module to halt. Any active transmissions and receptions will complete first.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBMD</name>
|
|
<description>Loop Back Mode. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Loop back is disabled and the TX and RX signals are connected to the corresponding external pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXONLY</name>
|
|
<description>Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXONLY</name>
|
|
<description>Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STPSTCLK</name>
|
|
<description>Stop State Clock Control. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>When the USART is a clock master, the clock is not generated during stop bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>When the USART is a clock master, the clock is generated during stop bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STRTSTCLK</name>
|
|
<description>Start State Clock Control. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>When the USART is a clock master, the clock is held idle during a start bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>When the USART is a clock master, the clock is generated during a start bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISTCLK</name>
|
|
<description>Idle Clock Control. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>When the USART is a clock master and CLKESEL is not equal to CLKIDLE, the clock is held idle between transmissions. When the USART is a clock master and CLKESEL equals CLKIDEL, the clock will still be generated between transmissions. When the USART is a clock slave, the USART will begin transmissions without waiting for the next clock edge.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>When the USART is a clock master, the clock is generated between transmissions or receptions. When the USART is a clock slave, the USART will wait until the next clock edge before transmitting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DUPLEXMD</name>
|
|
<description>Duplex Mode. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL_DUPLEX</name>
|
|
<description>Full-duplex mode. The transmitter and receiver can operate simultaneously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF_DUPLEX</name>
|
|
<description>Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKIDLE</name>
|
|
<description>Clock Idle State. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE_LOW</name>
|
|
<description>The synchronous clock is low when idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLE_HIGH</name>
|
|
<description>The synchronous clock is high when idle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKESEL</name>
|
|
<description>Clock Edge Select. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>The clock falls in the middle of each bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>The clock rises in the middle of each bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITSEN</name>
|
|
<description>Idle TX/UCLK Tristate Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The TX pin is tristated when idle. If ISTCLK is cleared to 0 and the transmitter is configured in synchronous master mode, the UCLK pin will also be tristated when idle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPMD</name>
|
|
<description>Operational Mode. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLAVE</name>
|
|
<description>The USART operates as a slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER</name>
|
|
<description>The USART operates as a master.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLOWCN</name>
|
|
<description>Flow Control</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00020001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTS</name>
|
|
<description>RTS State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>RTS pin (before optional inversion) is driven low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>RTS pin (before optional inversion) is driven high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RX</name>
|
|
<description>RX Pin Status. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>RX pin (after optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>RX pin (after optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSINVEN</name>
|
|
<description>RTS Invert Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The USART does not invert the RTS signal before driving the pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The USART inverts the RTS signal driving the pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSTH</name>
|
|
<description>RTS Threshold Control. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL</name>
|
|
<description>RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_BYTE_FREE</name>
|
|
<description>RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>RTS Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>CTS State. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Indicates the CTS pin state (after optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Indicates the CTS pin state (after optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>TX State. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The TX pin (before optional inversion) is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The TX pin (before optional inversion) is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UCLK</name>
|
|
<description>UCLK State. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The UCLK pin is low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The UCLK pin is high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSINVEN</name>
|
|
<description>CTS Invert Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The USART does not invert CTS.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The USART inverts CTS.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTS Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The CTS pin state does not affect transmissions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Transmissions will begin only if the CTS pin (after optional inversion) is low.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIRDAPW</name>
|
|
<description>Transmit IrDA Pulse Width. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1_16TH</name>
|
|
<description>The IrDA pulse width is 1/16th of a bit period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_8TH</name>
|
|
<description>The IrDA pulse width is 1/8th of a bit period.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_16TH</name>
|
|
<description>The IrDA pulse width is 3/16th of a bit period.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_4TH</name>
|
|
<description>The IrDA pulse width is 1/4th of a bit period.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFRMERI</name>
|
|
<description>Receive Frame Error Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A frame error occurred. Write: Force a frame error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RPARERI</name>
|
|
<description>Receive Parity Error Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROREI</name>
|
|
<description>Receive Overrun Error Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDREQI</name>
|
|
<description>Receive Data Request Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Fewer than RFTH FIFO slots are filled with data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>At least RFTH FIFO slots are filled with data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RERIEN</name>
|
|
<description>Receive Error Interrupt Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receive error interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receive error interrupt. A receive error interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDREQIEN</name>
|
|
<description>Receive Data Request Interrupt Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the read data request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATMD</name>
|
|
<description>Match Mode. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Disable the match function.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCE</name>
|
|
<description>(MCE) Data whose last data bit equals RBIT is accepted and stored. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAME</name>
|
|
<description>(Frame) A framing error is asserted if the last received bit matches RBIT.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STORE</name>
|
|
<description>(Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RABDEN</name>
|
|
<description>Receiver Auto-Baud Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable receiver auto-baud.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable receiver auto-baud.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RBUSYF</name>
|
|
<description>Receiver Busy Flag. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The USART receiver is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The USART receiver is receiving data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RBIT</name>
|
|
<description>Last Receive Bit. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROSEN</name>
|
|
<description>Receiver One-Shot Enable. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable one-shot receive mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable one-shot receive mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RINH</name>
|
|
<description>Receiver Inhibit. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The receiver operates normally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REN</name>
|
|
<description>Receiver Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the receiver. The receiver can receive one data transaction only if ROSEN is set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the receiver.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSCERI</name>
|
|
<description>Smartcard Parity Error Interrupt Flag. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TUREI</name>
|
|
<description>Transmit Underrun Error Interrupt Flag. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A transmitter underrun has not occurred since TUREI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A transmitter underrun occurred. Write: Force a transmitter underrun interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDREQI</name>
|
|
<description>Transmit Data Request Interrupt Flag. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The transmitter is not requesting more FIFO data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The transmitter is requesting more FIFO data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTI</name>
|
|
<description>Transmit Complete Interrupt Flag. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTTH</name>
|
|
<description>Transmit Complete Threshold. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET_ON_TX</name>
|
|
<description>A transmit is completed (TCPTI = 1) at the end of each transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_ON_EMPTY</name>
|
|
<description>A transmit is completed (TCPTI = 1) only at the end of a transmission when no more data is available to transmit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TERIEN</name>
|
|
<description>Transmit Error Interrupt Enable. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit error interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDREQIEN</name>
|
|
<description>Transmit Data Request Interrupt Enable. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit data request interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCPTIEN</name>
|
|
<description>Transmit Complete Interrupt Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmit complete interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TBUSYF</name>
|
|
<description>Transmitter Busy Flag. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The USART transmitter is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The USART transmitter is active and transmitting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TBIT</name>
|
|
<description>Last Transmit Bit. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TINH</name>
|
|
<description>Transmit Inhibit. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>The transmitter operates normally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Transmissions are inhibited. The transmitter will stall after any current transmission is complete.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transmitter Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. </description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPDELAY</name>
|
|
<description>Inter-Packet Delay</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPDELAY</name>
|
|
<description>Inter-Packet Delay. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUDRATE</name>
|
|
<description>Transmit and Receive Baud Rate</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBAUD</name>
|
|
<description>Receiver Baud Rate Control. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBAUD</name>
|
|
<description>Transmitter Baud Rate Control. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOCN</name>
|
|
<description>FIFO Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCNT</name>
|
|
<description>Receive FIFO Count. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFTH</name>
|
|
<description>Receive FIFO Threshold. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A DMA request or read data request interrupt (RDREQI) is asserted when >= 1 FIFO slot is full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A DMA request or read data request interrupt (RDREQI) is asserted when >= 2 FIFO slots are full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A DMA request or read data request interrupt (RDREQ) is asserted when >= 4 FIFO slots are full.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMAEN</name>
|
|
<description>Receiver DMA Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable receive FIFO DMA requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable receive FIFO DMA requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFIFOFL</name>
|
|
<description>Receive FIFO Flush. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the contents of the receive FIFO and any data in the receive shift register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFERI</name>
|
|
<description>Receive FIFO Error Interrupt Flag. </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A receive FIFO error has not occurred since RFERI was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A receive FIFO error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRFULLF</name>
|
|
<description>Receive Shift Register Full Flag. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The receive data shift register is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The receive data shift register is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCNT</name>
|
|
<description>Transmit FIFO Count. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFTH</name>
|
|
<description>Transmit FIFO Threshold. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO slot is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>A DMA request or transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO slots are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>A DMA request or transmit data request interrupt (TDREQ) is asserted when >= 4 FIFO slots are empty.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAEN</name>
|
|
<description>Transmitter DMA Enable. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable transmit FIFO DMA requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable transmit FIFO DMA requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFIFOFL</name>
|
|
<description>Transmit FIFO Flush. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFERI</name>
|
|
<description>Transmit FIFO Error Interrupt Flag. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A transmit FIFO error has not occurred since TFERI was last cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A transmit FIFO error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSRFULLF</name>
|
|
<description>Transmit Shift Register Full Flag. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The transmit shift register is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The transmit shift register is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>FIFO Input/Output Data</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>FIFO Data. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>USB_0</groupName>
|
|
<baseAddress>0x40018000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB0_IRQn</name>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>FADDR</name>
|
|
<description>Function Address</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FADDR</name>
|
|
<description>Function Address. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FADDRUPD</name>
|
|
<description>Function Address Update. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The last address written to FADDR is in effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The last address written to FADDR is not yet in effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POWER</name>
|
|
<description>Power Control</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SUSDEN</name>
|
|
<description>Suspend Detection Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable suspend detection. The USB module will ignore suspend signaling on the bus.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable suspend detection. The USB module will enter suspend mode if it detects suspend signalling on the bus.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUSMDF</name>
|
|
<description>Suspend Mode Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The USB module is not in suspend mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The USB module is in suspend mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESUME</name>
|
|
<description>Force Resume. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GENERATE</name>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTDETF</name>
|
|
<description>Reset Detect Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Reset signaling is not present on the bus.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Reset signaling detected on the bus.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBINH</name>
|
|
<description>USB Inhibit. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Enable the USB module.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>USB module inhibited. All USB traffic is ignored.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DITHEN</name>
|
|
<description>USB Dither Enable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable automatic USB dithering.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable automatic USB dithering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISOUPDMD</name>
|
|
<description>ISO Update Mode. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SEND_ON_IN</name>
|
|
<description>When software writes IPRDYI = 1, USB will send the packet when the next IN token is received.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEND_ON_SOF</name>
|
|
<description>When software writes IPRDYI = 1, USB will wait for a SOF token before sending the packet. If an IN token is received before a SOF token, USB will send a zero-length data packet.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOINT</name>
|
|
<description>IN/OUT Endpoint Interrupt Flags</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EP0I</name>
|
|
<description>Endpoint 0 Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: Endpoint 0 interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Endpoint 0 interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN1I</name>
|
|
<description>IN Endpoint 1 Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: IN Endpoint 1 interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: IN Endpoint 1 interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN2I</name>
|
|
<description>IN Endpoint 2 Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: IN Endpoint 2 interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: IN Endpoint 2 interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN3I</name>
|
|
<description>IN Endpoint 3 Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: IN Endpoint 3 interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: IN Endpoint 3 interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN4I</name>
|
|
<description>IN Endpoint 4 Interrupt Flag. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: IN Endpoint 4 interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: IN Endpoint 4 interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT1I</name>
|
|
<description>OUT Endpoint 1 Interrupt Flag. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: OUT Endpoint 1 interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: OUT Endpoint 1 interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT2I</name>
|
|
<description>OUT Endpoint 2 Interrupt Flag. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: OUT Endpoint 2 interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: OUT Endpoint 2 interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT3I</name>
|
|
<description>OUT Endpoint 3 Interrupt Flag. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: OUT Endpoint 3 interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: OUT Endpoint 3 interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT4I</name>
|
|
<description>OUT Endpoint 4 Interrupt Flag. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: OUT Endpoint 4 interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: OUT Endpoint 4 interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMINT</name>
|
|
<description>Common Interrupt Flags</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SUSI</name>
|
|
<description>Suspend Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: Suspend interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Suspend interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESI</name>
|
|
<description>Resume Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: Resume interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Resume interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTI</name>
|
|
<description>Reset Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: Reset interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: Reset interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOFI</name>
|
|
<description>Start of Frame Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: SOF interrupt has not occurred. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: SOF interrupt occurred. Write: Clear the interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOINTE</name>
|
|
<description>IN/OUT Endpoint Interrupt Control</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x001E001F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EP0IEN</name>
|
|
<description>Endpoint 0 Interrupt Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Endpoint 0 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Endpoint 0 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN1IEN</name>
|
|
<description>IN Endpoint 1 Interrupt Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the IN Endpoint 1 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the IN Endpoint 1 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN2IEN</name>
|
|
<description>IN Endpoint 2 Interrupt Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the IN Endpoint 2 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the IN Endpoint 2 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN3IEN</name>
|
|
<description>IN Endpoint 3 Interrupt Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the IN Endpoint 3 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the IN Endpoint 3 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IN4IEN</name>
|
|
<description>IN Endpoint 4 Interrupt Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the IN Endpoint 4 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the IN Endpoint 4 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT1IEN</name>
|
|
<description>OUT Endpoint 1 Interrupt Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the OUT Endpoint 1 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the OUT Endpoint 1 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT2IEN</name>
|
|
<description>OUT Endpoint 2 Interrupt Enable. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the OUT Endpoint 2 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the OUT Endpoint 2 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT3IEN</name>
|
|
<description>OUT Endpoint 3 Interrupt Enable. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the OUT Endpoint 3 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the OUT Endpoint 3 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUT4IEN</name>
|
|
<description>OUT Endpoint 4 Interrupt Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the OUT Endpoint 4 interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the OUT Endpoint 4 interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMINTEPE</name>
|
|
<description>Common Interrupt and Endpoint Control</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x001F0006</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SUSIEN</name>
|
|
<description>Suspend Interrupt Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Suspend interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Suspend interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESIEN</name>
|
|
<description>Resume Interrupt Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Resume interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Resume interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTIEN</name>
|
|
<description>Reset Interrupt Enable. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Reset interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Reset interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOFIEN</name>
|
|
<description>Start of Frame Interrupt Enable. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the SOF interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the SOF interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EP0EN</name>
|
|
<description>Endpoint 0 Enable. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Endpoint 0 (no NACK, ACK, or STALL on the USB network).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Endpoint 0 (normal).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EP1EN</name>
|
|
<description>Endpoint 1 Enable. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Endpoint 1 (no NACK, ACK, or STALL on the USB network).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Endpoint 1 (normal).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EP2EN</name>
|
|
<description>Endpoint 2 Enable. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Endpoint 2 (no NACK, ACK, or STALL on the USB network).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Endpoint 2 (normal).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EP3EN</name>
|
|
<description>Endpoint 3 Enable. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Endpoint 3 (no NACK, ACK, or STALL on the USB network).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Endpoint 3 (normal).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EP4EN</name>
|
|
<description>Endpoint 4 Enable. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable Endpoint 4 (no NACK, ACK, or STALL on the USB network).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable Endpoint 4 (normal).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCONTROL</name>
|
|
<description>Clock Recovery Control</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OLEN</name>
|
|
<description>Oscillator Open-Loop Mode Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not freeze the USB oscillator output frequency (closed loop mode).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Freeze the USB oscillator output frequency (open loop mode).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSCRMD</name>
|
|
<description>Low Speed Clock Recovery Mode. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL_SPEED</name>
|
|
<description>Full Speed Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_SPEED</name>
|
|
<description>Low Speed Mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRSSEN</name>
|
|
<description>Clock Recovery Single Step Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Normal calibration mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Single step mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CREN</name>
|
|
<description>Clock Recovery Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable clock recovery.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable clock recovery.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRAME</name>
|
|
<description>Frame Number</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAMENUM</name>
|
|
<description>Frame Number. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCONTROL</name>
|
|
<description>Transceiver Control</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DN</name>
|
|
<description>D- Signal State. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOGIC_0</name>
|
|
<description>D- signal currently at logic 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOGIC_1</name>
|
|
<description>D- signal currently at logic 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DP</name>
|
|
<description>D+ Signal State. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOGIC_0</name>
|
|
<description>D+ signal currently at logic 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOGIC_1</name>
|
|
<description>D+ signal currently at logic 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFREC</name>
|
|
<description>Differential Receiver State. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIFF_0</name>
|
|
<description>Differential 0 signalling is present on the bus.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIFF_1</name>
|
|
<description>Differential 1 signalling is present on the bus.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHYTST</name>
|
|
<description>Physical Layer Test. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>Mode 0: Normal (non-test mode) (D+ = X, D- = X).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>Mode 1: Differential 1 Forced (D+ = 1, D- = 0).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>Mode 2: Differential 0 Forced (D+ = 0, D- = 1).</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE3</name>
|
|
<description>Mode 3: Single-Ended 0 Forced (D+ = 0, D- = 0).</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSEL</name>
|
|
<description>USB Speed Select. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_SPEED</name>
|
|
<description>USB operates as a Low Speed device. If enabled, the internal pull-up resistor appears on the D- line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL_SPEED</name>
|
|
<description>USB operates as a Full Speed device. If enabled, the internal pull-up resistor appears on the D+ line.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHYEN</name>
|
|
<description>Physical Layer Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the USB physical layer Transceiver (suspend).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the USB physical layer Transceiver (normal).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUEN</name>
|
|
<description>Internal Pull-up Resistor Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the internal pull-up resistor (device effectively detached from the USB network).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the internal pull-up resistor when VBUS is present (device is attached to the USB network).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKSEL</name>
|
|
<description>Module Clock Select</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>USB Clock Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USBNOSC</name>
|
|
<description>Select the USB Oscillator as the USB clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLLNOSC</name>
|
|
<description>Select the PLL output as the USB clock.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTOSCN</name>
|
|
<description>Select the External Oscillator output (EXTOSCn) as the USB clock.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>USB Clock Divider. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>The USB module uses the selected input clock divided by 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>The USB module uses the selected input clock divided by 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>The USB module uses the selected input clock divided by 4.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>The USB module uses the selected input clock divided by 8.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>USB Reset. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Do not reset the USB module.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Reset the USB module.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSCCONTROL</name>
|
|
<description>Oscillator Control</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SUSPEND</name>
|
|
<description>USB Oscillator Suspend. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The USB oscillator is not suspended.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Suspend the USB oscillator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCEN</name>
|
|
<description>USB Oscillator Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the USB oscillator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the USB oscillator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFADJUST</name>
|
|
<description>Oscillator Additional Frequency Adjust</description>
|
|
<addressOffset>0x320</addressOffset>
|
|
<resetValue>0x00000020</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FINEFADJ</name>
|
|
<description>USB Oscillator Fine Output Frequency Adjust. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DITHEN</name>
|
|
<description>USB Oscillator Dithering Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable USB oscillator dithering.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable USB oscillator dithering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FADJUST</name>
|
|
<description>Oscillator Frequency Adjust</description>
|
|
<addressOffset>0x330</addressOffset>
|
|
<resetValue>0x00000040</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FADJ</name>
|
|
<description>Oscillator Output Frequency Adjust. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAFIFO</name>
|
|
<description>DMA Data FIFO Access</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DMAFIFO</name>
|
|
<description>DMA Data FIFO Access. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACONTROL</name>
|
|
<description>DMA Control</description>
|
|
<addressOffset>0x410</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>USB DMA Debug Mode. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The USB module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will prevent the USB DMA buffer from transferring data to and from the USB FIFOs when the core is halted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TERRF</name>
|
|
<description>Timeout Error Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A timeout error has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A timeout error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBUSYF</name>
|
|
<description>USB DMA Busy Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The DMA buffer is not busy.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The DMA buffer is busy reading or writing an 8-word packet.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFIFOFL</name>
|
|
<description>USB DMA Buffer Flush Control. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the USB DMA buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP0CONTROL</name>
|
|
<description>Endpoint 0 Control</description>
|
|
<addressOffset>0x810</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPRDYI</name>
|
|
<description>OUT Packet Ready Interrupt Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A packet is not available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A packet is available.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IPRDYI</name>
|
|
<description>IN Packet Ready Indicator. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A packet is not ready for transmission to host.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A packet is ready for transmission to host.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STSTLI</name>
|
|
<description>Sent Stall Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A STALL handshake has not been sent or is cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: STALL handshake sent. Write: No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEND</name>
|
|
<description>Data End. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The current packet is not the last packet of the transfer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The current packet is the last packet of the transfer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUENDI</name>
|
|
<description>Setup End Interrupt Flag. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The current packet is not the last packet of setup.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The current packet is the last packet of setup.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDSTL</name>
|
|
<description>Send Stall. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The STALL handshake has been transmitted or not triggered.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Initiate a STALL condition.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPRDYIS</name>
|
|
<description>Serviced Out Packet Ready Interrupt Flag. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The out packet has not been processed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The out packet has been received and accepted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUENDIS</name>
|
|
<description>Serviced Setup End Interrupt Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Setup end has not been serviced.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Setup end has been serviced.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP0COUNT</name>
|
|
<description>Endpoint 0 Data Count</description>
|
|
<addressOffset>0x820</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Endpoint 0 OUT Data Count. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP0FIFO</name>
|
|
<description>Endpoint 0 Data FIFO Access</description>
|
|
<addressOffset>0x830</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO</name>
|
|
<description>Endpoint 0 Data FIFO. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_2-->
|
|
<register>
|
|
<name>EPMPSIZE_1</name>
|
|
<description>Endpoint Maximum Packet Size</description>
|
|
<addressOffset>0x880</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMAXP</name>
|
|
<description>IN Maximum Packet Size. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OMAXP</name>
|
|
<description>OUT Maximum Packet Size. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPCONTROL_1</name>
|
|
<description>Endpoint Control</description>
|
|
<addressOffset>0x890</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPRDYI</name>
|
|
<description>IN Packet Ready Indicator. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The packet has been sent or there is an open FIFO slot.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A packet is loaded in the FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFIFONEF</name>
|
|
<description>IN FIFO Not Empty Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The IN Endpoint FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The IN Endpoint FIFO contains one or more packets.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IURF</name>
|
|
<description>IN FIFO Underrun Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Underrun has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Underrun occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFIFOFL</name>
|
|
<description>IN FIFO Flush. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the IN FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISDSTL</name>
|
|
<description>IN Send Stall. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Stop sending a stall.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Generate a stall.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISTSTLI</name>
|
|
<description>IN Sent Stall Interrupt Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt. </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A stall condition has been sent since this bit was last cleared. Write: No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICLRDT</name>
|
|
<description>IN Clear Data Toggle. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_RESET</name>
|
|
<description>Do not reset the IN data toggle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset the IN data toggle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLITEN</name>
|
|
<description>FIFO Split Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not split the endpoint FIFO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Split the endpoint FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FDTEN</name>
|
|
<description>Force Data Toggle Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The endpoint data toggle switches only when an ACK is received following a data packet transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The endpoint data toggle is forced to switch after every data packet is transmitted, regardless of ACK reception.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDMAEN</name>
|
|
<description>IN Endpoint DMA Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the DMA request for the IN endpoint.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the DMA request for the IN endpoint.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRSEL</name>
|
|
<description>Endpoint Direction Select. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT</name>
|
|
<description>Select the endpoint direction as OUT.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IN</name>
|
|
<description>Select the endpoint direction as IN.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IISOEN</name>
|
|
<description>IN Isochronous Transfer Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BULK_INT</name>
|
|
<description>Configure the endpoint for Bulk/Interrupt transfers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Configure the endpoint for Isochronous transfers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSETEN</name>
|
|
<description>IN Endpoint IPRDYI Automatic Set Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The IPRDYI bit is not automatically set by hardware.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The IPRDYI bit is automatically set by hardware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPRDYI</name>
|
|
<description>OUT Packet Ready. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A data packet is not available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A data packet is available.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFIFOFF</name>
|
|
<description>OUT FIFO Full. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The OUT endpoint FIFO is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The OUT endpoint FIFO is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OORF</name>
|
|
<description>OUT FIFO Overrun Flag. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>No data overrun.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A data packet was lost because of a full FIFO since this flag was last cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODERRF</name>
|
|
<description>OUT Data Error Flag. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A CRC or bit-stuff error has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A CRC or bit-stuff error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFIFOFL</name>
|
|
<description>OUT FIFO Flush. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the OUT FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSDSTL</name>
|
|
<description>OUT Send Stall. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop sending a stall.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEND</name>
|
|
<description>Generate a stall.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSTSTLI</name>
|
|
<description>OUT Sent Stall Interrupt Flag. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A stall condition has been sent since this bit was last cleared. Write: No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCLRDT</name>
|
|
<description>OUT Clear Data Toggle. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_RESET</name>
|
|
<description>Do not reset the OUT data toggle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset the OUT data toggle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODMAMD</name>
|
|
<description>OUT Endpoint DMA Mode. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTO_DMA</name>
|
|
<description>Automatic DMA service is requested on the last packet of the transfer until less than four bytes remain in the packet. At this time, an interrupt is generated. The firmware must read or write the last few bytes of the packet, if any remain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_DMA</name>
|
|
<description>No DMA service is requested on the last packet of the transfer. When the DMA recognizes the last packet, an interrupt is generated. The firmware must handle the entirety of the last packet.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODMAEN</name>
|
|
<description>OUT Endpoint DMA Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the DMA request for the OUT endpoint.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the DMA request for the OUT endpoint.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OISOEN</name>
|
|
<description>OUT Isochronous Transfer Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BULK_INT</name>
|
|
<description>Configure the endpoint for Bulk/Interrupt transfers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Configure the endpoint for Isochronous transfers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCLREN</name>
|
|
<description>OUT Endpoint OPRDYI Auto-Clear Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The OPRDYI bit is not automatically cleared by hardware.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The OPRDYI bit is automatically cleared by hardware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPCOUNT_1</name>
|
|
<description>Endpoint Data Count</description>
|
|
<addressOffset>0x8a0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Endpoint OUT Data Count. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPFIFO_1</name>
|
|
<description>Endpoint Data FIFO Access</description>
|
|
<addressOffset>0x8b0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO</name>
|
|
<description>Endpoint Data FIFO. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_3-->
|
|
<register>
|
|
<name>EPMPSIZE_2</name>
|
|
<description>Endpoint Maximum Packet Size</description>
|
|
<addressOffset>0x900</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMAXP</name>
|
|
<description>IN Maximum Packet Size. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OMAXP</name>
|
|
<description>OUT Maximum Packet Size. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPCONTROL_2</name>
|
|
<description>Endpoint Control</description>
|
|
<addressOffset>0x910</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPRDYI</name>
|
|
<description>IN Packet Ready Indicator. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The packet has been sent or there is an open FIFO slot.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A packet is loaded in the FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFIFONEF</name>
|
|
<description>IN FIFO Not Empty Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The IN Endpoint FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The IN Endpoint FIFO contains one or more packets.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IURF</name>
|
|
<description>IN FIFO Underrun Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Underrun has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Underrun occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFIFOFL</name>
|
|
<description>IN FIFO Flush. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the IN FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISDSTL</name>
|
|
<description>IN Send Stall. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Stop sending a stall.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Generate a stall.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISTSTLI</name>
|
|
<description>IN Sent Stall Interrupt Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt. </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A stall condition has been sent since this bit was last cleared. Write: No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICLRDT</name>
|
|
<description>IN Clear Data Toggle. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_RESET</name>
|
|
<description>Do not reset the IN data toggle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset the IN data toggle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLITEN</name>
|
|
<description>FIFO Split Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not split the endpoint FIFO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Split the endpoint FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FDTEN</name>
|
|
<description>Force Data Toggle Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The endpoint data toggle switches only when an ACK is received following a data packet transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The endpoint data toggle is forced to switch after every data packet is transmitted, regardless of ACK reception.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDMAEN</name>
|
|
<description>IN Endpoint DMA Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the DMA request for the IN endpoint.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the DMA request for the IN endpoint.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRSEL</name>
|
|
<description>Endpoint Direction Select. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT</name>
|
|
<description>Select the endpoint direction as OUT.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IN</name>
|
|
<description>Select the endpoint direction as IN.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IISOEN</name>
|
|
<description>IN Isochronous Transfer Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BULK_INT</name>
|
|
<description>Configure the endpoint for Bulk/Interrupt transfers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Configure the endpoint for Isochronous transfers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSETEN</name>
|
|
<description>IN Endpoint IPRDYI Automatic Set Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The IPRDYI bit is not automatically set by hardware.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The IPRDYI bit is automatically set by hardware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPRDYI</name>
|
|
<description>OUT Packet Ready. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A data packet is not available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A data packet is available.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFIFOFF</name>
|
|
<description>OUT FIFO Full. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The OUT endpoint FIFO is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The OUT endpoint FIFO is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OORF</name>
|
|
<description>OUT FIFO Overrun Flag. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>No data overrun.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A data packet was lost because of a full FIFO since this flag was last cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODERRF</name>
|
|
<description>OUT Data Error Flag. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A CRC or bit-stuff error has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A CRC or bit-stuff error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFIFOFL</name>
|
|
<description>OUT FIFO Flush. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the OUT FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSDSTL</name>
|
|
<description>OUT Send Stall. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop sending a stall.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEND</name>
|
|
<description>Generate a stall.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSTSTLI</name>
|
|
<description>OUT Sent Stall Interrupt Flag. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A stall condition has been sent since this bit was last cleared. Write: No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCLRDT</name>
|
|
<description>OUT Clear Data Toggle. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_RESET</name>
|
|
<description>Do not reset the OUT data toggle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset the OUT data toggle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODMAMD</name>
|
|
<description>OUT Endpoint DMA Mode. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTO_DMA</name>
|
|
<description>Automatic DMA service is requested on the last packet of the transfer until less than four bytes remain in the packet. At this time, an interrupt is generated. The firmware must read or write the last few bytes of the packet, if any remain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_DMA</name>
|
|
<description>No DMA service is requested on the last packet of the transfer. When the DMA recognizes the last packet, an interrupt is generated. The firmware must handle the entirety of the last packet.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODMAEN</name>
|
|
<description>OUT Endpoint DMA Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the DMA request for the OUT endpoint.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the DMA request for the OUT endpoint.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OISOEN</name>
|
|
<description>OUT Isochronous Transfer Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BULK_INT</name>
|
|
<description>Configure the endpoint for Bulk/Interrupt transfers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Configure the endpoint for Isochronous transfers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCLREN</name>
|
|
<description>OUT Endpoint OPRDYI Auto-Clear Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The OPRDYI bit is not automatically cleared by hardware.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The OPRDYI bit is automatically cleared by hardware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPCOUNT_2</name>
|
|
<description>Endpoint Data Count</description>
|
|
<addressOffset>0x920</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Endpoint OUT Data Count. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPFIFO_2</name>
|
|
<description>Endpoint Data FIFO Access</description>
|
|
<addressOffset>0x930</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO</name>
|
|
<description>Endpoint Data FIFO. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_4-->
|
|
<register>
|
|
<name>EPMPSIZE_3</name>
|
|
<description>Endpoint Maximum Packet Size</description>
|
|
<addressOffset>0x980</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMAXP</name>
|
|
<description>IN Maximum Packet Size. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OMAXP</name>
|
|
<description>OUT Maximum Packet Size. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPCONTROL_3</name>
|
|
<description>Endpoint Control</description>
|
|
<addressOffset>0x990</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPRDYI</name>
|
|
<description>IN Packet Ready Indicator. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The packet has been sent or there is an open FIFO slot.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A packet is loaded in the FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFIFONEF</name>
|
|
<description>IN FIFO Not Empty Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The IN Endpoint FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The IN Endpoint FIFO contains one or more packets.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IURF</name>
|
|
<description>IN FIFO Underrun Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Underrun has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Underrun occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFIFOFL</name>
|
|
<description>IN FIFO Flush. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the IN FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISDSTL</name>
|
|
<description>IN Send Stall. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Stop sending a stall.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Generate a stall.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISTSTLI</name>
|
|
<description>IN Sent Stall Interrupt Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt. </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A stall condition has been sent since this bit was last cleared. Write: No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICLRDT</name>
|
|
<description>IN Clear Data Toggle. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_RESET</name>
|
|
<description>Do not reset the IN data toggle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset the IN data toggle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLITEN</name>
|
|
<description>FIFO Split Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not split the endpoint FIFO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Split the endpoint FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FDTEN</name>
|
|
<description>Force Data Toggle Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The endpoint data toggle switches only when an ACK is received following a data packet transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The endpoint data toggle is forced to switch after every data packet is transmitted, regardless of ACK reception.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDMAEN</name>
|
|
<description>IN Endpoint DMA Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the DMA request for the IN endpoint.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the DMA request for the IN endpoint.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRSEL</name>
|
|
<description>Endpoint Direction Select. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT</name>
|
|
<description>Select the endpoint direction as OUT.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IN</name>
|
|
<description>Select the endpoint direction as IN.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IISOEN</name>
|
|
<description>IN Isochronous Transfer Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BULK_INT</name>
|
|
<description>Configure the endpoint for Bulk/Interrupt transfers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Configure the endpoint for Isochronous transfers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSETEN</name>
|
|
<description>IN Endpoint IPRDYI Automatic Set Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The IPRDYI bit is not automatically set by hardware.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The IPRDYI bit is automatically set by hardware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPRDYI</name>
|
|
<description>OUT Packet Ready. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A data packet is not available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A data packet is available.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFIFOFF</name>
|
|
<description>OUT FIFO Full. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The OUT endpoint FIFO is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The OUT endpoint FIFO is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OORF</name>
|
|
<description>OUT FIFO Overrun Flag. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>No data overrun.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A data packet was lost because of a full FIFO since this flag was last cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODERRF</name>
|
|
<description>OUT Data Error Flag. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A CRC or bit-stuff error has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A CRC or bit-stuff error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFIFOFL</name>
|
|
<description>OUT FIFO Flush. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the OUT FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSDSTL</name>
|
|
<description>OUT Send Stall. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop sending a stall.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEND</name>
|
|
<description>Generate a stall.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSTSTLI</name>
|
|
<description>OUT Sent Stall Interrupt Flag. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A stall condition has been sent since this bit was last cleared. Write: No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCLRDT</name>
|
|
<description>OUT Clear Data Toggle. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_RESET</name>
|
|
<description>Do not reset the OUT data toggle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset the OUT data toggle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODMAMD</name>
|
|
<description>OUT Endpoint DMA Mode. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTO_DMA</name>
|
|
<description>Automatic DMA service is requested on the last packet of the transfer until less than four bytes remain in the packet. At this time, an interrupt is generated. The firmware must read or write the last few bytes of the packet, if any remain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_DMA</name>
|
|
<description>No DMA service is requested on the last packet of the transfer. When the DMA recognizes the last packet, an interrupt is generated. The firmware must handle the entirety of the last packet.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODMAEN</name>
|
|
<description>OUT Endpoint DMA Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the DMA request for the OUT endpoint.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the DMA request for the OUT endpoint.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OISOEN</name>
|
|
<description>OUT Isochronous Transfer Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BULK_INT</name>
|
|
<description>Configure the endpoint for Bulk/Interrupt transfers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Configure the endpoint for Isochronous transfers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCLREN</name>
|
|
<description>OUT Endpoint OPRDYI Auto-Clear Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The OPRDYI bit is not automatically cleared by hardware.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The OPRDYI bit is automatically cleared by hardware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPCOUNT_3</name>
|
|
<description>Endpoint Data Count</description>
|
|
<addressOffset>0x9a0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Endpoint OUT Data Count. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPFIFO_3</name>
|
|
<description>Endpoint Data FIFO Access</description>
|
|
<addressOffset>0x9b0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO</name>
|
|
<description>Endpoint Data FIFO. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<!--BASEPOINTER_START_5-->
|
|
<register>
|
|
<name>EPMPSIZE_4</name>
|
|
<description>Endpoint Maximum Packet Size</description>
|
|
<addressOffset>0xa00</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMAXP</name>
|
|
<description>IN Maximum Packet Size. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OMAXP</name>
|
|
<description>OUT Maximum Packet Size. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPCONTROL_4</name>
|
|
<description>Endpoint Control</description>
|
|
<addressOffset>0xa10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPRDYI</name>
|
|
<description>IN Packet Ready Indicator. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The packet has been sent or there is an open FIFO slot.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A packet is loaded in the FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFIFONEF</name>
|
|
<description>IN FIFO Not Empty Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The IN Endpoint FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The IN Endpoint FIFO contains one or more packets.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IURF</name>
|
|
<description>IN FIFO Underrun Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Underrun has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Underrun occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFIFOFL</name>
|
|
<description>IN FIFO Flush. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the IN FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISDSTL</name>
|
|
<description>IN Send Stall. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Stop sending a stall.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Generate a stall.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISTSTLI</name>
|
|
<description>IN Sent Stall Interrupt Flag. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt. </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A stall condition has been sent since this bit was last cleared. Write: No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICLRDT</name>
|
|
<description>IN Clear Data Toggle. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_RESET</name>
|
|
<description>Do not reset the IN data toggle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset the IN data toggle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLITEN</name>
|
|
<description>FIFO Split Enable. </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Do not split the endpoint FIFO.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Split the endpoint FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FDTEN</name>
|
|
<description>Force Data Toggle Enable. </description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The endpoint data toggle switches only when an ACK is received following a data packet transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The endpoint data toggle is forced to switch after every data packet is transmitted, regardless of ACK reception.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDMAEN</name>
|
|
<description>IN Endpoint DMA Enable. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the DMA request for the IN endpoint.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the DMA request for the IN endpoint.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRSEL</name>
|
|
<description>Endpoint Direction Select. </description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT</name>
|
|
<description>Select the endpoint direction as OUT.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IN</name>
|
|
<description>Select the endpoint direction as IN.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IISOEN</name>
|
|
<description>IN Isochronous Transfer Enable. </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BULK_INT</name>
|
|
<description>Configure the endpoint for Bulk/Interrupt transfers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Configure the endpoint for Isochronous transfers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSETEN</name>
|
|
<description>IN Endpoint IPRDYI Automatic Set Enable. </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The IPRDYI bit is not automatically set by hardware.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The IPRDYI bit is automatically set by hardware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPRDYI</name>
|
|
<description>OUT Packet Ready. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A data packet is not available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A data packet is available.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFIFOFF</name>
|
|
<description>OUT FIFO Full. </description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The OUT endpoint FIFO is not full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The OUT endpoint FIFO is full.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OORF</name>
|
|
<description>OUT FIFO Overrun Flag. </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>No data overrun.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A data packet was lost because of a full FIFO since this flag was last cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODERRF</name>
|
|
<description>OUT Data Error Flag. </description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>A CRC or bit-stuff error has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>A CRC or bit-stuff error occurred.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFIFOFL</name>
|
|
<description>OUT FIFO Flush. </description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Flush the OUT FIFO.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSDSTL</name>
|
|
<description>OUT Send Stall. </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop sending a stall.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEND</name>
|
|
<description>Generate a stall.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSTSTLI</name>
|
|
<description>OUT Sent Stall Interrupt Flag. </description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: A stall condition has been sent since this bit was last cleared. Write: No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCLRDT</name>
|
|
<description>OUT Clear Data Toggle. </description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_RESET</name>
|
|
<description>Do not reset the OUT data toggle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset the OUT data toggle.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODMAMD</name>
|
|
<description>OUT Endpoint DMA Mode. </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTO_DMA</name>
|
|
<description>Automatic DMA service is requested on the last packet of the transfer until less than four bytes remain in the packet. At this time, an interrupt is generated. The firmware must read or write the last few bytes of the packet, if any remain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_DMA</name>
|
|
<description>No DMA service is requested on the last packet of the transfer. When the DMA recognizes the last packet, an interrupt is generated. The firmware must handle the entirety of the last packet.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODMAEN</name>
|
|
<description>OUT Endpoint DMA Enable. </description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the DMA request for the OUT endpoint.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the DMA request for the OUT endpoint.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OISOEN</name>
|
|
<description>OUT Isochronous Transfer Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BULK_INT</name>
|
|
<description>Configure the endpoint for Bulk/Interrupt transfers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Configure the endpoint for Isochronous transfers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCLREN</name>
|
|
<description>OUT Endpoint OPRDYI Auto-Clear Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The OPRDYI bit is not automatically cleared by hardware.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The OPRDYI bit is automatically cleared by hardware.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPCOUNT_4</name>
|
|
<description>Endpoint Data Count</description>
|
|
<addressOffset>0xa20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Endpoint OUT Data Count. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EPFIFO_4</name>
|
|
<description>Endpoint Data FIFO Access</description>
|
|
<addressOffset>0xa30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO</name>
|
|
<description>Endpoint Data FIFO. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>VMON_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>VMON_0</groupName>
|
|
<baseAddress>0x4002f000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>VDDLOW_IRQn</name>
|
|
<value>43</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>VREGLOW_IRQn</name>
|
|
<value>53</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VREGINSEN</name>
|
|
<description>VREGIN Supply Monitor Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the VREGIN supply monitor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the VREGIN supply monitor.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREGINLI</name>
|
|
<description>VREGIN Low Interrupt Flag. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VREGIN_IS_LOW</name>
|
|
<description>VREGIN is not above the interrupt threshold.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VREGIN_IS_OK</name>
|
|
<description>VREGIN is above the interrupt threshold.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VDDRSTF</name>
|
|
<description>VDD Reset Threshold Status Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VDD_IS_BELOW_RESET</name>
|
|
<description>The VDD voltage is below the VDD reset threshold.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDD_IS_ABOVE_RESET</name>
|
|
<description>The VDD voltage is above the VDD reset threshold.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VDDLI</name>
|
|
<description>VDD Low Interrupt Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VDD_IS_LOW</name>
|
|
<description>The VDD voltage is below the early warning threshold.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDD_IS_OK</name>
|
|
<description>The VDD voltage is above the early warning threshold.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VDDHITHEN</name>
|
|
<description>VDD High Threshold Enable. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the standard VDD thresholds.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Use the high VDD thresholds.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VDDLIEN</name>
|
|
<description>VDD Low Interrupt Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the VDD low interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the VDD low interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREGINLIEN</name>
|
|
<description>VREGIN Low Interrupt Enable. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the VREGIN low interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the VREGIN low interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VMONEN</name>
|
|
<description>VDD Supply Monitor Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the VDD supply monitor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the VDD supply monitor.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>VREF_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>VREF_0</groupName>
|
|
<baseAddress>0x40039010</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Voltage Reference Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VREF2X</name>
|
|
<description>Voltage Reference Doubler. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>VREF output is nominally 1.2 V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>VREF output is nominally 2.4 V</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMPEN</name>
|
|
<description>Temperature Sensor Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the temperature sensor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the temperature sensor.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREFEN</name>
|
|
<description>Voltage Reference Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the Voltage Reference.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the Voltage Reference.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EXTVREG_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Voltage_Regulators</groupName>
|
|
<baseAddress>0x40042000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SAEN</name>
|
|
<description>Stand-Alone Mode Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Use the external regulator in normal mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Use the external regulator in stand-alone mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPULLEN</name>
|
|
<description>Weak Pull Up/Down Enable. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the external regulator weak pull-up/down resistor on the EXREGBD pin and weak pull-down resistor on the EXREGOUT pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the external regulator weak pull-up/down resistor on the EXREGBD pin and weak pull-down resistor on the EXREGOUT pin.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FBLEN</name>
|
|
<description>Foldback Limiting Enable. </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable foldback limiting.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable foldback limiting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PNSEL</name>
|
|
<description>NPN/PNP Type Select. </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NPN</name>
|
|
<description>Select NPN Mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PNP</name>
|
|
<description>Select PNP Mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FBPINSEL</name>
|
|
<description>Foldback Sensing Pin Select. </description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EXREGSN</name>
|
|
<description>Use the input to the EXREGSN pin for foldback limiting.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VREGIN</name>
|
|
<description>Use the input to the VREGIN pin for foldback limiting.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EVREGEN</name>
|
|
<description>External Regulator Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the external regulator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the external regulator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Module Configuration</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMINFINE</name>
|
|
<description>Minimum Current Fine Select. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0_UA</name>
|
|
<description>Minimum current limit is IMIN current + 0 uA. </description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0P25_UA</name>
|
|
<description>Minimum current limit is IMIN current + 0.25 uA.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0P5_UA</name>
|
|
<description>Minimum current limit is IMIN current + 0.50 uA.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0P75_UA</name>
|
|
<description>Minimum current limit is IMIN current + 0.75 uA.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMIN</name>
|
|
<description>Minimum Current Select. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1_UA</name>
|
|
<description>Minimum current limit is 1 uA + IMINFINE current.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_UA</name>
|
|
<description>Minimum current limit is 2 uA + IMINFINE current.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_UA</name>
|
|
<description>Minimum current limit is 3 uA + IMINFINE current.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_UA</name>
|
|
<description>Minimum current limit is 4 uA + IMINFINE current.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_UA</name>
|
|
<description>Minimum current limit is 5 uA + IMINFINE current.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_UA</name>
|
|
<description>Minimum current limit is 6 uA + IMINFINE current.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_UA</name>
|
|
<description>Minimum current limit is 7 uA + IMINFINE current.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_UA</name>
|
|
<description>Minimum current limit is 8 uA + IMINFINE current.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FBVOSEL</name>
|
|
<description>Foldback Voltage Offset Select. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0_V</name>
|
|
<description>Foldback voltage offset is 0 V.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0P5_V</name>
|
|
<description>Foldback voltage offset is 0.5 V.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_V</name>
|
|
<description>Foldback voltage offset is 1 V.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1P5_V</name>
|
|
<description>Foldback voltage offset is 1.5 V.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_V</name>
|
|
<description>Foldback voltage offset is 2 V.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2P5_V</name>
|
|
<description>Foldback voltage offset is 2.5 V.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_V</name>
|
|
<description>Foldback voltage offset is 3 V.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3P5_V</name>
|
|
<description>Foldback voltage offset is 3.5 V.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FBRATE</name>
|
|
<description>Voltage Sense Gain Multiplier. </description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>4_UA_PER_V</name>
|
|
<description>Set the foldback rate to 4 uA/V.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_UA_PER_V</name>
|
|
<description>Set the foldback rate to 2 uA/V.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_UA_PER_V</name>
|
|
<description>Set the foldback rate to 1 uA/V.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0P5_UA_PER_V</name>
|
|
<description>Set the foldback rate to 0.5 uA/V.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_UA_PER_V</name>
|
|
<description>Set the foldback rate to 8 uA/V.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_UA_PER_V</name>
|
|
<description>Set the foldback rate to 16 uA/V.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32_UA_PER_V</name>
|
|
<description>Set the foldback rate to 32 uA/V.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAX</name>
|
|
<description>Maximum Current Select. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>2_UA</name>
|
|
<description>Maximum current limit is 2 uA.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_UA</name>
|
|
<description>Maximum current limit is 3 uA.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_UA</name>
|
|
<description>Maximum current limit is 4 uA.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_UA</name>
|
|
<description>Maximum current limit is 5 uA.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_UA</name>
|
|
<description>Maximum current limit is 6 uA.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_UA</name>
|
|
<description>Maximum current limit is 7 uA.</description>
|
|
<value>5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_UA</name>
|
|
<description>Maximum current limit is 8 uA.</description>
|
|
<value>6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_UA</name>
|
|
<description>Maximum current limit is 9 uA.</description>
|
|
<value>7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VOUTSEL</name>
|
|
<description>Regulator Output Voltage Select. </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FBMAXF</name>
|
|
<description>Maximum Foldback Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Maximum foldback has not been reached.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Maximum foldback has been reached.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCONTROL</name>
|
|
<description>Current Sense Control</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISNSEN</name>
|
|
<description>External Regulator Current Sense Enable. </description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable external regulator current sensing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable external regulator current sensing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCISNSEN</name>
|
|
<description>ADC Current Sense Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable ADC current sensing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable ADC current sensing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCONFIG</name>
|
|
<description>Current Sense Configuration</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISADCGAIN</name>
|
|
<description>ADC Current Sense Gain. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>16X</name>
|
|
<description>ADC current sensing input gain is 16.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8X</name>
|
|
<description>ADC current sensing input gain is 8.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4X</name>
|
|
<description>ADC current sensing input gain is 4.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2X</name>
|
|
<description>ADC current sensing input gain is 2.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1X</name>
|
|
<description>ADC current sensing input gain is 1.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISOGAIN</name>
|
|
<description>External Regulator Current Sense Gain. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>16X</name>
|
|
<description>External regulator current sensing gain is 16.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8X</name>
|
|
<description>External regulator current sensing gain is 8.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4X</name>
|
|
<description>External regulator current sensing gain is 4.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2X</name>
|
|
<description>External regulator current sensing gain is 2.</description>
|
|
<value>3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1X</name>
|
|
<description>External regulator current sensing gain is 1.</description>
|
|
<value>4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISINSEL</name>
|
|
<description>External Regulator Current Sense Input Select. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE0</name>
|
|
<description>Select external regulator current sensing mode 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE1</name>
|
|
<description>Select external regulator current sensing mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE2</name>
|
|
<description>Select external regulator current sensing mode 2.</description>
|
|
<value>2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>VREG_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Voltage_Regulators</groupName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>VREGDROPOUT_IRQn</name>
|
|
<value>52</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x40000100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VBUSVLDF</name>
|
|
<description>VBUS Valid Flag. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The current voltage on the VBUS pin is below the valid threshold.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The current voltage on the VBUS pin is above the valid threshold.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUSEN</name>
|
|
<description>Voltage Regulator Suspend Enable. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable regulator suspend mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable regulator suspend mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BGDIS</name>
|
|
<description>Band Gap Disable. </description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Enable the voltage regulator band gap.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Disable the voltage regulator band gap.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SENSEEN</name>
|
|
<description>VREGIN Sense Enable. </description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable VREGIN voltage sensing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable VREGIN voltage sensing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBUSIVLDI</name>
|
|
<description>VBUS Invalid Interrupt Flag. </description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>The voltage on the VBUS pin has not dropped below the valid threshold.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>The voltage on the VBUS pin dropped below the valid threshold since the last time this bit was cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBUSIVLDIEN</name>
|
|
<description>VBUS Invalid Interrupt Enable. </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the VBUS invalid interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the VBUS invalid interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREGDIS</name>
|
|
<description>Voltage Regulator Disable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Enable the voltage regulator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Disable the voltage regulator.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LDO_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>Voltage_Regulators</groupName>
|
|
<baseAddress>0x40039000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LDOIBIAS</name>
|
|
<description>LDO Bias Current Selection. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HIGHBIAS</name>
|
|
<description>Select high bias.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOWBIAS</name>
|
|
<description>Select low bias (AHB frequency <= 2.5 MHz).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDOAEN</name>
|
|
<description>LDO Analog Enable. </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>LDO0 analog output disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>LDO0 analog output enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WDTIMER_0</name>
|
|
<version>A</version>
|
|
<description>None</description>
|
|
<groupName>WDTIMER_0</groupName>
|
|
<baseAddress>0x40030000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xffc</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WDTIMER_IRQn</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<registers>
|
|
<!--BASEPOINTER_START_1-->
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Module Control</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWIEN</name>
|
|
<description>Early Warning Interrupt Enable. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disable the early warning interrupt (EWI).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enable the early warning interrupt (EWI).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGMD</name>
|
|
<description>Watchdog Timer Debug Mode. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The WDTIMER module will continue to operate while the core is halted in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>A debug breakpoint will cause the WDTIMER module to halt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Module Status</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEYSTS</name>
|
|
<description>Key Status. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>No keys have been processed by the interface.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READY</name>
|
|
<description>The attention key has been received and the module is awaiting a command.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRIVSTS</name>
|
|
<description>Register Access Status. </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READ_ONLY</name>
|
|
<description>The watchdog timer registers are currently read-only.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READ_WRITE</name>
|
|
<description>A write transaction can be performed on the module registers.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EWI</name>
|
|
<description>Early Warning Interrupt Flag. </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOT_SET</name>
|
|
<description>Read: An early warning match did not occur. Write: Clear the early warning interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Read: An early warning match occurred and the interrupt is pending. Write: Force a watchdog timer early warning interrupt to occur.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTHF</name>
|
|
<description>Reset Threshold Flag. </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LT</name>
|
|
<description>The counter is currently less than the reset threshold (RTH) value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GTE</name>
|
|
<description>The counter is currently greater than or equal to the reset threshold (RTH) value.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UPDSTS</name>
|
|
<description>Watchdog Timer Threshold Update Status. </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>An update completed or is not pending. The EWTH and RTH fields can be written.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATING</name>
|
|
<description>An update of the threshold register is occurring. The EWTH and RTH fields should not be modified until hardware clears UPDSTS to 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THRESHOLD</name>
|
|
<description>Threshold Values</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<resetValue>0xFFFF7FFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWTH</name>
|
|
<description>Early Warning Threshold. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTH</name>
|
|
<description>Reset Threshold. </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTKEY</name>
|
|
<description>Module Key</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Watchdog Timer Key. </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ATTN</name>
|
|
<description>Attention key to start the command sequence.</description>
|
|
<value>165</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset the watchdog timer.</description>
|
|
<value>204</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable the watchdog timer.</description>
|
|
<value>221</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start the watchdog timer.</description>
|
|
<value>238</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITE</name>
|
|
<description>Allow one write access to the module registers.</description>
|
|
<value>241</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK</name>
|
|
<description>Lock the module from any other writes until the next system reset.</description>
|
|
<value>255</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|