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RMUL2025/lib/cmsis_svd/data/SiliconLabs/SiM3_NRND/SIM3L1x4.svd

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<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
<name>SIM3L164_C</name>
<version>1</version>
<description>256K Flash, 32K RAM, 40 PIN</description>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>32</size>
<access>read-write</access>
<peripherals>
<peripheral>
<name>ACCTR_0</name>
<version>A</version>
<description>None</description>
<groupName>ACCTR_0</groupName>
<baseAddress>0x40042000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ACCTR0_IRQn</name>
<value>22</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONFIG</name>
<description>Configuration</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x02000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UPDSTSF</name>
<description>Write Update Status Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>An internal pulse counter register update is not in progress.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An internal pulse counter register update is in progress.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGSEL</name>
<description>Debug Signal Select. </description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NONE</name>
<description>No debug signals output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LCC0_LCC1</name>
<description>(LC Mode) DBG0 = CMP0OUT, DBG1 = CMP1OUT.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>LCC0_INT0</name>
<description>(LC Mode) DBG0 = CMP0OUT, DBG1 = INTEG0.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>LCC1_INT1</name>
<description>(LC Mode) DBG0 = CMP1OUT, DBG1 = INTEG1.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_INT1</name>
<description>(Any Mode) DBG0 = INTEG0 DBG1 = INTEG1.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CMP0_CMP1</name>
<description>(Switch Mode) DBG0 = CMP0OUT, DBG1 = CMP1OUT.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>CMP0_INT0</name>
<description>(Switch Mode) DBG0 = CMP0OUT, DBG1 = INTEG0.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>CMP1_INT1</name>
<description>(Switch Mode) DBG0= CMP1OUT, DBG1 = INTEG1.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLQDEN</name>
<description>Flutter Quadrature-to-Dual Switch Enable. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The pulse counter remains in quadrature mode during a flutter event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The pulse counter switches from quadrature mode to dual mode during a flutter event.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLSTPEN</name>
<description>Flutter Stop Enable. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The pulse counter continues operating during a flutter event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The 24-bit counters stop counting during a flutter event.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOPMD</name>
<description>Topology Mode. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SWITCH</name>
<description>Select the switch closure topology.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LC</name>
<description>Select the LC resonant topology.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCMD</name>
<description>Pulse Counter Mode. </description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the pulse counter.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SINGLE</name>
<description>Select single channel mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DUAL</name>
<description>Select dual channel mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>QUADRATURE</name>
<description>Select quadrature mode.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<description>Control Register</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x44000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CMPLTH</name>
<description>Comparator Low Threshold. </description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>32_PERCENT</name>
<description>Set the digital comparator low threshold to 32% of VIO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>36_PERCENT</name>
<description>Set the digital comparator low threshold to 36% of VIO.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>40_PERCENT</name>
<description>Set the digital comparator low threshold to 40% of VIO.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>44_PERCENT</name>
<description>Set the digital comparator low threshold to 44% of VIO.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPHTH</name>
<description>Comparator High Threshold. </description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>48_PERCENT</name>
<description>Set the digital comparator high threshold to 48% of VIO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>52_PERCENT</name>
<description>Set the digital comparator high threshold to 52% of VIO.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>56_PERCENT</name>
<description>Set the digital comparator high threshold to 56% of VIO.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>60_PERCENT</name>
<description>Set the digital comparator high threshold to 60% of VIO.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CALMD</name>
<description>Automatic Calibration Mode. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNTIL_PASS</name>
<description>Continue to calibrate until a passing condition occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UNTIL_FAIL</name>
<description>Continue to calibrate until a failing condition occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CALPUMD</name>
<description>Automatic Calibration Pull-up Mode. </description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>FULL</name>
<description>Use full pull-up mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SMALL</name>
<description>Use small pull-up mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MEDIUM</name>
<description>Use medium pull-up mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>LARGE</name>
<description>Use large pull-up mode.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FPUPEN</name>
<description>Force Continuous Pull-up Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Pull-ups are enabled automatically by hardware.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Always enable the pull-ups.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FPDNEN</name>
<description>Force Ground Input Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable input grounding.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable input grounding. The IN0 and IN1 inputs are grounded.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PUVAL</name>
<description>Pull-up Value. </description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CALSEL</name>
<description>Automatic Calibration Input Select. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>IN0</name>
<description>Calibrate the IN0 input.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IN1</name>
<description>Calibrate the IN1 input.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CALRF</name>
<description>Calibration Result Flag. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The automatic calibration operation did not succeed.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The automatic calibration operation succeeded.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CALBUSYF</name>
<description>Calibration Busy Flag. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A calibration operation is not in progress.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A calibration operation is in progress. Hardware will clear this flag when the operation completes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LCCONFIG</name>
<description>LC Configuration</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x01718C61</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PEMD</name>
<description>LC Pulse Extension Mode. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Stretch the LC comparator output low pulses by approximately 20 ns.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Stretch the LC comparator output high pulses by approximately 20 ns.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>NONE</name>
<description>No pulse extension.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0FTH</name>
<description>LC Comparator 0 Fine Threshold. </description>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CMP0CTH</name>
<description>LC Comparator 0 Coarse Threshold. </description>
<bitOffset>5</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>CMP0THR</name>
<description>LC Comparator 0 Threshold Range. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the comparator 0 threshold to the low range (0 V to VIO/8 in 48 steps).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FULL</name>
<description>Set the comparator 0 threshold to a full range (0 V to VIO in 64 steps).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1FTH</name>
<description>LC Comparator 1 Fine Threshold. </description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CMP1CTH</name>
<description>LC Comparator 1 Coarse Threshold. </description>
<bitOffset>15</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>CMP1THR</name>
<description>LC Comparator 1 Threshold Range. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the comparator 1 threshold to the low range (0 V to VIO/8 in 48 steps).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FULL</name>
<description>Set the comparator 1 threshold to a full range (0 V to VIO in 64 steps).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPLHYS</name>
<description>LC Comparator Low-side Hysteresis. </description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0_MV</name>
<description>Set both LC comparators to use 0 mV low-side hysteresis.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>5_MV</name>
<description>Set both LC comparators to use 5 mV low-side hysteresis.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>10_MV</name>
<description>Set both LC comparators to use 10 mV low-side hysteresis.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>20_MV</name>
<description>Set both LC comparators to use 20 mV low-side hysteresis.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPHHYS</name>
<description>LC Comparator High-side Hysteresis. </description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0_MV</name>
<description>Set both LC comparators to use 0 mV high-side hysteresis.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>5_MV</name>
<description>Set both LC comparators to use 5 mV high-side hysteresis.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>10_MV</name>
<description>Set both LC comparators to use 10 mV high-side hysteresis.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>20_MV</name>
<description>Set both LC comparators to use 20 mV high-side hysteresis.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPMD</name>
<description>LC Comparator Mode. </description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>5_US</name>
<description>Mode 0 (slowest response time, lowest power consumption).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_US</name>
<description>Mode 1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>400_NS</name>
<description>Mode 2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>200_NS</name>
<description>Mode 3 (fastest response time, highest power consumption).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0CNT1EN</name>
<description>LC Comparator 0 to Count 1 Enable. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Use LC comparator 0 as an input to counter 0 and LC comparator 1 as an input to counter 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Use LC comparator 0 as an input to both counter 0 and counter 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FCMP0EN</name>
<description>Force LC Comparator 0 On Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Hardware automatically turns LC comparator 0 on and off.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Force LC comparator 0 always on.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FCMP1EN</name>
<description>Force LC Comparator 1 On Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Hardware automatically turns LC comparator 1 on and off.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Force LC comparator 1 always on.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TIMING</name>
<description>Timing</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x40000018</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STATE</name>
<description>Timing State. </description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>B0OEN</name>
<description>Bias 0 Offset Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The bias 0 pulse is a full width (minimum 2 RTC cycles).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The bias 0 pulse is delayed 1/2 an RTC cycle and de-asserts 1/2 an RTC cycle early (minimum 3 RTC cycles).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1OEN</name>
<description>Bias 1 Offset Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The bias 1 pulse is a full width (minimum 2 RTC cycles).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The bias 1 pulse is delayed 1/2 an RTC cycle and de-asserts 1/2 an RTC cycle early (minimum 3 RTC cycles).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ZONED</name>
<description>Zone D Count. </description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ZONEC</name>
<description>Zone C Count. </description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ZONEB</name>
<description>Zone B Count. </description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ZONEA</name>
<description>Zone A Count. </description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ZONEP</name>
<description>Zone P Count. </description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>WAKEMD</name>
<description>LC Wake Mode. </description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable wake up events.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WZONEP</name>
<description>Wake or interrupt at the start of zone P.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>WZONEA</name>
<description>Wake or interrupt at the start of zone A.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>WZONEB</name>
<description>Wake or interrupt at the start of zone B.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>WZONEC</name>
<description>Wake or interrupt at the start of zone C.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>WZONED</name>
<description>Wake or interrupt at the start of zone D.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>WEND</name>
<description>Wake or interrupt at the end of the LC sequence.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>WKSTOP</name>
<description>Wake or interrupt at the end of the LC sequence and stop the sequencer when this event occurs.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START</name>
<description>Sequencer Start. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not start the sequencer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Start the sequencer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PERIOD</name>
<description>Pulse Counter Period. </description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>4_CYCLES</name>
<description>Set the period to 4 RTC cycles.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>8_CYCLES</name>
<description>Set the period to 8 RTC cycles.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>16_CYCLES</name>
<description>Set the period to 16 RTC cycles.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>32_CYCLES</name>
<description>Set the period to 32 RTC cycles.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>64_CYCLES</name>
<description>Set the period to 64 RTC cycles.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>128_CYCLES</name>
<description>Set the period to 128 RTC cycles.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>256_CYCLES</name>
<description>Set the period to 256 RTC cycles.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>512_CYCLES</name>
<description>Set the period to 512 RTC cycles.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>1024_CYCLES</name>
<description>Set the period to 1024 RTC cycles.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>2048_CYCLES</name>
<description>Set the period to 2048 RTC cycles.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>4096_CYCLES</name>
<description>Set the period to 4096 RTC cycles.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>SINGLE_SAMPLE</name>
<description>Set the module to single sample mode and disable the period counter after the next completion of the sequencer. In this mode, firmware must start each sample by setting FLCSEN to 1. </description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>CONSECUTIVE_SAMPLE</name>
<description>Set the module to consecutive sample mode and disable the period counter. After completing zone D, the timing engine will jump directly to zone A, skipping both the W and P zones.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LCMODE</name>
<description>LC Mode</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x0258A742</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ATRKEN</name>
<description>Automatic Tracking Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable automatic tracking.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable automatic tracking. A new MAX value of any size will increase both the MAX and MIN by 1, and a new MIN value of any size will decrease both the MAX and MIN by 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACDEN</name>
<description>Automatic Center Discriminator Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable automatic center discriminator mode. Firmware must set the CD0 and CD1 fields. </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable automatic center discriminator mode. Hardware will keep the CD0 and CD1 fields centered between MAX and MIN.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCD0HYS</name>
<description>LC Discriminator 0 Digital Hysterisis. </description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ZERO</name>
<description>A high-to-low transition occurs if LCCOUNT0 is less than CD0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MINUS1</name>
<description>A high-to-low transition occurs if LCCOUNT0 is less than CD0 - 1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MINUS2</name>
<description>A high-to-low transition occurs if LCCOUNT0 is less than CD0 - 2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>MINUS3</name>
<description>A high-to-low transition occurs if LCCOUNT0 is less than CD0 - 3.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCD1HYS</name>
<description>LC Discriminator 1 Digital Hysterisis. </description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ZERO</name>
<description>A high-to-low transition occurs if LCCOUNT1 is less than CD1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MINUS1</name>
<description>A high-to-low transition occurs if LCCOUNT1 is less than CD1 - 1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MINUS2</name>
<description>A high-to-low transition occurs if LCCOUNT1 is less than CD1 - 2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>MINUS3</name>
<description>A high-to-low transition occurs if LCCOUNT1 is less than CD1 - 3.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C0ZONE</name>
<description>Counter 0 Active Zone Select. </description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ZONEA</name>
<description>Select zone A as the active zone for counter 0 (LCIN0 input).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ZONEB</name>
<description>Select zone B as the active zone for counter 0 (LCIN0 input).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ZONEC</name>
<description>Select zone C as the active zone for counter 0 (LCIN0 input).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ZONED</name>
<description>Select zone D as the active zone for counter 0 (LCIN0 input).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C1ZONE</name>
<description>Counter 1 Active Zone Select. </description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ZONEA</name>
<description>Select zone A as the active zone for counter 1 (LCIN1 input).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ZONEB</name>
<description>Select zone B as the active zone for counter 1 (LCIN1 input).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ZONEC</name>
<description>Select zone C as the active zone for counter 1 (LCIN1 input).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ZONED</name>
<description>Select zone D as the active zone for counter 1 (LCIN1 input).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>P0ZONE</name>
<description>Pulse 0 Active Zone Select. </description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the pulse 0 output (LCPUL0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>C_ONLY</name>
<description>Select zone C only as the active zone for the pulse 0 output (LCPUL0).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>A_ONLY</name>
<description>Select zone A only as the active zone for the pulse 0 output (LCPUL0).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>A_AND_C</name>
<description>Select zones A and C as the active zones for the pulse 0 output (LCPUL0).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>P1ZONE</name>
<description>Pulse 1 Active Zone Select. </description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the pulse 1 output (LCPUL1).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>C_ONLY</name>
<description>Select zone C only as the active zone for the pulse 1 output (LCPUL1).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>A_ONLY</name>
<description>Select zone A only as the active zone for the pulse 1 output (LCPUL1).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>A_AND_C</name>
<description>Select zones A and C as the active zones for the pulse 1 output (LCPUL1).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMD</name>
<description>LC Pulse Mode. </description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable pulse mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>Toggle at the start of zone A or zone C.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULSE_LOW</name>
<description>Set the pulse mode to idle high, pulse low.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>PULSE_HIGH</name>
<description>Set the pulse mode to idle low, pulse high.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B0ZONECEN</name>
<description>Bias 0 Zone C Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable bias 0 during zone C.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable bias 0 during zone C.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B0ZONEBEN</name>
<description>Bias 0 Zone B Enable. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable bias 0 during zone B.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable bias 0 during zone B.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B0ZONEAEN</name>
<description>Bias 0 Zone A Enable. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable bias 0 during zone A.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable bias 0 during zone A.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B0ZONEPEN</name>
<description>Bias 0 Zone P Enable. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable bias 0 during zone P.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable bias 0 during zone P.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B0POL</name>
<description>Bias 0 Polarity. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>PULSE_LOW</name>
<description>Set bias 0 to idle high, pulse low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULSE_HIGH</name>
<description>Set bias 0 to idle low, pulse high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1ZONECEN</name>
<description>Bias 1 Zone C Enable. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable bias 1 during zone C.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable bias 1 during zone C.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1ZONEBEN</name>
<description>Bias 1 Zone B Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable bias 1 during zone B.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable bias 1 during zone B.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1ZONEAEN</name>
<description>Bias 1 Zone A Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable bias 1 during zone A.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable bias 1 during zone A.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1ZONEPEN</name>
<description>Bias 1 Zone P Enable. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable bias 1 during zone P.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable bias 1 during zone P.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>B1POL</name>
<description>Bias 1 Polarity. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>PULSE_LOW</name>
<description>Set bias 1 to idle high, pulse low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULSE_HIGH</name>
<description>Set bias 1 to idle low, pulse high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BMD</name>
<description>Bias Mode. </description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MODE0</name>
<description>Disable the bias signals.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>Use the bias signals externally only (LCBIAS0 and LCBIAS1 outputs).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>Use the bias signals internally only.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE3</name>
<description>Use the bias signals externally (LCBIAS0 and LCBIAS1 outputs) and internally.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCMD</name>
<description>LC Mode. </description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MODE0</name>
<description>The LC pulse asserts throughout zone A or zone C with a single-ended comparator using the counter and discriminator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>The LC pulse asserts throughout zone A or zone C with differential comparators using the counter and discriminator.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>The LC pulse asserts throughout zone A or zone C with a single-ended comparator sampling and holding at the end of the LC pulse.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE3</name>
<description>The LC pulse asserts throughout zone A or zone C with differential comparators sampling and holding at the end of the LC pulse.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE4</name>
<description>The LC pulse starts at the beginning of zone A or C and stops with the timer with a single-ended comparator using the counter and discriminator.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE5</name>
<description>The LC pulse starts at the beginning of zone A or C and stops with the timer with differential comparators using the counter and discriminator.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE6</name>
<description>The LC pulse starts at the beginning of zone A or C and stops with the timer with a single-ended comparator sampling and holding at the end of the LC pulse.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE7</name>
<description>The LC pulse starts at the beginning of zone A or C and stops with the timer with differential comparators sampling and holding at the end of the LC pulse.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE8</name>
<description>The LC pulse starts at beginning of zone A or C and stops with the rising edge of the external stop input (STOPx) with a single-ended comparator using the counter and discriminator.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE9</name>
<description>The LC pulse starts at beginning of zone A or C and stops with the falling edge of the external stop input (STOPx) with single-ended comparators using the counter and discriminator.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE10</name>
<description>The LC pulse starts at beginning of zone A or C and stops with the rising edge of the external stop input (STOPx) with a single-ended comparator sampling and holding at the end of the LC pulse.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE11</name>
<description>The LC pulse starts at beginning of zone A or C and stops with the falling edge of the external stop input (STOPx) with single-ended comparators sampling and holding at the end of the LC pulse.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE12</name>
<description>Do not generate a pulse with a single-ended comparator using the timer and discrimintor.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE13</name>
<description>Do not generate a pulse with differential comparators using the timer and discrimintor.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE14</name>
<description>Do not generate a pulse with a single-ended comparator sampling and holding at the end of the zone.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE15</name>
<description>Do not genreate a pulse with differential comparators sampling and holding at the end of the zone.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LCCLKCONTROL</name>
<description>LC Clock Control</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKCYCLES</name>
<description>LC Oscillator Clock Cycles. </description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CLKCAL</name>
<description>LC Oscillator Calibration Start. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_IN_PROGRESS</name>
<description>A calibration operation is not in progress.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Start an oscillator calibration or a calibration operation is in progress.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RELOAD</name>
<description>LC Oscillator Reload Value. </description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>LCLIMITS</name>
<description>LC Counter Limits</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00FF00FF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MIN0</name>
<description>LC Counter 0 Minimum Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MAX0</name>
<description>LC Counter 0 Maximum Value. </description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MIN1</name>
<description>LC Counter 1 Minimum Value. </description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MAX1</name>
<description>LC Counter 1 Maximum Value. </description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>LCCOUNT</name>
<description>LC Counters</description>
<addressOffset>0x70</addressOffset>
<resetValue>0x0F000F00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCCOUNT0</name>
<description>LC Counter 0. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CD0</name>
<description>LC Counter 0 Discriminator. </description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LCCOUNT1</name>
<description>LC Counter 1. </description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CD1</name>
<description>LC Counter 1 Discriminator. </description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DBCONFIG</name>
<description>Pulse Counter Debounce Configuration</description>
<addressOffset>0x80</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LDBTH</name>
<description>Integrator Low Debounce. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HDBTH</name>
<description>Integrator High Debounce. </description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>INTEGDCEN</name>
<description>PC Integrator Disconnect Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Connect integrator to 24 bit counter state machine logic.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Disconnect the integrators from the IN0 and IN1 inputs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTEG0</name>
<description>PC Integrator 0 Output. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The integrator 0 output is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The integrator 0 output is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTEG1</name>
<description>PC Integrator 1 Output. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The integrator 1 output is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The integrator 1 output is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>COUNT0</name>
<description>Pulse Counter 0</description>
<addressOffset>0x90</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT0</name>
<description>Pulse Counter 0. </description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>COUNT1</name>
<description>Pulse Counter 1</description>
<addressOffset>0xa0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNT1</name>
<description>Pulse Counter 1. </description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>COMP0</name>
<description>Comparator 0</description>
<addressOffset>0xb0</addressOffset>
<resetValue>0x00FFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COMP0</name>
<description>Pulse Counter Comparator 0 Threshold. </description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMP1</name>
<description>Pulse Counter Comparator 1 Threshold</description>
<addressOffset>0xc0</addressOffset>
<resetValue>0x00FFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COMP1</name>
<description>Pulse Counter Comparator 1 Threshold. </description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Pulse Counter Status</description>
<addressOffset>0xd0</addressOffset>
<resetValue>0x3F400000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIRCHGI</name>
<description>Direction Change Interrupt Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A direction change did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A direction change occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVFI</name>
<description>Counter Overflow Interrupt Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Neither of the counters overflowed.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>One of the counters overflowed.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0I</name>
<description>Digital Comparator 0 Interrupt Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A digital comparator 0 and counter 0 match did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A digital comparator 0 and counter 0 match occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1I</name>
<description>Digital Comparator 1 Interrupt Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A digital comparator 1 and counter 1 match did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A digital comparator 1 and counter 1 match occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRANSI</name>
<description>Integrator Transition Interrupt Flag. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>An integrator output transition did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An integrator output transition occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QERRI</name>
<description>Quadrature Error Interrupt Flag. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A quadrature error did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A quadrature error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLSTOPI</name>
<description>Flutter Stop Interrupt Flag. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A flutter detection end event did not occur. </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A flutter detection end event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLSTARTI</name>
<description>Flutter Start Interrupt Flag. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A flutter detection start event did not occur. </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A flutter detection start event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIRCHGIEN</name>
<description>Direction Change Interrupt Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable direction change as an interrupt or wake up source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable direction change as an interrupt or wake up source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVFIEN</name>
<description>Counter Overflow Interrupt Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable counter overflows as an interrupt or wake up source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable counter overflows as an interrupt or wake up source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0IEN</name>
<description>Digital Comparator 0 Interrupt Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable comparator 0 as an interrupt or wake up source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable comparator 0 as an interrupt or wake up source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1IEN</name>
<description>Digital Comparator 1 Interrupt Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable comparator 1 as an interrupt or wake up source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable comparator 1 as an interrupt or wake up source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRANSIEN</name>
<description>Integrator Transition Interrupt Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable integrator transitions as an interrupt or wake up source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable integrator transitions as an interrupt or wake up source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>QERRIEN</name>
<description>Quadrature Error Interrupt Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable quadrature error as an interrupt or wake up source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable quadrature error as an interrupt or wake up source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLSTOPIEN</name>
<description>Flutter Stop Interrupt Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable flutter detection end events as an interrupt or wake up source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable flutter detection end events as an interrupt or wake up source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLSTARTIEN</name>
<description>Flutter Start Interrupt Enable. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable flutter detection start events as an interrupt or wake up source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable flutter detection start events as an interrupt or wake up source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IN0</name>
<description>Integrator 0 Output. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The integrator 0 output is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The integrator 0 output is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IN1</name>
<description>Integrator 1 Output. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The integrator 1 output is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The integrator 1 output is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IN0PREV</name>
<description>Previous Integrator 0 Output. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The previous integrator 0 output was low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The previous integrator 0 output was high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IN1PREV</name>
<description>Previous Integrator 1 Output. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The previous integrator 1 output was low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The previous integrator 1 output was high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STATE</name>
<description>Pulse Counter State. </description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>ST0</name>
<description>The pulse counter is in state 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ST1</name>
<description>The pulse counter is in state 1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ST2</name>
<description>The pulse counter is in state 2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ST3</name>
<description>The pulse counter is in state 3.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIRF</name>
<description>Direction Flag. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>COUNTER_CLOCKWISE</name>
<description>The current direction is counter-clockwise.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLOCKWISE</name>
<description>The current direction is clockwise.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLF</name>
<description>Flutter Detected Flag. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The switch operates normally.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A flutter event was detected.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIRHIST</name>
<description>Direction History . </description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CMP0OUT</name>
<description>Comparator 0 Output. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The output of comparator 0 is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The output of comparator 0 is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1OUT</name>
<description>Comparator 1 Output. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The output of comparator 1 is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The output of comparator1 is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DEBUGEN</name>
<description>Calibration</description>
<addressOffset>0xe0</addressOffset>
<resetValue>0x00000624</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DBGOEN</name>
<description>Debug Output Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>AES_0</name>
<version>B</version>
<description>None</description>
<groupName>AES_0</groupName>
<baseAddress>0x40027000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>AES0_IRQn</name>
<value>35</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>XFRSTA</name>
<description>AES Transfer Start. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>START</name>
<description>Start the AES operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>KEYCPEN</name>
<description>Key Capture Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable key capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable key capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EDMD</name>
<description>Encryption/Decryption Mode. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DECRYPT</name>
<description>AES module performs a decryption operation</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENCRYPT</name>
<description>AES module performs an encryption operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWMDEN</name>
<description>Software Mode Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable software mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable software mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BEN</name>
<description>Bypass AES Operation Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not bypass AES operations.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Bypass AES operations.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XOREN</name>
<description>XOR Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>XOR_DISABLED</name>
<description>Disable the XOR paths.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>XOR_INPUT</name>
<description>Enable the XOR input path, disable the XOR output path.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>XOR_OUTPUT</name>
<description>Disable the XOR input path, enable the XOR output path.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HCTREN</name>
<description>Hardware Counter Mode Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable hardware counter mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable hardware counter mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HCBCEN</name>
<description>Hardware Cipher-Block Chaining Mode Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable hardware cipher-block chaining (CBC) mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable hardware cipher-block chaining (CBC) mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>KEYSIZE</name>
<description>Keystore Size Select. </description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>KEY128</name>
<description>Key is composed of 128 bits.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>KEY192</name>
<description>Key is composed of 192 bits.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>KEY256</name>
<description>Key is composed of 256 bits.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERRIEN</name>
<description>Error Interrupt Enable. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the error interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the error interrupt. An interrupt is generated when the Input/Output Data FIFO Overun (DORI), Input/Output Data FIFO Underun (DURI), or XOR Data FIFO Overrun (XORI) flags are set.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCIEN</name>
<description>Operation Complete Interrupt Enable. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the operation complete interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the operation complete interrupt. An interrupt is generated when the Operation Complete Interrupt (OCI) flag is set.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>AES Debug Mode. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the AES module to halt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RUN</name>
<description>The AES module will continue to operate while the core is halted in debug mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET</name>
<description>Module Soft Reset. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>AES module is not in soft reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>AES module is in soft reset and none of the module bits can be accessed.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>XFRSIZE</name>
<description>Number of Blocks</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>XFRSIZE</name>
<description>Transfer Size. </description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATAFIFO</name>
<description>Input/Output Data FIFO Access</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<readAction>modifyExternal</readAction>
<fields>
<field>
<name>DATAFIFO</name>
<description>Input/Output Data FIFO Access. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>XORFIFO</name>
<description>XOR Data FIFO Access</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>XORFIFO</name>
<description>XOR Data FIFO Access. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWKEY0</name>
<description>Hardware Key Word 0</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWKEY0</name>
<description>Hardware Key Word 0. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWKEY1</name>
<description>Hardware Key Word 1</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWKEY1</name>
<description>Hardware Key Word 1. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWKEY2</name>
<description>Hardware Key Word 2</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWKEY2</name>
<description>Hardware Key Word 2. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWKEY3</name>
<description>Hardware Key Word 3</description>
<addressOffset>0x70</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWKEY3</name>
<description>Hardware Key Word 3. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWKEY4</name>
<description>Hardware Key Word 4</description>
<addressOffset>0x80</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWKEY4</name>
<description>Hardware Key Word 4. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWKEY5</name>
<description>Hardware Key Word 5</description>
<addressOffset>0x90</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWKEY5</name>
<description>Hardware Key Word 5. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWKEY6</name>
<description>Hardware Key Word 6</description>
<addressOffset>0xa0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWKEY6</name>
<description>Hardware Key Word 6. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWKEY7</name>
<description>Hardware Key Word 7</description>
<addressOffset>0xb0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWKEY7</name>
<description>Hardware Key Word 7. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCTR0</name>
<description>Hardware Counter Word 0</description>
<addressOffset>0xc0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWCTR0</name>
<description>Hardware Counter Word 0. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCTR1</name>
<description>Hardware Counter Word 1</description>
<addressOffset>0xd0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWCTR1</name>
<description>Hardware Counter Word 1. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCTR2</name>
<description>Hardware Counter Word 2</description>
<addressOffset>0xe0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWCTR2</name>
<description>Hardware Counter Word 2. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCTR3</name>
<description>Hardware Counter Word 3</description>
<addressOffset>0xf0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HWCTR3</name>
<description>Hardware Counter Word 3. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Module Status</description>
<addressOffset>0x100</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFIFOLVL</name>
<description>Input/Output Data FIFO Level. </description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>EMPTY</name>
<description>Input/Output data FIFO is empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_BYTE</name>
<description>Input/Output data FIFO contains 1 byte.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_BYTES</name>
<description>Input/Output data FIFO contains 2 bytes.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_BYTES</name>
<description>Input/Output data FIFO contains 3 bytes.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>4_BYTES</name>
<description>Input/Output data FIFO contains 4 bytes.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>5_BYTES</name>
<description>Input/Output data FIFO contains 5 bytes.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>6_BYTES</name>
<description>Input/Output data FIFO contains 6 bytes.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>7_BYTES</name>
<description>Input/Output data FIFO contains 7 bytes.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BYTES</name>
<description>Input/Output data FIFO contains 8 bytes.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BYTES</name>
<description>Input/Output data FIFO contains 9 bytes.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>10_BYTES</name>
<description>Input/Output data FIFO contains 10 bytes.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>11_BYTES</name>
<description>Input/Output data FIFO contains 11 bytes.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>12_BYTES</name>
<description>Input/Output data FIFO contains 12 bytes.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>13_BYTES</name>
<description>Input/Output data FIFO contains 13 bytes.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>14_BYTES</name>
<description>Input/Output data FIFO contains 14 bytes.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>15_BYTES</name>
<description>Input/Output data FIFO contains 15 bytes.</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>FULL</name>
<description>Input/Output data FIFO contains 16 bytes (full).</description>
<value>16</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XFIFOLVL</name>
<description>XOR Data FIFO Level. </description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>EMPTY</name>
<description>XOR data FIFO is empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_BYTE</name>
<description>XOR data FIFO contains 1 byte.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_BYTES</name>
<description>XOR data FIFO contains 2 bytes.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_BYTES</name>
<description>XOR data FIFO contains 3 bytes.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>4_BYTES</name>
<description>XOR data FIFO contains 4 bytes.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>5_BYTES</name>
<description>XOR data FIFO contains 5 bytes.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>6_BYTES</name>
<description>XOR data FIFO contains 6 bytes.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>7_BYTES</name>
<description>XOR data FIFO contains 7 bytes.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BYTES</name>
<description>XOR data FIFO contains 8 bytes.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BYTES</name>
<description>XOR data FIFO contains 9 bytes.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>10_BYTES</name>
<description>XOR data FIFO contains 10 bytes.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>11_BYTES</name>
<description>XOR data FIFO contains 11 bytes.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>12_BYTES</name>
<description>XOR data FIFO contains 12 bytes.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>13_BYTES</name>
<description>XOR data FIFO contains 13 bytes.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>14_BYTES</name>
<description>XOR data FIFO contains 14 bytes.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>15_BYTES</name>
<description>XOR data FIFO contains 15 bytes.</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>FULL</name>
<description>XOR data FIFO contains 16 bytes (full).</description>
<value>16</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSYF</name>
<description>Module Busy Flag. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>AES module is not busy.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>AES module is completing an operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DURI</name>
<description>Input/Output Data FIFO Underrun Interrupt Flag. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>No input/output data FIFO underrun.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An input/output data FIFO underrun has occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DORI</name>
<description>Input/Output Data FIFO Overrun Interrupt Flag. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>No input/output data FIFO overrun.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An input/output data FIFO overrun has occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XORI</name>
<description>XOR Data FIFO Overrun Interrupt Flag. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>No XOR data FIFO overrun.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An XOR data FIFO overrun has occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OCI</name>
<description>Operation Complete Interrupt Flag. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>AES operation complete interrupt has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>AES operation complete interrupt occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CLKCTRL_0</name>
<version>A</version>
<description>None</description>
<groupName>CLKCTRL_0</groupName>
<baseAddress>0x4002d000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x10000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AHBSEL</name>
<description>AHB Clock Source Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LPOSC0</name>
<description>AHB clock source is the Low-Power Oscillator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LFOSC0</name>
<description>AHB clock source is the Low-Frequency Oscillator.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RTC0TCLK</name>
<description>AHB clock source is the RTC0TCLK signal.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTOSC0</name>
<description>AHB clock source is the External Oscillator.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>VIORFCLK</name>
<description>AHB clock source is the VIORFCLK input pin.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>PLL0OSC</name>
<description>AHB clock source is the PLL.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>LPOSC0_DIV</name>
<description>AHB clock source is a divided version of the Low-Power Oscillator.</description>
<value>6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AHBDIV</name>
<description>AHB Clock Divider. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DIV1</name>
<description>AHB clock divided by 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV2</name>
<description>AHB clock divided by 2.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV4</name>
<description>AHB clock divided by 4.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV8</name>
<description>AHB clock divided by 8.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV16</name>
<description>AHB clock divided by 16.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV32</name>
<description>AHB clock divided by 32.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV64</name>
<description>AHB clock divided by 64.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV128</name>
<description>AHB clock divided by 128.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>APBDIV</name>
<description>APB Clock Divider. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DIV1</name>
<description>APB clock is the same as the AHB clock (divided by 1).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV2</name>
<description>APB clock is the AHB clock divided by 2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXTESEL</name>
<description>External Clock Edge Select. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>BOTH_EDGES</name>
<description>External clock generated by both rising and falling edges of the external oscillator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_ONLY</name>
<description>External clock generated by only rising edges of the external oscillator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OBUSYF</name>
<description>Oscillators Busy Flag. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>AHB and APB oscillators are not busy.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>AHB and APB oscillators are busy and the AHBSEL, AHBDIV, and APBDIV fields should not be modified.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VIORFCLKEN</name>
<description>VIORF Clock Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the VIORFCLK input.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the VIORFCLK input.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXTOSCEN</name>
<description>External Clock Input Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the EXTOSC input.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the EXTOSC input.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AHBCLKG</name>
<description>AHB Clock Gate</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000005</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RAMCEN</name>
<description>RAM Clock Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the AHB clock to the RAM.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the AHB clock to the RAM.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMACEN</name>
<description>DMA Clock Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the AHB clock to the DMA Controller.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the AHB clock to the DMA Controller.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLASHCEN</name>
<description>Flash Clock Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the AHB clock to the Flash.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the AHB clock to the Flash.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTM0EN</name>
<description>DTM0 Clock Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the AHB clock to Data Transfer Manager 0 (DTM0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the AHB clock to Data Transfer Manager 0 (DTM0).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTM1EN</name>
<description>DTM1 Clock Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the AHB clock to Data Transfer Manager 1 (DTM1).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the AHB clock to Data Transfer Manager 1 (DTM1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTM2EN</name>
<description>DTM2 Clock Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the AHB clock to Data Transfer Manager 2 (DTM2).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the AHB clock to Data Transfer Manager 2 (DTM2).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>APBCLKG0</name>
<description>APB Clock Gate 0</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLCTRLCEN</name>
<description>Flash Controller Clock Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the Flash Controller Module (FLASHCTRL0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the Flash Controller Module (FLASHCTRL0).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PB0CEN</name>
<description>Port Bank Clock Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the Port Bank Modules.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the Port Bank Modules.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART0CEN</name>
<description>USART0 Clock Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the USART0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the USART0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0CEN</name>
<description>UART0 Clock Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the UART0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the UART0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI0CEN</name>
<description>SPI0 Clock Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the SPI0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the SPI0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI1CEN</name>
<description>SPI1 Clock Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the SPI1 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the SPI1 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C0CEN</name>
<description>I2C0 Clock Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the I2C0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the I2C0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EPCA0CEN</name>
<description>EPCA0 Clock Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the EPCA0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the EPCA0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMER0CEN</name>
<description>TIMER0 Clock Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the TIMER0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the TIMER0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMER1CEN</name>
<description>TIMER1 Clock Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the TIMER1 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the TIMER1 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMER2CEN</name>
<description>TIMER2 Clock Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the TIMER2 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the TIMER2 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADC0CEN</name>
<description>SARADC0 Clock Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the SARADC0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the SARADC0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0CEN</name>
<description>CMP0 Clock Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the Comparator 0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the Comparator 0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1CEN</name>
<description>CMP1 Clock Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the Comparator 1 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the Comparator 1 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AES0CEN</name>
<description>AES0 Clock Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the AES0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the AES0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRC0CEN</name>
<description>CRC0 Clock Enable. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the CRC0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the CRC0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDAC0CEN</name>
<description>IDAC0 Clock Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the IDAC0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the IDAC0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPT0CEN</name>
<description>LPT0 Clock Enable. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the LPTIMER0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the LPTIMER0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACCTR0CEN</name>
<description>ACCTR0 Enable. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the ACCTR0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the ACCTR0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTM0CEN</name>
<description>DTM0 Clock Enable. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the DTM0 Register interface.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the DTM0 Register interface.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTM1CEN</name>
<description>DTM1 Clock Enable. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the DTM1 Register interface.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the DTM1 Register interface.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTM2CEN</name>
<description>DTM2 Clock Enable. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the DTM2 Register interface.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the DTM2 Register interface.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCD0CEN</name>
<description>LCD0 Clock Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the LCD0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the LCD0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCDC0CEN</name>
<description>DCDC0 Clock Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the DCDC0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the DCDC0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENCDEC0CEN</name>
<description>ENCDEC0 Clock Enable. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the ENCDEC0 Module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the ENCDEC0 Module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLL0CEN</name>
<description>PLL0 Clock Enable. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the PLL0 registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the PLL0 registers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>APBCLKG1</name>
<description>APB Clock Gate 1</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000002</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MISC0CEN</name>
<description>Miscellaneous 0 Clock Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC modules.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC modules.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MISC1CEN</name>
<description>Miscellaneous 1 Clock Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the APB clock to the Watchdog Timer (WDTIMER0) and DMA Crossbar (DMAXBAR0) modules.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the APB clock to the Watchdog Timer (WDTIMER0) and DMA Crossbar (DMAXBAR0) modules.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PM3CN</name>
<description>Power Mode 3 Clock Control</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PM3CSEL</name>
<description>Power Mode 3 Fast-Wake Clock Source. </description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LPOSC0_DIV</name>
<description>Power Mode 3 clock source is the Low-Power Oscillator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LFOSC0</name>
<description>Power Mode 3 clock source is the Low-Frequency Oscillator.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RTC0TCLK</name>
<description>Power Mode 3 clock source is the RTC0TCLK signal.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTOSC0</name>
<description>Power Mode 3 clock source is the External Oscillator.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>VIORFCLK</name>
<description>Power Mode 3 clock source is the VIORFCLK input pin.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>PLL0OSC</name>
<description>Power Mode 3 clock source is the PLL.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>LPOSC0</name>
<description>Power Mode 3 clock source is a divided version of the Low-Power Oscillator.</description>
<value>6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PM3CEN</name>
<description>Power Mode 3 Fast-Wake Clock Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the core clock when in Power Mode 3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The core clock is enabled and runs off the clock selected by PM3CSEL in Power Mode 3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONFIG</name>
<description>Configuration Options</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMSEL</name>
<description>Power Mode Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>PM8_DIS</name>
<description>Power Mode &lt; PM8.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PM8_EN</name>
<description>Power Mode = PM8.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CMP_0</name>
<version>A</version>
<description>None</description>
<groupName>Comparator</groupName>
<baseAddress>0x4001f000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CMP0_IRQn</name>
<value>30</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CMPFI</name>
<description>Falling Edge Interrupt Flag. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>No comparator falling edge has occurred since this flag was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A comparator falling edge occurred since last flag was cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPRI</name>
<description>Rising Edge Interrupt Flag. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>No comparator rising edge has occurred since this flag was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A comparator rising edge occurred since last flag was cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPOUT</name>
<description>Output State. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>POS_LT_NEG</name>
<description>Voltage on CMP+ &lt; CMP- (INVEN = 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POS_GT_NEG</name>
<description>Voltage on CMP+ &gt; CMP- (INVEN = 0).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPEN</name>
<description>Comparator Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the comparator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the comparator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODE</name>
<description>Input and Module Mode</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000800</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NMUX</name>
<description>Negative Input Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CMPNN0</name>
<description>Select CMPnN.0 (PB0.1).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN1</name>
<description>Select CMPnN.1 (PB0.2).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN2</name>
<description>Select CMPnN.2 (RESERVED).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN3</name>
<description>Select CMPnN.3 (RESERVED).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN4</name>
<description>Select CMPnN.4 (PB2.1).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN5</name>
<description>Select CMPnN.5 (PB2.5).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN6</name>
<description>Select CMPnN.6 (RESERVED).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN7</name>
<description>Select CMPnN.7 (PB3.0).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN8</name>
<description>Select CMPnN.8 (VREF Pin).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN9</name>
<description>Select CMPnN.9 (VBAT).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN10</name>
<description>Select CMPnN.10 (VDC).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN11</name>
<description>Select CMPnN.11 (Digital LDO Output).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN12</name>
<description>Select CMPnN.12 (Memory LDO Output).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN13</name>
<description>Select CMPnN.13 (Analog LDO Output).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN14</name>
<description>Select CMPnN.14 (VIO).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN15</name>
<description>Select CMPnN.15 (RESERVED).</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMUX</name>
<description>Positive Input Select. </description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CMPNP0</name>
<description>Select CMPnP.0 (PB0.0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP1</name>
<description>Select CMPnP.1 (PB0.3).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP2</name>
<description>Select CMPnP.2 (RESERVED).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP3</name>
<description>Select CMPnP.3 (RESERVED).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP4</name>
<description>Select CMPnP.4 (PB2.0).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP5</name>
<description>Select CMPnP.5 (PB2.4).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP6</name>
<description>Select CMPnP.6 (RESERVED).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP7</name>
<description>Select CMPnP.7 (RESERVED).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP8</name>
<description>Select CMPnP.8 (VREF Pin).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP9</name>
<description>Select CMPnP.9 (RESERVED).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP10</name>
<description>Select CMPnP.10 (Temperature Sensor Output).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP11</name>
<description>Select CMPnP.11 (Charge Pump / 2).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP12</name>
<description>Select CMPnP.12 (Digital LDO Output).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP13</name>
<description>Select CMPnP.13 (Memory LDO Output).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP14</name>
<description>Select CMPnP.14 (Analog LDO Output).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP15</name>
<description>Select CMPnP.15 (RESERVED).</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INMUX</name>
<description>Input MUX Select. </description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DIRECT</name>
<description>Connects the NMUX signal to CMP- and the PMUX signal to CMP+.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPP_VSS</name>
<description>Connects VSS to CMP- and the PMUX signal to CMP+.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPP_DAC</name>
<description>Connects the NMUX signal to CMP-, the PMUX signal to the Comparator DAC voltage reference, and the DAC output to CMP+.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPN_DAC</name>
<description>Connects the PMUX signal to CMP+, the NMUX signal to the Comparator DAC voltage reference, and the DAC output to CMP-.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPMD</name>
<description>Comparator Mode. </description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MODE0</name>
<description>Mode 0 (fastest response time, highest power consumption).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>Mode 1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>Mode 2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE3</name>
<description>Mode 3 (slowest response time, lowest power consumption).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIEN</name>
<description>Falling Edge Interrupt Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the comparator falling edge interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the comparator falling edge interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIEN</name>
<description>Rising Edge Interrupt Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the comparator rising edge interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the comparator rising edge interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACLVL</name>
<description>Comparator DAC Output Level. </description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>NWPUEN</name>
<description>Negative Input Weak Pullup Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the negative input weak pull up.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the negative input weak pull up.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWPUEN</name>
<description>Positive Input Weak Pullup Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the positive input weak pull up.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the positive input weak pull up.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPHYN</name>
<description>Negative Hysteresis Control. </description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable negative hysteresis.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NEG_5_MV</name>
<description>Set negative hysteresis to 5 mV.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>NEG_10_MV</name>
<description>Set negative hysteresis to 10 mV.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NEG_20_MV</name>
<description>Set negative hysteresis to 20 mV.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPHYP</name>
<description>Positive Hysteresis Control. </description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable positive hysteresis.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POS_5_MV</name>
<description>Set positive hysteresis to 5 mV.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POS_10_MV</name>
<description>Set positive hysteresis to 10 mV.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>POS_20_MV</name>
<description>Set positive hysteresis to 20 mV.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INVEN</name>
<description>Invert Comparator Output Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not invert the comparator output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Invert the comparator output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CMP_1</name>
<version>A</version>
<description>None</description>
<groupName>Comparator</groupName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CMP1_IRQn</name>
<value>31</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CMPFI</name>
<description>Falling Edge Interrupt Flag. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>No comparator falling edge has occurred since this flag was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A comparator falling edge occurred since last flag was cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPRI</name>
<description>Rising Edge Interrupt Flag. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>No comparator rising edge has occurred since this flag was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A comparator rising edge occurred since last flag was cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPOUT</name>
<description>Output State. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>POS_LT_NEG</name>
<description>Voltage on CMP+ &lt; CMP- (INVEN = 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POS_GT_NEG</name>
<description>Voltage on CMP+ &gt; CMP- (INVEN = 0).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPEN</name>
<description>Comparator Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the comparator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the comparator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODE</name>
<description>Input and Module Mode</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000800</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NMUX</name>
<description>Negative Input Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CMPNN0</name>
<description>Select CMPnN.0 (PB0.2).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN1</name>
<description>Select CMPnN.1 (RESERVED).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN2</name>
<description>Select CMPnN.2 (PB0.8).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN3</name>
<description>Select CMPnN.3 (RESERVED).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN4</name>
<description>Select CMPnN.4 (PB2.3).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN5</name>
<description>Select CMPnN.5 (PB2.7).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN6</name>
<description>Select CMPnN.6 (RESERVED).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN7</name>
<description>Select CMPnN.7 (PB3.2).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN8</name>
<description>Select CMPnN.8 (VREF Pin).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN9</name>
<description>Select CMPnN.9 (VBAT).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN10</name>
<description>Select CMPnN.10 (VDC).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN11</name>
<description>Select CMPnN.11 (Digital LDO Output).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN12</name>
<description>Select CMPnN.12 (Memory LDO Output).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN13</name>
<description>Select CMPnN.13 (Analog LDO Output).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN14</name>
<description>Select CMPnN.14 (VIO).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNN15</name>
<description>Select CMPnN.15 (RESERVED).</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMUX</name>
<description>Positive Input Select. </description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CMPNP0</name>
<description>Select CMPnP.0 (PB0.1).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP1</name>
<description>Select CMPnP.1 (RESERVED).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP2</name>
<description>Select CMPnP.2 (PB0.7).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP3</name>
<description>Select CMPnP.3 (RESERVED).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP4</name>
<description>Select CMPnP.4 (PB2.2).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP5</name>
<description>Select CMPnP.5 (PB2.6).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP6</name>
<description>Select CMPnP.6 (RESERVED).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP7</name>
<description>Select CMPnP.7 (PB3.1).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP8</name>
<description>Select CMPnP.8 (VREF Pin).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP9</name>
<description>Select CMPnP.9 (RESERVED).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP10</name>
<description>Select CMPnP.10 (Temperature Sensor Output).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP11</name>
<description>Select CMPnP.11 (Charge Pump / 2).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP12</name>
<description>Select CMPnP.12 (Digital LDO Output).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP13</name>
<description>Select CMPnP.13 (Memory LDO Output).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP14</name>
<description>Select CMPnP.14 (Analog LDO Output).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPNP15</name>
<description>Select CMPnP.15 (RESERVED).</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INMUX</name>
<description>Input MUX Select. </description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DIRECT</name>
<description>Connects the NMUX signal to CMP- and the PMUX signal to CMP+.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPP_VSS</name>
<description>Connects VSS to CMP- and the PMUX signal to CMP+.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPP_DAC</name>
<description>Connects the NMUX signal to CMP-, the PMUX signal to the Comparator DAC voltage reference, and the DAC output to CMP+.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CMPN_DAC</name>
<description>Connects the PMUX signal to CMP+, the NMUX signal to the Comparator DAC voltage reference, and the DAC output to CMP-.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPMD</name>
<description>Comparator Mode. </description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MODE0</name>
<description>Mode 0 (fastest response time, highest power consumption).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>Mode 1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>Mode 2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE3</name>
<description>Mode 3 (slowest response time, lowest power consumption).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIEN</name>
<description>Falling Edge Interrupt Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the comparator falling edge interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the comparator falling edge interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIEN</name>
<description>Rising Edge Interrupt Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the comparator rising edge interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the comparator rising edge interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DACLVL</name>
<description>Comparator DAC Output Level. </description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>NWPUEN</name>
<description>Negative Input Weak Pullup Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the negative input weak pull up.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the negative input weak pull up.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWPUEN</name>
<description>Positive Input Weak Pullup Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the positive input weak pull up.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the positive input weak pull up.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPHYN</name>
<description>Negative Hysteresis Control. </description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable negative hysteresis.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>NEG_5_MV</name>
<description>Set negative hysteresis to 5 mV.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>NEG_10_MV</name>
<description>Set negative hysteresis to 10 mV.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NEG_20_MV</name>
<description>Set negative hysteresis to 20 mV.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPHYP</name>
<description>Positive Hysteresis Control. </description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable positive hysteresis.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>POS_5_MV</name>
<description>Set positive hysteresis to 5 mV.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>POS_10_MV</name>
<description>Set positive hysteresis to 10 mV.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>POS_20_MV</name>
<description>Set positive hysteresis to 20 mV.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INVEN</name>
<description>Invert Comparator Output Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not invert the comparator output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Invert the comparator output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DCDC_0</name>
<version>A</version>
<description>None</description>
<groupName>DCDC_0</groupName>
<baseAddress>0x4004e000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DCDC_IRQn</name>
<value>40</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x0C0C0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDYLOWF</name>
<description>DC-DC Converter Ready Low Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The output voltage (VDC) is below the threshold set in the RDYLOWTH threshold field (RDYLOWTH).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The output voltage (VDC) is above the threshold set in the RDYLOWTH threshold field (RDYLOWTH).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDYHIGHF</name>
<description>DC-DC Converter Ready High Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The output voltage (VDC) has not exceeded 105% of the programmed output value.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The output voltage (VDC) has exceeded 105% of the programmed output value.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DROPOUTF</name>
<description>DC-DC Converter Dropout Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The input voltage (VBATDC) is more than 0.4 V above the output voltage (VDC). The DC-DC converter is not in dropout.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The input voltage (VBATDC) is less than 0.4 V above the output voltage (VDC). The DC-DC converter is in dropout, and firmware should enable the bypass switch (BEN=1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BGRDYF</name>
<description>Bandgap Ready Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The bandgap voltage is not above the threshold.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The bandgap voltage is above the threshold.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSCDIS</name>
<description>Oscillator Disable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Enable the DC-DC local oscillator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Disable the DC-DC local oscillator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKSEL</name>
<description>Clock Source Select. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DCDCOSC</name>
<description>Select the local DC-DC oscillator as the clock source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>APB</name>
<description>Select the APB clock as the clock source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Clock Divider. </description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DIV1</name>
<description>Use the APB clock divided by 1 as the converter switching frequency.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV2</name>
<description>Use the APB clock divided by 2 as the converter switching frequency.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV4</name>
<description>Use the APB clock divided by 4 as the converter switching frequency.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV8</name>
<description>Use the APB clock divided by 8 as the converter switching frequency.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV16</name>
<description>Use the APB clock divided by 16 as the converter switching frequency.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCSYNCEN</name>
<description>ADC Synchronization Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not synchronize the ADC to the DC-DC converter.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Synchronize the ADC to the DC-DC converter.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKINVEN</name>
<description>Clock Inversion Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not invert the APB clock input.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Invert the APB clock input.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCCLKINVEN</name>
<description>ADC Clock Inversion Enable. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not invert the ADC clock derived from the DC-DC switching frequency.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Invert the ADC clock derived from the DC-DC switching frequency.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUTVSEL</name>
<description>Output Voltage Select. </description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>MIEN</name>
<description>Module Interrupt Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DC-DC module interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable DC-DC module interrupts.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MINPWSEL</name>
<description>Minimum Pulse Width Select. </description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable pulse skipping.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>10_NS</name>
<description>Set the minimum pulse width to 10 ns.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>20_NS</name>
<description>Set the minimum pulse width to 20 ns.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>40_NS</name>
<description>Set the minimum pulse width to 40 ns.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSMD</name>
<description>Power Switch Mode. </description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SWSEL0</name>
<description>Mode 0. Set the M1 and M2 power switches to each use one MOSFET only.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SWSEL1</name>
<description>Mode 1. Set the M1 and M2 power switches to each use 2 MOSFETS in parallel.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SWSEL2</name>
<description>Mode 2. Set the M1 and M2 power switches to each use 3 MOSFETS in parallel.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SWSEL3</name>
<description>Mode 3. Set the M1 and M2 power switches to each use 4 MOSFETS in parallel.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ASYNCEN</name>
<description>Asynchronous Mode Enable. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Enable DC-DC synchronous mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable DC-DC asynchronous mode. This mode is more efficient for very light output loads.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ABEN</name>
<description>Automatic Bypass Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable automatic bypass.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable automatic bypass.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BEN</name>
<description>Bypass Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the MBYP bypass switch.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the MBYP bypass switch.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCDCEN</name>
<description>DC-DC Converter Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the DC-DC converter.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the DC-DC converter.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONFIG</name>
<description>Module Configuration</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00001F40</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ILIMIT</name>
<description>Inductor Peak Current Limit. </description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LIMIT1</name>
<description>Limit the peak inductor current to 200 mA.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>LIMIT2</name>
<description>Limit the peak inductor current to 300 mA.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>LIMIT3</name>
<description>Limit the peak inductor current to 400 mA.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>LIMIT4</name>
<description>Limit the peak inductor current to 500 mA.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>LIMIT5</name>
<description>Limit the peak inductor current to 600 mA.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>LIMIT6</name>
<description>Limit the peak inductor current to 700 mA.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>LIMIT7</name>
<description>Limit the peak inductor current to 800 mA.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTMD</name>
<description>Interrupt Mode. </description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>OUTPUT_TOO_LOW</name>
<description>Generate an interrupt when the regulated converter output voltage is too low, according to the RDYLOWF flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTPUT_NOT_TOO_LOW</name>
<description>Generate an interrupt when the regulated converter output voltage is not too low according to the RDYLOWF flag.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>OUT_OF_REG</name>
<description>Generate an interrupt when the output voltage is out of regulation. The converter output can be either too high or too low, according to the RDYLOWF and RDYHIGHF flags.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>IN_REG</name>
<description>Generate an interrupt when the output voltage is in regulation.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDYLOWTH</name>
<description>Converter Ready Low Threshold. </description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>95_PERCENT</name>
<description>Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 95% of the programmed output voltage.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>90_PERCENT</name>
<description>Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 90% of the programmed output voltage.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>85_PERCENT</name>
<description>Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 85% of the programmed output voltage.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>80_PERCENT</name>
<description>Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 80% of the programmed output voltage.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMACTRL_0</name>
<version>A</version>
<description>None</description>
<groupName>DMA</groupName>
<baseAddress>0x40036000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>STATUS</name>
<description>Controller Status</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00090000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMAENSTS</name>
<description>DMA Enable Status. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>DMA controller is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>DMA controller is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STATE</name>
<description>State Machine State. </description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>IDLE</name>
<description>Idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>READING_CHANNEL_CONFIG</name>
<description>Reading channel controller data.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>READING_SOURCE_POINTER</name>
<description>Reading source data end pointer.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>READING_DEST_POINTER</name>
<description>Reading destination data end pointer.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>READING_SOURCE_DATA</name>
<description>Reading source data.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>WRITING_DEST_DATA</name>
<description>Writing destination data.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>WAITING_DMA_REQ_CLEAR</name>
<description>Waiting for a DMA request to clear.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>WRITING_CHANNEL_CONFIG</name>
<description>Writing channel controller data.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>STALLED</name>
<description>Stalled.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DONE</name>
<description>Done.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>SCATTER_GATHER_TRANSITION</name>
<description>Peripheral scatter-gather transition.</description>
<value>10</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NUMCHAN</name>
<description>Number of Supported DMA Channels. </description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CONFIG</name>
<description>Controller Configuration</description>
<addressOffset>0x4</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMAEN</name>
<description>DMA Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the DMA controller.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the DMA controller.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BASEPTR</name>
<description>Base Pointer</description>
<addressOffset>0x8</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BASEPTR</name>
<description>Control Base Pointer. </description>
<bitOffset>9</bitOffset>
<bitWidth>23</bitWidth>
</field>
</fields>
</register>
<register>
<name>ABASEPTR</name>
<description>Alternate Base Pointer</description>
<addressOffset>0xc</addressOffset>
<resetValue>0x00000100</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ABASEPTR</name>
<description>Alternate Control Base Pointer. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CHSTATUS</name>
<description>Channel Status</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x000003FF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Status. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_WAITING</name>
<description>DMA Channel 0 is not waiting for a data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WAITING</name>
<description>DMA Channel 0 is waiting for a data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Status. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_WAITING</name>
<description>DMA Channel 1 is not waiting for a data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WAITING</name>
<description>DMA Channel 1 is waiting for a data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2</name>
<description>Channel 2 Status. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_WAITING</name>
<description>DMA Channel 2 is not waiting for a data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WAITING</name>
<description>DMA Channel 2 is waiting for a data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3</name>
<description>Channel 3 Status. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_WAITING</name>
<description>DMA Channel 3 is not waiting for a data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WAITING</name>
<description>DMA Channel 3 is waiting for a data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4</name>
<description>Channel 4 Status. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_WAITING</name>
<description>DMA Channel 4 is not waiting for a data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WAITING</name>
<description>DMA Channel 4 is waiting for a data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5</name>
<description>Channel 5 Status. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_WAITING</name>
<description>DMA Channel 5 is not waiting for a data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WAITING</name>
<description>DMA Channel 5 is waiting for a data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6</name>
<description>Channel 6 Status. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_WAITING</name>
<description>DMA Channel 6 is not waiting for a data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WAITING</name>
<description>DMA Channel 6 is waiting for a data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7</name>
<description>Channel 7 Status. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_WAITING</name>
<description>DMA Channel 7 is not waiting for a data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WAITING</name>
<description>DMA Channel 7 is waiting for a data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH8</name>
<description>Channel 8 Status. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_WAITING</name>
<description>DMA Channel 8 is not waiting for a data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WAITING</name>
<description>DMA Channel 8 is waiting for a data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9</name>
<description>Channel 9 Status. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_WAITING</name>
<description>DMA Channel 9 is not waiting for a data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>WAITING</name>
<description>DMA Channel 9 is waiting for a data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHSWRCN</name>
<description>Channel Software Request Control</description>
<addressOffset>0x14</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Software Request. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOT_GENERATE_SW_REQ</name>
<description>DMA Channel 0 does not generate a software data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GENERATE_SW_REQ</name>
<description>DMA Channel 0 generates a software data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Software Request. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOT_GENERATE_SW_REQ</name>
<description>DMA Channel 1 does not generate a software data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GENERATE_SW_REQ</name>
<description>DMA Channel 1 generates a software data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2</name>
<description>Channel 2 Software Request. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOT_GENERATE_SW_REQ</name>
<description>DMA Channel 2 does not generate a software data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GENERATE_SW_REQ</name>
<description>DMA Channel 2 generates a software data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3</name>
<description>Channel 3 Software Request. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOT_GENERATE_SW_REQ</name>
<description>DMA Channel 3 does not generate a software data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GENERATE_SW_REQ</name>
<description>DMA Channel 3 generates a software data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4</name>
<description>Channel 4 Software Request. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOT_GENERATE_SW_REQ</name>
<description>DMA Channel 4 does not generate a software data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GENERATE_SW_REQ</name>
<description>DMA Channel 4 generates a software data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5</name>
<description>Channel 5 Software Request. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOT_GENERATE_SW_REQ</name>
<description>DMA Channel 5 does not generate a software data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GENERATE_SW_REQ</name>
<description>DMA Channel 5 generates a software data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6</name>
<description>Channel 6 Software Request. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOT_GENERATE_SW_REQ</name>
<description>DMA Channel 6 does not generate a software data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GENERATE_SW_REQ</name>
<description>DMA Channel 6 generates a software data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7</name>
<description>Channel 7 Software Request. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOT_GENERATE_SW_REQ</name>
<description>DMA Channel 7 does not generate a software data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GENERATE_SW_REQ</name>
<description>DMA Channel 7 generates a software data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH8</name>
<description>Channel 8 Software Request. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOT_GENERATE_SW_REQ</name>
<description>DMA Channel 8 does not generate a software data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GENERATE_SW_REQ</name>
<description>DMA Channel 8 generates a software data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9</name>
<description>Channel 9 Software Request. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DO_NOT_GENERATE_SW_REQ</name>
<description>DMA Channel 9 does not generate a software data request.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GENERATE_SW_REQ</name>
<description>DMA Channel 9 generates a software data request.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHREQMSET</name>
<description>Channel Request Mask Set</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Request Mask Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 0 peripheral data requests enabled. 1: DMA Channel 0 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 0 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Request Mask Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 1 peripheral data requests enabled. 1: DMA Channel 1 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 1 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2</name>
<description>Channel 2 Request Mask Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 2 peripheral data requests enabled. 1: DMA Channel 2 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 2 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3</name>
<description>Channel 3 Request Mask Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 3 peripheral data requests enabled. 1: DMA Channel 3 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 3 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4</name>
<description>Channel 4 Request Mask Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 4 peripheral data requests enabled. 1: DMA Channel 4 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 4 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5</name>
<description>Channel 5 Request Mask Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 5 peripheral data requests enabled. 1: DMA Channel 5 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 5 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6</name>
<description>Channel 6 Request Mask Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 6 peripheral data requests enabled. 1: DMA Channel 6 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 6 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7</name>
<description>Channel 7 Request Mask Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 7 peripheral data requests enabled. 1: DMA Channel 7 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 7 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH8</name>
<description>Channel 8 Request Mask Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 8 peripheral data requests enabled. 1: DMA Channel 8 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 8 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9</name>
<description>Channel 9 Request Mask Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 9 peripheral data requests enabled. 1: DMA Channel 9 peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). 1: Disable DMA Channel 9 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHREQMCLR</name>
<description>Channel Request Mask Clear</description>
<addressOffset>0x24</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Request Mask Disable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Enable DMA Channel 0 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Request Mask Disable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Enable DMA Channel 1 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2</name>
<description>Channel 2 Request Mask Disable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Enable DMA Channel 2 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3</name>
<description>Channel 3 Request Mask Disable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Enable DMA Channel 3 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4</name>
<description>Channel 4 Request Mask Disable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Enable DMA Channel 4 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5</name>
<description>Channel 5 Request Mask Disable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Enable DMA Channel 5 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6</name>
<description>Channel 6 Request Mask Disable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Enable DMA Channel 6 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7</name>
<description>Channel 7 Request Mask Disable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Enable DMA Channel 7 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH8</name>
<description>Channel 8 Request Mask Disable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Enable DMA Channel 8 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9</name>
<description>Channel 9 Request Mask Disable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Enable DMA Channel 9 peripheral data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHENSET</name>
<description>Channel Enable Set</description>
<addressOffset>0x28</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 0 disabled. 1: DMA Channel 0 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 1 disabled. 1: DMA Channel 1 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2</name>
<description>Channel 2 Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 2 disabled. 1: DMA Channel 2 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3</name>
<description>Channel 3 Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 3 disabled. 1: DMA Channel 3 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4</name>
<description>Channel 4 Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 4 disabled. 1: DMA Channel 4 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 4.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5</name>
<description>Channel 5 Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 5 disabled. 1: DMA Channel 5 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 5.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6</name>
<description>Channel 6 Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 6 disabled. 1: DMA Channel 6 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 6.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7</name>
<description>Channel 7 Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 7 disabled. 1: DMA Channel 7 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 7.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH8</name>
<description>Channel 8 Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 8 disabled. 1: DMA Channel 8 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 8.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9</name>
<description>Channel 9 Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 9 disabled. 1: DMA Channel 9 enabled. Write: 0: No effect (use CHENCLR to clear). 1: Enable DMA Channel 9.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHENCLR</name>
<description>Channel Enable Clear</description>
<addressOffset>0x2c</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Disable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA Channel 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Disable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA Channel 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2</name>
<description>Channel 2 Disable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA Channel 2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3</name>
<description>Channel 3 Disable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA Channel 3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4</name>
<description>Channel 4 Disable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA Channel 4.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5</name>
<description>Channel 5 Disable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA Channel 5.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6</name>
<description>Channel 6 Disable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA Channel 6.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7</name>
<description>Channel 7 Disable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA Channel 7.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH8</name>
<description>Channel 8 Disable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA Channel 8.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9</name>
<description>Channel 9 Disable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA Channel 9.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHALTSET</name>
<description>Channel Alternate Select Set</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Alternate Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 0 is using primary data structure. 1: DMA Channel 0 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Alternate Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 1 is using primary data structure. 1: DMA Channel 1 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2</name>
<description>Channel 2 Alternate Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 2 is using primary data structure. 1: DMA Channel 2 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3</name>
<description>Channel 3 Alternate Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 3 is using primary data structure. 1: DMA Channel 3 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4</name>
<description>Channel 4 Alternate Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 4 is using primary data structure. 1: DMA Channel 4 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 4.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5</name>
<description>Channel 5 Alternate Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 5 is using primary data structure. 1: DMA Channel 5 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 5.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6</name>
<description>Channel 6 Alternate Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 6 is using primary data structure. 1: DMA Channel 6 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 6.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7</name>
<description>Channel 7 Alternate Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 7 is using primary data structure. 1: DMA Channel 7 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 7.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH8</name>
<description>Channel 8 Alternate Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 8 is using primary data structure. 1: DMA Channel 8 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 8.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9</name>
<description>Channel 9 Alternate Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 9 is using primary data structure. 1: DMA Channel 9 is using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: Use the alternate data structure for DMA Channel 9.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHALTCLR</name>
<description>Channel Alternate Select Clear</description>
<addressOffset>0x34</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 Alternate Disable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the primary data structure for DMA Channel 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1</name>
<description>Channel 1 Alternate Disable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the primary data structure for DMA Channel 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2</name>
<description>Channel 2 Alternate Disable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the primary data structure for DMA Channel 2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3</name>
<description>Channel 3 Alternate Disable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the primary data structure for DMA Channel 3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4</name>
<description>Channel 4 Alternate Disable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the primary data structure for DMA Channel 4.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5</name>
<description>Channel 5 Alternate Disable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the primary data structure for DMA Channel 5.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6</name>
<description>Channel 6 Alternate Disable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the primary data structure for DMA Channel 6.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7</name>
<description>Channel 7 Alternate Disable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the primary data structure for DMA Channel 7.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH8</name>
<description>Channel 8 Alternate Disable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the primary data structure for DMA Channel 8.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9</name>
<description>Channel 9 Alternate Disable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the primary data structure for DMA Channel 9.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHHPSET</name>
<description>Channel High Priority Set</description>
<addressOffset>0x38</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 High Priority Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 0 is using the default priority level. 1: DMA Channel 0 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1</name>
<description>Channel 1 High Priority Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 1 is using the default priority level. 1: DMA Channel 1 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2</name>
<description>Channel 2 High Priority Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 2 is using the default priority level. 1: DMA Channel 2 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3</name>
<description>Channel 3 High Priority Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 3 is using the default priority level. 1: DMA Channel 3 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4</name>
<description>Channel 4 High Priority Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 4 is using the default priority level. 1: DMA Channel 4 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 4.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5</name>
<description>Channel 5 High Priority Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 5 is using the default priority level. 1: DMA Channel 5 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 5.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6</name>
<description>Channel 6 High Priority Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 6 is using the default priority level. 1: DMA Channel 6 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 6.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7</name>
<description>Channel 7 High Priority Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 7 is using the default priority level. 1: DMA Channel 7 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 7.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH8</name>
<description>Channel 8 High Priority Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 8 is using the default priority level. 1: DMA Channel 8 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 8.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9</name>
<description>Channel 9 High Priority Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: 0: DMA Channel 9 is using the default priority level. 1: DMA Channel 9 is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: Use the high priority level for DMA Channel 9.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHHPCLR</name>
<description>Channel High Priority Clear</description>
<addressOffset>0x3c</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0</name>
<description>Channel 0 High Priority Disable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the high default level for DMA Channel 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1</name>
<description>Channel 1 High Priority Disable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the high default level for DMA Channel 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2</name>
<description>Channel 2 High Priority Disable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the high default level for DMA Channel 2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3</name>
<description>Channel 3 High Priority Disable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the high default level for DMA Channel 3.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4</name>
<description>Channel 4 High Priority Disable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the high default level for DMA Channel 4.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5</name>
<description>Channel 5 High Priority Disable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the high default level for DMA Channel 5.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6</name>
<description>Channel 6 High Priority Disable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the high default level for DMA Channel 6.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7</name>
<description>Channel 7 High Priority Disable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the high default level for DMA Channel 7.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH8</name>
<description>Channel 8 High Priority Disable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the high default level for DMA Channel 8.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9</name>
<description>Channel 9 High Priority Disable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESERVED</name>
<description>No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the high default level for DMA Channel 9.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BERRCLR</name>
<description>Bus Error Clear</description>
<addressOffset>0x4c</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ERROR</name>
<description>DMA Bus Error Clear. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CLEAR</name>
<description>Read: 0: DMA error did not occur. 1: DMA error occurred since the last time ERROR was cleared. Write: 0: No effect. 1: Clear the DMA error flag.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMAXBAR_0</name>
<version>A</version>
<description>None</description>
<groupName>DMA</groupName>
<baseAddress>0x40037000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMAERR_IRQn</name>
<value>5</value>
</interrupt>
<interrupt>
<name>DMACH0_IRQn</name>
<value>6</value>
</interrupt>
<interrupt>
<name>DMACH1_IRQn</name>
<value>7</value>
</interrupt>
<interrupt>
<name>DMACH2_IRQn</name>
<value>8</value>
</interrupt>
<interrupt>
<name>DMACH3_IRQn</name>
<value>9</value>
</interrupt>
<interrupt>
<name>DMACH4_IRQn</name>
<value>10</value>
</interrupt>
<interrupt>
<name>DMACH5_IRQn</name>
<value>11</value>
</interrupt>
<interrupt>
<name>DMACH6_IRQn</name>
<value>12</value>
</interrupt>
<interrupt>
<name>DMACH7_IRQn</name>
<value>13</value>
</interrupt>
<interrupt>
<name>DMACH8_IRQn</name>
<value>14</value>
</interrupt>
<interrupt>
<name>DMACH9_IRQn</name>
<value>15</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>DMAXBAR0</name>
<description>Channel 0-7 Trigger Select</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0SEL</name>
<description>DMA Channel 0 Peripheral Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTM0_A</name>
<description>Service DTM0 A data requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI0_TX</name>
<description>Service SPI0 TX data requests.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>AES0_TX</name>
<description>Service AES0 TX data requests.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>USART0_RX</name>
<description>Service USART0 RX data requests.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0_RX</name>
<description>Service I2C0 RX data requests.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0_TX</name>
<description>Service I2C0 TX data requests.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCA0_CAPTURE</name>
<description>Service EPCA0 capture data requests.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER0L</name>
<description>Service TIMER0L overflow data requests.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER0H</name>
<description>Service TIMER0H overflow data requests.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T0_RISE</name>
<description>Service DMA0T0 rising edge data requests.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T0_FALL</name>
<description>Service DMA0T0 falling edge data requests.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>UNASSIGNED</name>
<description>Unassigned.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH1SEL</name>
<description>DMA Channel 1 Peripheral Select. </description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTM0_B</name>
<description>Service DTM0 B data requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI0_RX</name>
<description>Service SPI0 RX data requests.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>AES0_RX</name>
<description>Service AES0 RX data requests.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>USART0_TX</name>
<description>Service USART0 TX data requests.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>SARADC0</name>
<description>Service SARADC0 data requests.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCA0_CAPTURE</name>
<description>Service EPCA0 capture data requests.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCA0_CONTROL</name>
<description>Service EPCA0 control data requests.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER1L</name>
<description>Service TIMER1L overflow data requests.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER1H</name>
<description>Service TIMER1H overflow data requests.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T1_RISE</name>
<description>Service DMA0T1 rising edge data requests.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T1_FALL</name>
<description>Service DMA0T1 falling edge data requests.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>UNASSIGNED</name>
<description>Unassigned.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH2SEL</name>
<description>DMA Channel 2 Peripheral Select. </description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTM0_C</name>
<description>Service DTM0 C data requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTM2_A</name>
<description>Service DTM2 A data requests.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ENCDEC0_TX</name>
<description>Service ENCDEC0 TX data requests.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>AES0_XOR</name>
<description>Service AES0 XOR data requests.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI1_TX</name>
<description>Service SPI1 TX data requests.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>USART0_RX</name>
<description>Service USART0 RX data requests.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0_RX</name>
<description>Service I2C0 RX data requests.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>IDAC0</name>
<description>Service IDAC0 data requests.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER0L</name>
<description>Service TIMER0L overflow data requests.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER0H</name>
<description>Service TIMER0H overflow data requests.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T0_RISE</name>
<description>Service DMA0T0 rising edge data requests.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T0_FALL</name>
<description>Service DMA0T0 falling edge data requests.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>UNASSIGNED</name>
<description>Unassigned.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH3SEL</name>
<description>DMA Channel 3 Peripheral Select. </description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTM0_D</name>
<description>Service DTM0 D data requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTM2_B</name>
<description>Service DTM2 B data requests.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ENCDEC0_RX</name>
<description>Service ENCDEC0 RX data requests.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI1_RX</name>
<description>Service SPI1 RX data requests.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>USART0_TX</name>
<description>Service USART0 TX data requests.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0_RX</name>
<description>Service I2C0 RX data requests.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0_TX</name>
<description>Service I2C0 TX data requests.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER1L</name>
<description>Service TIMER1L overflow data requests.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER1H</name>
<description>Service TIMER1H overflow data requests.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T1_RISE</name>
<description>Service DMA0T1 rising edge data requests.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T1_FALL</name>
<description>Service DMA0T1 falling edge data requests.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>UNASSIGNED</name>
<description>Unassigned.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH4SEL</name>
<description>DMA Channel 4 Peripheral Select. </description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTM1_A</name>
<description>Service DTM1 A data requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTM2_C</name>
<description>Service DTM2 C data requests.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI0_TX</name>
<description>Service SPI1 TX data requests.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>AES0_TX</name>
<description>Service AES0 TX data requests.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>SARADC0</name>
<description>Service SARADC0 data requests.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCA0_CAPTURE</name>
<description>Service EPCA0 capture data requests.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCA0_CONTROL</name>
<description>Service EPCA0 control data requests.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER0L</name>
<description>Service TIMER0L overflow data requests.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER0H</name>
<description>Service TIMER0H overflow data requests.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T0_RISE</name>
<description>Service DMA0T0 rising edge data requests.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T0_FALL</name>
<description>Service DMA0T0 falling edge data requests.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>UNASSIGNED</name>
<description>Unassigned.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH5SEL</name>
<description>DMA Channel 5 Peripheral Select. </description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTM1_B</name>
<description>Service DTM1 B data requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTM2_D</name>
<description>Service DTM2 D data requests.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI0_RX</name>
<description>Service SPI0 RX data requests.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>AES0_RX</name>
<description>Service AES0 RX data requests.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>USART0_RX</name>
<description>Service USART0 RX data requests.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0_RX</name>
<description>Service I2C0 RX data requests.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>IDAC0</name>
<description>Service IDAC0 data requests.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCA0_CONTROL</name>
<description>Service EPCA0 control data requests.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER1L</name>
<description>Service TIMER1L overflow data requests.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER1H</name>
<description>Service TIMER1H overflow data requests.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T1_RISE</name>
<description>Service DMA0T1 rising edge data requests.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T1_FALL</name>
<description>Service DMA0T1 falling edge data requests.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>UNASSIGNED</name>
<description>Unassigned.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH6SEL</name>
<description>DMA Channel 6 Peripheral Select. </description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTM1_C</name>
<description>Service DTM1 C data requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTM2_A</name>
<description>Service DTM2 A data requests.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ENCDEC0_TX</name>
<description>Service ENCDEC0 TX data requests.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>AES0_XOR</name>
<description>Service AES0 XOR data requests.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>USART0_TX</name>
<description>Service USART0 TX data requests.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0_RX</name>
<description>Service I2C0 RX data requests.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0_TX</name>
<description>Service I2C0 TX data requests.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>SARADC0</name>
<description>Service SARADC0 data requests.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER0L</name>
<description>Service TIMER0L overflow data requests.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER0H</name>
<description>Service TIMER0H overflow data requests.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T0_RISE</name>
<description>Service DMA0T0 rising edge data requests.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T0_FALL</name>
<description>Service DMA0T0 falling edge data requests.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>UNASSIGNED</name>
<description>Unassigned.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH7SEL</name>
<description>DMA Channel 7 Peripheral Select. </description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTM1_D</name>
<description>Service DTM1 D data requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTM2_B</name>
<description>Service DTM2 B data requests.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ENCDEC0_RX</name>
<description>Service ENCDEC0 RX data requests.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI1_TX</name>
<description>Service SPI1 TX data requests.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>USART0_RX</name>
<description>Service USART0 RX data requests.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>IDAC0</name>
<description>Service IDAC0 data requests.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER1L</name>
<description>Service TIMER1L overflow data requests.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER1H</name>
<description>Service TIMER1H overflow data requests.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T1_RISE</name>
<description>Service DMA0T1 rising edge data requests.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T1_FALL</name>
<description>Service DMA0T1 falling edge data requests.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>UNASSIGNED</name>
<description>Unassigned.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DMAXBAR1</name>
<description>Channel 8-15 Trigger Select</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH8SEL</name>
<description>DMA Channel 8 Peripheral Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTM2_C</name>
<description>Service DTM2 C data requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI0_TX</name>
<description>Service SPI0 TX data requests.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI1_RX</name>
<description>Service SPI1 RX data requests.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>USART0_TX</name>
<description>Service USART0 TX data requests.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0_RX</name>
<description>Service I2C0 RX data requests.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>SARADC0</name>
<description>Service SARADC0 data requests.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCA0_CAPTURE</name>
<description>Service EPCA0 capture data requests.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER0L</name>
<description>Service TIMER0L overflow data requests.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER0H</name>
<description>Service TIMER0H overflow data requests.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T0_RISE</name>
<description>Service DMA0T0 rising edge data requests.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T0_FALL</name>
<description>Service DMA0T0 falling edge data requests.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>UNASSIGNED</name>
<description>Unassigned.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CH9SEL</name>
<description>DMA Channel 9 Peripheral Select. </description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTM2_D</name>
<description>Service DTM2 D data requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI0_RX</name>
<description>Service SPI0 TX data requests.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0_RX</name>
<description>Service I2C0 RX data requests.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0_TX</name>
<description>Service I2C0 TX data requests.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>IDAC0</name>
<description>Service IDAC0 data requests.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCA0_CAPTURE</name>
<description>Service EPCA0 capture data requests.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCA0_CONTROL</name>
<description>Service EPCA0 control data requests.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER1L</name>
<description>Service TIMER1L overflow data requests.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER1H</name>
<description>Service TIMER1H overflow data requests.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T1_RISE</name>
<description>Service DMA0T1 rising edge data requests.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DMA0T1_FALL</name>
<description>Service DMA0T1 falling edge data requests.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>UNASSIGNED</name>
<description>Unassigned.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DTM_0</name>
<version>A</version>
<description>None</description>
<groupName>DTM</groupName>
<baseAddress>0x4004a000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DTM0_IRQn</name>
<value>32</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x0600FF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STCOUNT</name>
<description>Active State Counter. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ST</name>
<description>Active State. </description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>LASTST</name>
<description>Last State. </description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INHSSEL</name>
<description>Inhibit Signal Select. </description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTMNINH0</name>
<description>Select inhibit signal source DTMnINH.0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH1</name>
<description>Select inhibit signal source DTMnINH.1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH2</name>
<description>Select inhibit signal source DTMnINH.2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH3</name>
<description>Select inhibit signal source DTMnINH.3.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH4</name>
<description>Select inhibit signal source DTMnINH.4.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH5</name>
<description>Select inhibit signal source DTMnINH.5.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH6</name>
<description>Select inhibit signal source DTMnINH.6.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH7</name>
<description>Select inhibit signal source DTMnINH.7.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH8</name>
<description>Select inhibit signal source DTMnINH.8.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH9</name>
<description>Select inhibit signal source DTMnINH.9.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH10</name>
<description>Select inhibit signal source DTMnINH.10.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH11</name>
<description>Select inhibit signal source DTMnINH.11.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH12</name>
<description>Select inhibit signal source DTMnINH.12.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH13</name>
<description>Select inhibit signal source DTMnINH.13.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH14</name>
<description>Select inhibit signal source DTMnINH.14.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH15</name>
<description>Select inhibit signal source DTMnINH.15.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>Debug Mode. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The DTM module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the DTM module to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INHF</name>
<description>Inhibit Status Flag. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The inhibit signal is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The inhibit signal is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSTREQF</name>
<description>Destination Peripheral DMA Request Status Flag. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The destination peripheral did not request a DMA transfer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The destination peripheral requested a DMA transfer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRCREQF</name>
<description>Source Peripheral DMA Request Status Flag. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The source peripheral did not request a DMA transfer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The source peripheral requested a DMA transfer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMINH</name>
<description>DTM Module Inhibit. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The DTM module does not ignore DMA requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>The DTM module ignores DMA requests until this bit is cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOERRI</name>
<description>Timeout Error Interrupt Flag. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A timeout error has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A timeout error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAERRI</name>
<description>DMA Error Interrupt Flag. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A DMA error has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A DMA error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMI</name>
<description>Module Interrupt Flag. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A state transition or timeout has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A state transition (SECSTIEN or PRISTIEN set to 1) or timeout (TOERRIEN = 1) occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMEN</name>
<description>Module Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the DTM module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the DTM module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TIMEOUT</name>
<description>Module Timeout</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TORELOAD</name>
<description>Timeout Counter Reload. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOCOUNT</name>
<description>Timeout Counter. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MSTCOUNT</name>
<description>Master Counter</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MSTCOUNT</name>
<description>Master Counter. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATEADDR</name>
<description>State Address</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STATEADDR</name>
<description>State Address. </description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATE</name>
<description>Active DTM State</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00FFFF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STRELOAD</name>
<description>Active State Counter Reload. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SECST</name>
<description>Secondary State. </description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PRIST</name>
<description>Primary State. </description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DSTMOD</name>
<description>Destination Module. </description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DTMNDST0</name>
<description>Select destination module DTMnDST.0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST1</name>
<description>Select destination module DTMnDST.1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST2</name>
<description>Select destination module DTMnDST.2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST3</name>
<description>Select destination module DTMnDST.3.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST4</name>
<description>Select destination module DTMnDST.4.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST5</name>
<description>Select destination module DTMnDST.5.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST6</name>
<description>Select destination module DTMnDST.6.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST7</name>
<description>Select destination module DTMnDST.7.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST8</name>
<description>Select destination module DTMnDST.8.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST9</name>
<description>Select destination module DTMnDST.9.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST10</name>
<description>Select destination module DTMnDST.10.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST11</name>
<description>Select destination module DTMnDST.11.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST12</name>
<description>Select destination module DTMnDST.12.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST13</name>
<description>Select destination module DTMnDST.13.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST14</name>
<description>Select destination module DTMnDST.14.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST15</name>
<description>Select no destination module (DTMnDST.15).</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRCMOD</name>
<description>Source Module. </description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DTMNSRC0</name>
<description>Select source module DTMnSRC.0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC1</name>
<description>Select source module DTMnSRC.1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC2</name>
<description>Select source module DTMnSRC.2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC3</name>
<description>Select source module DTMnSRC.3.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC4</name>
<description>Select source module DTMnSRC.4.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC5</name>
<description>Select source module DTMnSRC.5.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC6</name>
<description>Select source module DTMnSRC.6.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC7</name>
<description>Select source module DTMnSRC.7.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC8</name>
<description>Select source module DTMnSRC.8.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC9</name>
<description>Select source module DTMnSRC.9.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC10</name>
<description>Select source module DTMnSRC.10.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC11</name>
<description>Select source module DTMnSRC.11.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC12</name>
<description>Select source module DTMnSRC.12.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC13</name>
<description>Select source module DTMnSRC.13.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC14</name>
<description>Select source module DTMnSRC.14.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC15</name>
<description>Select no source module (DTMnSRC.15).</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMCHSEL</name>
<description>DTM Channel Select. </description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>CH_A</name>
<description>Select DTMn channel A for this state.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_B</name>
<description>Select DTMn channel B for this state.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_C</name>
<description>Select DTMn channel C for this state.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_D</name>
<description>Select DTMn channel D for this state.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INHSPOL</name>
<description>Inhibit Signal Polarity. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>ACTIVE_LOW</name>
<description>A logic low on the pin selected by INHSEL will allow the DTM to proceed.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE_HIGH</name>
<description>A logic high on the pin selected by INHSEL will allow the DTM to proceed.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMINH</name>
<description>Module Inhibit Enable. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The DTM module does not ignore any DMA requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>The DTM module ignores all DMA requests until the inhibit signal selected by INHSSEL matches the polarity polarity set by INHSPOL.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTDECEN</name>
<description>Master Decrement Enable. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable master counter decrements.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable master counter decrements.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOERRIEN</name>
<description>Timeout Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable timeouts and timeout interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable timeouts and timeout interrupts.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SECSTIEN</name>
<description>Secondary State Transition Interrupt Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable secondary state transition interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable secondary state transition interrupts.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRISTIEN</name>
<description>Primary State Transition Interrupt Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable primary state transition interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable primary state transition interrupts.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DTM_1</name>
<version>A</version>
<description>None</description>
<groupName>DTM</groupName>
<baseAddress>0x4004b000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DTM1_IRQn</name>
<value>33</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x0600FF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STCOUNT</name>
<description>Active State Counter. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ST</name>
<description>Active State. </description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>LASTST</name>
<description>Last State. </description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INHSSEL</name>
<description>Inhibit Signal Select. </description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTMNINH0</name>
<description>Select inhibit signal source DTMnINH.0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH1</name>
<description>Select inhibit signal source DTMnINH.1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH2</name>
<description>Select inhibit signal source DTMnINH.2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH3</name>
<description>Select inhibit signal source DTMnINH.3.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH4</name>
<description>Select inhibit signal source DTMnINH.4.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH5</name>
<description>Select inhibit signal source DTMnINH.5.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH6</name>
<description>Select inhibit signal source DTMnINH.6.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH7</name>
<description>Select inhibit signal source DTMnINH.7.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH8</name>
<description>Select inhibit signal source DTMnINH.8.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH9</name>
<description>Select inhibit signal source DTMnINH.9.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH10</name>
<description>Select inhibit signal source DTMnINH.10.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH11</name>
<description>Select inhibit signal source DTMnINH.11.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH12</name>
<description>Select inhibit signal source DTMnINH.12.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH13</name>
<description>Select inhibit signal source DTMnINH.13.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH14</name>
<description>Select inhibit signal source DTMnINH.14.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH15</name>
<description>Select inhibit signal source DTMnINH.15.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>Debug Mode. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The DTM module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the DTM module to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INHF</name>
<description>Inhibit Status Flag. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The inhibit signal is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The inhibit signal is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSTREQF</name>
<description>Destination Peripheral DMA Request Status Flag. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The destination peripheral did not request a DMA transfer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The destination peripheral requested a DMA transfer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRCREQF</name>
<description>Source Peripheral DMA Request Status Flag. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The source peripheral did not request a DMA transfer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The source peripheral requested a DMA transfer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMINH</name>
<description>DTM Module Inhibit. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The DTM module does not ignore DMA requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>The DTM module ignores DMA requests until this bit is cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOERRI</name>
<description>Timeout Error Interrupt Flag. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A timeout error has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A timeout error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAERRI</name>
<description>DMA Error Interrupt Flag. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A DMA error has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A DMA error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMI</name>
<description>Module Interrupt Flag. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A state transition or timeout has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A state transition (SECSTIEN or PRISTIEN set to 1) or timeout (TOERRIEN = 1) occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMEN</name>
<description>Module Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the DTM module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the DTM module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TIMEOUT</name>
<description>Module Timeout</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TORELOAD</name>
<description>Timeout Counter Reload. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOCOUNT</name>
<description>Timeout Counter. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MSTCOUNT</name>
<description>Master Counter</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MSTCOUNT</name>
<description>Master Counter. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATEADDR</name>
<description>State Address</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STATEADDR</name>
<description>State Address. </description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATE</name>
<description>Active DTM State</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00FFFF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STRELOAD</name>
<description>Active State Counter Reload. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SECST</name>
<description>Secondary State. </description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PRIST</name>
<description>Primary State. </description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DSTMOD</name>
<description>Destination Module. </description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DTMNDST0</name>
<description>Select destination module DTMnDST.0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST1</name>
<description>Select destination module DTMnDST.1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST2</name>
<description>Select destination module DTMnDST.2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST3</name>
<description>Select destination module DTMnDST.3.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST4</name>
<description>Select destination module DTMnDST.4.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST5</name>
<description>Select destination module DTMnDST.5.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST6</name>
<description>Select destination module DTMnDST.6.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST7</name>
<description>Select destination module DTMnDST.7.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST8</name>
<description>Select destination module DTMnDST.8.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST9</name>
<description>Select destination module DTMnDST.9.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST10</name>
<description>Select destination module DTMnDST.10.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST11</name>
<description>Select destination module DTMnDST.11.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST12</name>
<description>Select destination module DTMnDST.12.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST13</name>
<description>Select destination module DTMnDST.13.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST14</name>
<description>Select destination module DTMnDST.14.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST15</name>
<description>Select no destination module (DTMnDST.15).</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRCMOD</name>
<description>Source Module. </description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DTMNSRC0</name>
<description>Select source module DTMnSRC.0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC1</name>
<description>Select source module DTMnSRC.1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC2</name>
<description>Select source module DTMnSRC.2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC3</name>
<description>Select source module DTMnSRC.3.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC4</name>
<description>Select source module DTMnSRC.4.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC5</name>
<description>Select source module DTMnSRC.5.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC6</name>
<description>Select source module DTMnSRC.6.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC7</name>
<description>Select source module DTMnSRC.7.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC8</name>
<description>Select source module DTMnSRC.8.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC9</name>
<description>Select source module DTMnSRC.9.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC10</name>
<description>Select source module DTMnSRC.10.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC11</name>
<description>Select source module DTMnSRC.11.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC12</name>
<description>Select source module DTMnSRC.12.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC13</name>
<description>Select source module DTMnSRC.13.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC14</name>
<description>Select source module DTMnSRC.14.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC15</name>
<description>Select no source module (DTMnSRC.15).</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMCHSEL</name>
<description>DTM Channel Select. </description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>CH_A</name>
<description>Select DTMn channel A for this state.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_B</name>
<description>Select DTMn channel B for this state.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_C</name>
<description>Select DTMn channel C for this state.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_D</name>
<description>Select DTMn channel D for this state.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INHSPOL</name>
<description>Inhibit Signal Polarity. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>ACTIVE_LOW</name>
<description>A logic low on the pin selected by INHSEL will allow the DTM to proceed.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE_HIGH</name>
<description>A logic high on the pin selected by INHSEL will allow the DTM to proceed.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMINH</name>
<description>Module Inhibit Enable. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The DTM module does not ignore any DMA requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>The DTM module ignores all DMA requests until the inhibit signal selected by INHSSEL matches the polarity polarity set by INHSPOL.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTDECEN</name>
<description>Master Decrement Enable. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable master counter decrements.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable master counter decrements.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOERRIEN</name>
<description>Timeout Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable timeouts and timeout interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable timeouts and timeout interrupts.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SECSTIEN</name>
<description>Secondary State Transition Interrupt Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable secondary state transition interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable secondary state transition interrupts.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRISTIEN</name>
<description>Primary State Transition Interrupt Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable primary state transition interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable primary state transition interrupts.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DTM_2</name>
<version>A</version>
<description>None</description>
<groupName>DTM</groupName>
<baseAddress>0x4004c000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DTM2_IRQn</name>
<value>34</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x0600FF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STCOUNT</name>
<description>Active State Counter. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ST</name>
<description>Active State. </description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>LASTST</name>
<description>Last State. </description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INHSSEL</name>
<description>Inhibit Signal Select. </description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DTMNINH0</name>
<description>Select inhibit signal source DTMnINH.0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH1</name>
<description>Select inhibit signal source DTMnINH.1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH2</name>
<description>Select inhibit signal source DTMnINH.2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH3</name>
<description>Select inhibit signal source DTMnINH.3.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH4</name>
<description>Select inhibit signal source DTMnINH.4.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH5</name>
<description>Select inhibit signal source DTMnINH.5.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH6</name>
<description>Select inhibit signal source DTMnINH.6.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH7</name>
<description>Select inhibit signal source DTMnINH.7.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH8</name>
<description>Select inhibit signal source DTMnINH.8.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH9</name>
<description>Select inhibit signal source DTMnINH.9.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH10</name>
<description>Select inhibit signal source DTMnINH.10.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH11</name>
<description>Select inhibit signal source DTMnINH.11.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH12</name>
<description>Select inhibit signal source DTMnINH.12.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH13</name>
<description>Select inhibit signal source DTMnINH.13.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH14</name>
<description>Select inhibit signal source DTMnINH.14.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNINH15</name>
<description>Select inhibit signal source DTMnINH.15.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>Debug Mode. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The DTM module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the DTM module to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INHF</name>
<description>Inhibit Status Flag. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The inhibit signal is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The inhibit signal is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSTREQF</name>
<description>Destination Peripheral DMA Request Status Flag. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The destination peripheral did not request a DMA transfer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The destination peripheral requested a DMA transfer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRCREQF</name>
<description>Source Peripheral DMA Request Status Flag. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The source peripheral did not request a DMA transfer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The source peripheral requested a DMA transfer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMINH</name>
<description>DTM Module Inhibit. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The DTM module does not ignore DMA requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>The DTM module ignores DMA requests until this bit is cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOERRI</name>
<description>Timeout Error Interrupt Flag. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A timeout error has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A timeout error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAERRI</name>
<description>DMA Error Interrupt Flag. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A DMA error has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A DMA error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMI</name>
<description>Module Interrupt Flag. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A state transition or timeout has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A state transition (SECSTIEN or PRISTIEN set to 1) or timeout (TOERRIEN = 1) occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMEN</name>
<description>Module Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the DTM module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the DTM module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TIMEOUT</name>
<description>Module Timeout</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TORELOAD</name>
<description>Timeout Counter Reload. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOCOUNT</name>
<description>Timeout Counter. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MSTCOUNT</name>
<description>Master Counter</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MSTCOUNT</name>
<description>Master Counter. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATEADDR</name>
<description>State Address</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STATEADDR</name>
<description>State Address. </description>
<bitOffset>2</bitOffset>
<bitWidth>30</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATE</name>
<description>Active DTM State</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00FFFF00</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>STRELOAD</name>
<description>Active State Counter Reload. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SECST</name>
<description>Secondary State. </description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PRIST</name>
<description>Primary State. </description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DSTMOD</name>
<description>Destination Module. </description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DTMNDST0</name>
<description>Select destination module DTMnDST.0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST1</name>
<description>Select destination module DTMnDST.1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST2</name>
<description>Select destination module DTMnDST.2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST3</name>
<description>Select destination module DTMnDST.3.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST4</name>
<description>Select destination module DTMnDST.4.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST5</name>
<description>Select destination module DTMnDST.5.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST6</name>
<description>Select destination module DTMnDST.6.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST7</name>
<description>Select destination module DTMnDST.7.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST8</name>
<description>Select destination module DTMnDST.8.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST9</name>
<description>Select destination module DTMnDST.9.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST10</name>
<description>Select destination module DTMnDST.10.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST11</name>
<description>Select destination module DTMnDST.11.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST12</name>
<description>Select destination module DTMnDST.12.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST13</name>
<description>Select destination module DTMnDST.13.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST14</name>
<description>Select destination module DTMnDST.14.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNDST15</name>
<description>Select no destination module (DTMnDST.15).</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRCMOD</name>
<description>Source Module. </description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DTMNSRC0</name>
<description>Select source module DTMnSRC.0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC1</name>
<description>Select source module DTMnSRC.1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC2</name>
<description>Select source module DTMnSRC.2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC3</name>
<description>Select source module DTMnSRC.3.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC4</name>
<description>Select source module DTMnSRC.4.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC5</name>
<description>Select source module DTMnSRC.5.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC6</name>
<description>Select source module DTMnSRC.6.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC7</name>
<description>Select source module DTMnSRC.7.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC8</name>
<description>Select source module DTMnSRC.8.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC9</name>
<description>Select source module DTMnSRC.9.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC10</name>
<description>Select source module DTMnSRC.10.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC11</name>
<description>Select source module DTMnSRC.11.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC12</name>
<description>Select source module DTMnSRC.12.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC13</name>
<description>Select source module DTMnSRC.13.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC14</name>
<description>Select source module DTMnSRC.14.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>DTMNSRC15</name>
<description>Select no source module (DTMnSRC.15).</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMCHSEL</name>
<description>DTM Channel Select. </description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>CH_A</name>
<description>Select DTMn channel A for this state.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_B</name>
<description>Select DTMn channel B for this state.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_C</name>
<description>Select DTMn channel C for this state.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CH_D</name>
<description>Select DTMn channel D for this state.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INHSPOL</name>
<description>Inhibit Signal Polarity. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>ACTIVE_LOW</name>
<description>A logic low on the pin selected by INHSEL will allow the DTM to proceed.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE_HIGH</name>
<description>A logic high on the pin selected by INHSEL will allow the DTM to proceed.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTMINH</name>
<description>Module Inhibit Enable. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The DTM module does not ignore any DMA requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>The DTM module ignores all DMA requests until the inhibit signal selected by INHSSEL matches the polarity polarity set by INHSPOL.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTDECEN</name>
<description>Master Decrement Enable. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable master counter decrements.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable master counter decrements.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOERRIEN</name>
<description>Timeout Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable timeouts and timeout interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable timeouts and timeout interrupts.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SECSTIEN</name>
<description>Secondary State Transition Interrupt Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable secondary state transition interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable secondary state transition interrupts.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRISTIEN</name>
<description>Primary State Transition Interrupt Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable primary state transition interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable primary state transition interrupts.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DEVICEID_0</name>
<version>A</version>
<description>None</description>
<groupName>DEVICEID_0</groupName>
<baseAddress>0x400490c0</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>DEVICEID0</name>
<description>Device ID Word 0</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>REVID</name>
<description>Revision ID. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>REVA</name>
<description>Revision A.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>REVB</name>
<description>Revision B.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>REVC</name>
<description>Revision C.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEVICEID0</name>
<description>Device ID 0. </description>
<bitOffset>4</bitOffset>
<bitWidth>28</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVICEID1</name>
<description>Device ID Word 1</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICEID1</name>
<description>Device ID 1. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVICEID2</name>
<description>Device ID Word 2</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICEID2</name>
<description>Device ID 2. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEVICEID3</name>
<description>Device ID Word 3</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DEVICEID3</name>
<description>Device ID 3. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ECRC_0</name>
<version>A</version>
<description>None</description>
<groupName>ECRC_0</groupName>
<baseAddress>0x40028000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000002</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SINITEN</name>
<description>Seed Initialization Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not initialize the CRC module to the value set by the SEED bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Initialize the CRC module to the value set by the SEED bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEED</name>
<description>Seed Setting. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ALL_ZEROES</name>
<description>CRC seed value is all 0's (0x00000000)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ALL_ONES</name>
<description>CRC seed value is all 1's (0xFFFFFFFF).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRCEN</name>
<description>CRC Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable CRC operations.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable CRC operations.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POLYSEL</name>
<description>Polynomial Selection. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CRC32_FIXED</name>
<description>Select the fixed 32-bit polynomial: 0x04C11DB7.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CRC16_PROG</name>
<description>Select the programmable 16-bit polynomial. The POLY register sets the polynomial coefficients.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BMDEN</name>
<description>Byte Mode Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable byte mode (word/byte width is determined automatically by the hardware).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable byte mode (all writes are considered as bytes).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BBREN</name>
<description>Byte-Level Bit Reversal Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>No byte-level bit reversal (input is same order as written).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Byte-level bit reversal enabled (the bits in each byte are reversed).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORDER</name>
<description>Input Processing Order. </description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NO_REORDER</name>
<description>No byte reorientation (output is same order as input).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BIG_ENDIAN_16</name>
<description>Swap for 16-bit big endian order (input: B3 B2 B1 B0, output: B2 B3 B0 B1).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BIG_ENDIAN_32</name>
<description>Swap for 32-bit big endian order (input: B3 B2 B1 B0, output: B0 B1 B2 B3).</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ASEEDEN</name>
<description>Automatic Seed Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable automatic seeding.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable automatic seeding. Reading the byte of the DATA register selected by ASEEDSEL re-seeds the CRC result with the setting selected by SEED.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ASEEDSEL</name>
<description>Automatic Seed Byte Select. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LSB_READ</name>
<description>Select a read of the least-significant byte ([7:0]) of DATA, RDATA or BRDATA for automatic re-seeding.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MSB_READ</name>
<description>Select a read of the most-significant byte [31:24] for 32-bit operations, and [15:8] for 16-bit operations) of DATA, RDATA or BRDATA for automatic re-seeding.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>POLY</name>
<description>16-bit Programmable Polynomial</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00001021</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>POLY</name>
<description>16-bit Programmable Polynomial. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description>Input/Result Data</description>
<addressOffset>0x20</addressOffset>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Input/Result Data. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDATA</name>
<description>Bit-Reversed Output Data</description>
<addressOffset>0x30</addressOffset>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDATA</name>
<description>Bit-Reversed Output Data. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BRDATA</name>
<description>Byte-Reversed Output Data</description>
<addressOffset>0x40</addressOffset>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BRDATA</name>
<description>Byte-Reversed Output Data. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SCONTROL</name>
<description>Bus Snooping Control</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SEN</name>
<description>Snooping Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable automatic bus snooping.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable automatic bus snooping.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDIRSEL</name>
<description>Snooping Direction Select. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>WRITES</name>
<description>ECRC will snoop writes to the selected peripheral.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>READS</name>
<description>ECRC will snoop reads from the selected peripheral.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPERISEL</name>
<description>Snooping Peripheral Select. </description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SADDR</name>
<description>Snooping Address. </description>
<bitOffset>18</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ENCDEC_0</name>
<version>A</version>
<description>None</description>
<groupName>ENCDEC_0</groupName>
<baseAddress>0x4004f000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ENDEC0_IRQn</name>
<value>36</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INRDYIEN</name>
<description>Input Ready Interrupt Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the input ready interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the input ready interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORDYIEN</name>
<description>Output Ready Interrupt Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the output ready interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the output ready interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERRIEN</name>
<description>Error Interrupt Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the error interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the error interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET</name>
<description>Module Reset. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>ACTIVE</name>
<description>Reset the module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MOSIZE</name>
<description>Manchester Output Size. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SMALL</name>
<description>Manchester encode operations generate a half-word output, and decode operations generate a byte output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LARGE</name>
<description>Manchester encode operations generate a word output, and decode operations generate a half-word output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EDMD</name>
<description>Encode Decode Mode. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DECODE</name>
<description>Decode data written to DATAIN.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENCODE</name>
<description>Encode data written to DATAIN.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPMD</name>
<description>Operation Mode. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MANCHESTER</name>
<description>The operation selected by EDMD uses Manchester mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>3OUTOF6</name>
<description>The operation selected by EDMD uses Three-out-of-Six mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BEN</name>
<description>Bypass Encoder/Decoder Operation Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not bypass ENCDEC operations.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Bypass ENCDEC operations.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Mode Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable DMA mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>Debug Mode. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The ENCDEC module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the ENCDEC module to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OORDER</name>
<description>Output Order Mode. </description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>The module outputs data to DATAOUT in the same order as it was processed (input: B3 B2 B1 B0, output: B3 B2 B1 B0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALF_WORD</name>
<description>The module flips the data in half-words before outputting to DATAOUT (input: B3 B2 B1 B0, output: B2 B3 B0 B1).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>WORD</name>
<description>The module flips the data in words before outputting to DATAOUT (input: B3 B2 B1 B0, output: B0 B1 B2 B3).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>LOWER_THREE_BYTES</name>
<description>The module flips the lower three bytes before outputting to DATAOUT (input: B3 B2 B1 B0, output: B3 B0 B1 B2).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IORDER</name>
<description>Input Order Mode. </description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>Data written to DATAIN is processed in the order written (input: B3 B2 B1 B0, output: B3 B2 B1 B0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALF_WORD</name>
<description>The module flips the DATAIN input data in half-words (input: B2 B3 B0 B1, output: B3 B2 B1 B0).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>WORD</name>
<description>The module flips the DATAIN input data in words (input: B0 B1 B2 B3, output: B3 B2 B1 B0).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>LOWER_THREE_BYTES</name>
<description>The module flips the lower three bytes of the DATAIN input data (input: B3 B0 B1 B2, output: B3 B2 B1 B0).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Module Status</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INRDYI</name>
<description>Input Ready Interrupt Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The input FIFO is not ready for new data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Firmware can write new input data to DATAIN.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORDYI</name>
<description>Output Ready Interrupt Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The output data is not ready.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The output data is ready to be read by firmware.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DERRI</name>
<description>Data Error Interrupt Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DURI</name>
<description>Data Underrun Interrupt Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>No output data FIFO underrun.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An output data FIFO underrun has occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DORI</name>
<description>Data Overrun Interrupt Flag. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>No input data FIFO overrun.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An input data FIFO overrun has occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DATAIN</name>
<description>Data Input</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<readAction>modifyExternal</readAction>
<fields>
<field>
<name>DATAIN</name>
<description>Data Input. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATAOUT</name>
<description>Data Output</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<readAction>modifyExternal</readAction>
<fields>
<field>
<name>DATAOUT</name>
<description>Data Output. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATAOUTC</name>
<description>Data Output Complement</description>
<addressOffset>0x40</addressOffset>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<readAction>modifyExternal</readAction>
<fields>
<field>
<name>DATAOUTC</name>
<description>Data Output Complement. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>EPCA_0</name>
<version>A</version>
<description>None</description>
<groupName>EPCA_0</groupName>
<baseAddress>0x4000e000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>EPCA0_IRQn</name>
<value>23</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>MODE</name>
<description>Module Operating Mode</description>
<addressOffset>0x180</addressOffset>
<resetValue>0x01FF0000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKDIV</name>
<description>Input Clock Divider. </description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>CLKSEL</name>
<description>Input Clock (F&lt;subscript&gt;CLKIN&lt;/subscript&gt;) Select. </description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>APB</name>
<description>Set the APB as the input clock (FCLKIN).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER0</name>
<description>Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>HL_ECI</name>
<description>Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTOSCN</name>
<description>Set the external oscillator module output (EXTOSCn) divided by 2 as the input clock (FCLKIN).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ECI</name>
<description>Set ECI transitions divided by 2 as the input clock (FCLKIN).</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DEND</name>
<description>DMA Write End Index. </description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LIMIT</name>
<description>Set the last register in a DMA write transfer to LIMITUPD.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CH0</name>
<description>Set the last register in a DMA write transfer to Channel 0 CCAPVUPD.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CH1</name>
<description>Set the last register in a DMA write transfer to Channel 1 CCAPVUPD.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CH2</name>
<description>Set the last register in a DMA write transfer to Channel 2 CCAPVUPD.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CH3</name>
<description>Set the last register in a DMA write transfer to Channel 3 CCAPVUPD.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CH4</name>
<description>Set the last register in a DMA write transfer to Channel 4 CCAPVUPD.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>CH5</name>
<description>Set the last register in a DMA write transfer to Channel 5 CCAPVUPD.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>EMPTY</name>
<description>Empty slot.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DPTR</name>
<description>DMA Write Transfer Pointer. </description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LIMIT</name>
<description>The DMA channel will write to LIMITUPD next.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CH0</name>
<description>The DMA channel will write to Channel 0 CCAPVUPD next.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CH1</name>
<description>The DMA channel will write to Channel 1 CCAPVUPD next.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CH2</name>
<description>The DMA channel will write to Channel 2 CCAPVUPD next.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CH3</name>
<description>The DMA channel will write to Channel 3 CCAPVUPD next.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CH4</name>
<description>The DMA channel will write to Channel 4 CCAPVUPD next.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>CH5</name>
<description>The DMA channel will write to Channel 5 CCAPVUPD next.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>EMPTY</name>
<description>Empty slot.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSTART</name>
<description>DMA Target Start Index. </description>
<bitOffset>22</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LIMIT</name>
<description>Set the first register in a DMA write transfer to LIMITUPD.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CH0</name>
<description>Set the first register in a DMA write transfer to Channel 0 CCAPVUPD.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CH1</name>
<description>Set the first register in a DMA write transfer to Channel 1 CCAPVUPD.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CH2</name>
<description>Set the first register in a DMA write transfer to Channel 2 CCAPVUPD.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CH3</name>
<description>Set the first register in a DMA write transfer to Channel 3 CCAPVUPD.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CH4</name>
<description>Set the first register in a DMA write transfer to Channel 4 CCAPVUPD.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>CH5</name>
<description>Set the first register in a DMA write transfer to Channel 5 CCAPVUPD.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>EMPTY</name>
<description>Empty slot.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBUSYF</name>
<description>DMA Busy Flag. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>IDLE</name>
<description>The DMA channel is not servicing an EPCA control transfer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BUSY</name>
<description>The DMA channel is busy servicing an EPCA control transfer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STDOSEL</name>
<description>Standard Port Bank Output Select. </description>
<bitOffset>27</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NO_DIFF</name>
<description>Select the non-differential channel outputs (Channels 0-5) for the standard PB pins.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_DIFF</name>
<description>Select the differential output from Channel 2 and non-differential outputs from Channels 0, 1, 2, and 3 for the standard PB pins.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TWO_DIFF</name>
<description>Select the differential outputs from Channels 1 and 2 and non-differential outputs from Channels 0 and 1 for the standard PB pins.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>THREE_DIFF</name>
<description>Select three differential outputs from Channels 0, 1, and 2 for the standard PB pins.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x190</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OVFIEN</name>
<description>EPCA Counter Overflow/Limit Interrupt Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the EPCA counter overflow/limit event interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the EPCA counter overflow/limit event interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVFDEN</name>
<description>EPCA Counter Overflow/Limit DMA Request Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a EPCA counter overflow/limit event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a EPCA counter overflow/limit event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVFSEN</name>
<description>EPCA Counter Overflow/Limit Synchronization Signal Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a EPCA counter overflow/limit event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a EPCA counter overflow/limit event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NOUPD</name>
<description>Internal Register Update Inhibit. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The EPCA registers will automatically load any new update values after an overflow/limit event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>The EPCA registers will not load any new update values after an overflow/limit event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>EPCA Debug Mode. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will stop the EPCA counter/timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RUN</name>
<description>The EPCA will continue to operate while the core is halted in debug mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STSEL</name>
<description>Synchronous Input Trigger Select. </description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>EPCANT0</name>
<description>Select input trigger 0, Comparator0 output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCANT1</name>
<description>Select input trigger 1, Comparator1 output.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCANT2</name>
<description>Select input trigger 2, Timer 0 high overflow.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>EPCANT3</name>
<description>Select input trigger 3, Timer 1 high overflow.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STESEL</name>
<description>Synchronous Input Trigger Edge Select. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>FALLING</name>
<description>A high-to-low transition (falling edge) on EPCAnTx will start the counter/timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>A low-to-high transition (rising edge) on EPCAnTx will start the counter/timer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STEN</name>
<description>Synchronous Input Trigger Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the input trigger (EPCAnTx). The EPCA counter/timer will continue to run if the RUN bit is set regardless of the value on the input trigger.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the input trigger (EPCAnTx). If RUN is set to 1, the EPCA counter/timer will start running when the selected input trigger (STSEL) meets the criteria set by STESEL. It will not stop running if the criteria is no longer met.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIVST</name>
<description>Clock Divider Output State. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>OUTPUT_HIGH</name>
<description>The clock divider is currently in the first half-cycle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OUTPUT_LOW</name>
<description>The clock divider is currently in the second half-cycle.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIV</name>
<description>Current Clock Divider Count. </description>
<bitOffset>22</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Module Status</description>
<addressOffset>0x1a0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>C0CCI</name>
<description>Channel 0 Capture/Compare Interrupt Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Channel 0 match or capture event did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Channel 0 match or capture event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C1CCI</name>
<description>Channel 1 Capture/Compare Interrupt Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Channel 1 match or capture event did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Channel 1 match or capture event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C2CCI</name>
<description>Channel 2 Capture/Compare Interrupt Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Channel 2 match or capture event did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Channel 2 match or capture event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C3CCI</name>
<description>Channel 3 Capture/Compare Interrupt Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Channel 3 match or capture event did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Channel 3 match or capture event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C4CCI</name>
<description>Channel 4 Capture/Compare Interrupt Flag. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Channel 4 match or capture event did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Channel 4 match or capture event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C5CCI</name>
<description>Channel 5 Capture/Compare Interrupt Flag. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Channel 5 match or capture event did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Channel 5 match or capture event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RUN</name>
<description>Counter/Timer Run. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop the EPCA Counter/Timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Start the EPCA Counter/Timer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVFI</name>
<description>Counter/Timer Overflow/Limit Interrupt Flag. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>An EPCA Counter/Timer overflow/limit event did not occur.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An EPCA Counter/Timer overflow/limit event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UPDCF</name>
<description>Register Update Complete Flag. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>EMPTY</name>
<description>An EPCA register update completed or is not pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FULL</name>
<description>An EPCA register update has not completed and is still pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C0IOVFI</name>
<description>Channel 0 Intermediate Overflow Interrupt Flag. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Channel 0 did not count past the channel n-bit mode limit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Channel 0 counted past the channel n-bit mode limit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C1IOVFI</name>
<description>Channel 1 Intermediate Overflow Interrupt Flag. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Channel 1 did not count past the channel n-bit mode limit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Channel 1 counted past the channel n-bit mode limit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C2IOVFI</name>
<description>Channel 2 Intermediate Overflow Interrupt Flag. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Channel 2 did not count past the channel n-bit mode limit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Channel 2 counted past the channel n-bit mode limit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C3IOVFI</name>
<description>Channel 3 Intermediate Overflow Interrupt Flag. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Channel 3 did not count past the channel n-bit mode limit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Channel 3 counted past the channel n-bit mode limit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C4IOVFI</name>
<description>Channel 4 Intermediate Overflow Interrupt Flag. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Channel 4 did not count past the channel n-bit mode limit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Channel 4 counted past the channel n-bit mode limit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>C5IOVFI</name>
<description>Channel 5 Intermediate Overflow Interrupt Flag. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Channel 5 did not count past the channel n-bit mode limit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Channel 5 counted past the channel n-bit mode limit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>COUNTER</name>
<description>Module Counter/Timer</description>
<addressOffset>0x1b0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUNTER</name>
<description>Counter/Timer. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>LIMIT</name>
<description>Module Upper Limit</description>
<addressOffset>0x1c0</addressOffset>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LIMIT</name>
<description>Upper Limit. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>LIMITUPD</name>
<description>Module Upper Limit Update Value</description>
<addressOffset>0x1d0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LIMITUPD</name>
<description>Module Upper Limit Update Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTIME</name>
<description>Phase Delay Time</description>
<addressOffset>0x1e0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTIMEX</name>
<description>X Phase Delay Time. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DTIMEY</name>
<description>Y Phase Delay Time. </description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTARGET</name>
<description>DMA Transfer Target</description>
<addressOffset>0x200</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DTARGET</name>
<description>DMA Transfer Target. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<!--BASEPOINTER_START_2-->
<register>
<name>MODE_0</name>
<description>Channel Capture/Compare Mode</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COSEL</name>
<description>Channel Output Function Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_OUTPUT</name>
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_OUTPUT</name>
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMMD</name>
<description>PWM N-Bit Mode. </description>
<bitOffset>2</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DIFGEN</name>
<description>Differential Signal Generator Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMD</name>
<description>Channel Operating Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>EDGE_PWM</name>
<description>Configure the channel for edge-aligned PWM mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CENTER_ALIGNED_PWM</name>
<description>Configure the channel for center-aligned PWM mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>HF_SQUARE_WAVE</name>
<description>Configure the channel for high-frequency/square-wave mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CAPTURE</name>
<description>Configure the channel for timer/capture mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>N_BIT_PWM</name>
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL_0</name>
<description>Channel Capture/Compare Control</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUTST</name>
<description>Channel Output State. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The channel output state is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The channel output state is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPCAPEN</name>
<description>Positive Edge Input Capture Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable positive-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable positive-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNCAPEN</name>
<description>Negative Edge Input Capture Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable negative-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable negative-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CUPDCF</name>
<description>Channel Register Update Complete Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A EPCA channel register update completed or is not pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A EPCA channel register update has not completed and is still pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>YPHST</name>
<description>Differential Y Phase State. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the Y Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the Y Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACTIVEPH</name>
<description>Active Channel Select. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>YACTIVE</name>
<description>The Y Phase is active and X Phase is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>XACTIVE</name>
<description>The X Phase is active and Y Phase is inactive.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XPHST</name>
<description>Differential X Phase State. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the X Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the X Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIEN</name>
<description>Capture/Compare Interrupt Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel capture/compare interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel capture/compare interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCDEN</name>
<description>Capture/Compare DMA Request Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCSEN</name>
<description>Capture/Compare Synchronization Signal Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFIEN</name>
<description>Intermediate Overflow Interrupt Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel intermediate overflow interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel intermediate overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFDEN</name>
<description>Intermediate Overflow DMA Request Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFSEN</name>
<description>Intermediate Overflow Synchronization Signal Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCAPV_0</name>
<description>Channel Compare Value</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPV</name>
<description>Channel Compare Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCAPVUPD_0</name>
<description>Channel Compare Update Value</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPVUPD</name>
<description>Channel Compare Update Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<!--BASEPOINTER_START_3-->
<register>
<name>MODE_1</name>
<description>Channel Capture/Compare Mode</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COSEL</name>
<description>Channel Output Function Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_OUTPUT</name>
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_OUTPUT</name>
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMMD</name>
<description>PWM N-Bit Mode. </description>
<bitOffset>2</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DIFGEN</name>
<description>Differential Signal Generator Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMD</name>
<description>Channel Operating Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>EDGE_PWM</name>
<description>Configure the channel for edge-aligned PWM mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CENTER_ALIGNED_PWM</name>
<description>Configure the channel for center-aligned PWM mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>HF_SQUARE_WAVE</name>
<description>Configure the channel for high-frequency/square-wave mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CAPTURE</name>
<description>Configure the channel for timer/capture mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>N_BIT_PWM</name>
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL_1</name>
<description>Channel Capture/Compare Control</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUTST</name>
<description>Channel Output State. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The channel output state is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The channel output state is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPCAPEN</name>
<description>Positive Edge Input Capture Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable positive-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable positive-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNCAPEN</name>
<description>Negative Edge Input Capture Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable negative-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable negative-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CUPDCF</name>
<description>Channel Register Update Complete Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A EPCA channel register update completed or is not pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A EPCA channel register update has not completed and is still pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>YPHST</name>
<description>Differential Y Phase State. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the Y Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the Y Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACTIVEPH</name>
<description>Active Channel Select. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>YACTIVE</name>
<description>The Y Phase is active and X Phase is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>XACTIVE</name>
<description>The X Phase is active and Y Phase is inactive.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XPHST</name>
<description>Differential X Phase State. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the X Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the X Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIEN</name>
<description>Capture/Compare Interrupt Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel capture/compare interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel capture/compare interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCDEN</name>
<description>Capture/Compare DMA Request Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCSEN</name>
<description>Capture/Compare Synchronization Signal Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFIEN</name>
<description>Intermediate Overflow Interrupt Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel intermediate overflow interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel intermediate overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFDEN</name>
<description>Intermediate Overflow DMA Request Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFSEN</name>
<description>Intermediate Overflow Synchronization Signal Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCAPV_1</name>
<description>Channel Compare Value</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPV</name>
<description>Channel Compare Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCAPVUPD_1</name>
<description>Channel Compare Update Value</description>
<addressOffset>0x70</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPVUPD</name>
<description>Channel Compare Update Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<!--BASEPOINTER_START_4-->
<register>
<name>MODE_2</name>
<description>Channel Capture/Compare Mode</description>
<addressOffset>0x80</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COSEL</name>
<description>Channel Output Function Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_OUTPUT</name>
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_OUTPUT</name>
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMMD</name>
<description>PWM N-Bit Mode. </description>
<bitOffset>2</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DIFGEN</name>
<description>Differential Signal Generator Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMD</name>
<description>Channel Operating Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>EDGE_PWM</name>
<description>Configure the channel for edge-aligned PWM mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CENTER_ALIGNED_PWM</name>
<description>Configure the channel for center-aligned PWM mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>HF_SQUARE_WAVE</name>
<description>Configure the channel for high-frequency/square-wave mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CAPTURE</name>
<description>Configure the channel for timer/capture mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>N_BIT_PWM</name>
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL_2</name>
<description>Channel Capture/Compare Control</description>
<addressOffset>0x90</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUTST</name>
<description>Channel Output State. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The channel output state is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The channel output state is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPCAPEN</name>
<description>Positive Edge Input Capture Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable positive-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable positive-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNCAPEN</name>
<description>Negative Edge Input Capture Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable negative-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable negative-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CUPDCF</name>
<description>Channel Register Update Complete Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A EPCA channel register update completed or is not pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A EPCA channel register update has not completed and is still pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>YPHST</name>
<description>Differential Y Phase State. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the Y Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the Y Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACTIVEPH</name>
<description>Active Channel Select. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>YACTIVE</name>
<description>The Y Phase is active and X Phase is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>XACTIVE</name>
<description>The X Phase is active and Y Phase is inactive.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XPHST</name>
<description>Differential X Phase State. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the X Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the X Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIEN</name>
<description>Capture/Compare Interrupt Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel capture/compare interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel capture/compare interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCDEN</name>
<description>Capture/Compare DMA Request Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCSEN</name>
<description>Capture/Compare Synchronization Signal Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFIEN</name>
<description>Intermediate Overflow Interrupt Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel intermediate overflow interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel intermediate overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFDEN</name>
<description>Intermediate Overflow DMA Request Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFSEN</name>
<description>Intermediate Overflow Synchronization Signal Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCAPV_2</name>
<description>Channel Compare Value</description>
<addressOffset>0xa0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPV</name>
<description>Channel Compare Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCAPVUPD_2</name>
<description>Channel Compare Update Value</description>
<addressOffset>0xb0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPVUPD</name>
<description>Channel Compare Update Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<!--BASEPOINTER_START_5-->
<register>
<name>MODE_3</name>
<description>Channel Capture/Compare Mode</description>
<addressOffset>0xc0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COSEL</name>
<description>Channel Output Function Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_OUTPUT</name>
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_OUTPUT</name>
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMMD</name>
<description>PWM N-Bit Mode. </description>
<bitOffset>2</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DIFGEN</name>
<description>Differential Signal Generator Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMD</name>
<description>Channel Operating Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>EDGE_PWM</name>
<description>Configure the channel for edge-aligned PWM mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CENTER_ALIGNED_PWM</name>
<description>Configure the channel for center-aligned PWM mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>HF_SQUARE_WAVE</name>
<description>Configure the channel for high-frequency/square-wave mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CAPTURE</name>
<description>Configure the channel for timer/capture mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>N_BIT_PWM</name>
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL_3</name>
<description>Channel Capture/Compare Control</description>
<addressOffset>0xd0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUTST</name>
<description>Channel Output State. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The channel output state is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The channel output state is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPCAPEN</name>
<description>Positive Edge Input Capture Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable positive-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable positive-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNCAPEN</name>
<description>Negative Edge Input Capture Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable negative-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable negative-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CUPDCF</name>
<description>Channel Register Update Complete Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A EPCA channel register update completed or is not pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A EPCA channel register update has not completed and is still pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>YPHST</name>
<description>Differential Y Phase State. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the Y Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the Y Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACTIVEPH</name>
<description>Active Channel Select. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>YACTIVE</name>
<description>The Y Phase is active and X Phase is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>XACTIVE</name>
<description>The X Phase is active and Y Phase is inactive.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XPHST</name>
<description>Differential X Phase State. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the X Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the X Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIEN</name>
<description>Capture/Compare Interrupt Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel capture/compare interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel capture/compare interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCDEN</name>
<description>Capture/Compare DMA Request Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCSEN</name>
<description>Capture/Compare Synchronization Signal Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFIEN</name>
<description>Intermediate Overflow Interrupt Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel intermediate overflow interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel intermediate overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFDEN</name>
<description>Intermediate Overflow DMA Request Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFSEN</name>
<description>Intermediate Overflow Synchronization Signal Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCAPV_3</name>
<description>Channel Compare Value</description>
<addressOffset>0xe0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPV</name>
<description>Channel Compare Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCAPVUPD_3</name>
<description>Channel Compare Update Value</description>
<addressOffset>0xf0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPVUPD</name>
<description>Channel Compare Update Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<!--BASEPOINTER_START_6-->
<register>
<name>MODE_4</name>
<description>Channel Capture/Compare Mode</description>
<addressOffset>0x100</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COSEL</name>
<description>Channel Output Function Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_OUTPUT</name>
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_OUTPUT</name>
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMMD</name>
<description>PWM N-Bit Mode. </description>
<bitOffset>2</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DIFGEN</name>
<description>Differential Signal Generator Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMD</name>
<description>Channel Operating Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>EDGE_PWM</name>
<description>Configure the channel for edge-aligned PWM mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CENTER_ALIGNED_PWM</name>
<description>Configure the channel for center-aligned PWM mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>HF_SQUARE_WAVE</name>
<description>Configure the channel for high-frequency/square-wave mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CAPTURE</name>
<description>Configure the channel for timer/capture mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>N_BIT_PWM</name>
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL_4</name>
<description>Channel Capture/Compare Control</description>
<addressOffset>0x110</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUTST</name>
<description>Channel Output State. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The channel output state is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The channel output state is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPCAPEN</name>
<description>Positive Edge Input Capture Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable positive-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable positive-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNCAPEN</name>
<description>Negative Edge Input Capture Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable negative-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable negative-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CUPDCF</name>
<description>Channel Register Update Complete Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A EPCA channel register update completed or is not pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A EPCA channel register update has not completed and is still pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>YPHST</name>
<description>Differential Y Phase State. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the Y Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the Y Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACTIVEPH</name>
<description>Active Channel Select. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>YACTIVE</name>
<description>The Y Phase is active and X Phase is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>XACTIVE</name>
<description>The X Phase is active and Y Phase is inactive.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XPHST</name>
<description>Differential X Phase State. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the X Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the X Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIEN</name>
<description>Capture/Compare Interrupt Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel capture/compare interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel capture/compare interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCDEN</name>
<description>Capture/Compare DMA Request Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCSEN</name>
<description>Capture/Compare Synchronization Signal Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFIEN</name>
<description>Intermediate Overflow Interrupt Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel intermediate overflow interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel intermediate overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFDEN</name>
<description>Intermediate Overflow DMA Request Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFSEN</name>
<description>Intermediate Overflow Synchronization Signal Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCAPV_4</name>
<description>Channel Compare Value</description>
<addressOffset>0x120</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPV</name>
<description>Channel Compare Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCAPVUPD_4</name>
<description>Channel Compare Update Value</description>
<addressOffset>0x130</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPVUPD</name>
<description>Channel Compare Update Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<!--BASEPOINTER_START_7-->
<register>
<name>MODE_5</name>
<description>Channel Capture/Compare Mode</description>
<addressOffset>0x140</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COSEL</name>
<description>Channel Output Function Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>TOGGLE_OUTPUT</name>
<description>Toggle the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_OUTPUT</name>
<description>Set the channel output at the next capture/compare, overflow, or intermediate event.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_OUTPUT</name>
<description>Clear the output at the next capture/compare, overflow, or intermediate event.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>NO_CHANGE</name>
<description>Capture/Compare, overflow, or intermediate events do not control the output state.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWMMD</name>
<description>PWM N-Bit Mode. </description>
<bitOffset>2</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DIFGEN</name>
<description>Differential Signal Generator Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the differential signal generator. The channel will output a single non-differential output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the differential signal generator. The channel will output two differential outputs: X Phase (XPH) and Y Phase (YPH).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMD</name>
<description>Channel Operating Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>EDGE_PWM</name>
<description>Configure the channel for edge-aligned PWM mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CENTER_ALIGNED_PWM</name>
<description>Configure the channel for center-aligned PWM mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>HF_SQUARE_WAVE</name>
<description>Configure the channel for high-frequency/square-wave mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CAPTURE</name>
<description>Configure the channel for timer/capture mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>N_BIT_PWM</name>
<description>Configure the channel for n-bit edge-aligned PWM mode.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL_5</name>
<description>Channel Capture/Compare Control</description>
<addressOffset>0x150</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COUTST</name>
<description>Channel Output State. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The channel output state is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The channel output state is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPCAPEN</name>
<description>Positive Edge Input Capture Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable positive-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable positive-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CNCAPEN</name>
<description>Negative Edge Input Capture Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable negative-edge input capture.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable negative-edge input capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CUPDCF</name>
<description>Channel Register Update Complete Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A EPCA channel register update completed or is not pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A EPCA channel register update has not completed and is still pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>YPHST</name>
<description>Differential Y Phase State. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the Y Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the Y Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACTIVEPH</name>
<description>Active Channel Select. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>YACTIVE</name>
<description>The Y Phase is active and X Phase is inactive.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>XACTIVE</name>
<description>The X Phase is active and Y Phase is inactive.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XPHST</name>
<description>Differential X Phase State. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Set the X Phase output state to low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Set the X Phase output state to high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCIEN</name>
<description>Capture/Compare Interrupt Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel capture/compare interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel capture/compare interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCDEN</name>
<description>Capture/Compare DMA Request Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CCSEN</name>
<description>Capture/Compare Synchronization Signal Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel capture/compare event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel capture/compare event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFIEN</name>
<description>Intermediate Overflow Interrupt Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the channel intermediate overflow interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the channel intermediate overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFDEN</name>
<description>Intermediate Overflow DMA Request Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not request DMA data when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Request DMA data when a channel intermediate overflow event occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CIOVFSEN</name>
<description>Intermediate Overflow Synchronization Signal Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a synchronization signal when a channel intermediate overflow event occurs.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a synchronization signal when a channel intermediate overflow occurs.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCAPV_5</name>
<description>Channel Compare Value</description>
<addressOffset>0x160</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPV</name>
<description>Channel Compare Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCAPVUPD_5</name>
<description>Channel Compare Update Value</description>
<addressOffset>0x170</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CCAPVUPD</name>
<description>Channel Compare Update Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LPOSC_0</name>
<version>A</version>
<description>None</description>
<groupName>Factory</groupName>
<baseAddress>0x40041000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>OSCVAL</name>
<description>Low Power Oscillator Output Value</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000008</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OSCVAL</name>
<description>Low Power Oscillator Output Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FLASHCTRL_0</name>
<version>A</version>
<description>None</description>
<groupName>FLASHCTRL_0</groupName>
<baseAddress>0x4002e000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONFIG</name>
<description>Controller Configuration</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000720</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SPMD</name>
<description>Flash Speed Mode. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MODE0</name>
<description>Read and write the flash at speed mode 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>Read and write the flash at speed mode 1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>Read and write the flash at speed mode 2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE3</name>
<description>Read and write the flash at speed mode 3.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDSEN</name>
<description>Read Store Mode Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable read store mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable read store mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DPFEN</name>
<description>Data Prefetch Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Data accesses are excluded from the prefetch buffer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Data accesses are included in the prefetch buffer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PFINH</name>
<description>Prefetch Inhibit. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Any reads from flash are prefetched until the prefetch buffer is full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Inhibit the prefetch engine.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SQWEN</name>
<description>Flash Write Sequence Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable sequential write mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable sequential write mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ERASEEN</name>
<description>Flash Page Erase Enable. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Writes to the WRDATA field will initiate a write to flash at the address in the WRADDR field.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Writes to the WRDATA field will initiate an erase of the flash page containing the address in the WRADDR field.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUFSTS</name>
<description>Flash Buffer Status. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>EMPTY</name>
<description>The flash controller write data buffer is empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FULL</name>
<description>The flash controller write data buffer is full.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSYF</name>
<description>Flash Operation Busy Flag. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The flash interface is not busy.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The flash interface is busy with an operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WRADDR</name>
<description>Flash Write Address</description>
<addressOffset>0xa0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WRADDR</name>
<description>Flash Write Address. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WRDATA</name>
<description>Flash Write Data</description>
<addressOffset>0xb0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WRDATA</name>
<description>Flash Write Data. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>KEY</name>
<description>Flash Modification Key</description>
<addressOffset>0xc0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Flash Key. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MULTI_LOCK</name>
<value>90</value>
</enumeratedValue>
<enumeratedValue>
<name>INITIAL_UNLOCK</name>
<value>165</value>
</enumeratedValue>
<enumeratedValue>
<name>SINGLE_UNLOCK</name>
<value>241</value>
</enumeratedValue>
<enumeratedValue>
<name>MULTI_UNLOCK</name>
<value>242</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TCONTROL</name>
<description>Flash Timing Control</description>
<addressOffset>0xd0</addressOffset>
<resetValue>0x0003005C</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLRTMD</name>
<description>Flash Read Timing Mode. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SLOW</name>
<description>Configure the flash read controller for AHB clocks below 12 MHz.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST</name>
<description>Configure the flash read controller for AHB clocks above 12 MHz.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C_0</name>
<version>A</version>
<description>None</description>
<groupName>I2C_0</groupName>
<baseAddress>0x40009000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C0_IRQn</name>
<value>28</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x10000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BUSYF</name>
<description>Busy Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A transaction is not currently taking place.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A transaction is currently taking place.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACK</name>
<description>Acknowledge. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: ACK has not been received. Write: Do not send an ACK.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: ACK received. Write: Send an ACK.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ARBLF</name>
<description>Arbitration Lost Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Arbitration lost error has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Arbitration lost error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKRQF</name>
<description>Acknowledge Request Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>ACK has not been requested.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>ACK requested.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STO</name>
<description>Stop. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A stop is not pending and a stop / repeat start has not been detected. Write: Clear the STO bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Stop or stop / repeat start detected. This bit must be cleared by firmware. Write: Generate a stop.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STA</name>
<description>Start. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A start is not pending and a repeat start has not been detected. Write: Clear the STA bit. </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Start or repeat start detected. This bit must be cleared by firmware. Write: Generate a start or repeat start. </description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXMDF</name>
<description>Transmit Mode Flag. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RECEIVE</name>
<description>Module is in receiver mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSMIT</name>
<description>Module is in transmitter mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSMDF</name>
<description>Master/Slave Mode Flag. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>SLAVE</name>
<description>Module is operating in Slave mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MASTER</name>
<description>Module is operating in Master mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STOI</name>
<description>Stop Interrupt Flag. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A stop interrupt has not occurred. Write: Clear the stop interrupt flag (STOI).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Stop interrupt detected. In Slave mode, a stop has been detected on the bus. In Master mode, a stop has been generated. Write: Force a stop interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKI</name>
<description>Acknowledge Interrupt Flag. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: An acknowledge interrupt has not occurred. Write: Clear the acknowledge interrupt (ACKI).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: An acknowledge interrupt occurred. Write: Force an acknowledge interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXI</name>
<description>Receive Done Interrupt Flag. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A receive done interrupt has not occurred. Write: Clear the receive done interrupt (RXI). </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Receive done interrupt occurred. Write: Force a receive done interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXI</name>
<description>Transmit Done Interrupt Flag. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A transmit done interrupt has not occurred. Write: Clear the transmit done interrupt (TXI).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Transmit done interrupt detected. If the transmit is forced to abort by a NACK response, the acknowledge interrupt (ACKI) will also be set. Write: Force a transmit done interrupt. </description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STAI</name>
<description>Start Interrupt Flag. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: Start interrupt has not occurred. Write: Clear the start interrupt (STAI). </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Start or repeat start interrupt occurred. In Slave mode, a start or repeat start is detected. In Master mode, a start or repeat start has been generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ARBLI</name>
<description>Arbitration Lost Interrupt Flag. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: An arbitration lost interrupt has not occurred. Write: Clear the arbitration lost interrupt (ARBLI).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Arbitration lost interrupt detected. Write: Force an arbitration lost interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T0I</name>
<description>I2C Timer Byte 0 Interrupt Flag. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A I2C Timer Byte 0 interrupt has not occurred. Write: Clear the I2C Timer Byte 0 interrupt (T0I).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: I2C Timer Byte 0 overflow interrupt detected. Write: Force a I2C Timer Byte 0 interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T1I</name>
<description>I2C Timer Byte 1 Interrupt Flag. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: No interrupt occurred. Write: Clear the I2C Timer Byte 1 interrupt (T1I).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: I2C Timer Byte 1 overflow interrupt is detected. Write: Force a I2C Timer Byte 1 interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T2I</name>
<description>I2C Timer Byte 2 Interrupt Flag. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A I2C Timer Byte 2 interrupt has not occurred. Write: Clear the I2C Timer Byte 2 interrupt (T2I).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: I2C Timer Byte 2 overflow interrupt detected. Write: Force a I2C Timer Byte 2 interrupt. </description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T3I</name>
<description>I2C Timer Byte 3 Interrupt Flag. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A I2C Timer Byte 3 interrupt or SCL low timeout has not occurred. Write: Clear the I2C Timer Byte 3 interrupt (T3I).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: I2C Timer Byte 3 overflow or SCL low timeout interrupt detected. Write: Force a I2C Timer Byte 3 interrupt. </description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXARM</name>
<description>Receive Arm. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable data and address reception.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the module to perform a receive operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXARM</name>
<description>Transmit Arm. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable data and address transmission.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the module to perform a transmit operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVAF</name>
<description>Slave Address Type Flag. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>SLAVE_ADDRESS</name>
<description>Slave address detected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GENERAL_CALL</name>
<description>General Call address detected.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ATXRXEN</name>
<description>Auto Transmit or Receive Enable. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not automatically switch to transmit or receive mode after a Start.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>If automatic hardware acknowledge mode is enabled (HACKEN = 1), automatically switch to transmit or receive mode after a Start.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FMD</name>
<description>Filter Mode. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the input filter.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the input filter.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>I2C Debug Mode. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The I2C module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the I2C module to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SMINH</name>
<description>Slave Mode Inhibit. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>Enable Slave modes.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Inhibit Slave modes. The module will not respond to a Master on the bus.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HACKEN</name>
<description>Auto Acknowledge Enable . </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable automatic hardware acknowledge.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable automatic hardware acknowledge.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBACKEN</name>
<description>Last Byte Acknowledge Enable. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>NACK after the last byte is received.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>ACK after the last byte is received.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GCEN</name>
<description>General Call Address Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable General Call address decoding.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable General Call address decoding.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET</name>
<description>Module Soft Reset. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>I2C module is not in soft reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>I2C module is in soft reset and firmware cannot access all bits in the module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2CEN</name>
<description>I2C Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the I2C module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the I2C module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONFIG</name>
<description>Module Configuration</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SCALER</name>
<description>I2C Clock Scaler. </description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>STOIEN</name>
<description>Stop Interrupt Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the stop interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the stop interrupt (STOI).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACKIEN</name>
<description>Acknowledge Interrupt Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the acknowledge interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the acknowledge interrupt (ACKI).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXIEN</name>
<description>Receive Done Interrupt Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the receive done interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the receive done interrupt (RXI).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXIEN</name>
<description>Transmit Done Interrupt Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmit done interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmit done interrupt (TXI).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STAIEN</name>
<description>Start Interrupt Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the start interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the start interrupt (STAI).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ARBLIEN</name>
<description>Arbitration Lost Interrupt Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the arbitration lost interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the arbitration lost interrupt (ARBLI).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T0IEN</name>
<description>I2C Timer Byte 0 Interrupt Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the I2C Timer Byte 0 interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the I2C Timer Byte 0 interrupt (T0I).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T1IEN</name>
<description>I2C Timer Byte 1 Interrupt Enable. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the I2C Timer Byte 1 interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the I2C Timer Byte 1 interrupt (T1I).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T2IEN</name>
<description>I2C Timer Byte 2 Interrupt Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the I2C Timer Byte 2 interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the I2C Timer Byte 2 interrupt (T2I).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T3IEN</name>
<description>I2C Timer Byte 3 Interrupt Enable. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the I2C Timer Byte 3 and SCL low timeout interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the I2C Timer Byte 3 and SCL low timeout interrupt (T3I).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BC</name>
<description>Transfer Byte Count. </description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>BP</name>
<description>Transfer Byte Pointer. </description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>T0RUN</name>
<description>I2C Timer Byte 0 Run. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop Timer Byte 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Start Timer Byte 0 running.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T1RUN</name>
<description>I2C Timer Byte 1 Run. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop Timer Byte 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Start Timer Byte 1 running.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T2RUN</name>
<description>I2C Timer Byte 2 Run. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop Timer Byte 2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Start Timer Byte 2 running.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>T3RUN</name>
<description>I2C Timer Byte 3 Run. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop Timer Byte 3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Start Timer Byte 3 running.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMD</name>
<description>I2C Timer Mode. </description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MODE0</name>
<description>I2C Timer Mode 0: Operate the I2C timer as a single 32-bit timer : Timer Bytes [3 : 2 : 1 : 0].</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>I2C Timer Mode 1: Operate the I2C timer as two 16-bit timers : Timer Bytes [3 : 2] and Timer Bytes [1 : 0].</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>I2C Timer Mode 2: Operate the I2C timer as four independent 8-bit timers : Timer Byte 3, Timer Byte 2, Timer Byte 1, and Timer Byte 0.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE3</name>
<description>I2C Timer Mode 3: Operate the I2C timer as one 16-bit and two 8-bit timers : Timer Bytes [3 : 2], Timer Byte 1, and Timer Byte 0.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMEREN</name>
<description>I2C Timer Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable I2C Timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable I2C Timer for general purpose use. This setting should not be used when the I2C module is enabled (I2CEN = 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SADDRESS</name>
<description>Slave Address</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADDRESS</name>
<description>Slave Address. </description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMASK</name>
<description>Slave Address Mask</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MASK</name>
<description>Slave Address Mask. </description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description>Data Buffer Access</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Data. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER</name>
<description>Timer Data</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0</name>
<description>Timer Byte 0. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>T1</name>
<description>Timer Byte 1. </description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>T2</name>
<description>Timer Byte 2. </description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>T3</name>
<description>Timer Byte 3. </description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMERRL</name>
<description>Timer Reload Values</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>T0RL</name>
<description>Timer Byte 0 Reload / Bus Free Timeout. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>T1RL</name>
<description>Timer Byte 1 Reload / SCL High Time. </description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>T2RL</name>
<description>Timer Byte 2 Reload / SCL Low Timeout Bits [11:4]. </description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>T3RL</name>
<description>Timer Byte 3 Reload / SCL Low Timeout Bits [19:12]. </description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCONFIG</name>
<description>SCL Signal Configuration</description>
<addressOffset>0x70</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SETUP</name>
<description>Data Setup Time Extension. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>HOLD</name>
<description>Data Hold Time Extension. </description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SCLL</name>
<description>SCL Low Time. </description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SCLLTIMER</name>
<description>SCL Low Timeout Bits [3:0]. </description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>I2CDMA</name>
<description>DMA Configuration</description>
<addressOffset>0x80</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMALEN</name>
<description>DMA Transfer Length. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA Mode Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable I2C DMA data requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable I2C DMA data requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>IDAC_0</name>
<version>A</version>
<description>None</description>
<groupName>IDAC_0</groupName>
<baseAddress>0x40031000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>IDAC0_IRQn</name>
<value>42</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000007</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OUPDT</name>
<description>Output Update Trigger. </description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DACNT8</name>
<description>The IDAC output updates using the DACnT8 (Timer 0 Low Overflow) trigger source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT9</name>
<description>The IDAC output updates using the DACnT9 (Timer 0 High Overflow) trigger source.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT10</name>
<description>The IDAC output updates using the DACnT10 (Timer 1 Low Overflow) trigger source.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT11</name>
<description>The IDAC output updates using the DACnT11 (Timer 1 High Overflow) trigger source.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT12</name>
<description>The IDAC output updates on the rising edge of the trigger source selected by ETRIG.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT13</name>
<description>The IDAC output updates on the falling edge of the trigger source selected by ETRIG.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT14</name>
<description>The IDAC output updates on any edge of the trigger source selected by ETRIG.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT15</name>
<description>The IDAC output updates on write to DATA register (On Demand).</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ETRIG</name>
<description>Edge Trigger Source Select. </description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DACNT0</name>
<description>Select DACnT0 (DAC0T0 routed through crossbar) as the IDAC external trigger source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT1</name>
<description>Select DACnT1 (RESERVED) as the IDAC external trigger source.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT2</name>
<description>Select DACnT2 (RESERVED) as the IDAC external trigger source.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT3</name>
<description>Select DACnT3 (RESERVED) as the IDAC external trigger source.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT4</name>
<description>Select DACnT4 (RESERVED) as the IDAC external trigger source.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT5</name>
<description>Select DACnT5 (RESERVED) as the IDAC external trigger source.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT6</name>
<description>Select DACnT6 (RESERVED) as the IDAC external trigger source.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>DACNT7</name>
<description>Select DACnT7 (RESERVED) as the IDAC external trigger source.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUTMD</name>
<description>Output Mode. </description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0P5_MA</name>
<description>The full-scale output current is 0.5 mA.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_MA</name>
<description>The full-scale output current is 1 mA.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_MA</name>
<description>The full-scale output current is 2 mA.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INFMT</name>
<description>Data Input Format. </description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>1_10_BIT</name>
<description>Writes are interpreted as one 10-bit sample.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>2_10_BIT</name>
<description>Writes are interpreted as two 10-bit samples.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>4_8_BIT</name>
<description>Writes are interpreted as four 8-bit samples.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMARUN</name>
<description>DMA Run. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Read: No DMA operations are occurring or the DMA is done. Write: No effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Read: A DMA operation is currently in progress. Write: Start a DMA operation.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>JSEL</name>
<description>Data Justification Select. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RIGHT</name>
<description>Data is right-justified.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LEFT</name>
<description>Data is left-justified.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUFRESET</name>
<description>Data Buffer Reset. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>RESET</name>
<description>Initiate a data buffer reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRIGINH</name>
<description>Trigger Source Inhibit. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The selected trigger source will cause the IDAC output to update.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>The selected trigger source will not update the IDAC output, except for On-Demand DATA writes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WRAPEN</name>
<description>Wrap Mode Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The IDAC will not wrap when it reaches the end of the data buffer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The IDAC will cycle through the data buffer contents.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORIEN</name>
<description>FIFO Overrun Interrupt Enable. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the FIFO overrun interrupt (ORI).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the FIFO overrun interrupt (ORI).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>URIEN</name>
<description>FIFO Underrun Interrupt Enable. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the FIFO underrun interrupt (URI).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the FIFO underrun interrupt (URI).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WEIEN</name>
<description>FIFO Went Empty Interrupt Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the FIFO went empty interrupt (WEI).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the FIFO went empty interrupt (WEI).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>IDAC Debug Mode. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The IDAC module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the IDAC module to halt (ignore update triggers).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOADEN</name>
<description>Load Resistor Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the internal load resistor.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the internal load resistor.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDACEN</name>
<description>IDAC Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the IDAC.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the IDAC.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description>Output Data</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Output Data. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BUFSTATUS</name>
<description>FIFO Buffer Status</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LEVEL</name>
<description>FIFO Level. </description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>EMPTY</name>
<description>The data FIFO is empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1WORD</name>
<description>The data FIFO contains one word.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>2WORDS</name>
<description>The data FIFO contains two words.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>3WORDS</name>
<description>The data FIFO contains three words.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>4WORDS</name>
<description>The data FIFO is full and contains four words.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ORI</name>
<description>FIFO Overrun Interrupt Flag. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A FIFO overrun has not occurred. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A FIFO overrun occurred. Write: Force a FIFO overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>URI</name>
<description>FIFO Underrun Interrupt Flag. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A FIFO underrun has not occurred. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A FIFO underrun occurred. Write: Force a FIFO underrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WEI</name>
<description>FIFO Went Empty Interrupt Flag. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A FIFO went empty condition has not occurred. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: The FIFO is empty. Write: Force a FIFO went empty interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BUFFER10</name>
<description>FIFO Buffer Entries 0 and 1</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BUFFER0</name>
<description>FIFO Buffer Entry 0. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BUFFER1</name>
<description>FIFO Buffer Entry 1. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BUFFER32</name>
<description>FIFO Buffer Entries 2 and 3</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BUFFER2</name>
<description>FIFO Buffer Entry 2. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BUFFER3</name>
<description>FIFO Buffer Entry 3. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GAINADJ</name>
<description>Output Current Gain Adjust</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x0000000D</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GAINADJ</name>
<description>Output Current Gain Adjust. </description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LDO_0</name>
<version>A</version>
<description>None</description>
<groupName>LDO_0</groupName>
<baseAddress>0x40039000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00343434</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ALDOOVAL</name>
<description>Analog LDO Output Value Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>ALDOBSEL</name>
<description>Analog LDO Bias Select. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Select a low bias for the analog LDO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Select a high bias for the analog LDO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALDOSSEL</name>
<description>Analog LDO Source Select. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>VBAT</name>
<description>Select the VBAT pin as the input voltage to the analog LDO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DCDC</name>
<description>Select the output of the DC-DC converter as the input voltage to the analog LDO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MLDOOVAL</name>
<description>Memory LDO Output Value Select. </description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>MLDOBSEL</name>
<description>Memory LDO Bias Select. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Select a low bias for the memory LDO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Select a high bias for the memory LDO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MLDOSSEL</name>
<description>Memory LDO Source Select. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>VBAT</name>
<description>Select the VBAT pin as the input voltage to the memory LDO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DCDC</name>
<description>Select the output of the DC-DC converter as the input voltage to the memory LDO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DLDOOVAL</name>
<description>Digital LDO Output Value Select. </description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DLDOBSEL</name>
<description>Digital LDO Bias Select. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Select a low bias for the digital LDO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Select a high bias for the digital LDO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DLDOSSEL</name>
<description>Digital LDO Source Select. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>VBAT</name>
<description>Select the VBAT pin as the input voltage to the digital LDO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DCDC</name>
<description>Select the output of the DC-DC converter as the input voltage to the digital LDO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LOCK_0</name>
<version>A</version>
<description>None</description>
<groupName>LOCK_0</groupName>
<baseAddress>0x40049000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>KEY</name>
<description>Security Key</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Peripheral Lock Mask Key. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOCKED</name>
<description>PERIPHLOCK registers are locked and no valid values have been written to KEY.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INTERMEDIATE</name>
<description>PERIPHLOCK registers are locked and the first valid value (0xA5) has been written to KEY.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>UNLOCKED</name>
<description>PERIPHLOCK registers are unlocked. Any subsequent writes to KEY will lock the interface.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PERIPHLOCK0</name>
<description>Peripheral Lock Control 0</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>USARTL</name>
<description>USART/UART Module Lock Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the USART0 and UART0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the USART0 and UART0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIL</name>
<description>SPI Module Lock Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the SPI0 and SPI1 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the SPI0 and SPI1 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2CL</name>
<description>I2C Module Lock Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the I2C0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the I2C0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PCAL</name>
<description>PCA Module Lock Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the EPCA0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the EPCA0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIMERL</name>
<description>Timer Module Lock Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the TIMER0, TIMER1, and TIMER2 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the TIMER0, TIMER1, and TIMER2 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SARADCL</name>
<description>SARADC Module Lock Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the SARADC0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the SARADC0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMPL</name>
<description>Comparator Module Lock Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the Comparator 0 and Comparator 1 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the Comparator 0 and Comparator 1 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AESL</name>
<description>AES Module Lock Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the AES0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the AES0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRCL</name>
<description>CRC Module Lock Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the CRC0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the CRC0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCL</name>
<description>RTC Module Lock Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the RTC0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the RTC0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTSRCL</name>
<description>Reset Sources Module Lock Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the Reset Sources (RSTSRC) Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the Reset Sources (RSTSRC) Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKCTRL</name>
<description>Clock Control Lock Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the Clock Control (CLKCTRL)Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the Clock Control (CLKCTRL) Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VMONL</name>
<description>Voltage Supply Monitor Module Lock Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the Voltage Supply Monitor (VMON0) Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the Voltage Supply Monitor (VMON0) Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDACL</name>
<description>IDAC Module Lock Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the IDAC0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the IDAC0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMACTRLL</name>
<description>DMA Controller Module Lock Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the DMA Controller (DMACTRL0) Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the DMA Controller (DMACTRL0) Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAXBARL</name>
<description>DMA Crossbar Module Lock Enable. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the DMA Crossbar (DMAXBAR0) Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the DMA Crossbar (DMAXBAR0) Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTL</name>
<description>Low Power Timer Module Lock Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the Low Power Timer (LPTIMER0) Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the Low Power Timer (LPTIMER0) Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LDOL</name>
<description>Voltage Reference Module Lock Enable. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the LDO0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the LDO0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PLLL</name>
<description>PLL Module Lock Enable. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the PLL0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the PLL0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXTOSCL</name>
<description>External Oscillator Module Lock Enable. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the External Oscillator (EXTOSC0) Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the External Oscillator (EXTOSC0) Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PVTL</name>
<description>PVT Oscillator Module Lock Enable. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the PVTOSC0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the PVTOSC0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPOSCL</name>
<description>Low Power Oscillator Lock Enable. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the Low Power Oscillator (LPOSC0) Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the Low Power Oscillator (LPOSC0) Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACCTRL</name>
<description>Advanced Capture Counter Module Lock. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the Advanced Capture Counter (ACCTR0) Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the Advanced Capture Counter (ACCTR0) Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMUL</name>
<description>PMU Module Lock Enable. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the PMU Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the PMU Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DTML</name>
<description>DTM Module Lock. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the DTM0, DTM1, and DTM2 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the DTM0, DTM1, and DTM2 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCDL</name>
<description>LCD Module Lock. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the LCD0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the LCD0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DCDCL</name>
<description>DC-DC Converter Module Lock. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the DCDC0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the DCDC0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PERIPHLOCK1</name>
<description>Peripheral Lock Control 1</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENCDECL</name>
<description>Encoder Decoder Module Lock. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Unlock the ENCDEC0 Module registers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>Lock the ENCDEC0 Module registers (bits can still be read).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LPTIMER_0</name>
<version>B</version>
<description>None</description>
<groupName>LPTIMER_0</groupName>
<baseAddress>0x40038000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LPTIMER0_IRQn</name>
<value>4</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x20000400</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CMD</name>
<description>Count Mode. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>FREE</name>
<description>The timer is free running mode on the RTC timer clock (RTC0TCLK).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGE</name>
<description>The timer is incremented on the rising edges of the selected external trigger (LPTnTx).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING_EDGE</name>
<description>The timer is incremented on the falling edges of the selected external trigger (LPTnTx).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ANY_EDGE</name>
<description>The timer is incremented on both edges of the selected external trigger (LPTnTx).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EXTSEL</name>
<description>External Trigger Source Select. </description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LPTNT0</name>
<description>Select external trigger LPTnT0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT1</name>
<description>Select external trigger LPTnT1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT2</name>
<description>Select external trigger LPTnT2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT3</name>
<description>Select external trigger LPTnT3.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT4</name>
<description>Select external trigger LPTnT4.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT5</name>
<description>Select external trigger LPTnT5.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT6</name>
<description>Select external trigger LPTnT6.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT7</name>
<description>Select external trigger LPTnT7.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT8</name>
<description>Select external trigger LPTnT8.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT9</name>
<description>Select external trigger LPTnT9.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT10</name>
<description>Select external trigger LPTnT10.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT11</name>
<description>Select external trigger LPTnT11.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT12</name>
<description>Select external trigger LPTnT12.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT13</name>
<description>Select external trigger LPTnT13.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT14</name>
<description>Select external trigger LPTnT14.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>LPTNT15</name>
<description>Select external trigger LPTnT15.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMRSET</name>
<description>Timer Set. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Writing a 1 to TMRSET initiates a copy of the value from the COUNT register into the internal timer register. This field is automatically cleared by hardware when the copy is complete and does not need to be cleared by software.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMRCAP</name>
<description>Timer Capture. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Writing a 1 to TMRCAP initiates a read of internal timer register into the COUNT register. This field is automatically cleared by hardware when the operation completes and does not need to be cleared by software.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSMDEN</name>
<description>High Speed Timer Access Mode Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable high speed timer access mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable high speed timer access mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0EN</name>
<description>Timer Compare 0 Threshold Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1EN</name>
<description>Timer Compare 1 Threshold Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUTEN</name>
<description>Output Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the LPTIMER0 output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the LPTIMER0 output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVFIEN</name>
<description>Timer Overflow Interrupt Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the timer overflow interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the timer overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0IEN</name>
<description>Timer Compare 0 Event Interrupt Enable. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the timer compare 0 event interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the timer compare 0 event interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OVFOEN</name>
<description>Timer Overflow Output Enable. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Timer overflows do not modify the Low Power Timer output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Timer overflows set the Low Power Timer output to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0OEN</name>
<description>Timer Compare 0 Event Output Enable. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Timer compare 0 events do not modify the Low Power Timer output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Timer compare 0 events clear the Low Power Timer output to 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1IEN</name>
<description>Timer Compare 1 Event Interrupt Enable. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the timer compare 1 event interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the timer compare 1 event interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1OEN</name>
<description>Timer Compare 1 Event Output Enable. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Timer compare 1 events do not modify the Low Power Timer output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Timer compare 1 events set the Low Power Timer output to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUTINVEN</name>
<description>Output Inversion Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not invert the LPTIMER0 output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Invert the LPTIMER0 output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0RSTEN</name>
<description>Timer Compare 0 Event Reset Enable. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Timer compare 0 events do not reset the timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Timer compare 0 events reset the timer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1RSTEN</name>
<description>Timer Compare 1 Event Reset Enable. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Timer compare 1 events do not reset the timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Timer compare 1 events reset the timer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCLKEN</name>
<description>Low Power Timer Module Clock Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the clock to the Low Power Timer module.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the clock to the Low Power Timer module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>Low Power Timer Debug Mode. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The Low Power Timer module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the Low Power Timer module to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RUN</name>
<description>Timer Run Control and Compare Threshold Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop the timer and disable the compare threshold.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Start the timer running and enable the compare threshold.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>COUNT</name>
<description>Timer Value</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIMER</name>
<description>Timer Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>THRESHOLD</name>
<description>Threshold Values</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>COMPARE0</name>
<description>Timer Compare 0 Threshold Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>COMPARE1</name>
<description>Timer Compare 1 Threshold Value. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Module Status</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OVFI</name>
<description>Timer Overflow Interrupt Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A timer overflow has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A timer overflow occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0I</name>
<description>Timer Compare 0 Event Interrupt Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A timer compare 0 event has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A timer compare 0 event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1I</name>
<description>Timer Compare 1 Event Interrupt Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A timer compare 1 event has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A timer compare 1 event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PLL_0</name>
<version>A</version>
<description>None</description>
<groupName>Oscillators</groupName>
<baseAddress>0x4003b000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PLL0_IRQn</name>
<value>43</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>DIVIDER</name>
<description>Reference Divider Setting</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>M</name>
<description>M Divider Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>N</name>
<description>N Divider Value. </description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00010800</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LLMTF</name>
<description>CAL Saturation (Low) Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>DCO period is not saturated low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>DCO period is saturated low.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HLMTF</name>
<description>CAL Saturation (High) Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>DCO period is not saturated high.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>DCO period is saturated high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCKI</name>
<description>Phase-Lock and Frequency-Lock Locked Interrupt Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>DCO is disabled or not locked.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>DCO is enabled and locked.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LMTIEN</name>
<description>Limit Interrupt Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Saturation (high and low) interrupt disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Saturation (high and low) interrupt enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCKIEN</name>
<description>Locked Interrupt Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The PLL locking does not cause an interrupt</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>An interrupt is generated if LCKI matches the state selected by LCKPOL.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCKPOL</name>
<description>Lock Interrupt Polarity. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ACTIVE_LOW</name>
<description>The lock state PLL interrupt will occur when LCKI is 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE_HIGH</name>
<description>The lock state PLL interrupt will occur when LCKI is 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REFSEL</name>
<description>Reference Clock Selection Control. </description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RTC0TCLK</name>
<description>PLL reference clock (FREF) is the RTC0 oscillator (RTC0TCLK).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LPOSC0DIV</name>
<description>PLL reference clock (FREF) is the divided Low Power Oscillator (LPOSC0).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTOSC0</name>
<description>PLL reference clock (FREF) is the external oscillator output (EXTOSC0).</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCKTH</name>
<description>Lock Threshold Control. </description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>STALL</name>
<description>DCO Output Updates Stall. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>In phase-lock and frequency-lock modes, spectrum spreading, and dithering operate normally, if enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>In phase-lock and frequency-lock modes, spectrum spreading, and dithering are prevented from updating the output of the DCO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DITHEN</name>
<description>Dithering Enable. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Automatic DCO output dithering disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Automatic DCO output dithering enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EDGSEL</name>
<description>Edge Lock Select. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>FALLING_EDGE</name>
<description>Lock DCO output frequency to the falling edge of the reference frequency.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING_EDGE</name>
<description>Lock DCO output frequency to the rising edge of the reference frequency.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OUTMD</name>
<description>PLL Output Mode. </description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>DCO output is off.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DCO</name>
<description>DCO output is in Free-Running DCO mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FLL</name>
<description>DCO output is in frequency-lock mode (reference source required).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>PLL</name>
<description>DCO output is in phase-lock mode (reference source required).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SSPR</name>
<description>Spectrum Spreading Control</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SSAMP</name>
<description>Spectrum Spreading Amplitude. </description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable Spectrum Spreading.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SETTING1</name>
<description>Spectrum Spreading set to approximately +/- 0.1% of TDCO.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SETTING2</name>
<description>Spectrum Spreading set to approximately +/- 0.2% of TDCO.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SETTING3</name>
<description>Spectrum Spreading set to approximately +/- 0.4% of TDCO.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>SETTING4</name>
<description>Spectrum Spreading set to approximately +/- 0.8% of TDCO.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>SETTING5</name>
<description>Spectrum Spreading set to approximately +/- 1.6% of TDCO.</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SSUINV</name>
<description>Spectrum Spreading Update Interval. </description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALCONFIG</name>
<description>Calibration Configuration</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DITHER</name>
<description>DCO Dither Setting. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CAL</name>
<description>DCO Calibration Value. </description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>RANGE</name>
<description>DCO Range. </description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RANGE0</name>
<description>DCO operates from 23 to 37 MHz.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE1</name>
<description>DCO operates from 33 to 50 MHz.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE2</name>
<description>DCO operates from 45 to 50 MHz.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>EXTOSC_0</name>
<version>A</version>
<description>None</description>
<groupName>Oscillators</groupName>
<baseAddress>0x4003c000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Oscillator Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FREQCN</name>
<description>Frequency Control. </description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RANGE0</name>
<description>Set the external oscillator to range 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE1</name>
<description>Set the external oscillator to range 1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE2</name>
<description>Set the external oscillator to range 2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE3</name>
<description>Set the external oscillator to range 3.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE4</name>
<description>Set the external oscillator to range 4.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE5</name>
<description>Set the external oscillator to range 5.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE6</name>
<description>Set the external oscillator to range 6.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>RANGE7</name>
<description>Set the external oscillator to range 7.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSCVLDF</name>
<description>Oscillator Valid Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The external oscillator is unused or not yet stable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The external oscillator is running and stable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSCMD</name>
<description>Oscillator Mode. </description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>External oscillator off.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CMOS</name>
<description>External CMOS clock mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CMOSDIV2</name>
<description>External CMOS with divide by 2 stage.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>RC</name>
<description>RC oscillator mode with divide by 2 stage.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>C</name>
<description>C oscillator mode with divide by 2 stage.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>XTAL</name>
<description>Crystal oscillator mode.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>XTALDIV2</name>
<description>Crystal oscillator mode with divide by 2 stage.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PVTOSC_0</name>
<version>A</version>
<description>None</description>
<groupName>Oscillators</groupName>
<baseAddress>0x4003d000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIGOSCEN</name>
<description>Digital LDO Oscillator Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the digital LDO PVT oscillator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the digital LDO PVT oscillator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MEMOSCEN</name>
<description>Memory LDO Oscillator Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the memory LDO PVT oscillator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the memory LDO PVT oscillator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIGOSCMD</name>
<description>Digital LDO Oscillator Mode. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>FAST</name>
<description>Select fast mode for the digital LDO PVT oscillator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SLOW</name>
<description>Select slow mode for the digital LDO PVT oscillator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MEMOSCMD</name>
<description>High Voltage Oscillator Mode. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>FAST</name>
<description>Select fast mode for the memory LDO PVT oscillator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SLOW</name>
<description>Select slow mode for the memory LDO PVT oscillator.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKSEL</name>
<description>Clock Select. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>OSCILLATORS</name>
<description>Select the digital and memory oscillators as the inputs to the clock dividers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AHB</name>
<description>Select the APB clock as the input to the clock dividers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PMU_0</name>
<version>A</version>
<description>None</description>
<groupName>PMU_0</groupName>
<baseAddress>0x40048000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CPFAIL_IRQn</name>
<value>39</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00FF0060</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WAKECLR</name>
<description>Wakeup Source Clear. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>CLEAR</name>
<description>Clear all wakeup sources.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWAKEEN</name>
<description>Pin Wake Match Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable Pin Wake.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable Pin Wake.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMUASLPEN</name>
<description>PMU Asleep Pin Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the PMU Asleep pin.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the PMU Asleep pin.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPMONEN</name>
<description>Low Power Charge Pump Voltage Monitor Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the low power charge pump voltage monitor.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the low power charge pump voltage monitor.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPMONIEN</name>
<description>Low Power Charge Pump Voltage Monitor Interrupt Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the low power charge pump voltage monitor interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the low power charge pump voltage monitor interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM0REN</name>
<description>RAM 0 Retention Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable power to RAM 0 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable power to RAM 0 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM1REN</name>
<description>RAM 1 Retention Enable. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable power to RAM 1 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable power to RAM 1 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM2REN</name>
<description>RAM 2 Retention Enable. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable power to RAM 2 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable power to RAM 2 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM3REN</name>
<description>RAM 3 Retention Enable. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable power to RAM 3 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable power to RAM 3 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM4REN</name>
<description>RAM 4 Retention Enable. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable power to RAM 4 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable power to RAM 4 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM5REN</name>
<description>RAM 5 Retention Enable. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable power to RAM 5 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable power to RAM 5 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM6REN</name>
<description>RAM 6 Retention Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable power to RAM 6 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable power to RAM 6 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RAM7REN</name>
<description>RAM 7 Retention Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable power to RAM 7 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable power to RAM 7 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONFIG</name>
<description>Module Configuration</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VBATMONEN</name>
<description>VBAT Monitor Disable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the 0.8 V VBAT monitor.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the 0.8V VBAT monitor.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VDRVSMD</name>
<description>VDRV Switch Mode. </description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>HIGHZ</name>
<description>High-Z.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VBAT</name>
<description>VBAT connected to VDRV.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>VDC</name>
<description>DC-DC output connected to VDRV.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPEN</name>
<description>Low Power Charge Pump Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPLOAD</name>
<description>Charge Pump Load Setting. </description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Module Status</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x0000000C</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PM8EF</name>
<description>Power Mode 8 Exited Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The device has not exited Power Mode 8.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The device has exited Power Mode 8. This bit must be cleared by firmware.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWAKEF</name>
<description>Pin Wake Status Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Pin Wake event has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Pin Wake event has occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORF</name>
<description>Power-On Reset Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A power-on reset did not occur since the last time PORF was cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A power-on reset occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPSTS</name>
<description>Low Power Charge Pump Voltage Monitor Status. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The low power charge pump supply voltage is below the threshold.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The low power charge pump supply voltage is greater than the threshold.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WAKEEN</name>
<description>Wakeup Enable</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RTC0FWEN</name>
<description>RTC0 Fail Wake Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>An RTC0 Fail event does not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>An RTC0 Fail event awakens the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTC0A0WEN</name>
<description>RTC0 Alarm Wake Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>An RTC0 Alarm event does not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>An RTC0 Alarm event awakens the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0WEN</name>
<description>Comparator 0 Wake Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>A Comparator 0 event does not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A Comparator 0 event awakens the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACC0WEN</name>
<description>Advanced Capture Counter 0 Wake Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>An Advanced Capture Counter (ACCTR0) event does not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>An Advanced Capture Counter (ACCTR0) event awakens the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCDMONWEN</name>
<description>LCD VBAT Voltage Monitor Wake Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>An LCD VBAT voltage monitor event does not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>An LCD VBAT voltage monitor event awakens the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWAKEWEN</name>
<description>Pin Wake Wake Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>A Pin Wake event does not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A Pin Wake event awakens the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPT0WEN</name>
<description>Low Power Timer Wake Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>An LPTIMER0 event does not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>An LPTIMER0 event awakens the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0WEN</name>
<description>UART0 Wake Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>A UART0 event does not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A UART0 event awakens the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPFWEN</name>
<description>Low Power Charge Pump Supply Fail Wake Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>A low power charge pump supply fail event does not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A low power charge pump supply fail event awakens the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WAKESTATUS</name>
<description>Wakeup Status</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RTC0FWF</name>
<description>RTC0 Fail Wake Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>An RTC0 Fail event did not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An RTC0 Fail event woke the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTC0A0WF</name>
<description>RTC0 Alarm Wake Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>An RTC0 Alarm event did not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An RTC0 Alarm event woke the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0WF</name>
<description>Comparator 0 Wake Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Comparator 0 event did not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Comparator 0 event woke the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACC0WF</name>
<description>Advanced Capture Counter 0 Wake Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>An Advanced Capture Counter (ACCTR0) event did not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An Advanced Capture Counter (ACCTR0) event woke the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCDMONWF</name>
<description>LCD VBAT Voltage Monitor Wake Flag. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A LCD VBAT voltage monitor event did not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A LCD VBAT voltage monitor event woke the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWAKEWF</name>
<description>Pin Wake Wake Flag. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Pin Wake event did not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Pin Wake event woke the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPT0WF</name>
<description>Low Power Timer Wake Flag. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>An LPTIMER0 event did not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An LPTIMER0 event woke the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0WF</name>
<description>UART0 Wake Flag. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A UART0 event did not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A UART0 event woke the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPFWF</name>
<description>Low Power Charge Pump Supply Fail Wake Flag. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A low power charge pump supply fail event did not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A low power charge pump supply fail event woke the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTWF</name>
<description>Reset Pin Wake Flag. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A /RESET Pin event did not wake the device.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A /RESET Pin event woke the device.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWEN</name>
<description>Pin Wake Pin Enable</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PW0EN</name>
<description>WAKE.0 Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.0 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.0 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW1EN</name>
<description>WAKE.1 Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.1 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.1 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW2EN</name>
<description>WAKE.2 Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.2 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.2 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW3EN</name>
<description>WAKE.3 Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.3 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.3 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW4EN</name>
<description>WAKE.4 Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.4 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.4 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW5EN</name>
<description>WAKE.5 Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.5 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.5 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW6EN</name>
<description>WAKE.6 Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.6 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.6 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW7EN</name>
<description>WAKE.7 Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.7 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.7 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW8EN</name>
<description>WAKE.8 Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.8 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.8 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW9EN</name>
<description>WAKE.9 Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.9 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.9 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW10EN</name>
<description>WAKE.10 Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.10 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.10 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW11EN</name>
<description>WAKE.11 Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.11 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.11 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW12EN</name>
<description>WAKE.12 Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.12 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.12 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW13EN</name>
<description>WAKE.13 Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.13 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.13 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW14EN</name>
<description>WAKE.14 Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.14 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.14 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW15EN</name>
<description>WAKE.15 Enable. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>WAKE.15 does not cause a Pin Wake event.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable WAKE.15 as a Pin Wake source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWPOL</name>
<description>Pin Wake Pin Polarity Select</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PW0POL</name>
<description>WAKE.0 Polarity Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.0 causes a Pin Wake event if PW0EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.0 causes a Pin Wake event if PW0EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW1POL</name>
<description>WAKE.1 Polarity Select. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.1 causes a Pin Wake event if PW1EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.1 causes a Pin Wake event if PW1EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW2POL</name>
<description>WAKE.2 Polarity Select. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.2 causes a Pin Wake event if PW2EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.2 causes a Pin Wake event if PW2EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW3POL</name>
<description>WAKE.3 Polarity Select. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.3 causes a Pin Wake event if PW3EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.3 causes a Pin Wake event if PW3EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW4POL</name>
<description>WAKE.4 Polarity Select. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.4 causes a Pin Wake event if PW4EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.4 causes a Pin Wake event if PW4EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW5POL</name>
<description>WAKE.5 Polarity Select. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.5 causes a Pin Wake event if PW5EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.5 causes a Pin Wake event if PW5EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW6POL</name>
<description>WAKE.6 Polarity Select. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.6 causes a Pin Wake event if PW6EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.6 causes a Pin Wake event if PW6EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW7POL</name>
<description>WAKE.7 Polarity Select. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.7 causes a Pin Wake event if PW7EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.7 causes a Pin Wake event if PW7EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW8POL</name>
<description>WAKE.8 Polarity Select. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.8 causes a Pin Wake event if PW8EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.8 causes a Pin Wake event if PW8EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW9POL</name>
<description>WAKE.9 Polarity Select. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.9 causes a Pin Wake event if PW9EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.9 causes a Pin Wake event if PW9EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW10POL</name>
<description>WAKE.10 Polarity Select. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.10 causes a Pin Wake event if PW10EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.10 causes a Pin Wake event if PW10EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW11POL</name>
<description>WAKE.11 Polarity Select. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.11 causes a Pin Wake event if PW11EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.11 causes a Pin Wake event if PW11EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW12POL</name>
<description>WAKE.12 Polarity Select. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.12 causes a Pin Wake event if PW12EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.12 causes a Pin Wake event if PW12EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW13POL</name>
<description>WAKE.13 Polarity Select. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.13 causes a Pin Wake event if PW13EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.13 causes a Pin Wake event if PW13EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW14POL</name>
<description>WAKE.14 Polarity Select. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.14 causes a Pin Wake event if PW14EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.14 causes a Pin Wake event if PW14EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PW15POL</name>
<description>WAKE.15 Polarity Select. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A logic low on WAKE.15 causes a Pin Wake event if PW15EN is set to 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A logic high on WAKE.15 causes a Pin Wake event if PW15EN is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PBCFG_0</name>
<version>A</version>
<description>None</description>
<groupName>PBCFG_0</groupName>
<baseAddress>0x4002a000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PBEXT0_IRQn</name>
<value>1</value>
</interrupt>
<interrupt>
<name>PBEXT1_IRQn</name>
<value>2</value>
</interrupt>
<interrupt>
<name>PMATCH_IRQn</name>
<value>41</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL0</name>
<description>Global Port Control 0</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INT0SEL</name>
<description>External Interrupt 0 Pin Selection. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INT0_0</name>
<description>Select INT0.0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_1</name>
<description>Select INT0.1</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_2</name>
<description>Select INT0.2</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_3</name>
<description>Select INT0.3</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_4</name>
<description>Select INT0.4</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_5</name>
<description>Select INT0.5</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_6</name>
<description>Select INT0.6</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_7</name>
<description>Select INT0.7</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_8</name>
<description>Select INT0.8</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_9</name>
<description>Select INT0.9</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_10</name>
<description>Select INT0.10</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_11</name>
<description>Select INT0.11</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_12</name>
<description>Select INT0.12</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_13</name>
<description>Select INT0.13</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_14</name>
<description>Select INT0.14</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>INT0_15</name>
<description>Select INT0.15</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INT0POL</name>
<description>External Interrupt 0 Polarity. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A low value or falling edge on the selected pin will cause interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A high value or rising edge on the selected pin will cause interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INT0MD</name>
<description>External Interrupt 0 Mode. </description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LEVEL</name>
<description>Interrupt on logic level at pin, as selected by the INT0POL field.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EDGE</name>
<description>Interrupt on either rising or falling edge, as selected by the INT0POL field.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DUAL_EDGE</name>
<description>Interrupt on both rising and falling edges (ignores INT0POL).</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INT0EN</name>
<description>External Interrupt 0 Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable external interrupt 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable external interrupt 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INT1SEL</name>
<description>External Interrupt 1 Pin Selection. </description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INT1_0</name>
<description>Select INT1.0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_1</name>
<description>Select INT1.1</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_2</name>
<description>Select INT1.2</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_3</name>
<description>Select INT1.3</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_4</name>
<description>Select INT1.4</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_5</name>
<description>Select INT1.5</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_6</name>
<description>Select INT1.6</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_7</name>
<description>Select INT1.7</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_8</name>
<description>Select INT1.8</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_9</name>
<description>Select INT1.9</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_10</name>
<description>Select INT1.10</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_11</name>
<description>Select INT1.11</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_12</name>
<description>Select INT1.12</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_13</name>
<description>Select INT1.13</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_14</name>
<description>Select INT1.14</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>INT1_15</name>
<description>Select INT1.15</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INT1POL</name>
<description>External Interrupt 1 Polarity. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>A low value or falling edge on the selected pin will cause interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>A high value or rising edge on the selected pin will cause interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INT1MD</name>
<description>External Interrupt 1 Mode. </description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LEVEL</name>
<description>Interrupt on logic level at pin, as selected by the INT1POL field.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EDGE</name>
<description>Interrupt on either rising or falling edge, as selected by the INT1POL field.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DUAL_EDGE</name>
<description>Interrupt on both rising and falling edges (ignores INT1POL).</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INT1EN</name>
<description>External Interrupt 1 Enable. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable external interrupt 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable external interrupt 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PGTIMER</name>
<description>Pulse Generator Timer. </description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>PGDONEF</name>
<description>Pulse Generator Timer Done Flag. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Firmware has written to the PBPGPHASE register, but the Pulse Generator timer has not expired.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The Pulse Generator cycle finished since the last time PBPGPHASE was written.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL1</name>
<description>Global Port Control 1</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>JTAGEN</name>
<description>JTAG Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>JTAG functionality is not pinned out.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>JTAG functionality is pinned out.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ETMEN</name>
<description>ETM Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>ETM not pinned out.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>ETM is enabled and pinned out.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWVEN</name>
<description>SWV Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>SWV is not pinned out.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>SWV is enabled and pinned out.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI1SEL</name>
<description>SPI1 Fixed Port Selection. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disconnect SPI1 from the dedicated pins.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Connect SPI1 to the dedicated pins.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PMATCHEN</name>
<description>Port Match Interrupt Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the port match logic. The PBnMAT registers are not read/write accessible on the APB bus.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the port match logic to generate a port match interrupt. The PBnMAT registers are read/write accessible on the APB bus.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPTOSEL</name>
<description>Low Power Timer Output Pin Select. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LPT0OUT0</name>
<description>Route the Low Power Timer output to LPT0OUT0. </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LPT0OUT1</name>
<description>Route the Low Power Timer output to LPT0OUT1. </description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCK</name>
<description>Port Bank Configuration Lock. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Port Bank Configuration and Control registers are unlocked.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCKED</name>
<description>The following registers are locked from write access: CONTROL1, XBAR0, and all PBSKIP registers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>XBAR0</name>
<description>Crossbar 0 Control</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>USART0EN</name>
<description>USART0 Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable USART0 RX and TX on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable USART0 RX and TX on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART0FCEN</name>
<description>USART0 Flow Control Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable USART0 flow control on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable USART0 flow control on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>USART0CEN</name>
<description>USART0 Clock Signal Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable USART0 clock on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable USART0 clock on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA0T0EN</name>
<description>DMA Trigger 0 Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the DMA trigger 0 on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the DMA trigger 0 on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMA0T1EN</name>
<description>DMA Trigger 1 Enabled. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the DMA trigger 1 on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the DMA trigger 1 on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IDAC0TEN</name>
<description>IDAC0 Trigger Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the IDAC0 trigger on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the IDAC0 trigger on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI0EN</name>
<description>SPI0 Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable SPI0 SCK, MISO, and MOSI on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable SPI0 SCK, MISO, and MOSI on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPI0NSSEN</name>
<description>SPI0 NSS Pin Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable SPI0 NSS on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable SPI0 NSS on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EPCA0EN</name>
<description>EPCA0 Channel Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NONE</name>
<description>Disable all EPCA0 channels on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CEX0_0</name>
<description>Enable EPCA0 CEX0 on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CEX0_1</name>
<description>Enable EPCA0 CEX0 and CEX1 on Crossbar 0.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CEX0_2</name>
<description>Enable EPCA0 CEX0, CEX1, and CEX2 on Crossbar 0.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>CEX0_3</name>
<description>Enable EPCA0 CEX0, CEX1, CEX2, and CEX3 on Crossbar 0.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>CEX0_4</name>
<description>Enable EPCA0 CEX0, CEX1, CEX2, CEX3, and CEX4 on Crossbar 0.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>CEX0_5</name>
<description>Enable EPCA0 CEX0, CEX1, CEX2, CEX3, CEX4, and CEX5 on Crossbar 0.</description>
<value>6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EECI0EN</name>
<description>EPCA0 ECI Enable. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable EPCA0 ECI on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable EPCA0 ECI on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>I2C0EN</name>
<description>I2C0 Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable I2C0 SDA and SCL on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable I2C0 SDA and SCL on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0SEN</name>
<description>Comparator 0 Synchronous Output (CMP0S) Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0AEN</name>
<description>Comparator 0 Asynchronous Output (CMP0A) Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1SEN</name>
<description>Comparator 1 Synchronous Output (CMP1S) Enable. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1AEN</name>
<description>Comparator 1 Asynchronous Output (CMP1A) Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR0CTEN</name>
<description>TIMER0 T0CT Enable. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable TIMER0 CT on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable TIMER0 CT on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR0EXEN</name>
<description>TIMER0 T0EX Enable. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable TIMER0 EX on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable TIMER0 EX on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR1CTEN</name>
<description>TIMER1 T1CT Enable. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable TIMER1 CT on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable TIMER1 CT on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMR1EXEN</name>
<description>TIMER1 T1EX Enable. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable TIMER1 EX on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable TIMER1 EX on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SARADC0TEN</name>
<description>SARADC0 Trigger Enable. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable SARADC0 conversion start trigger on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable SARADC0 conversion start trigger on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AHBEN</name>
<description>AHB Clock Output Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the AHB Clock / 16 output on Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the AHB Clock / 16 output on Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>XBAR0EN</name>
<description>Crossbar 0 Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable Crossbar 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable Crossbar 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PBKEY</name>
<description>Global Port Key</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Port Bank Key. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOCKED</name>
<description>Port Bank registers are locked and no valid values have been written to PBKEY.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INTERMEDIATE</name>
<description>Port Bank registers are locked and the first valid value (0xA5) has been written to PBKEY.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>UNLOCKED</name>
<description>Port Bank registers are unlocked. Any subsequent writes to the Port Bank registers or PBKEY will lock the interface.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PBGP_4</name>
<version>A</version>
<description>None</description>
<groupName>PBGP_4</groupName>
<baseAddress>0x4002a320</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>PB</name>
<description>Output Latch</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PB</name>
<description>Output Latch. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBPIN</name>
<description>Pin Value</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBPIN</name>
<description>Pin Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PBMDSEL</name>
<description>Mode Select</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBMDSEL</name>
<description>Mode Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBOUTMD</name>
<description>Output Mode</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBOUTMD</name>
<description>Output Mode. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBDRV</name>
<description>Drive Strength</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00010000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBDRV</name>
<description>Drive Strength. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>PBPUEN</name>
<description>Port Bank Weak Pull-up Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable weak pull-ups for this port.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable weak pull-ups for this port.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PM</name>
<description>Port Match Value</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PM</name>
<description>Port Match Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PMEN</name>
<description>Port Match Enable</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMEN</name>
<description>Port Match Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PBSTD_0</name>
<version>A</version>
<description>None</description>
<groupName>Port_Standard</groupName>
<baseAddress>0x4002a0a0</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>PB</name>
<description>Output Latch</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PB</name>
<description>Output Latch. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBPIN</name>
<description>Pin Value</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBPIN</name>
<description>Pin Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PBMDSEL</name>
<description>Mode Select</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBMDSEL</name>
<description>Mode Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBSKIPEN</name>
<description>Crossbar Pin Skip Enable</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBSKIPEN</name>
<description>Crossbar Pin Skip Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBOUTMD</name>
<description>Output Mode</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBOUTMD</name>
<description>Output Mode. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBDRV</name>
<description>Drive Strength</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00010000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBDRV</name>
<description>Drive Strength. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>PBPUEN</name>
<description>Port Bank Weak Pull-up Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable weak pull-ups for this port.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable weak pull-ups for this port.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PM</name>
<description>Port Match Value</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PM</name>
<description>Port Match Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PMEN</name>
<description>Port Match Enable</description>
<addressOffset>0x70</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMEN</name>
<description>Port Match Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBPGEN</name>
<description>Pulse Generator Pin Enable</description>
<addressOffset>0x80</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBPGEN</name>
<description>Pulse Generator Pin Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBPGPHASE</name>
<description>Pulse Generator Phase</description>
<addressOffset>0x90</addressOffset>
<resetValue>0x00000FFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBPGPH0</name>
<description>Pulse Generator Phase 0. </description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>PBPGPH1</name>
<description>Pulse Generator Phase 1. </description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PBSTD_1</name>
<version>A</version>
<description>None</description>
<groupName>Port_Standard</groupName>
<baseAddress>0x4002a140</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>PB</name>
<description>Output Latch</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PB</name>
<description>Output Latch. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBPIN</name>
<description>Pin Value</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBPIN</name>
<description>Pin Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PBMDSEL</name>
<description>Mode Select</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBMDSEL</name>
<description>Mode Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBSKIPEN</name>
<description>Crossbar Pin Skip Enable</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBSKIPEN</name>
<description>Crossbar Pin Skip Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBOUTMD</name>
<description>Output Mode</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBOUTMD</name>
<description>Output Mode. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBDRV</name>
<description>Drive Strength</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00010000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBDRV</name>
<description>Drive Strength. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>PBPUEN</name>
<description>Port Bank Weak Pull-up Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable weak pull-ups for this port.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable weak pull-ups for this port.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PM</name>
<description>Port Match Value</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PM</name>
<description>Port Match Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PMEN</name>
<description>Port Match Enable</description>
<addressOffset>0x70</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMEN</name>
<description>Port Match Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PBSTD_2</name>
<version>A</version>
<description>None</description>
<groupName>Port_Standard</groupName>
<baseAddress>0x4002a1e0</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>PB</name>
<description>Output Latch</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PB</name>
<description>Output Latch. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBPIN</name>
<description>Pin Value</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBPIN</name>
<description>Pin Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PBMDSEL</name>
<description>Mode Select</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBMDSEL</name>
<description>Mode Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBSKIPEN</name>
<description>Crossbar Pin Skip Enable</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBSKIPEN</name>
<description>Crossbar Pin Skip Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBOUTMD</name>
<description>Output Mode</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBOUTMD</name>
<description>Output Mode. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBDRV</name>
<description>Drive Strength</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00010000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBDRV</name>
<description>Drive Strength. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>PBPUEN</name>
<description>Port Bank Weak Pull-up Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable weak pull-ups for this port.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable weak pull-ups for this port.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PM</name>
<description>Port Match Value</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PM</name>
<description>Port Match Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PMEN</name>
<description>Port Match Enable</description>
<addressOffset>0x70</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMEN</name>
<description>Port Match Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PBSTD_3</name>
<version>A</version>
<description>None</description>
<groupName>Port_Standard</groupName>
<baseAddress>0x4002a280</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>PB</name>
<description>Output Latch</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PB</name>
<description>Output Latch. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBPIN</name>
<description>Pin Value</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBPIN</name>
<description>Pin Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PBMDSEL</name>
<description>Mode Select</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBMDSEL</name>
<description>Mode Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBSKIPEN</name>
<description>Crossbar Pin Skip Enable</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBSKIPEN</name>
<description>Crossbar Pin Skip Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBOUTMD</name>
<description>Output Mode</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBOUTMD</name>
<description>Output Mode. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PBDRV</name>
<description>Drive Strength</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00010000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PBDRV</name>
<description>Drive Strength. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>PBPUEN</name>
<description>Port Bank Weak Pull-up Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable weak pull-ups for this port.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable weak pull-ups for this port.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PM</name>
<description>Port Match Value</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PM</name>
<description>Port Match Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PMEN</name>
<description>Port Match Enable</description>
<addressOffset>0x70</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMEN</name>
<description>Port Match Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTC_0</name>
<version>B</version>
<description>None</description>
<groupName>RTC_0</groupName>
<baseAddress>0x40029000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTC0ALRM_IRQn</name>
<value>3</value>
</interrupt>
<interrupt>
<name>RTC0FAIL_IRQn</name>
<value>37</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONFIG</name>
<description>RTC Configuration</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ALM0AREN</name>
<description>Alarm 0 Automatic Reset Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the Alarm 0 automatic reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the Alarm 0 automatic reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RUN</name>
<description>RTC Timer Run Control. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop the RTC timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Run the RTC timer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCLKEN</name>
<description>Missing Clock Detector Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the missing clock detector.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the missing clock detector. If the missing clock detector triggers, it will generate an RTC Fail event.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ASEN</name>
<description>Automatic Crystal Load Capacitance Stepping Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable automatic load capacitance stepping.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable automatic load capacitance stepping.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCLC</name>
<description>Load Capacitance Value. </description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BDEN</name>
<description>Bias Doubler Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the bias doubler, saving power.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the bias doubler. </description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CRYSEN</name>
<description>Crystal Oscillator Enable. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the crystal oscillator circuitry.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the crystal oscillator circuitry.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AGCEN</name>
<description>Automatic Gain Control Enable. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable automatic gain control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable automatic gain control, saving power.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALM0EN</name>
<description>Alarm 0 Enable. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable RTC Alarm 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable RTC Alarm 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALM1EN</name>
<description>Alarm 1 Enable. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable RTC Alarm 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable RTC Alarm 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALM2EN</name>
<description>Alarm 2 Enable. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable RTC Alarm 2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable RTC Alarm 2.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKOEN</name>
<description>RTC Clock Output Enable. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the RTCnTCLK output to the timer and other internal modules.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the RTCnTCLK output to the timer and other internal modules.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCOEN</name>
<description>RTC External Output Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the external RTCnTCLK_OUT output.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the external RTCnTCLK_OUT output.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKSEL</name>
<description>RTC Timer Clock Select. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RTCNOSC</name>
<description>Select the External Crystal or External CMOS Clock as the RTC Timer clock (RTCnTCLK) source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LFOSCN</name>
<description>Select the Low Frequency Oscillator as the RTC Timer clock (RTCnTCLK) source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCEN</name>
<description>RTC Timer Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the RTC timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the RTC timer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<description>RTC Control</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ALM0I</name>
<description>Alarm 0 Interrupt Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Alarm 0 event has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Alarm 0 event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALM1I</name>
<description>Alarm 1 Interrupt Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Alarm 1 event has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Alarm 1 event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALM2I</name>
<description>Alarm 2 Interrupt Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Alarm 2 event has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Alarm 2 event occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMRCAP</name>
<description>RTC Timer Capture. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>RTC timer capture operation is complete.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Start the RTC timer capture.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TMRSET</name>
<description>RTC Timer Set. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>RTC timer set operation is complete.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Start the RTC timer set.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKVF</name>
<description>RTC External Oscillator Valid Flag. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>External oscillator is not valid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>External oscillator is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OSCFI</name>
<description>RTC Oscillator Fail Interrupt Flag. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Oscillator is running.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Oscillator has failed.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSMDEN</name>
<description>RTC High Speed Mode Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable high speed mode. (AHBCLK &lt; 4x RTCnTCLK)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable high speed mode. (AHBCLK &gt;= 4x RTCnTCLK)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LRDYF</name>
<description>RTC Load Capacitance Ready Flag. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The load capacitance is currently stepping.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The load capacitance has reached its programmed value.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ALARM0</name>
<description>RTC Alarm 0</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ALARM0</name>
<description>RTC Alarm 0. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALARM1</name>
<description>RTC Alarm 1</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ALARM1</name>
<description>RTC Alarm 1. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALARM2</name>
<description>RTC Alarm 2</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ALARM2</name>
<description>RTC Alarm 2. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SETCAP</name>
<description>RTC Timer Set/Capture Value</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SETCAP</name>
<description>RTC Timer Set/Capture Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LFOCONTROL</name>
<description>LFOSC Control</description>
<addressOffset>0x60</addressOffset>
<resetValue>0xC0000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LFOOEN</name>
<description>Low Frequency Oscillator Output Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the Low Frequency Oscillator output to internal modules.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the Low Frequency Oscillator output to internal module.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LFOSCEN</name>
<description>Low Frequency Oscillator Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the Low Frequency Oscillator (LFOSCn).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the Low Frequency Oscillator (LFOSCn).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RSTSRC_0</name>
<version>A</version>
<description>None</description>
<groupName>RSTSRC_0</groupName>
<baseAddress>0x4002c000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>RESETEN</name>
<description>System Reset Source Enable</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x0000082F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VMONREN</name>
<description>Voltage Supply Monitor VBAT Reset Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the Voltage Supply Monitor VBAT event as a reset source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the Voltage Supply Monitor VBAT event as a reset source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCDREN</name>
<description>Missing Clock Detector Reset Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the Missing Clock Detector event as a reset source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the Missing Clock Detector event as a reset source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDTREN</name>
<description>Watchdog Timer Reset Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the Watchdog Timer event as a reset source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the Watchdog Timer event as a reset source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWREN</name>
<description>Software Reset. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not generate a Software Reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Generate a Software Reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0REN</name>
<description>Comparator 0 Reset Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the Comparator 0 event as a reset source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the Comparator 0 event as a reset source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1REN</name>
<description>Comparator 1 Reset Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the Comparator 1 event as a reset source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the Comparator 1 event as a reset source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPFREN</name>
<description>Low Power Mode Charge Pump Supply Fail Reset Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the low power mode charge pump supply fail event as a reset source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the low power mode charge pump supply fail event as a reset source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTC0REN</name>
<description>RTC0 Reset Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the RTC0 event as a reset source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the RTC0 event as a reset source.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPMREN</name>
<description>Low Power Mode Charge Pump Module Reset Enable. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable low power mode charge pump module resets.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable low power mode charge pump module resets.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UART0MREN</name>
<description>UART0 Module Reset Enable. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable UART0 module resets.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable UART0 module resets.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LCD0MREN</name>
<description>LCD0 Module Reset Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable LCD0 module resets.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable LCD0 module resets.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACC0MREN</name>
<description>ACCTR0 Module Reset Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable ACCTR0 module resets.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable ACCTR0 module resets.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTC0MREN</name>
<description>RTC0 Module Reset Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable RTC0 module resets.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable RTC0 module resets.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RESETFLAG</name>
<description>System Reset Flags</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000002</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PINRF</name>
<description>Pin Reset Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A /RESET pin event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A /RESET pin event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PORRF</name>
<description>Power-On Reset Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Power-On Reset event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Power-On Reset event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VMONRF</name>
<description>Voltage Supply Monitor VBAT Reset Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Voltage Supply Monitor VBAT Reset event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Voltage Supply Monitor VBAT Reset event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CORERF</name>
<description>Core Reset Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Core Reset event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Core Reset event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MCDRF</name>
<description>Missing Clock Detector Reset Flag. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Missing Clock Detector event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Missing Clock Detector event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDTRF</name>
<description>Watchdog Timer Reset Flag. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Watchdog Timer event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Watchdog Timer event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SWRF</name>
<description>Software Reset Flag. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Software Reset event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Software Reset event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP0RF</name>
<description>Comparator 0 Reset Flag. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Comparator 0 event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Comparator 0 event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CMP1RF</name>
<description>Comparator 1 Reset Flag. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A Comparator 1 event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A Comparator 1 event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CPFRF</name>
<description>Low Power Mode Charge Pump Supply Fail Reset Flag. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A low power mode charge pump supply fail event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A low power mode charge pump supply fail event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTC0RF</name>
<description>RTC0 Reset Flag. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>An RTC0 event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>An RTC0 event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WAKERF</name>
<description>PMU Wakeup Reset Flag. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A PMU Wakeup event did not cause the last system reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A PMU Wakeup event caused the last system reset.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SARADC_0</name>
<version>A</version>
<description>None</description>
<groupName>SARADC_0</groupName>
<baseAddress>0x4001a000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SARADC0_IRQn</name>
<value>29</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONFIG</name>
<description>Module Configuration</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PACKMD</name>
<description>Output Packing Mode. </description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UPPER_ONLY</name>
<description>Data is written to the upper half-word and the lower half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOWER_ONLY</name>
<description>Data is written to the lower half-word, and the upper half-word is filled with 0's. An SCI interrupt is triggered when data is written, if enabled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>UPPER_FIRST</name>
<description>Two data words are packed into the register with the upper half-word representing the earlier data, and the lower half-word representing the later data. The ADC write to the lower half-word will trigger the SCI interrupt, if enabled.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>LOWER_FIRST</name>
<description>Two data words are packed into the register with the lower half-word representing the earlier data, and the upper half-word representing the later data. The ADC write to the upper half-word will trigger the SCI interrupt, if enabled.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCANEN</name>
<description>Scan Mode Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable ADC scan mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable ADC scan mode. The ADC will scan through the defined time slots in sequence on every start of conversion.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCANMD</name>
<description>Scan Mode Select. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ONCE</name>
<description>The channel sequencer will cycle through all of the specified time slots once.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOOP</name>
<description>The channel sequencer will cycle through all of the specified time slots in a loop until SCANEN is cleared to 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA Interface Enable . </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the ADC module DMA interface.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the ADC module DMA interface.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BCLKSEL</name>
<description>Burst Mode Clock Select. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LPOSC0</name>
<description>Burst mode uses the Low Power Oscillator.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>APB</name>
<description>Burst mode uses the APB clock.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>SAR Clock Divider. </description>
<bitOffset>16</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>SCCIEN</name>
<description>Single Conversion Complete Interrupt Enable. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the ADC single data conversion complete interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the ADC single data conversion complete interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDIEN</name>
<description>Scan Done Interrupt Enable. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the ADC scan complete interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the ADC scan complete interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FORIEN</name>
<description>FIFO Overrun Interrupt Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the data FIFO overrun interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the data FIFO overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FURIEN</name>
<description>FIFO Underrun Interrupt Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the data FIFO underrun interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the data FIFO underrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<description>Measurement Control</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x1008F078</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>REFGNDSEL</name>
<description>Reference Ground Select. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INTERNAL</name>
<description>The internal device ground is used as the ground reference for ADC conversions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTERNAL</name>
<description>The VREFGND pin is used as the ground reference for ADC conversions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKESEL</name>
<description>Sampling Clock Edge Select. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RISING</name>
<description>Select the rising edge of the APB clock.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FALLING</name>
<description>Select the falling edge of the APB clock.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BMTK</name>
<description>Burst Mode Tracking Time. </description>
<bitOffset>2</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SCSEL</name>
<description>Start-Of-Conversion Source Select. </description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ADCNT0</name>
<description>An ADC conversion triggers from the ADCnT0 (&quot;On Demand&quot; by writing 1 to ADBUSY) trigger source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT1</name>
<description>An ADC conversion triggers from the ADCnT1 (Timer 0 Low Overflow) trigger source.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT2</name>
<description>An ADC conversion triggers from the ADCnT2 (Timer 0 High Overflow) trigger source.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT3</name>
<description>An ADC conversion triggers from the ADCnT3 (Timer 1 Low Overflow) trigger source.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT4</name>
<description>An ADC conversion triggers from the ADCnT4 (Timer 1 High Overflow) trigger source.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT5</name>
<description>An ADC conversion triggers from the ADCnT5 (EPCA0 synchronization pulse) trigger source.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT6</name>
<description>An ADC conversion triggers from the ADCnT6 (I2C0 Timer overflow) trigger source.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT7</name>
<description>An ADC conversion triggers from the ADCnT7 (RESERVED) trigger source.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT8</name>
<description>An ADC conversion triggers from the ADCnT8 (RESERVED) trigger source.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT9</name>
<description>An ADC conversion triggers from the ADCnT9 (RESERVED) trigger source.</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT10</name>
<description>An ADC conversion triggers from the ADCnT10 (RESERVED) trigger source.</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT11</name>
<description>An ADC conversion triggers from the ADCnT11 (RESERVED) trigger source.</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT12</name>
<description>An ADC conversion triggers from the ADCnT12 (RESERVED) trigger source.</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT13</name>
<description>An ADC conversion triggers from the ADCnT13 (RESERVED) trigger source.</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT14</name>
<description>An ADC conversion triggers from the ADCnT14 (RESERVED) trigger source.</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCNT15</name>
<description>An ADC conversion triggers from the ADCnT15 (ADCnT15 routed through crossbar) trigger source.</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PWRTIME</name>
<description>Burst Mode Power Up Time. </description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BURSTEN</name>
<description>Burst Mode Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable burst mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable burst mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADCEN</name>
<description>ADC Enable. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the ADC (low-power shutdown).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the ADC (active and ready for data conversions).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AD12BSSEL</name>
<description>12-Bit Mode Sample Select. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>FOUR</name>
<description>The ADC re-samples the input before each of the four conversions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE</name>
<description>The ADC samples once before the first conversion and converts four times.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VCMEN</name>
<description>Common Mode Buffer Enable. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the common mode buffer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the common mode buffer.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ACCMD</name>
<description>Accumulation Mode. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ACCUMULATE</name>
<description>Conversions will be accumulated for the specified number of cycles in burst mode according to the channel configuration.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEAT</name>
<description>Conversions will not be accumulated in burst mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TRKMD</name>
<description>ADC Tracking Mode. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NORMAL</name>
<description>Normal Tracking Mode: When the ADC is enabled, a conversion begins immediately following the start-of-conversion signal.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DELAYED</name>
<description>Delayed Tracking Mode: When the ADC is enabled, a conversion begins 3 SAR clock cycles following the start-of-conversion signal. The ADC is allowed to track during this time.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ADBUSY</name>
<description>ADC Busy. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIASSEL</name>
<description>Bias Power Select. </description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MODE0</name>
<description>Select bias current mode 0. Recommended to use modes 1, 2, or 3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE1</name>
<description>Select bias current mode 1 (SARCLK = 16 MHz).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE2</name>
<description>Select bias current mode 2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>MODE3</name>
<description>Select bias current mode 3 (SARCLK = 4 MHz).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LPMDEN</name>
<description>Low Power Mode Enable. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable low power mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable low power mode (requires extended tracking time).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MREFLPEN</name>
<description>MUX and VREF Low Power Enable. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable low power mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable low power mode (SAR clock &lt;= 4 MHz).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFSEL</name>
<description>Voltage Reference Select. </description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INTERNAL_VREF</name>
<description>Select the internal, dedicated SARADC voltage reference as the ADC reference.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VDD</name>
<description>Select the VBAT pin as the ADC reference.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>LDO_OUT</name>
<description>Select the output of the internal LDO regulator (~1.8 V) as the ADC reference.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTERNAL_VREF</name>
<description>Select the VREF pin as the ADC reference. This option is used for either an external VREF or the on-chip VREF driving out to the VREF pin.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SQ7654</name>
<description>Channel Sequencer Time Slots 4-7 Setup</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TS4CHR</name>
<description>Time Slot 4 Conversion Characteristic. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CC0</name>
<description>Select conversion characteristic 0 for time slot 4.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CC1</name>
<description>Select conversion characteristic 1 for time slot 4.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CC2</name>
<description>Select conversion characteristic 2 for time slot 4.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CC3</name>
<description>Select conversion characteristic 3 for time slot 4.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS4MUX</name>
<description>Time Slot 4 Input Channel. </description>
<bitOffset>2</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ADCN0</name>
<description>Select channel ADCn.0 (PB0.3).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN1</name>
<description>Select channel ADCn.1 (PB0.9).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN2</name>
<description>Select channel ADCn.2 (PB2.0).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN3</name>
<description>Select channel ADCn.3 (PB2.1).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN4</name>
<description>Select channel ADCn.4 (PB2.2).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN5</name>
<description>Select channel ADCn.5 (PB2.3).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN6</name>
<description>Select channel ADCn.6 (PB2.4).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN7</name>
<description>Select channel ADCn.7 (PB2.5).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN8</name>
<description>Select channel ADCn.8 (PB2.6).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN9</name>
<description>Select channel ADCn.9 (PB2.7).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN10</name>
<description>Select channel ADCn.10 (PB3.3).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN11</name>
<description>Select channel ADCn.11 (PB3.4).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN12</name>
<description>Select channel ADCn.12 (PB3.5).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN13</name>
<description>Select channel ADCn.13 (PB3.6).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN14</name>
<description>Select channel ADCn.14 (PB3.7).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN15</name>
<description>Select channel ADCn.15 (PB3.8).</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN16</name>
<description>Select channel ADCn.16 (PB3.9).</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN17</name>
<description>Select channel ADCn.17 (RESERVED).</description>
<value>17</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN18</name>
<description>Select channel ADCn.18 (RESERVED).</description>
<value>18</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN19</name>
<description>Select channel ADCn.19 (RESERVED).</description>
<value>19</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN20</name>
<description>Select channel ADCn.20 (PB0.0).</description>
<value>20</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN21</name>
<description>Select channel ADCn.21 (RESERVED).</description>
<value>21</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN22</name>
<description>Select channel ADCn.22 (PB0.2).</description>
<value>22</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN23</name>
<description>Select channel ADCn.23 (PB0.3).</description>
<value>23</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN24</name>
<description>Select channel ADCn.24 (VSS).</description>
<value>24</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN25</name>
<description>Select channel ADCn.25 (Digital LDO Output).</description>
<value>25</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN26</name>
<description>Select channel ADCn.26 (Memory LDO Output).</description>
<value>26</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN27</name>
<description>Select channel ADCn.27 (VDC).</description>
<value>27</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN28</name>
<description>Select channel ADCn.28 (VBAT).</description>
<value>28</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN29</name>
<description>Select channel ADCn.29 (1/2 Charge Pump Output).</description>
<value>29</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN30</name>
<description>Select channel ADCn.30 (Temperature Sensor Output).</description>
<value>30</value>
</enumeratedValue>
<enumeratedValue>
<name>END</name>
<description>None - End the sequence.</description>
<value>31</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS5CHR</name>
<description>Time Slot 5 Conversion Characteristic. </description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CC0</name>
<description>Select conversion characteristic 0 for time slot 5.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CC1</name>
<description>Select conversion characteristic 1 for time slot 5.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CC2</name>
<description>Select conversion characteristic 2 for time slot 5.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CC3</name>
<description>Select conversion characteristic 3 for time slot 5.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS5MUX</name>
<description>Time Slot 5 Input Channel. </description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ADCN0</name>
<description>Select channel ADCn.0 (PB0.3).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN1</name>
<description>Select channel ADCn.1 (PB0.9).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN2</name>
<description>Select channel ADCn.2 (PB2.0).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN3</name>
<description>Select channel ADCn.3 (PB2.1).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN4</name>
<description>Select channel ADCn.4 (PB2.2).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN5</name>
<description>Select channel ADCn.5 (PB2.3).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN6</name>
<description>Select channel ADCn.6 (PB2.4).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN7</name>
<description>Select channel ADCn.7 (PB2.5).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN8</name>
<description>Select channel ADCn.8 (PB2.6).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN9</name>
<description>Select channel ADCn.9 (PB2.7).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN10</name>
<description>Select channel ADCn.10 (PB3.3).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN11</name>
<description>Select channel ADCn.11 (PB3.4).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN12</name>
<description>Select channel ADCn.12 (PB3.5).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN13</name>
<description>Select channel ADCn.13 (PB3.6).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN14</name>
<description>Select channel ADCn.14 (PB3.7).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN15</name>
<description>Select channel ADCn.15 (PB3.8).</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN16</name>
<description>Select channel ADCn.16 (PB3.9).</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN17</name>
<description>Select channel ADCn.17 (RESERVED).</description>
<value>17</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN18</name>
<description>Select channel ADCn.18 (RESERVED).</description>
<value>18</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN19</name>
<description>Select channel ADCn.19 (RESERVED).</description>
<value>19</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN20</name>
<description>Select channel ADCn.20 (PB0.0).</description>
<value>20</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN21</name>
<description>Select channel ADCn.21 (RESERVED).</description>
<value>21</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN22</name>
<description>Select channel ADCn.22 (PB0.2).</description>
<value>22</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN23</name>
<description>Select channel ADCn.23 (PB0.3).</description>
<value>23</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN24</name>
<description>Select channel ADCn.24 (VSS).</description>
<value>24</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN25</name>
<description>Select channel ADCn.25 (Digital LDO Output).</description>
<value>25</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN26</name>
<description>Select channel ADCn.26 (Memory LDO Output).</description>
<value>26</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN27</name>
<description>Select channel ADCn.27 (VDC).</description>
<value>27</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN28</name>
<description>Select channel ADCn.28 (VBAT).</description>
<value>28</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN29</name>
<description>Select channel ADCn.29 (1/2 Charge Pump Output).</description>
<value>29</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN30</name>
<description>Select channel ADCn.30 (Temperature Sensor Output).</description>
<value>30</value>
</enumeratedValue>
<enumeratedValue>
<name>END</name>
<description>None - End the sequence.</description>
<value>31</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS6CHR</name>
<description>Time Slot 6 Conversion Characteristic. </description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CC0</name>
<description>Select conversion characteristic 0 for time slot 6.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CC1</name>
<description>Select conversion characteristic 1 for time slot 6.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CC2</name>
<description>Select conversion characteristic 2 for time slot 6.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CC3</name>
<description>Select conversion characteristic 3 for time slot 6.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS6MUX</name>
<description>Time Slot 6 Input Channel. </description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ADCN0</name>
<description>Select channel ADCn.0 (PB0.3).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN1</name>
<description>Select channel ADCn.1 (PB0.9).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN2</name>
<description>Select channel ADCn.2 (PB2.0).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN3</name>
<description>Select channel ADCn.3 (PB2.1).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN4</name>
<description>Select channel ADCn.4 (PB2.2).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN5</name>
<description>Select channel ADCn.5 (PB2.3).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN6</name>
<description>Select channel ADCn.6 (PB2.4).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN7</name>
<description>Select channel ADCn.7 (PB2.5).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN8</name>
<description>Select channel ADCn.8 (PB2.6).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN9</name>
<description>Select channel ADCn.9 (PB2.7).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN10</name>
<description>Select channel ADCn.10 (PB3.3).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN11</name>
<description>Select channel ADCn.11 (PB3.4).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN12</name>
<description>Select channel ADCn.12 (PB3.5).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN13</name>
<description>Select channel ADCn.13 (PB3.6).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN14</name>
<description>Select channel ADCn.14 (PB3.7).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN15</name>
<description>Select channel ADCn.15 (PB3.8).</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN16</name>
<description>Select channel ADCn.16 (PB3.9).</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN17</name>
<description>Select channel ADCn.17 (RESERVED).</description>
<value>17</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN18</name>
<description>Select channel ADCn.18 (RESERVED).</description>
<value>18</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN19</name>
<description>Select channel ADCn.19 (RESERVED).</description>
<value>19</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN20</name>
<description>Select channel ADCn.20 (PB0.0).</description>
<value>20</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN21</name>
<description>Select channel ADCn.21 (RESERVED).</description>
<value>21</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN22</name>
<description>Select channel ADCn.22 (PB0.2).</description>
<value>22</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN23</name>
<description>Select channel ADCn.23 (PB0.3).</description>
<value>23</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN24</name>
<description>Select channel ADCn.24 (VSS).</description>
<value>24</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN25</name>
<description>Select channel ADCn.25 (Digital LDO Output).</description>
<value>25</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN26</name>
<description>Select channel ADCn.26 (Memory LDO Output).</description>
<value>26</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN27</name>
<description>Select channel ADCn.27 (VDC).</description>
<value>27</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN28</name>
<description>Select channel ADCn.28 (VBAT).</description>
<value>28</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN29</name>
<description>Select channel ADCn.29 (1/2 Charge Pump Output).</description>
<value>29</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN30</name>
<description>Select channel ADCn.30 (Temperature Sensor Output).</description>
<value>30</value>
</enumeratedValue>
<enumeratedValue>
<name>END</name>
<description>None - End the sequence.</description>
<value>31</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS7CHR</name>
<description>Time Slot 7 Conversion Characteristic. </description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CC0</name>
<description>Select conversion characteristic 0 for time slot 7.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CC1</name>
<description>Select conversion characteristic 1 for time slot 7.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CC2</name>
<description>Select conversion characteristic 2 for time slot 7.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CC3</name>
<description>Select conversion characteristic 3 for time slot 7.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS7MUX</name>
<description>Time Slot 7 Input Channel. </description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ADCN0</name>
<description>Select channel ADCn.0 (PB0.3).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN1</name>
<description>Select channel ADCn.1 (PB0.9).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN2</name>
<description>Select channel ADCn.2 (PB2.0).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN3</name>
<description>Select channel ADCn.3 (PB2.1).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN4</name>
<description>Select channel ADCn.4 (PB2.2).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN5</name>
<description>Select channel ADCn.5 (PB2.3).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN6</name>
<description>Select channel ADCn.6 (PB2.4).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN7</name>
<description>Select channel ADCn.7 (PB2.5).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN8</name>
<description>Select channel ADCn.8 (PB2.6).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN9</name>
<description>Select channel ADCn.9 (PB2.7).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN10</name>
<description>Select channel ADCn.10 (PB3.3).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN11</name>
<description>Select channel ADCn.11 (PB3.4).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN12</name>
<description>Select channel ADCn.12 (PB3.5).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN13</name>
<description>Select channel ADCn.13 (PB3.6).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN14</name>
<description>Select channel ADCn.14 (PB3.7).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN15</name>
<description>Select channel ADCn.15 (PB3.8).</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN16</name>
<description>Select channel ADCn.16 (PB3.9).</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN17</name>
<description>Select channel ADCn.17 (RESERVED).</description>
<value>17</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN18</name>
<description>Select channel ADCn.18 (RESERVED).</description>
<value>18</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN19</name>
<description>Select channel ADCn.19 (RESERVED).</description>
<value>19</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN20</name>
<description>Select channel ADCn.20 (PB0.0).</description>
<value>20</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN21</name>
<description>Select channel ADCn.21 (RESERVED).</description>
<value>21</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN22</name>
<description>Select channel ADCn.22 (PB0.2).</description>
<value>22</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN23</name>
<description>Select channel ADCn.23 (PB0.3).</description>
<value>23</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN24</name>
<description>Select channel ADCn.24 (VSS).</description>
<value>24</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN25</name>
<description>Select channel ADCn.25 (Digital LDO Output).</description>
<value>25</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN26</name>
<description>Select channel ADCn.26 (Memory LDO Output).</description>
<value>26</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN27</name>
<description>Select channel ADCn.27 (VDC).</description>
<value>27</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN28</name>
<description>Select channel ADCn.28 (VBAT).</description>
<value>28</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN29</name>
<description>Select channel ADCn.29 (1/2 Charge Pump Output).</description>
<value>29</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN30</name>
<description>Select channel ADCn.30 (Temperature Sensor Output).</description>
<value>30</value>
</enumeratedValue>
<enumeratedValue>
<name>END</name>
<description>None - End the sequence.</description>
<value>31</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SQ3210</name>
<description>Channel Sequencer Time Slots 0-3 Setup</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TS0CHR</name>
<description>Time Slot 0 Conversion Characteristic. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CC0</name>
<description>Select conversion characteristic 0 for time slot 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CC1</name>
<description>Select conversion characteristic 1 for time slot 0.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CC2</name>
<description>Select conversion characteristic 2 for time slot 0.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CC3</name>
<description>Select conversion characteristic 3 for time slot 0.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS0MUX</name>
<description>Time Slot 0 Input Channel. </description>
<bitOffset>2</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ADCN0</name>
<description>Select channel ADCn.0 (PB0.3).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN1</name>
<description>Select channel ADCn.1 (PB0.9).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN2</name>
<description>Select channel ADCn.2 (PB2.0).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN3</name>
<description>Select channel ADCn.3 (PB2.1).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN4</name>
<description>Select channel ADCn.4 (PB2.2).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN5</name>
<description>Select channel ADCn.5 (PB2.3).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN6</name>
<description>Select channel ADCn.6 (PB2.4).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN7</name>
<description>Select channel ADCn.7 (PB2.5).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN8</name>
<description>Select channel ADCn.8 (PB2.6).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN9</name>
<description>Select channel ADCn.9 (PB2.7).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN10</name>
<description>Select channel ADCn.10 (PB3.3).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN11</name>
<description>Select channel ADCn.11 (PB3.4).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN12</name>
<description>Select channel ADCn.12 (PB3.5).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN13</name>
<description>Select channel ADCn.13 (PB3.6).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN14</name>
<description>Select channel ADCn.14 (PB3.7).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN15</name>
<description>Select channel ADCn.15 (PB3.8).</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN16</name>
<description>Select channel ADCn.16 (PB3.9).</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN17</name>
<description>Select channel ADCn.17 (RESERVED).</description>
<value>17</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN18</name>
<description>Select channel ADCn.18 (RESERVED).</description>
<value>18</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN19</name>
<description>Select channel ADCn.19 (RESERVED).</description>
<value>19</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN20</name>
<description>Select channel ADCn.20 (PB0.0).</description>
<value>20</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN21</name>
<description>Select channel ADCn.21 (RESERVED).</description>
<value>21</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN22</name>
<description>Select channel ADCn.22 (PB0.2).</description>
<value>22</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN23</name>
<description>Select channel ADCn.23 (PB0.3).</description>
<value>23</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN24</name>
<description>Select channel ADCn.24 (VSS).</description>
<value>24</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN25</name>
<description>Select channel ADCn.25 (Digital LDO Output).</description>
<value>25</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN26</name>
<description>Select channel ADCn.26 (Memory LDO Output).</description>
<value>26</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN27</name>
<description>Select channel ADCn.27 (VDC).</description>
<value>27</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN28</name>
<description>Select channel ADCn.28 (VBAT).</description>
<value>28</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN29</name>
<description>Select channel ADCn.29 (1/2 Charge Pump Output).</description>
<value>29</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN30</name>
<description>Select channel ADCn.30 (Temperature Sensor Output).</description>
<value>30</value>
</enumeratedValue>
<enumeratedValue>
<name>END</name>
<description>None - End the sequence.</description>
<value>31</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS1CHR</name>
<description>Time Slot 1 Conversion Characteristic. </description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CC0</name>
<description>Select conversion characteristic 0 for time slot 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CC1</name>
<description>Select conversion characteristic 1 for time slot 1.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CC2</name>
<description>Select conversion characteristic 2 for time slot 1.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CC3</name>
<description>Select conversion characteristic 3 for time slot 1.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS1MUX</name>
<description>Time Slot 1 Input Channel. </description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ADCN0</name>
<description>Select channel ADCn.0 (PB0.3).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN1</name>
<description>Select channel ADCn.1 (PB0.9).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN2</name>
<description>Select channel ADCn.2 (PB2.0).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN3</name>
<description>Select channel ADCn.3 (PB2.1).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN4</name>
<description>Select channel ADCn.4 (PB2.2).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN5</name>
<description>Select channel ADCn.5 (PB2.3).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN6</name>
<description>Select channel ADCn.6 (PB2.4).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN7</name>
<description>Select channel ADCn.7 (PB2.5).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN8</name>
<description>Select channel ADCn.8 (PB2.6).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN9</name>
<description>Select channel ADCn.9 (PB2.7).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN10</name>
<description>Select channel ADCn.10 (PB3.3).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN11</name>
<description>Select channel ADCn.11 (PB3.4).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN12</name>
<description>Select channel ADCn.12 (PB3.5).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN13</name>
<description>Select channel ADCn.13 (PB3.6).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN14</name>
<description>Select channel ADCn.14 (PB3.7).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN15</name>
<description>Select channel ADCn.15 (PB3.8).</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN16</name>
<description>Select channel ADCn.16 (PB3.9).</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN17</name>
<description>Select channel ADCn.17 (RESERVED).</description>
<value>17</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN18</name>
<description>Select channel ADCn.18 (RESERVED).</description>
<value>18</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN19</name>
<description>Select channel ADCn.19 (RESERVED).</description>
<value>19</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN20</name>
<description>Select channel ADCn.20 (PB0.0).</description>
<value>20</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN21</name>
<description>Select channel ADCn.21 (RESERVED).</description>
<value>21</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN22</name>
<description>Select channel ADCn.22 (PB0.2).</description>
<value>22</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN23</name>
<description>Select channel ADCn.23 (PB0.3).</description>
<value>23</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN24</name>
<description>Select channel ADCn.24 (VSS).</description>
<value>24</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN25</name>
<description>Select channel ADCn.25 (Digital LDO Output).</description>
<value>25</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN26</name>
<description>Select channel ADCn.26 (Memory LDO Output).</description>
<value>26</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN27</name>
<description>Select channel ADCn.27 (VDC).</description>
<value>27</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN28</name>
<description>Select channel ADCn.28 (VBAT).</description>
<value>28</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN29</name>
<description>Select channel ADCn.29 (1/2 Charge Pump Output).</description>
<value>29</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN30</name>
<description>Select channel ADCn.30 (Temperature Sensor Output).</description>
<value>30</value>
</enumeratedValue>
<enumeratedValue>
<name>END</name>
<description>None - End the sequence.</description>
<value>31</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS2CHR</name>
<description>Time Slot 2 Conversion Characteristic. </description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CC0</name>
<description>Select conversion characteristic 0 for time slot 2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CC1</name>
<description>Select conversion characteristic 1 for time slot 2.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CC2</name>
<description>Select conversion characteristic 2 for time slot 2.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CC3</name>
<description>Select conversion characteristic 3 for time slot 2.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS2MUX</name>
<description>Time Slot 2 Input Channel. </description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ADCN0</name>
<description>Select channel ADCn.0 (PB0.3).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN1</name>
<description>Select channel ADCn.1 (PB0.9).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN2</name>
<description>Select channel ADCn.2 (PB2.0).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN3</name>
<description>Select channel ADCn.3 (PB2.1).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN4</name>
<description>Select channel ADCn.4 (PB2.2).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN5</name>
<description>Select channel ADCn.5 (PB2.3).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN6</name>
<description>Select channel ADCn.6 (PB2.4).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN7</name>
<description>Select channel ADCn.7 (PB2.5).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN8</name>
<description>Select channel ADCn.8 (PB2.6).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN9</name>
<description>Select channel ADCn.9 (PB2.7).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN10</name>
<description>Select channel ADCn.10 (PB3.3).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN11</name>
<description>Select channel ADCn.11 (PB3.4).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN12</name>
<description>Select channel ADCn.12 (PB3.5).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN13</name>
<description>Select channel ADCn.13 (PB3.6).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN14</name>
<description>Select channel ADCn.14 (PB3.7).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN15</name>
<description>Select channel ADCn.15 (PB3.8).</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN16</name>
<description>Select channel ADCn.16 (PB3.9).</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN17</name>
<description>Select channel ADCn.17 (RESERVED).</description>
<value>17</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN18</name>
<description>Select channel ADCn.18 (RESERVED).</description>
<value>18</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN19</name>
<description>Select channel ADCn.19 (RESERVED).</description>
<value>19</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN20</name>
<description>Select channel ADCn.20 (PB0.0).</description>
<value>20</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN21</name>
<description>Select channel ADCn.21 (RESERVED).</description>
<value>21</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN22</name>
<description>Select channel ADCn.22 (PB0.2).</description>
<value>22</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN23</name>
<description>Select channel ADCn.23 (PB0.3).</description>
<value>23</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN24</name>
<description>Select channel ADCn.24 (VSS).</description>
<value>24</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN25</name>
<description>Select channel ADCn.25 (Digital LDO Output).</description>
<value>25</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN26</name>
<description>Select channel ADCn.26 (Memory LDO Output).</description>
<value>26</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN27</name>
<description>Select channel ADCn.27 (VDC).</description>
<value>27</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN28</name>
<description>Select channel ADCn.28 (VBAT).</description>
<value>28</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN29</name>
<description>Select channel ADCn.29 (1/2 Charge Pump Output).</description>
<value>29</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN30</name>
<description>Select channel ADCn.30 (Temperature Sensor Output).</description>
<value>30</value>
</enumeratedValue>
<enumeratedValue>
<name>END</name>
<description>None - End the sequence.</description>
<value>31</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS3CHR</name>
<description>Time Slot 3 Conversion Characteristic. </description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CC0</name>
<description>Select conversion characteristic 0 for time slot 3.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CC1</name>
<description>Select conversion characteristic 1 for time slot 3.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CC2</name>
<description>Select conversion characteristic 2 for time slot 3.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CC3</name>
<description>Select conversion characteristic 3 for time slot 3.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TS3MUX</name>
<description>Time Slot 3 Input Channel. </description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ADCN0</name>
<description>Select channel ADCn.0 (PB0.3).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN1</name>
<description>Select channel ADCn.1 (PB0.9).</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN2</name>
<description>Select channel ADCn.2 (PB2.0).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN3</name>
<description>Select channel ADCn.3 (PB2.1).</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN4</name>
<description>Select channel ADCn.4 (PB2.2).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN5</name>
<description>Select channel ADCn.5 (PB2.3).</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN6</name>
<description>Select channel ADCn.6 (PB2.4).</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN7</name>
<description>Select channel ADCn.7 (PB2.5).</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN8</name>
<description>Select channel ADCn.8 (PB2.6).</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN9</name>
<description>Select channel ADCn.9 (PB2.7).</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN10</name>
<description>Select channel ADCn.10 (PB3.3).</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN11</name>
<description>Select channel ADCn.11 (PB3.4).</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN12</name>
<description>Select channel ADCn.12 (PB3.5).</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN13</name>
<description>Select channel ADCn.13 (PB3.6).</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN14</name>
<description>Select channel ADCn.14 (PB3.7).</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN15</name>
<description>Select channel ADCn.15 (PB3.8).</description>
<value>15</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN16</name>
<description>Select channel ADCn.16 (PB3.9).</description>
<value>16</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN17</name>
<description>Select channel ADCn.17 (RESERVED).</description>
<value>17</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN18</name>
<description>Select channel ADCn.18 (RESERVED).</description>
<value>18</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN19</name>
<description>Select channel ADCn.19 (RESERVED).</description>
<value>19</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN20</name>
<description>Select channel ADCn.20 (PB0.0).</description>
<value>20</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN21</name>
<description>Select channel ADCn.21 (RESERVED).</description>
<value>21</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN22</name>
<description>Select channel ADCn.22 (PB0.2).</description>
<value>22</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN23</name>
<description>Select channel ADCn.23 (PB0.3).</description>
<value>23</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN24</name>
<description>Select channel ADCn.24 (VSS).</description>
<value>24</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN25</name>
<description>Select channel ADCn.25 (Digital LDO Output).</description>
<value>25</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN26</name>
<description>Select channel ADCn.26 (Memory LDO Output).</description>
<value>26</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN27</name>
<description>Select channel ADCn.27 (VDC).</description>
<value>27</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN28</name>
<description>Select channel ADCn.28 (VBAT).</description>
<value>28</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN29</name>
<description>Select channel ADCn.29 (1/2 Charge Pump Output).</description>
<value>29</value>
</enumeratedValue>
<enumeratedValue>
<name>ADCN30</name>
<description>Select channel ADCn.30 (Temperature Sensor Output).</description>
<value>30</value>
</enumeratedValue>
<enumeratedValue>
<name>END</name>
<description>None - End the sequence.</description>
<value>31</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHAR32</name>
<description>Conversion Characteristic 2 and 3 Setup</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CHR2GN</name>
<description>Conversion Characteristic 2 Gain. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNITY</name>
<description>The on-chip PGA gain is 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALF</name>
<description>The on-chip PGA gain is 0.5.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR2RPT</name>
<description>Conversion Characteristic 2 Repeat Counter. </description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ACC1</name>
<description>Accumulate one sample.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC4</name>
<description>Accumulate four samples.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC8</name>
<description>Accumulate eight samples.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC16</name>
<description>Accumulate sixteen samples.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC32</name>
<description>Accumulate thirty-two samples (10-bit mode only).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC64</name>
<description>Accumulate sixty-four samples (10-bit mode only).</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR2LS</name>
<description>Conversion Characteristic 2 Left-Shift Bits. </description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CHR2RSEL</name>
<description>Conversion Characteristic 2 Resolution Selection. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>B10</name>
<description>Select 10-bit Mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>B12</name>
<description>Select 12-bit Mode (burst mode must be enabled).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR2WCIEN</name>
<description>Conversion Characteristic 2 Window Comparator Interrupt Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable window comparison interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR3GN</name>
<description>Conversion Characteristic 3 Gain. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNITY</name>
<description>The on-chip PGA gain is 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALF</name>
<description>The on-chip PGA gain is 0.5.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR3RPT</name>
<description>Conversion Characteristic 3 Repeat Counter. </description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ACC1</name>
<description>Accumulate one sample.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC4</name>
<description>Accumulate four samples.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC8</name>
<description>Accumulate eight samples.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC16</name>
<description>Accumulate sixteen samples.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC32</name>
<description>Accumulate thirty-two samples (10-bit mode only).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC64</name>
<description>Accumulate sixty-four samples (10-bit mode only).</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR3LS</name>
<description>Conversion Characteristic 3 Left-Shift Bits. </description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CHR3RSEL</name>
<description>Conversion Characteristic 3 Resolution Selection. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>B10</name>
<description>Select 10-bit Mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>B12</name>
<description>Select 12-bit Mode (burst mode must be enabled).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR3WCIEN</name>
<description>Conversion Characteristic 3 Window Comparator Interrupt Enable. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable window comparison interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CHAR10</name>
<description>Conversion Characteristic 0 and 1 Setup</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CHR0GN</name>
<description>Conversion Characteristic 0 Gain. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNITY</name>
<description>The on-chip PGA gain is 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALF</name>
<description>The on-chip PGA gain is 0.5.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR0RPT</name>
<description>Conversion Characteristic 0 Repeat Counter. </description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ACC1</name>
<description>Accumulate one sample.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC4</name>
<description>Accumulate four samples.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC8</name>
<description>Accumulate eight samples.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC16</name>
<description>Accumulate sixteen samples.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC32</name>
<description>Accumulate thirty-two samples (10-bit mode only).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC64</name>
<description>Accumulate sixty-four samples (10-bit mode only).</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR0LS</name>
<description>Conversion Characteristic 0 Left-Shift Bits. </description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CHR0RSEL</name>
<description>Conversion Characteristic 0 Resolution Selection. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>B10</name>
<description>Select 10-bit Mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>B12</name>
<description>Select 12-bit Mode (burst mode must be enabled).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR0WCIEN</name>
<description>Conversion Characteristic 0 Window Comparator Interrupt Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable window comparison interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR1GN</name>
<description>Conversion Characteristic 1 Gain. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>UNITY</name>
<description>The on-chip PGA gain is 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALF</name>
<description>The on-chip PGA gain is 0.5.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR1RPT</name>
<description>Conversion Characteristic 1 Repeat Counter. </description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ACC1</name>
<description>Accumulate one sample.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC4</name>
<description>Accumulate four samples.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC8</name>
<description>Accumulate eight samples.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC16</name>
<description>Accumulate sixteen samples.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC32</name>
<description>Accumulate thirty-two samples (10-bit mode only).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>ACC64</name>
<description>Accumulate sixty-four samples (10-bit mode only).</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR1LS</name>
<description>Conversion Characteristic 1 Left-Shift Bits. </description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CHR1RSEL</name>
<description>Conversion Characteristic 1 Resolution Selection. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>B10</name>
<description>Select 10-bit Mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>B12</name>
<description>Select 12-bit Mode (burst mode must be enabled).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CHR1WCIEN</name>
<description>Conversion Characteristic 1 Window Comparator Interrupt Enable. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable window comparison interrupts.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled window comparison interrupts. The window comparator will be used to check the ADC result on channels that use this characteristic.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description>Output Data Word</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA</name>
<description>Output Data Word. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>WCLIMITS</name>
<description>Window Comparator Limits</description>
<addressOffset>0x70</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WCLT</name>
<description>Less-Than Window Comparator Limit. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>WCGT</name>
<description>Greater-Than Window Comparator Limit. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACC</name>
<description>Accumulator Initial Value</description>
<addressOffset>0x80</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ACC</name>
<description>Accumulator Initial Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Module Status</description>
<addressOffset>0x90</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WCI</name>
<description>Window Compare Interrupt. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A window compare interrupt has not occurred. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A window compare interrupt occurred. Write: Force a window compare interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SCCI</name>
<description>Single Conversion Complete Interrupt. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A single data conversion interrupt has not occurred. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A single data conversion interrupt occurred. Write: Force a single data conversion interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SDI</name>
<description>Scan Done Interrupt. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A scan done interrupt has not occurred. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A scan done interrupt occurred. Write: Force a scan done interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FORI</name>
<description>FIFO Overrun Interrupt. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A data FIFO overrun interrupt has not occurred. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A data FIFO overrun interrupt occurred. Write: Force a data FIFO overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FURI</name>
<description>FIFO Underrun Interrupt. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A data FIFO underrun interrupt has not occurred. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A data FIFO underrun interrupt occurred. Write: Force a data FIFO underrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FIFOSTATUS</name>
<description>FIFO Status</description>
<addressOffset>0xa0</addressOffset>
<resetValue>0x00000010</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FIFOLVL</name>
<description>FIFO Level. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DPSTS</name>
<description>Data Packing Status. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOWER</name>
<description>The next ADC conversion will be written to the lower half-word.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPPER</name>
<description>The next ADC conversion will be written to the upper half-word.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DRDYF</name>
<description>Data Ready Flag. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>New data is not produced yet.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>New data is ready.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI_0</name>
<version>B</version>
<description>None</description>
<groupName>SPI</groupName>
<baseAddress>0x40004000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI0_IRQn</name>
<value>26</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>DATA</name>
<description>Input/Output Data</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<readAction>modifyExternal</readAction>
<fields>
<field>
<name>DATA</name>
<description>Input/Output Data. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00004084</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFRQI</name>
<description>Receive FIFO Read Request Interrupt Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The RX FIFO has fewer bytes than the level defined by RFTH.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The RX FIFO has equal or more bytes than the level defined by RFTH.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFORI</name>
<description>Receive FIFO Overrun Interrupt Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A receive FIFO overrun has not occurred. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFRQI</name>
<description>Transmit FIFO Write Request Interrupt Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The TX FIFO has fewer empty slots than the level defined by TFTH.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The TX FIFO has at least as many empty slots as the level defined by TFTH.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFORI</name>
<description>Transmit FIFO Overrun Interrupt Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A transmit FIFO overrun has not occurred. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVSELI</name>
<description>Slave Selected Interrupt Flag. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The slave select signal (NSS) is not active.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The slave select signal (NSS) is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDFI</name>
<description>Mode Fault Interrupt Flag. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A master mode collision is not detected. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A master mode collision occurred. Write: Force a mode fault interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>URI</name>
<description>Underrun Interrupt Flag. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A data transfer is still in progress. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SREI</name>
<description>Shift Register Empty Interrupt Flag. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>There is data still present in the transmit FIFO or shift register.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFILI</name>
<description>Illegal Receive FIFO Access Interrupt Flag. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFILI</name>
<description>Illegal Transmit FIFO Access Interrupt Flag. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NSSSTS</name>
<description>NSS Instantaneous Pin Status. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>NSS is currently a logic low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>NSS is currently a logic high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSYF</name>
<description>SPI Busy. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The SPI is not busy and a transfer is not in progress.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The SPI is currently busy and a transfer is in progress.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFCNT</name>
<description>Receive FIFO Counter. </description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TFCNT</name>
<description>Transmit FIFO Counter. </description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DBGMD</name>
<description>SPI Debug Mode. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The SPI module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the SPI module to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONFIG</name>
<description>Module Configuration</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFRQIEN</name>
<description>Receive FIFO Read Request Interrupt Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the receive FIFO request interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the receive FIFO request interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFORIEN</name>
<description>Receive FIFO Overrun Interrupt Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the receive FIFO overrun interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the receive FIFO overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFRQIEN</name>
<description>Transmit FIFO Write Request Interrupt Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmit FIFO data request interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmit FIFO data request interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFORIEN</name>
<description>Transmit FIFO Overrun Interrupt Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmit FIFO overrun interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmit FIFO overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVSELIEN</name>
<description>Slave Selected Interrupt Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the slave select interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the slave select interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDFIEN</name>
<description>Mode Fault Interrupt Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the mode fault interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the mode fault interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>URIEN</name>
<description>Underrun Interrupt Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the underrun interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the underrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SREIEN</name>
<description>Shift Register Empty Interrupt Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the shift register empty interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the shift register empty interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIEN</name>
<description>SPI Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the SPI.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the SPI.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTEN</name>
<description>Master Mode Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Operate in slave mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Operate in master mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKPOL</name>
<description>SPI Clock Polarity. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The SCK line is low in the idle state.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The SCK line is high in the idle state.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKPHA</name>
<description>SPI Clock Phase. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CENTER</name>
<description>The first edge of SCK is the sample edge (center of data bit).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EDGE</name>
<description>The first edge of SCK is the shift edge (edge of data bit).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NSSPOL</name>
<description>Slave Select Polarity Select. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>NSS is active low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>NSS is active high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DDIRSEL</name>
<description>Data Direction Select. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MSB_FIRST</name>
<description>Data will be shifted MSB first.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LSB_FIRST</name>
<description>Data will be shifted LSB first.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NSSMD</name>
<description>Slave Select Mode. </description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>3_WIRE_MASTER_SLAVE</name>
<description>3-wire Slave or 3-wire Master.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>4_WIRE_SLAVE</name>
<description>4-wire slave (NSS input). This setting can also be used for multi-master configurations.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>4_WIRE_MASTER_NSS_LOW</name>
<description>4-wire master with NSS low (NSS output).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>4_WIRE_MASTER_NSS_HIGH</name>
<description>4-wire master with NSS high (NSS output).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFTH</name>
<description>Receive FIFO Threshold. </description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ONE</name>
<description>A DMA / RFRQ request asserts when &gt;= 1 FIFO slot is filled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TWO</name>
<description>A DMA / RFRQ request asserts when &gt;= 2 FIFO slots are filled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FOUR</name>
<description>A DMA / RFRQ request asserts when &gt;= 4 FIFO slots are filled.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>FULL</name>
<description>A DMA / RFRQ request asserts when all FIFO slots are filled.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFTH</name>
<description>Transmit FIFO Threshold. </description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ONE</name>
<description>A DMA / TFRQ request asserts when &gt;= 1 FIFO slot is empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TWO</name>
<description>A DMA / TFRQ request asserts when &gt;= 2 FIFO slots are empty.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FOUR</name>
<description>A DMA / TFRQ request asserts when &gt;= 4 FIFO slots are empty.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>EMPTY</name>
<description>A DMA / TFRQ request asserts when all FIFO slots are empty.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSIZE</name>
<description>Data Size. </description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA requests. </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable DMA requests according to the TFRQI and RFRQI flags.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFIFOFL</name>
<description>Receive FIFO Flush. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Flush the receive FIFO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFIFOFL</name>
<description>Transmit FIFO Flush. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Flush the transmit FIFO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET</name>
<description>Module Soft Reset. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>SPI module is not in soft reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLKRATE</name>
<description>Module Clock Rate Control</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKDIV</name>
<description>Clock Divider. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FSTATUS</name>
<description>FIFO Status</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFRPTR</name>
<description>Receive FIFO Read Pointer. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RFWPTR</name>
<description>Receive FIFO Write Pointer. </description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TFRPTR</name>
<description>Transmit FIFO Read Pointer. </description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TFWPTR</name>
<description>Transmit FIFO Write Pointer. </description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CONFIGMD</name>
<description>Mode Configuration</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OPMD</name>
<description>Operation Mode. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NORMAL</name>
<description>Full-duplex (normal) mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RECEIVE</name>
<description>Receive-only mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSMIT</name>
<description>Transmit only mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>FLOWCONTROL</name>
<description>Flow control mode.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AUTONSS</name>
<description>Auto NSS Mode. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTSEN</name>
<description>CTS Flow Control Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLOWMD</name>
<description>Flow Control Mode. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Store CTS byte (see chapter text for details).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Disregard CTS byte.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ABORT</name>
<description>Software Abort. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXONREQ</name>
<description>Transmit On Request. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NSSCNT</name>
<description>NSS Data Count. </description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>NSSDELAY</name>
<description>NSS Delay. </description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TFRCNT</name>
<description>Transfer Count. </description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>AUTO</name>
<description>Automatic. The request type determines the number of bytes to write/read.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSFER1</name>
<description>A single byte is written/read per request.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSFER2</name>
<description>Up to two bytes can be written/read per request.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSFER3</name>
<description>Up to three bytes can be written/read per request.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSFER4</name>
<description>Up to four bytes can be written/read per request.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI_1</name>
<version>B</version>
<description>None</description>
<groupName>SPI</groupName>
<baseAddress>0x40005000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI1_IRQn</name>
<value>27</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>DATA</name>
<description>Input/Output Data</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<readAction>modifyExternal</readAction>
<fields>
<field>
<name>DATA</name>
<description>Input/Output Data. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00004084</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFRQI</name>
<description>Receive FIFO Read Request Interrupt Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The RX FIFO has fewer bytes than the level defined by RFTH.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The RX FIFO has equal or more bytes than the level defined by RFTH.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFORI</name>
<description>Receive FIFO Overrun Interrupt Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A receive FIFO overrun has not occurred. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A receive FIFO overrun occurred. Write: Force a receive overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFRQI</name>
<description>Transmit FIFO Write Request Interrupt Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The TX FIFO has fewer empty slots than the level defined by TFTH.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The TX FIFO has at least as many empty slots as the level defined by TFTH.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFORI</name>
<description>Transmit FIFO Overrun Interrupt Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A transmit FIFO overrun has not occurred. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A transmit FIFO overrun occurred. Write: Force a transmit overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVSELI</name>
<description>Slave Selected Interrupt Flag. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The slave select signal (NSS) is not active.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The slave select signal (NSS) is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDFI</name>
<description>Mode Fault Interrupt Flag. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A master mode collision is not detected. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A master mode collision occurred. Write: Force a mode fault interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>URI</name>
<description>Underrun Interrupt Flag. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A data transfer is still in progress. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: The transmit FIFO and shift register are empty and the data transfer has ended. Write: Force an underrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SREI</name>
<description>Shift Register Empty Interrupt Flag. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>There is data still present in the transmit FIFO or shift register.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>All data has been transferred out of the shift register and there is no data waiting in the transmit FIFO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFILI</name>
<description>Illegal Receive FIFO Access Interrupt Flag. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: An illegal write or read of the receive FIFO has not occurred. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: An illegal write or read of the receive FIFO occurred. Write: Force an illegal receive access interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFILI</name>
<description>Illegal Transmit FIFO Access Interrupt Flag. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: An illegal write or read of the transmit FIFO has not occurred. Write: Clear the flag.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: An illegal write or read of the transmit FIFO occurred. Write: Force an illegal transmit access interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NSSSTS</name>
<description>NSS Instantaneous Pin Status. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>NSS is currently a logic low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>NSS is currently a logic high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUSYF</name>
<description>SPI Busy. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The SPI is not busy and a transfer is not in progress.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The SPI is currently busy and a transfer is in progress.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFCNT</name>
<description>Receive FIFO Counter. </description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TFCNT</name>
<description>Transmit FIFO Counter. </description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DBGMD</name>
<description>SPI Debug Mode. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The SPI module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the SPI module to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONFIG</name>
<description>Module Configuration</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFRQIEN</name>
<description>Receive FIFO Read Request Interrupt Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the receive FIFO request interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the receive FIFO request interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFORIEN</name>
<description>Receive FIFO Overrun Interrupt Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the receive FIFO overrun interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the receive FIFO overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFRQIEN</name>
<description>Transmit FIFO Write Request Interrupt Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmit FIFO data request interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmit FIFO data request interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFORIEN</name>
<description>Transmit FIFO Overrun Interrupt Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmit FIFO overrun interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmit FIFO overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SLVSELIEN</name>
<description>Slave Selected Interrupt Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the slave select interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the slave select interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MDFIEN</name>
<description>Mode Fault Interrupt Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the mode fault interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the mode fault interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>URIEN</name>
<description>Underrun Interrupt Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the underrun interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the underrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SREIEN</name>
<description>Shift Register Empty Interrupt Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the shift register empty interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the shift register empty interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPIEN</name>
<description>SPI Enable. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the SPI.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the SPI.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTEN</name>
<description>Master Mode Enable. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Operate in slave mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Operate in master mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKPOL</name>
<description>SPI Clock Polarity. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The SCK line is low in the idle state.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The SCK line is high in the idle state.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKPHA</name>
<description>SPI Clock Phase. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>CENTER</name>
<description>The first edge of SCK is the sample edge (center of data bit).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EDGE</name>
<description>The first edge of SCK is the shift edge (edge of data bit).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NSSPOL</name>
<description>Slave Select Polarity Select. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>NSS is active low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>NSS is active high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DDIRSEL</name>
<description>Data Direction Select. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MSB_FIRST</name>
<description>Data will be shifted MSB first.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LSB_FIRST</name>
<description>Data will be shifted LSB first.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NSSMD</name>
<description>Slave Select Mode. </description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>3_WIRE_MASTER_SLAVE</name>
<description>3-wire Slave or 3-wire Master.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>4_WIRE_SLAVE</name>
<description>4-wire slave (NSS input). This setting can also be used for multi-master configurations.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>4_WIRE_MASTER_NSS_LOW</name>
<description>4-wire master with NSS low (NSS output).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>4_WIRE_MASTER_NSS_HIGH</name>
<description>4-wire master with NSS high (NSS output).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFTH</name>
<description>Receive FIFO Threshold. </description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ONE</name>
<description>A DMA / RFRQ request asserts when &gt;= 1 FIFO slot is filled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TWO</name>
<description>A DMA / RFRQ request asserts when &gt;= 2 FIFO slots are filled.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FOUR</name>
<description>A DMA / RFRQ request asserts when &gt;= 4 FIFO slots are filled.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>FULL</name>
<description>A DMA / RFRQ request asserts when all FIFO slots are filled.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFTH</name>
<description>Transmit FIFO Threshold. </description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ONE</name>
<description>A DMA / TFRQ request asserts when &gt;= 1 FIFO slot is empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TWO</name>
<description>A DMA / TFRQ request asserts when &gt;= 2 FIFO slots are empty.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FOUR</name>
<description>A DMA / TFRQ request asserts when &gt;= 4 FIFO slots are empty.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>EMPTY</name>
<description>A DMA / TFRQ request asserts when all FIFO slots are empty.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSIZE</name>
<description>Data Size. </description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA Enable. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable DMA requests. </description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable DMA requests according to the TFRQI and RFRQI flags.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFIFOFL</name>
<description>Receive FIFO Flush. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Flush the receive FIFO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFIFOFL</name>
<description>Transmit FIFO Flush. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Flush the transmit FIFO.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET</name>
<description>Module Soft Reset. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>SPI module is not in soft reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>SPI module is in soft reset and some of the module bits cannot be accessed until this bit is cleared to 0 by hardware.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLKRATE</name>
<description>Module Clock Rate Control</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKDIV</name>
<description>Clock Divider. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FSTATUS</name>
<description>FIFO Status</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFRPTR</name>
<description>Receive FIFO Read Pointer. </description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RFWPTR</name>
<description>Receive FIFO Write Pointer. </description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TFRPTR</name>
<description>Transmit FIFO Read Pointer. </description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TFWPTR</name>
<description>Transmit FIFO Write Pointer. </description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CONFIGMD</name>
<description>Mode Configuration</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OPMD</name>
<description>Operation Mode. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NORMAL</name>
<description>Full-duplex (normal) mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RECEIVE</name>
<description>Receive-only mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSMIT</name>
<description>Transmit only mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>FLOWCONTROL</name>
<description>Flow control mode.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>AUTONSS</name>
<description>Auto NSS Mode. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTSEN</name>
<description>CTS Flow Control Enable. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FLOWMD</name>
<description>Flow Control Mode. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Store CTS byte (see chapter text for details).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Disregard CTS byte.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ABORT</name>
<description>Software Abort. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXONREQ</name>
<description>Transmit On Request. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NSSCNT</name>
<description>NSS Data Count. </description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>NSSDELAY</name>
<description>NSS Delay. </description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TFRCNT</name>
<description>Transfer Count. </description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>AUTO</name>
<description>Automatic. The request type determines the number of bytes to write/read.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSFER1</name>
<description>A single byte is written/read per request.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSFER2</name>
<description>Up to two bytes can be written/read per request.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSFER3</name>
<description>Up to three bytes can be written/read per request.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>TRANSFER4</name>
<description>Up to four bytes can be written/read per request.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCONFIG_0</name>
<version>A</version>
<description>None</description>
<groupName>SCONFIG_0</groupName>
<baseAddress>0x400490b0</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONFIG</name>
<description>System Configuration</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FDMAEN</name>
<description>Faster DMA Mode Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the faster DMA mode. The DMA module and channels will behave like a standard uDMA.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the faster DMA mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PM8DBGEN</name>
<description>Power Mode 8 Debug Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable debugging through Power Mode 8.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable debugging through Power Mode 8. Power measurements cannot be made with debugging enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIMER_0</name>
<version>A</version>
<description>None</description>
<groupName>Timer</groupName>
<baseAddress>0x40014000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIMER0L_IRQn</name>
<value>16</value>
</interrupt>
<interrupt>
<name>TIMER0H_IRQn</name>
<value>17</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONFIG</name>
<description>High and Low Timer Configuration</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCLK</name>
<description>Low Clock Source. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>APB</name>
<description>Select the APB clock as the timer source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTOSCN</name>
<description>Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLKDIV</name>
<description>Select the dedicated 8-bit prescaler as the timer source.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT_FALLING_EDGE</name>
<description>Select falling edges of the CT signal as the timer clock source.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LMSTREN</name>
<description>Low Run Master Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>MSTRUN does not need to be set for the low timer to run.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>MSTRUN must be set for the low timer to run.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPLITEN</name>
<description>Split Mode Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The timer operates as a single 32-bit timer controlled by the high timer fields.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The timer operates as two independent 16-bit timers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEXIEN</name>
<description>Low Timer Extra Interrupt Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of the LEXI flag does not affect the low timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A low timer interrupt request is generated if LEXI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOVFIEN</name>
<description>Low Timer Overflow Interrupt Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of LOVFI does not affect the low timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A low timer interrupt request is generated if LOVFI = 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LMD</name>
<description>Low Timer Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>AUTO_RELOAD</name>
<description>The low timer is in Auto-Reload Mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UP_DOWN</name>
<description>The low timer is in Up/Down Count Mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALL_CAPTURE</name>
<description>The low timer is in Falling Edge Capture Mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RISE_CAPTURE</name>
<description>The low timer is in Rising Edge Capture Mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_CAPTURE</name>
<description>The low timer is in Low Time Capture Mode.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_CAPTURE</name>
<description>The low timer is in High Time Capture Mode.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DC_CAPTURE</name>
<description>The low timer is in Duty Cycle Capture Mode.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ONESHOT</name>
<description>The low timer is in Oneshot Mode.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSTATE</name>
<description>Low Multi Purpose State Indicator. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LRUN</name>
<description>Run Control Low. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop the low timer if split mode is enabled (SPLITEN = 1).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>The low timer runs if split mode is enabled (SPLITEN = 1) and (LMSTREN = 0 or MSTRUN = 1 in Timer 0).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEXI</name>
<description>Low Timer Extra Interrupt Flag. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A low timer extra interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Indicates the low 16-bit timer has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by hardware in all modes except Auto-Reload and Toggle. This flag is not set by hardware when split mode is disabled (SPLITEN = 0). Write: Force a low timer extra interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOVFI</name>
<description>Low Timer Overflow Interrupt. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A low timer overflow interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: The low 16-bit timer has wrapped or reloaded after reaching all 1's. This bit is set by the module regardless of the state of SPLITEN and can be set in all modes. Write: Force a low timer overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HCLK</name>
<description>High Clock Source. </description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>APB</name>
<description>Select the APB clock as the timer source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTOSCN</name>
<description>Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLKDIV</name>
<description>Select the dedicated 8-bit prescaler as the timer source.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT_FALLING_EDGE</name>
<description>Select falling edges of the CT signal as the timer clock source.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTRUN</name>
<description>Master Run Control. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Disable the master run control for all timers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Enable the master run control for all timers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HMSTREN</name>
<description>High Master Enable. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>MSTRUN does not need to be set for the timer to run.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>MSTRUN must be set for the timer to run.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>Timer Debug Mode. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The timer will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the Timer to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HEXIEN</name>
<description>High Timer Extra Interrupt Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of the HEXI flag does not affect the high timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A high timer interrupt request is generated if HEXI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HOVFIEN</name>
<description>High Timer Overflow Interrupt Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of HOVFI does not affect the high timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A high timer interrupt request is generated if HOVFI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HMD</name>
<description>High Timer Mode. </description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>AUTO_RELOAD</name>
<description>The high 16-bit timer or entire 32-bit timer is in Auto-Reload Mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UP_DOWN</name>
<description>The high 16-bit timer or entire 32-bit timer is in Up/Down Count Mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALL_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Falling Edge Capture Mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RISE_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Rising Edge Capture Mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Low Time Capture Mode.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in High Time Capture Mode.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DC_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Duty Cycle Capture Mode.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ONESHOT</name>
<description>The high 16-bit timer or entire 32-bit timer is in Oneshot Mode.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Square Wave Output Mode.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>The high 16-bit timer or entire 32-bit timer is in PWM Mode.</description>
<value>9</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSTATE</name>
<description>High Multi Purpose State Indicator. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HRUN</name>
<description>High Run Control. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop the high timer or entire 32-bit timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>The high timer runs if HMSTREN = 0 or MSTRUN (in Timer 0) = 1. The full 32-bit timer runs if split mode is disabled and (HMSTREN = 0 or MSTRUN = 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HEXI</name>
<description>High Timer Extra Interrupt Flag. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A high timer extra interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Indicates the high 16-bit timer (or 32-bit timer if SPLITEN = 0) has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by the timer module in all modes except Auto-Reload and Toggle. Write: Force a high timer extra interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HOVFI</name>
<description>High Timer Overflow Interrupt Flag. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A high timer overflow interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: If split mode is enabled (SPLITEN = 1), this value indicates the high 16-bit timer has wrapped or reloaded after reaching all 1's. If split mode is disabled (SPLITEN = 0), this value indicates the 32-bit timer has wrapped or reloaded after reaching all 1's. The timer module can set this bit in all modes. Write: Force a high timer overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLKDIV</name>
<description>Module Clock Divider Control</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKDIVRL</name>
<description>Clock Divider Reload Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CLKDIVCT</name>
<description>Clock Divider Counter. </description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT</name>
<description>Timer Value</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCOUNT</name>
<description>Low Timer Count. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>HCOUNT</name>
<description>High Timer Count. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAPTURE</name>
<description>Timer Capture/Reload Value</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCCR</name>
<description>Low Timer Capture/Reload. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>HCCR</name>
<description>High Timer Capture/Reload. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIMER_1</name>
<version>A</version>
<description>None</description>
<groupName>Timer</groupName>
<baseAddress>0x40015000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIMER1L_IRQn</name>
<value>18</value>
</interrupt>
<interrupt>
<name>TIMER1H_IRQn</name>
<value>19</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONFIG</name>
<description>High and Low Timer Configuration</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCLK</name>
<description>Low Clock Source. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>APB</name>
<description>Select the APB clock as the timer source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTOSCN</name>
<description>Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLKDIV</name>
<description>Select the dedicated 8-bit prescaler as the timer source.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT_FALLING_EDGE</name>
<description>Select falling edges of the CT signal as the timer clock source.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LMSTREN</name>
<description>Low Run Master Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>MSTRUN does not need to be set for the low timer to run.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>MSTRUN must be set for the low timer to run.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPLITEN</name>
<description>Split Mode Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The timer operates as a single 32-bit timer controlled by the high timer fields.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The timer operates as two independent 16-bit timers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEXIEN</name>
<description>Low Timer Extra Interrupt Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of the LEXI flag does not affect the low timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A low timer interrupt request is generated if LEXI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOVFIEN</name>
<description>Low Timer Overflow Interrupt Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of LOVFI does not affect the low timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A low timer interrupt request is generated if LOVFI = 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LMD</name>
<description>Low Timer Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>AUTO_RELOAD</name>
<description>The low timer is in Auto-Reload Mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UP_DOWN</name>
<description>The low timer is in Up/Down Count Mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALL_CAPTURE</name>
<description>The low timer is in Falling Edge Capture Mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RISE_CAPTURE</name>
<description>The low timer is in Rising Edge Capture Mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_CAPTURE</name>
<description>The low timer is in Low Time Capture Mode.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_CAPTURE</name>
<description>The low timer is in High Time Capture Mode.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DC_CAPTURE</name>
<description>The low timer is in Duty Cycle Capture Mode.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ONESHOT</name>
<description>The low timer is in Oneshot Mode.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSTATE</name>
<description>Low Multi Purpose State Indicator. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LRUN</name>
<description>Run Control Low. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop the low timer if split mode is enabled (SPLITEN = 1).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>The low timer runs if split mode is enabled (SPLITEN = 1) and (LMSTREN = 0 or MSTRUN = 1 in Timer 0).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEXI</name>
<description>Low Timer Extra Interrupt Flag. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A low timer extra interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Indicates the low 16-bit timer has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by hardware in all modes except Auto-Reload and Toggle. This flag is not set by hardware when split mode is disabled (SPLITEN = 0). Write: Force a low timer extra interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOVFI</name>
<description>Low Timer Overflow Interrupt. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A low timer overflow interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: The low 16-bit timer has wrapped or reloaded after reaching all 1's. This bit is set by the module regardless of the state of SPLITEN and can be set in all modes. Write: Force a low timer overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HCLK</name>
<description>High Clock Source. </description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>APB</name>
<description>Select the APB clock as the timer source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTOSCN</name>
<description>Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLKDIV</name>
<description>Select the dedicated 8-bit prescaler as the timer source.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT_FALLING_EDGE</name>
<description>Select falling edges of the CT signal as the timer clock source.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTRUN</name>
<description>Master Run Control. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Disable the master run control for all timers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Enable the master run control for all timers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HMSTREN</name>
<description>High Master Enable. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>MSTRUN does not need to be set for the timer to run.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>MSTRUN must be set for the timer to run.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>Timer Debug Mode. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The timer will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the Timer to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HEXIEN</name>
<description>High Timer Extra Interrupt Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of the HEXI flag does not affect the high timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A high timer interrupt request is generated if HEXI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HOVFIEN</name>
<description>High Timer Overflow Interrupt Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of HOVFI does not affect the high timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A high timer interrupt request is generated if HOVFI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HMD</name>
<description>High Timer Mode. </description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>AUTO_RELOAD</name>
<description>The high 16-bit timer or entire 32-bit timer is in Auto-Reload Mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UP_DOWN</name>
<description>The high 16-bit timer or entire 32-bit timer is in Up/Down Count Mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALL_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Falling Edge Capture Mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RISE_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Rising Edge Capture Mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Low Time Capture Mode.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in High Time Capture Mode.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DC_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Duty Cycle Capture Mode.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ONESHOT</name>
<description>The high 16-bit timer or entire 32-bit timer is in Oneshot Mode.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Square Wave Output Mode.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>The high 16-bit timer or entire 32-bit timer is in PWM Mode.</description>
<value>9</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSTATE</name>
<description>High Multi Purpose State Indicator. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HRUN</name>
<description>High Run Control. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop the high timer or entire 32-bit timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>The high timer runs if HMSTREN = 0 or MSTRUN (in Timer 0) = 1. The full 32-bit timer runs if split mode is disabled and (HMSTREN = 0 or MSTRUN = 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HEXI</name>
<description>High Timer Extra Interrupt Flag. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A high timer extra interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Indicates the high 16-bit timer (or 32-bit timer if SPLITEN = 0) has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by the timer module in all modes except Auto-Reload and Toggle. Write: Force a high timer extra interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HOVFI</name>
<description>High Timer Overflow Interrupt Flag. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A high timer overflow interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: If split mode is enabled (SPLITEN = 1), this value indicates the high 16-bit timer has wrapped or reloaded after reaching all 1's. If split mode is disabled (SPLITEN = 0), this value indicates the 32-bit timer has wrapped or reloaded after reaching all 1's. The timer module can set this bit in all modes. Write: Force a high timer overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLKDIV</name>
<description>Module Clock Divider Control</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKDIVRL</name>
<description>Clock Divider Reload Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CLKDIVCT</name>
<description>Clock Divider Counter. </description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT</name>
<description>Timer Value</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCOUNT</name>
<description>Low Timer Count. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>HCOUNT</name>
<description>High Timer Count. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAPTURE</name>
<description>Timer Capture/Reload Value</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCCR</name>
<description>Low Timer Capture/Reload. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>HCCR</name>
<description>High Timer Capture/Reload. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIMER_2</name>
<version>A</version>
<description>None</description>
<groupName>Timer</groupName>
<baseAddress>0x40016000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIMER2L_IRQn</name>
<value>20</value>
</interrupt>
<interrupt>
<name>TIMER2H_IRQn</name>
<value>21</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONFIG</name>
<description>High and Low Timer Configuration</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCLK</name>
<description>Low Clock Source. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>APB</name>
<description>Select the APB clock as the timer source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTOSCN</name>
<description>Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLKDIV</name>
<description>Select the dedicated 8-bit prescaler as the timer source.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT_FALLING_EDGE</name>
<description>Select falling edges of the CT signal as the timer clock source.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LMSTREN</name>
<description>Low Run Master Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>MSTRUN does not need to be set for the low timer to run.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>MSTRUN must be set for the low timer to run.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPLITEN</name>
<description>Split Mode Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The timer operates as a single 32-bit timer controlled by the high timer fields.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The timer operates as two independent 16-bit timers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEXIEN</name>
<description>Low Timer Extra Interrupt Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of the LEXI flag does not affect the low timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A low timer interrupt request is generated if LEXI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOVFIEN</name>
<description>Low Timer Overflow Interrupt Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of LOVFI does not affect the low timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A low timer interrupt request is generated if LOVFI = 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LMD</name>
<description>Low Timer Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>AUTO_RELOAD</name>
<description>The low timer is in Auto-Reload Mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UP_DOWN</name>
<description>The low timer is in Up/Down Count Mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALL_CAPTURE</name>
<description>The low timer is in Falling Edge Capture Mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RISE_CAPTURE</name>
<description>The low timer is in Rising Edge Capture Mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_CAPTURE</name>
<description>The low timer is in Low Time Capture Mode.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_CAPTURE</name>
<description>The low timer is in High Time Capture Mode.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DC_CAPTURE</name>
<description>The low timer is in Duty Cycle Capture Mode.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ONESHOT</name>
<description>The low timer is in Oneshot Mode.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LSTATE</name>
<description>Low Multi Purpose State Indicator. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LRUN</name>
<description>Run Control Low. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop the low timer if split mode is enabled (SPLITEN = 1).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>The low timer runs if split mode is enabled (SPLITEN = 1) and (LMSTREN = 0 or MSTRUN = 1 in Timer 0).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEXI</name>
<description>Low Timer Extra Interrupt Flag. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A low timer extra interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Indicates the low 16-bit timer has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by hardware in all modes except Auto-Reload and Toggle. This flag is not set by hardware when split mode is disabled (SPLITEN = 0). Write: Force a low timer extra interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOVFI</name>
<description>Low Timer Overflow Interrupt. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A low timer overflow interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: The low 16-bit timer has wrapped or reloaded after reaching all 1's. This bit is set by the module regardless of the state of SPLITEN and can be set in all modes. Write: Force a low timer overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HCLK</name>
<description>High Clock Source. </description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>APB</name>
<description>Select the APB clock as the timer source.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTOSCN</name>
<description>Select the external oscillator clock as the timer source. The external oscillator must run slower than one-half the APB clock.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TIMER_CLKDIV</name>
<description>Select the dedicated 8-bit prescaler as the timer source.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>CT_FALLING_EDGE</name>
<description>Select falling edges of the CT signal as the timer clock source.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MSTRUN</name>
<description>Master Run Control. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Disable the master run control for all timers.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Enable the master run control for all timers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HMSTREN</name>
<description>High Master Enable. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>MSTRUN does not need to be set for the timer to run.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>MSTRUN must be set for the timer to run.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>Timer Debug Mode. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The timer will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the Timer to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HEXIEN</name>
<description>High Timer Extra Interrupt Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of the HEXI flag does not affect the high timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A high timer interrupt request is generated if HEXI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HOVFIEN</name>
<description>High Timer Overflow Interrupt Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The state of HOVFI does not affect the high timer interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>A high timer interrupt request is generated if HOVFI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HMD</name>
<description>High Timer Mode. </description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>AUTO_RELOAD</name>
<description>The high 16-bit timer or entire 32-bit timer is in Auto-Reload Mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UP_DOWN</name>
<description>The high 16-bit timer or entire 32-bit timer is in Up/Down Count Mode.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FALL_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Falling Edge Capture Mode.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RISE_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Rising Edge Capture Mode.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Low Time Capture Mode.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in High Time Capture Mode.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>DC_CAPTURE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Duty Cycle Capture Mode.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>ONESHOT</name>
<description>The high 16-bit timer or entire 32-bit timer is in Oneshot Mode.</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TOGGLE</name>
<description>The high 16-bit timer or entire 32-bit timer is in Square Wave Output Mode.</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>PWM</name>
<description>The high 16-bit timer or entire 32-bit timer is in PWM Mode.</description>
<value>9</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HSTATE</name>
<description>High Multi Purpose State Indicator. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HRUN</name>
<description>High Run Control. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop the high timer or entire 32-bit timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>The high timer runs if HMSTREN = 0 or MSTRUN (in Timer 0) = 1. The full 32-bit timer runs if split mode is disabled and (HMSTREN = 0 or MSTRUN = 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HEXI</name>
<description>High Timer Extra Interrupt Flag. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A high timer extra interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: Indicates the high 16-bit timer (or 32-bit timer if SPLITEN = 0) has been captured, reloaded with all 1's when counting down, or the timer matched the capture register in PWM mode. This interrupt flag can be set by the timer module in all modes except Auto-Reload and Toggle. Write: Force a high timer extra interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HOVFI</name>
<description>High Timer Overflow Interrupt Flag. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A high timer overflow interrupt is not pending. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: If split mode is enabled (SPLITEN = 1), this value indicates the high 16-bit timer has wrapped or reloaded after reaching all 1's. If split mode is disabled (SPLITEN = 0), this value indicates the 32-bit timer has wrapped or reloaded after reaching all 1's. The timer module can set this bit in all modes. Write: Force a high timer overflow interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLKDIV</name>
<description>Module Clock Divider Control</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKDIVRL</name>
<description>Clock Divider Reload Value. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CLKDIVCT</name>
<description>Clock Divider Counter. </description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT</name>
<description>Timer Value</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCOUNT</name>
<description>Low Timer Count. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>HCOUNT</name>
<description>High Timer Count. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAPTURE</name>
<description>Timer Capture/Reload Value</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LCCR</name>
<description>Low Timer Capture/Reload. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>HCCR</name>
<description>High Timer Capture/Reload. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART_0</name>
<version>B</version>
<description>None</description>
<groupName>UART_0</groupName>
<baseAddress>0x40001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART0_IRQn</name>
<value>25</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONFIG</name>
<description>Module Configuration</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x030D030D</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RSTRTEN</name>
<description>Receiver Start Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not expect a start bit during receptions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Expect a start bit during receptions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RPAREN</name>
<description>Receiver Parity Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not expect a parity bit during receptions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Expect a parity bit during receptions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTPEN</name>
<description>Receiver Stop Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not expect stop bits during receptions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Expect stop bits during receptions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTPMD</name>
<description>Receiver Stop Mode. </description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0P5_STOP</name>
<description>0.5 stop bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_STOP</name>
<description>1 stop bit.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>1P5_STOP</name>
<description>1.5 stop bits.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>2_STOP</name>
<description>2 stop bits.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RPARMD</name>
<description>Receiver Parity Mode. </description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ODD</name>
<description>Odd Parity.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EVEN</name>
<description>Even Parity.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MARK</name>
<description>Set (Parity = 1).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SPACE</name>
<description>Clear (Parity = 0).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDATLN</name>
<description>Receiver Data Length. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>5_BITS</name>
<description>5 bits.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>6_BITS</name>
<description>6 bits.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>7_BITS</name>
<description>7 bits.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BITS</name>
<description>8 bits.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BITS_STORED</name>
<description>9 bits. The 9th bit is stored in the FIFO (normal mode).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BITS_MATCH</name>
<description>9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD).</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSCEN</name>
<description>Receiver Smartcard Parity Response Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The receiver does not send a Smartcard parity error response.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The receiver sends a Smartcard parity response.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIRDAEN</name>
<description>Receiver IrDA Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The receiver does not operate in IrDA mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The receiver operates in IrDA mode. </description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RINVEN</name>
<description>Receiver Invert Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not invert the RX pin signals (the RX idle state is high).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Invert the RX pin signals (the RX idle state is low).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSTRTEN</name>
<description>Transmitter Start Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not generate a start bit during transmissions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Generate a start bit during transmissions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPAREN</name>
<description>Transmitter Parity Enable. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a parity bit during transmissions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a parity bit during transmissions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSTPEN</name>
<description>Transmitter Stop Enable. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send stop bits during transmissions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send stop bits during transmissions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSTPMD</name>
<description>Transmitter Stop Mode. </description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0P5_STOP</name>
<description>0.5 stop bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_STOP</name>
<description>1 stop bit.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>1P5_STOP</name>
<description>1.5 stop bits.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>2_STOP</name>
<description>2 stop bits.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPARMD</name>
<description>Transmitter Parity Mode. </description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ODD</name>
<description>Odd Parity.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EVEN</name>
<description>Even Parity.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MARK</name>
<description>Set (Parity = 1).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SPACE</name>
<description>Clear (Parity = 0).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDATLN</name>
<description>Transmitter Data Length. </description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>5_BITS</name>
<description>5 bits.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>6_BITS</name>
<description>6 bits.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>7_BITS</name>
<description>7 bits.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BITS</name>
<description>8 bits.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BITS_FIFO</name>
<description>9 bits. The 9th bit is taken from the FIFO data (normal mode).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BITS_TBIT</name>
<description>9 bits. The 9th bit is set by the value of TBIT (fixed mode).</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSCEN</name>
<description>Transmitter Smartcard Parity Response Enable. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The transmitter does not check for a Smartcard parity error response.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The transmitter checks for a Smartcard parity error response.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIRDAEN</name>
<description>Transmitter IrDA Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable IrDA transmit mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable IrDA transmit mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TINVEN</name>
<description>Transmitter Invert Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not invert the TX pin signals (the TX idle state is high).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Invert the TX pin signals (the TX idle state is low).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODE</name>
<description>Module Mode Select</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00600000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RTCCKMD</name>
<description>RTC Clock Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>APBCLK</name>
<description>UART clocked from the APB clock. The RBAUD and TBAUD controls will use the APB clock mode to determine the baudrate unless RTCBDMD = 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RTC0TCLK</name>
<description>UART clocked from RTC0TCLK. The RBAUD and TBAUD controls will use the RTC0TCLK mode to determine the baudrate. Software should only set this bit to one when the UART is idle.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTCBDMD</name>
<description>RTC Baud Rate Mode. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The RBAUD and TBAUD controls use the RTCCKMD setting to determine whether to use APB clock mode (RTCCKMD = 0) or the RTC0TCLK mode (RTCCKMD = 1). Use this setting when APB clock != RTC0TCLK.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The RBAUD and TBAUD controls use RTC0TCLK mode. Use this setting when APB clock = RTC0TCLK and RTCCKMD = 0 to force the RBAUD and TBAUD controls into RTC0TCLK mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FORCECLK</name>
<description>Force Clock On. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>UART clock is only on when necessary.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Force the UART clock to always be on.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKBUSY</name>
<description>Clock Switch Busy Status. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>IDLE</name>
<description>Clock switch completed.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BUSY</name>
<description>Clock switch in progress.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXCLKSW</name>
<description>Receive Automatic Clock Switch. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>UART will always use the selected clock for receive operations.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>UART will automatically switch from RTC0TCLK to the APB clock when a receive interrupt is pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXCLKSW</name>
<description>Transmit Automatic Clock Switch. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>UART will always use the selected clock for transmit operations.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>UART will automatically switch from RTC0TCLK to the APB clock when a transmit interrupt is pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>UART Debug Mode. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The UART module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the UART module to halt. Any active transmissions and receptions will complete first.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBMD</name>
<description>Loop Back Mode. </description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Loop back is disabled and the TX and RX signals are connected to the corresponding external pins.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RXONLY</name>
<description>Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TXONLY</name>
<description>Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH</name>
<description>Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DUPLEXMD</name>
<description>Duplex Mode. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>FULL_DUPLEX</name>
<description>Full-duplex mode. The transmitter and receiver can operate simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALF_DUPLEX</name>
<description>Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITSEN</name>
<description>Idle TX Tristate Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The TX pin is always an output in this mode, even when idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The TX pin is tristated when idle.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FLOWCN</name>
<description>Flow Control</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX</name>
<description>RX Pin Status. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>RX pin (after optional inversion) is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>RX pin (after optional inversion) is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOEN</name>
<description>TX Output Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The pin assigned to TX is controlled by the direct port output value.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The pin assigned to TX is controlled by the UART.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TX</name>
<description>TX State. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The TX pin (before optional inversion) is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The TX pin (before optional inversion) is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIRDAPW</name>
<description>Transmit IrDA Pulse Width. </description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>1_16TH</name>
<description>The IrDA pulse width is 1/16th of a bit period.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_8TH</name>
<description>The IrDA pulse width is 1/8th of a bit period.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>3_16TH</name>
<description>The IrDA pulse width is 3/16th of a bit period.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>1_4TH</name>
<description>The IrDA pulse width is 1/4th of a bit period.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFRMERI</name>
<description>Receive Frame Error Interrupt Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A frame error occurred. Write: Force a frame error interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RPARERI</name>
<description>Receive Parity Error Interrupt Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROREI</name>
<description>Receive Overrun Error Interrupt Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDREQI</name>
<description>Receive Data Request Interrupt Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Fewer than RFTH FIFO entries are filled with data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>At least RFTH FIFO entries are filled with data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RERIEN</name>
<description>Receive Error Interrupt Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the receive error interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the receive error interrupt. A receive interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDREQIEN</name>
<description>Receive Data Request Interrupt Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the read data request interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MATMD</name>
<description>Match Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Disable the match function.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MCE</name>
<description>(MCE) Data whose last data bit equals RBIT is accepted and stored. </description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FRAME</name>
<description>(Frame) A framing error is asserted if the last received data bit matches RBIT.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STORE</name>
<description>(Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RABDEN</name>
<description>Receiver Auto-Baud Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable receiver auto-baud.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable receiver auto-baud.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RBUSYF</name>
<description>Receiver Busy Flag. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The UART receiver is idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The UART receiver is receiving data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RBIT</name>
<description>Last Receive Bit. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROSEN</name>
<description>Receiver One-Shot Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable one-shot receive mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable one-shot receive mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RINH</name>
<description>Receiver Inhibit. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The receiver operates normally.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>The receiver will complete any ongoing reception, but ignore all traffic after that.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REN</name>
<description>Receiver Enable. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the receiver. The receiver can receive one data transaction only if ROSEN is set.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the receiver.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSCERI</name>
<description>Smartcard Parity Error Interrupt Flag. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDREQI</name>
<description>Transmit Data Request Interrupt Flag. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The transmitter is not requesting more FIFO data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The transmitter is requesting more FIFO data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCPTI</name>
<description>Transmit Complete Interrupt Flag. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCPTTH</name>
<description>Transmit Complete Threshold. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET_ON_TX</name>
<description>The TCPTI flag is set after each data transmission.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_ON_EMPTY</name>
<description>The TCPTI flag is set after transmission of the last available data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TERIEN</name>
<description>Transmit Error Interrupt Enable. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmit error interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDREQIEN</name>
<description>Transmit Data Request Interrupt Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmit data request interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCPTIEN</name>
<description>Transmit Complete Interrupt Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmit complete interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TBUSYF</name>
<description>Transmitter Busy Flag. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The UART transmitter is idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The UART transmitter is active and transmitting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TBIT</name>
<description>Last Transmit Bit. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TINH</name>
<description>Transmit Inhibit. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The transmitter operates normally.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Transmissions are inhibited. The transmitter will stall after any current transmission is complete.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TEN</name>
<description>Transmitter Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. </description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IPDELAY</name>
<description>Inter-Packet Delay</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IPDELAY</name>
<description>Inter-Packet Delay. </description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BAUDRATE</name>
<description>Transmit and Receive Baud Rate</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RBAUD</name>
<description>Receiver Baud Rate Control. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TBAUD</name>
<description>Transmitter Baud Rate Control. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FIFOCN</name>
<description>FIFO Control</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RCNT</name>
<description>Receive FIFO Count. </description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RFTH</name>
<description>Receive FIFO Threshold. </description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ONE</name>
<description>A read data request interrupt (RDREQI) is asserted when &gt;= 1 FIFO entry is full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TWO</name>
<description>A read data request interrupt (RDREQI) is asserted when &gt;= 2 FIFO entries are full.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>THREE</name>
<description>A read data request interrupt (RDREQI) is asserted when &gt;= 3 FIFO entries are full.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>FOUR</name>
<description>A read data request interrupt (RDREQI) is asserted when &gt;= 4 FIFO entries are full.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFIFOFL</name>
<description>Receive FIFO Flush. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Flush the contents of the receive FIFO and any data in the receive shift register.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFERI</name>
<description>Receive FIFO Error Interrupt Flag. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A receive FIFO error has not occurred since RFERI was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A receive FIFO error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRFULLF</name>
<description>Receive Shift Register Full Flag. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The receive data shift register is not full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The receive data shift register is full.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCNT</name>
<description>Transmit FIFO Count. </description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TFTH</name>
<description>Transmit FIFO Threshold. </description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ONE</name>
<description>A transmit data request interrupt (TDREQI) is asserted when &gt;= 1 FIFO entry is empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TWO</name>
<description>A transmit data request interrupt (TDREQI) is asserted when &gt;= 2 FIFO entries are empty.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>THREE</name>
<description>A transmit data request interrupt (TDREQI) is asserted when &gt;= 3 FIFO entries are empty.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>FOUR</name>
<description>A transmit data request interrupt (TDREQI) is asserted when &gt;= 4 FIFO entries are empty.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFIFOFL</name>
<description>Transmit FIFO Flush. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFERI</name>
<description>Transmit FIFO Error Interrupt Flag. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A transmit FIFO error has not occurred since TFERI was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A transmit FIFO error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSRFULLF</name>
<description>Transmit Shift Register Full Flag. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The transmit shift register is not full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The transmit shift register is full.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description>FIFO Input/Output Data</description>
<addressOffset>0x70</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<readAction>modifyExternal</readAction>
<fields>
<field>
<name>DATA</name>
<description>FIFO Data. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLKDIV</name>
<description>Clock Divider</description>
<addressOffset>0x80</addressOffset>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLKDIV</name>
<description>Clock Divider. </description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DIV1</name>
<description>Divide by 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV2</name>
<description>Divide by 2.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DIV4</name>
<description>Divide by 4.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USART_0</name>
<version>B</version>
<description>None</description>
<groupName>USART_0</groupName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART0_IRQn</name>
<value>24</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONFIG</name>
<description>Module Configuration</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x030D030D</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RSTRTEN</name>
<description>Receiver Start Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not expect a start bit during receptions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Expect a start bit during receptions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RPAREN</name>
<description>Receiver Parity Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not expect a parity bit during receptions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Expect a parity bit during receptions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTPEN</name>
<description>Receiver Stop Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not expect stop bits during receptions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Expect stop bits during receptions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSTPMD</name>
<description>Receiver Stop Mode. </description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0P5_STOP</name>
<description>0.5 stop bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_STOP</name>
<description>1 stop bit.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>1P5_STOP</name>
<description>1.5 stop bits.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>2_STOP</name>
<description>2 stop bits.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RPARMD</name>
<description>Receiver Parity Mode. </description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ODD</name>
<description>Odd Parity.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EVEN</name>
<description>Even Parity.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MARK</name>
<description>Set (Parity = 1).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SPACE</name>
<description>Clear (Parity = 0).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDATLN</name>
<description>Receiver Data Length. </description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>5_BITS</name>
<description>5 bits.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>6_BITS</name>
<description>6 bits.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>7_BITS</name>
<description>7 bits.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BITS</name>
<description>8 bits.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BITS_STORED</name>
<description>9 bits. The 9th bit is stored in the FIFO (normal mode).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BITS_MATCH</name>
<description>9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used when the 9th bit is only used for match operations (see MATMD).</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSCEN</name>
<description>Receiver Smartcard Parity Response Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The receiver does not send a Smartcard parity error response.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The receiver sends a Smartcard parity response.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RIRDAEN</name>
<description>Receiver IrDA Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The receiver does not operate in IrDA mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The receiver operates in IrDA mode. </description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RINVEN</name>
<description>Receiver Invert Enable. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not invert the RX pin signals (the RX idle state is high).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Invert the RX pin signals (the RX idle state is low).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSYNCEN</name>
<description>Receiver Synchronous Mode Enable. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The receiver operates in asynchronous mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The receiver operates in synchronous mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSTRTEN</name>
<description>Transmitter Start Enable. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not generate a start bit during transmissions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Generate a start bit during transmissions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPAREN</name>
<description>Transmitter Parity Enable. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send a parity bit during transmissions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send a parity bit during transmissions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSTPEN</name>
<description>Transmitter Stop Enable. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not send stop bits during transmissions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Send stop bits during transmissions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSTPMD</name>
<description>Transmitter Stop Mode. </description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0P5_STOP</name>
<description>0.5 stop bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_STOP</name>
<description>1 stop bit.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>1P5_STOP</name>
<description>1.5 stop bits.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>2_STOP</name>
<description>2 stop bits.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TPARMD</name>
<description>Transmitter Parity Mode. </description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ODD</name>
<description>Odd Parity.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EVEN</name>
<description>Even Parity.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>MARK</name>
<description>Set (Parity = 1).</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SPACE</name>
<description>Clear (Parity = 0).</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDATLN</name>
<description>Transmitter Data Length. </description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>5_BITS</name>
<description>5 bits.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>6_BITS</name>
<description>6 bits.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>7_BITS</name>
<description>7 bits.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>8_BITS</name>
<description>8 bits.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BITS_FIFO</name>
<description>9 bits. The 9th bit is taken from the FIFO data (normal mode).</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>9_BITS_TBIT</name>
<description>9 bits. The 9th bit is set by the value of TBIT (fixed mode).</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSCEN</name>
<description>Transmitter Smartcard Parity Response Enable. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The transmitter does not check for a Smartcard parity error response.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The transmitter checks for a Smartcard parity error response.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIRDAEN</name>
<description>Transmitter IrDA Enable. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable IrDA transmit mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable IrDA transmit mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TINVEN</name>
<description>Transmitter Invert Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Do not invert the TX pin signals (the TX idle state is high).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Invert the TX pin signals (the TX idle state is low).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSYNCEN</name>
<description>Transmitter Synchronous Mode Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The transmitter operates in asynchronous mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The transmitter operates in synchronous mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MODE</name>
<description>Module Mode Select</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00600000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DBGMD</name>
<description>USART Debug Mode. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The USART module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the USART module to halt. Any active transmissions and receptions will complete first.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LBMD</name>
<description>Loop Back Mode. </description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Loop back is disabled and the TX and RX signals are connected to the corresponding external pins.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RXONLY</name>
<description>Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TXONLY</name>
<description>Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BOTH</name>
<description>Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STPSTCLK</name>
<description>Stop State Clock Control. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>When the USART is a clock master, the clock is not generated during stop bits.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>When the USART is a clock master, the clock is generated during stop bits.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>STRTSTCLK</name>
<description>Start State Clock Control. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>When the USART is a clock master, the clock is held idle during a start bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>When the USART is a clock master, the clock is generated during a start bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ISTCLK</name>
<description>Idle Clock Control. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>When the USART is a clock master, the clock is held idle between transmissions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>When the USART is a clock master, the clock is generated between transmissions or receptions.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DUPLEXMD</name>
<description>Duplex Mode. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>FULL_DUPLEX</name>
<description>Full-duplex mode. The transmitter and receiver can operate simultaneously.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALF_DUPLEX</name>
<description>Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKIDLE</name>
<description>Clock Idle State. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>IDLE_LOW</name>
<description>The synchronous clock is low when idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>IDLE_HIGH</name>
<description>The synchronous clock is high when idle.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKESEL</name>
<description>Clock Edge Select. </description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>FALLING</name>
<description>The clock falls in the middle of each bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RISING</name>
<description>The clock rises in the middle of each bit.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ITSEN</name>
<description>Idle TX/UCLK Tristate Enable. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>If ISTCLK is cleared to 0, the TX pin is tristated when idle. The UCLK pin will also be tristated when idle if in synchronous master mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>OPMD</name>
<description>Operational Mode. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SLAVE</name>
<description>The USART operates as a slave.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MASTER</name>
<description>The USART operates as a master.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FLOWCN</name>
<description>Flow Control</description>
<addressOffset>0x20</addressOffset>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RTS</name>
<description>RTS State. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>RTS pin (before optional inversion) is driven low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>RTS pin (before optional inversion) is driven high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RX</name>
<description>RX Pin Status. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>RX pin (after optional inversion) is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>RX pin (after optional inversion) is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTSINVEN</name>
<description>RTS Invert Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The USART does not invert the RTS signal before driving the pin.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The USART inverts the RTS signal driving the pin.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTSTH</name>
<description>RTS Threshold Control. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>FULL</name>
<description>RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_BYTE_FREE</name>
<description>RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTSEN</name>
<description>RTS Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXOEN</name>
<description>TX Output Enable. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The pin assigned to TX is tri-stated, regardless of other settings.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The pin assigned to TX is controlled by the USART.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTS</name>
<description>CTS State. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>Indicates the CTS pin state (after optional inversion) is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Indicates the CTS pin state (after optional inversion) is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TX</name>
<description>TX State. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The TX pin (before optional inversion) is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The TX pin (before optional inversion) is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UCLK</name>
<description>UCLK State. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>The UCLK pin is low.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>The UCLK pin is high.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTSINVEN</name>
<description>CTS Invert Enable. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The USART does not invert CTS.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>The USART inverts CTS.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTSEN</name>
<description>CTS Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>The CTS pin state does not affect transmissions.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Transmissions will begin only if the CTS pin (after optional inversion) is low.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TIRDAPW</name>
<description>Transmit IrDA Pulse Width. </description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>1_16TH</name>
<description>The IrDA pulse width is 1/16th of a bit period.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_8TH</name>
<description>The IrDA pulse width is 1/8th of a bit period.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>3_16TH</name>
<description>The IrDA pulse width is 3/16th of a bit period.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>1_4TH</name>
<description>The IrDA pulse width is 1/4th of a bit period.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFRMERI</name>
<description>Receive Frame Error Interrupt Flag. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A frame error occurred. Write: Force a frame error interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RPARERI</name>
<description>Receive Parity Error Interrupt Flag. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROREI</name>
<description>Receive Overrun Error Interrupt Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDREQI</name>
<description>Receive Data Request Interrupt Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Fewer than RFTH FIFO entries are filled with data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>At least RFTH FIFO entries are filled with data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RERIEN</name>
<description>Receive Error Interrupt Enable. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the receive error interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the receive error interrupt. A receive interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDREQIEN</name>
<description>Receive Data Request Interrupt Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the read data request interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MATMD</name>
<description>Match Mode. </description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>OFF</name>
<description>Disable the match function.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>MCE</name>
<description>(MCE) Data whose last data bit equals RBIT is accepted and stored. </description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>FRAME</name>
<description>(Frame) A framing error is asserted if the last received data bit matches RBIT.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STORE</name>
<description>(Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RABDEN</name>
<description>Receiver Auto-Baud Enable. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable receiver auto-baud.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable receiver auto-baud.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RBUSYF</name>
<description>Receiver Busy Flag. </description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The USART receiver is idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The USART receiver is receiving data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RBIT</name>
<description>Last Receive Bit. </description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ROSEN</name>
<description>Receiver One-Shot Enable. </description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable one-shot receive mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable one-shot receive mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RINH</name>
<description>Receiver Inhibit. </description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The receiver operates normally.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REN</name>
<description>Receiver Enable. </description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the receiver. The receiver can receive one data transaction only if ROSEN is set.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the receiver.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSCERI</name>
<description>Smartcard Parity Error Interrupt Flag. </description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TUREI</name>
<description>Transmit Underrun Error Interrupt Flag. </description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A transmitter underrun has not occurred since TUREI was last cleared. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A transmitter underrun occurred. Write: Force a transmitter underrun interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDREQI</name>
<description>Transmit Data Request Interrupt Flag. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The transmitter is not requesting more FIFO data.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The transmitter is requesting more FIFO data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCPTI</name>
<description>Transmit Complete Interrupt Flag. </description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCPTTH</name>
<description>Transmit Complete Threshold. </description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET_ON_TX</name>
<description>The TCPTI flag is set after each data transmission.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET_ON_EMPTY</name>
<description>The TCPTI flag is set after transmission of the last available data.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TERIEN</name>
<description>Transmit Error Interrupt Enable. </description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmit error interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDREQIEN</name>
<description>Transmit Data Request Interrupt Enable. </description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmit data request interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCPTIEN</name>
<description>Transmit Complete Interrupt Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmit complete interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TBUSYF</name>
<description>Transmitter Busy Flag. </description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The USART transmitter is idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The USART transmitter is active and transmitting.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TBIT</name>
<description>Last Transmit Bit. </description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TINH</name>
<description>Transmit Inhibit. </description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>INACTIVE</name>
<description>The transmitter operates normally.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ACTIVE</name>
<description>Transmissions are inhibited. The transmitter will stall after any current transmission is complete.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TEN</name>
<description>Transmitter Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. </description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IPDELAY</name>
<description>Inter-Packet Delay</description>
<addressOffset>0x40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IPDELAY</name>
<description>Inter-Packet Delay. </description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BAUDRATE</name>
<description>Transmit and Receive Baud Rate</description>
<addressOffset>0x50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RBAUD</name>
<description>Receiver Baud Rate Control. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TBAUD</name>
<description>Transmitter Baud Rate Control. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>FIFOCN</name>
<description>FIFO Control</description>
<addressOffset>0x60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RCNT</name>
<description>Receive FIFO Count. </description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RFTH</name>
<description>Receive FIFO Threshold. </description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ONE</name>
<description>A DMA request or read data request interrupt (RDREQI) is asserted when &gt;= 1 FIFO entry is full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TWO</name>
<description>A DMA request or read data request interrupt (RDREQI) is asserted when &gt;= 2 FIFO entries are full.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>THREE</name>
<description>A DMA request or read data request interrupt (RDREQI) is asserted when &gt;= 3 FIFO entries are full.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>FOUR</name>
<description>A DMA request or read data request interrupt (RDREQI) is asserted when &gt;= 4 FIFO entries are full.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RDMAEN</name>
<description>Receiver DMA Enable. </description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable receive FIFO DMA requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable receive FIFO DMA requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFIFOFL</name>
<description>Receive FIFO Flush. </description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Flush the contents of the receive FIFO and any data in the receive shift register.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RFERI</name>
<description>Receive FIFO Error Interrupt Flag. </description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A receive FIFO error has not occurred since RFERI was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A receive FIFO error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RSRFULLF</name>
<description>Receive Shift Register Full Flag. </description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The receive data shift register is not full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The receive data shift register is full.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TCNT</name>
<description>Transmit FIFO Count. </description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TFTH</name>
<description>Transmit FIFO Threshold. </description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>ONE</name>
<description>A DMA request or transmit data request interrupt (TDREQI) is asserted when &gt;= 1 FIFO entry is empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TWO</name>
<description>A DMA request or transmit data request interrupt (TDREQI) is asserted when &gt;= 2 FIFO entries are empty.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>THREE</name>
<description>A DMA request or transmit data request interrupt (TDREQI) is asserted when &gt;= 3 FIFO entries are empty.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>FOUR</name>
<description>A DMA request or transmit data request interrupt (TDREQI) is asserted when &gt;= 4 FIFO entries are empty.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TDMAEN</name>
<description>Transmitter DMA Enable. </description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable transmit FIFO DMA requests.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable transmit FIFO DMA requests.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFIFOFL</name>
<description>Transmit FIFO Flush. </description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>SET</name>
<description>Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TFERI</name>
<description>Transmit FIFO Error Interrupt Flag. </description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>A transmit FIFO error has not occurred since TFERI was last cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>A transmit FIFO error occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TSRFULLF</name>
<description>Transmit Shift Register Full Flag. </description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>The transmit shift register is not full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>The transmit shift register is full.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description>FIFO Input/Output Data</description>
<addressOffset>0x70</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<readAction>modifyExternal</readAction>
<fields>
<field>
<name>DATA</name>
<description>FIFO Data. </description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>VMON_0</name>
<version>B</version>
<description>None</description>
<groupName>VMON_0</groupName>
<baseAddress>0x4002f000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>VDDLOW_IRQn</name>
<value>38</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x80000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VBATRSTF</name>
<description>VBAT Reset Threshold Status Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>VBAT_IS_BELOW_RESET</name>
<description>The VBAT voltage is below the VBAT reset threshold.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VBAT_IS_ABOVE_RESET</name>
<description>The VBAT voltage is above the VBAT reset threshold.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VBATLI</name>
<description>VBAT Low Interrupt Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>VBAT_IS_LOW</name>
<description>The VBAT voltage is below the early warning threshold.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>VBAT_IS_OK</name>
<description>The VBAT voltage is above the early warning threshold.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VBATHITHEN</name>
<description>VBAT High Threshold Enable. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Use the standard VBAT thresholds.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Use the high VBAT thresholds.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VBATLIEN</name>
<description>VBAT Low Interrupt Enable. </description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the VBAT low interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the VBAT low interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VMONEN</name>
<description>VBAT Supply Monitor Enable. </description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the VBAT supply monitor.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the VBAT supply monitor.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>VREF_0</name>
<version>B</version>
<description>None</description>
<groupName>VREF_0</groupName>
<baseAddress>0x40039010</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VREF2X</name>
<description>Voltage Reference Doubler. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>VREF output is nominally 1.2 V</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>VREF output is nominally 2.4 V</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TEMPEN</name>
<description>Temperature Sensor Enable. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the temperature sensor.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the temperature sensor.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>VREFOUTEN</name>
<description>VREF Output Enable. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Internal VREF is not driven on the VREF pin.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Internal VREF is driven out to the VREF pin.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WDTIMER_0</name>
<version>A</version>
<description>None</description>
<groupName>WDTIMER_0</groupName>
<baseAddress>0x40030000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xffc</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WDTIMER0_IRQn</name>
<value>0</value>
</interrupt>
<registers>
<!--BASEPOINTER_START_1-->
<register>
<name>CONTROL</name>
<description>Module Control</description>
<addressOffset>0x0</addressOffset>
<resetValue>0x00000002</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EWIEN</name>
<description>Early Warning Interrupt Enable. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable the early warning interrupt (EWI).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable the early warning interrupt (EWI).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBGMD</name>
<description>Watchdog Timer Debug Mode. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RUN</name>
<description>The WDTIMER module will continue to operate while the core is halted in debug mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HALT</name>
<description>A debug breakpoint will cause the WDTIMER module to halt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Module Status</description>
<addressOffset>0x10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>KEYSTS</name>
<description>Key Status. </description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>IDLE</name>
<description>No keys have been processed by the interface.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>READY</name>
<description>The attention key has been received and the module is awaiting a command.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRIVSTS</name>
<description>Register Access Status. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>READ_ONLY</name>
<description>The watchdog timer registers are currently read-only.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>READ_WRITE</name>
<description>A write transaction can be performed on the module registers.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EWI</name>
<description>Early Warning Interrupt Flag. </description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>NOT_SET</name>
<description>Read: An early warning match did not occur. Write: Clear the early warning interrupt.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SET</name>
<description>Read: An early warning match occurred and the interrupt is pending. Write: Force a watchdog timer early warning interrupt to occur.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RTHF</name>
<description>Reset Threshold Flag. </description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>LT</name>
<description>The counter is currently less than the reset threshold (RTH) value.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>GTE</name>
<description>The counter is currently greater than or equal to the reset threshold (RTH) value.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>UPDSTS</name>
<description>Watchdog Timer Threshold Update Status. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>IDLE</name>
<description>An update completed or is not pending. The EWTH and RTH fields can be written.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>UPDATING</name>
<description>An update of the threshold register is occurring. The EWTH and RTH fields should not be modified until hardware clears UPDSTS to 0.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>THRESHOLD</name>
<description>Threshold Values</description>
<addressOffset>0x20</addressOffset>
<resetValue>0xFFFF7FFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EWTH</name>
<description>Early Warning Threshold. </description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>RTH</name>
<description>Reset Threshold. </description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTKEY</name>
<description>Module Key</description>
<addressOffset>0x30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>KEY</name>
<description>Watchdog Timer Key. </description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>ATTN</name>
<description>Attention key to start the command sequence.</description>
<value>165</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET</name>
<description>Reset the watchdog timer.</description>
<value>204</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable the watchdog timer.</description>
<value>221</value>
</enumeratedValue>
<enumeratedValue>
<name>START</name>
<description>Start the watchdog timer.</description>
<value>238</value>
</enumeratedValue>
<enumeratedValue>
<name>WRITE</name>
<description>Allow one write access to the module registers.</description>
<value>241</value>
</enumeratedValue>
<enumeratedValue>
<name>LOCK</name>
<description>Lock the module from any other writes until the next system reset.</description>
<value>255</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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