69566 lines
2.7 MiB
69566 lines
2.7 MiB
<?xml version="1.0" encoding="utf-8"?>
|
|
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.3" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
|
|
<name>EFM32GG332F512</name>
|
|
<version>4.0.0</version>
|
|
<description>Silicon Labs EFM32GG332F512 Cortex-M MCU</description>
|
|
<licenseText>
|
|
*******************************************************************************\n
|
|
* # License \n
|
|
* Copyright 2021 Silicon Laboratories Inc. www.silabs.com \n
|
|
*******************************************************************************\n
|
|
* \n
|
|
* SPDX-License-Identifier: Zlib \n
|
|
* \n
|
|
* The licensor of this software is Silicon Laboratories Inc. \n
|
|
* \n
|
|
* This software is provided 'as-is', without any express or implied \n
|
|
* warranty. In no event will the authors be held liable for any damages \n
|
|
* arising from the use of this software. \n
|
|
* \n
|
|
* Permission is granted to anyone to use this software for any purpose, \n
|
|
* including commercial applications, and to alter it and redistribute it \n
|
|
* freely, subject to the following restrictions: \n
|
|
* \n
|
|
* 1. The origin of this software must not be misrepresented; you must not \n
|
|
* claim that you wrote the original software. If you use this software \n
|
|
* in a product, an acknowledgment in the product documentation would be \n
|
|
* appreciated but is not required. \n
|
|
* 2. Altered source versions must be plainly marked as such, and must not be \n
|
|
* misrepresented as being the original software. \n
|
|
* 3. This notice may not be removed or altered from any source distribution. \n
|
|
* \n
|
|
*******************************************************************************
|
|
</licenseText>
|
|
<cpu>
|
|
<name>CM3</name>
|
|
<revision>r2p1</revision>
|
|
<endian>little</endian>
|
|
<mpuPresent>true</mpuPresent>
|
|
<fpuPresent>false</fpuPresent>
|
|
<nvicPrioBits>3</nvicPrioBits>
|
|
<vendorSystickConfig>false</vendorSystickConfig>
|
|
</cpu>
|
|
<addressUnitBits>8</addressUnitBits>
|
|
<width>32</width>
|
|
<peripherals>
|
|
<peripheral>
|
|
<name>DMA</name>
|
|
<description>DMA</description>
|
|
<baseAddress>0x400C2000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00002000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>DMA Status Registers</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x100B0000</resetValue>
|
|
<resetMask>0x001F00F1</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>DMA Enable Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATE</name>
|
|
<description>Control Current State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>Idle</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDCHCTRLDATA</name>
|
|
<description>Reading channel controller data</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDSRCENDPTR</name>
|
|
<description>Reading source data end pointer</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDDSTENDPTR</name>
|
|
<description>Reading destination data end pointer</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDSRCDATA</name>
|
|
<description>Reading source data</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRDSTDATA</name>
|
|
<description>Writing destination data</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITREQCLR</name>
|
|
<description>Waiting for DMA request to clear</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRCHCTRLDATA</name>
|
|
<description>Writing channel controller data</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STALLED</name>
|
|
<description>Stalled</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DONE</name>
|
|
<description>Done</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERSCATTRANS</name>
|
|
<description>Peripheral scatter-gather transition</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHNUM</name>
|
|
<description>Channel Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>DMA Configuration Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000021</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enable DMA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHPROT</name>
|
|
<description>Channel Protection Control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLBASE</name>
|
|
<description>Channel Control Data Base Pointer Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRLBASE</name>
|
|
<description>Channel Control Data Base Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTCTRLBASE</name>
|
|
<description>Channel Alternate Control Data Base Pointer Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ALTCTRLBASE</name>
|
|
<description>Channel Alternate Control Data Base Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHWAITSTATUS</name>
|
|
<description>Channel Wait on Request Status Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000FFF</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0WAITSTATUS</name>
|
|
<description>Channel 0 Wait on Request Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1WAITSTATUS</name>
|
|
<description>Channel 1 Wait on Request Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2WAITSTATUS</name>
|
|
<description>Channel 2 Wait on Request Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3WAITSTATUS</name>
|
|
<description>Channel 3 Wait on Request Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4WAITSTATUS</name>
|
|
<description>Channel 4 Wait on Request Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5WAITSTATUS</name>
|
|
<description>Channel 5 Wait on Request Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6WAITSTATUS</name>
|
|
<description>Channel 6 Wait on Request Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7WAITSTATUS</name>
|
|
<description>Channel 7 Wait on Request Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8WAITSTATUS</name>
|
|
<description>Channel 8 Wait on Request Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9WAITSTATUS</name>
|
|
<description>Channel 9 Wait on Request Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10WAITSTATUS</name>
|
|
<description>Channel 10 Wait on Request Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11WAITSTATUS</name>
|
|
<description>Channel 11 Wait on Request Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHSWREQ</name>
|
|
<description>Channel Software Request Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0SWREQ</name>
|
|
<description>Channel 0 Software Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1SWREQ</name>
|
|
<description>Channel 1 Software Request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2SWREQ</name>
|
|
<description>Channel 2 Software Request</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3SWREQ</name>
|
|
<description>Channel 3 Software Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4SWREQ</name>
|
|
<description>Channel 4 Software Request</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5SWREQ</name>
|
|
<description>Channel 5 Software Request</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6SWREQ</name>
|
|
<description>Channel 6 Software Request</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7SWREQ</name>
|
|
<description>Channel 7 Software Request</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8SWREQ</name>
|
|
<description>Channel 8 Software Request</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9SWREQ</name>
|
|
<description>Channel 9 Software Request</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10SWREQ</name>
|
|
<description>Channel 10 Software Request</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11SWREQ</name>
|
|
<description>Channel 11 Software Request</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHUSEBURSTS</name>
|
|
<description>Channel Useburst Set Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0USEBURSTS</name>
|
|
<description>Channel 0 Useburst Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1USEBURSTS</name>
|
|
<description>Channel 1 Useburst Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2USEBURSTS</name>
|
|
<description>Channel 2 Useburst Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3USEBURSTS</name>
|
|
<description>Channel 3 Useburst Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4USEBURSTS</name>
|
|
<description>Channel 4 Useburst Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5USEBURSTS</name>
|
|
<description>Channel 5 Useburst Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6USEBURSTS</name>
|
|
<description>Channel 6 Useburst Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7USEBURSTS</name>
|
|
<description>Channel 7 Useburst Set</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8USEBURSTS</name>
|
|
<description>Channel 8 Useburst Set</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9USEBURSTS</name>
|
|
<description>Channel 9 Useburst Set</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10USEBURSTS</name>
|
|
<description>Channel 10 Useburst Set</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11USEBURSTS</name>
|
|
<description>Channel 11 Useburst Set</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHUSEBURSTC</name>
|
|
<description>Channel Useburst Clear Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0USEBURSTC</name>
|
|
<description>Channel 0 Useburst Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1USEBURSTC</name>
|
|
<description>Channel 1 Useburst Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2USEBURSTC</name>
|
|
<description>Channel 2 Useburst Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3USEBURSTC</name>
|
|
<description>Channel 3 Useburst Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4USEBURSTC</name>
|
|
<description>Channel 4 Useburst Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5USEBURSTC</name>
|
|
<description>Channel 5 Useburst Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6USEBURSTC</name>
|
|
<description>Channel 6 Useburst Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7USEBURSTC</name>
|
|
<description>Channel 7 Useburst Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH08USEBURSTC</name>
|
|
<description>Channel 8 Useburst Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9USEBURSTC</name>
|
|
<description>Channel 9 Useburst Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10USEBURSTC</name>
|
|
<description>Channel 10 Useburst Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11USEBURSTC</name>
|
|
<description>Channel 11 Useburst Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHREQMASKS</name>
|
|
<description>Channel Request Mask Set Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0REQMASKS</name>
|
|
<description>Channel 0 Request Mask Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1REQMASKS</name>
|
|
<description>Channel 1 Request Mask Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2REQMASKS</name>
|
|
<description>Channel 2 Request Mask Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3REQMASKS</name>
|
|
<description>Channel 3 Request Mask Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4REQMASKS</name>
|
|
<description>Channel 4 Request Mask Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5REQMASKS</name>
|
|
<description>Channel 5 Request Mask Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6REQMASKS</name>
|
|
<description>Channel 6 Request Mask Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7REQMASKS</name>
|
|
<description>Channel 7 Request Mask Set</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8REQMASKS</name>
|
|
<description>Channel 8 Request Mask Set</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9REQMASKS</name>
|
|
<description>Channel 9 Request Mask Set</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10REQMASKS</name>
|
|
<description>Channel 10 Request Mask Set</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11REQMASKS</name>
|
|
<description>Channel 11 Request Mask Set</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHREQMASKC</name>
|
|
<description>Channel Request Mask Clear Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0REQMASKC</name>
|
|
<description>Channel 0 Request Mask Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1REQMASKC</name>
|
|
<description>Channel 1 Request Mask Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2REQMASKC</name>
|
|
<description>Channel 2 Request Mask Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3REQMASKC</name>
|
|
<description>Channel 3 Request Mask Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4REQMASKC</name>
|
|
<description>Channel 4 Request Mask Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5REQMASKC</name>
|
|
<description>Channel 5 Request Mask Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6REQMASKC</name>
|
|
<description>Channel 6 Request Mask Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7REQMASKC</name>
|
|
<description>Channel 7 Request Mask Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8REQMASKC</name>
|
|
<description>Channel 8 Request Mask Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9REQMASKC</name>
|
|
<description>Channel 9 Request Mask Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10REQMASKC</name>
|
|
<description>Channel 10 Request Mask Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11REQMASKC</name>
|
|
<description>Channel 11 Request Mask Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHENS</name>
|
|
<description>Channel Enable Set Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0ENS</name>
|
|
<description>Channel 0 Enable Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1ENS</name>
|
|
<description>Channel 1 Enable Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2ENS</name>
|
|
<description>Channel 2 Enable Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3ENS</name>
|
|
<description>Channel 3 Enable Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4ENS</name>
|
|
<description>Channel 4 Enable Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5ENS</name>
|
|
<description>Channel 5 Enable Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6ENS</name>
|
|
<description>Channel 6 Enable Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7ENS</name>
|
|
<description>Channel 7 Enable Set</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8ENS</name>
|
|
<description>Channel 8 Enable Set</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9ENS</name>
|
|
<description>Channel 9 Enable Set</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10ENS</name>
|
|
<description>Channel 10 Enable Set</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11ENS</name>
|
|
<description>Channel 11 Enable Set</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHENC</name>
|
|
<description>Channel Enable Clear Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0ENC</name>
|
|
<description>Channel 0 Enable Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1ENC</name>
|
|
<description>Channel 1 Enable Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2ENC</name>
|
|
<description>Channel 2 Enable Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3ENC</name>
|
|
<description>Channel 3 Enable Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4ENC</name>
|
|
<description>Channel 4 Enable Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5ENC</name>
|
|
<description>Channel 5 Enable Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6ENC</name>
|
|
<description>Channel 6 Enable Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7ENC</name>
|
|
<description>Channel 7 Enable Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8ENC</name>
|
|
<description>Channel 8 Enable Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9ENC</name>
|
|
<description>Channel 9 Enable Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10ENC</name>
|
|
<description>Channel 10 Enable Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11ENC</name>
|
|
<description>Channel 11 Enable Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHALTS</name>
|
|
<description>Channel Alternate Set Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0ALTS</name>
|
|
<description>Channel 0 Alternate Structure Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1ALTS</name>
|
|
<description>Channel 1 Alternate Structure Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2ALTS</name>
|
|
<description>Channel 2 Alternate Structure Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3ALTS</name>
|
|
<description>Channel 3 Alternate Structure Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4ALTS</name>
|
|
<description>Channel 4 Alternate Structure Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5ALTS</name>
|
|
<description>Channel 5 Alternate Structure Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6ALTS</name>
|
|
<description>Channel 6 Alternate Structure Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7ALTS</name>
|
|
<description>Channel 7 Alternate Structure Set</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8ALTS</name>
|
|
<description>Channel 8 Alternate Structure Set</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9ALTS</name>
|
|
<description>Channel 9 Alternate Structure Set</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10ALTS</name>
|
|
<description>Channel 10 Alternate Structure Set</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11ALTS</name>
|
|
<description>Channel 11 Alternate Structure Set</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHALTC</name>
|
|
<description>Channel Alternate Clear Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0ALTC</name>
|
|
<description>Channel 0 Alternate Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1ALTC</name>
|
|
<description>Channel 1 Alternate Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2ALTC</name>
|
|
<description>Channel 2 Alternate Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3ALTC</name>
|
|
<description>Channel 3 Alternate Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4ALTC</name>
|
|
<description>Channel 4 Alternate Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5ALTC</name>
|
|
<description>Channel 5 Alternate Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6ALTC</name>
|
|
<description>Channel 6 Alternate Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7ALTC</name>
|
|
<description>Channel 7 Alternate Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8ALTC</name>
|
|
<description>Channel 8 Alternate Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9ALTC</name>
|
|
<description>Channel 9 Alternate Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10ALTC</name>
|
|
<description>Channel 10 Alternate Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11ALTC</name>
|
|
<description>Channel 11 Alternate Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHPRIS</name>
|
|
<description>Channel Priority Set Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0PRIS</name>
|
|
<description>Channel 0 High Priority Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1PRIS</name>
|
|
<description>Channel 1 High Priority Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2PRIS</name>
|
|
<description>Channel 2 High Priority Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3PRIS</name>
|
|
<description>Channel 3 High Priority Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4PRIS</name>
|
|
<description>Channel 4 High Priority Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5PRIS</name>
|
|
<description>Channel 5 High Priority Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6PRIS</name>
|
|
<description>Channel 6 High Priority Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7PRIS</name>
|
|
<description>Channel 7 High Priority Set</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8PRIS</name>
|
|
<description>Channel 8 High Priority Set</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9PRIS</name>
|
|
<description>Channel 9 High Priority Set</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10PRIS</name>
|
|
<description>Channel 10 High Priority Set</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11PRIS</name>
|
|
<description>Channel 11 High Priority Set</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHPRIC</name>
|
|
<description>Channel Priority Clear Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0PRIC</name>
|
|
<description>Channel 0 High Priority Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1PRIC</name>
|
|
<description>Channel 1 High Priority Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2PRIC</name>
|
|
<description>Channel 2 High Priority Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3PRIC</name>
|
|
<description>Channel 3 High Priority Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4PRIC</name>
|
|
<description>Channel 4 High Priority Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5PRIC</name>
|
|
<description>Channel 5 High Priority Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6PRIC</name>
|
|
<description>Channel 6 High Priority Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7PRIC</name>
|
|
<description>Channel 7 High Priority Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8PRIC</name>
|
|
<description>Channel 8 High Priority Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9PRIC</name>
|
|
<description>Channel 9 High Priority Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10PRIC</name>
|
|
<description>Channel 10 High Priority Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11PRIC</name>
|
|
<description>Channel 11 High Priority Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERRORC</name>
|
|
<description>Bus Error Clear Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERRORC</name>
|
|
<description>Bus Error Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHREQSTATUS</name>
|
|
<description>Channel Request Status</description>
|
|
<addressOffset>0xE10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0REQSTATUS</name>
|
|
<description>Channel 0 Request Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1REQSTATUS</name>
|
|
<description>Channel 1 Request Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2REQSTATUS</name>
|
|
<description>Channel 2 Request Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3REQSTATUS</name>
|
|
<description>Channel 3 Request Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4REQSTATUS</name>
|
|
<description>Channel 4 Request Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5REQSTATUS</name>
|
|
<description>Channel 5 Request Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6REQSTATUS</name>
|
|
<description>Channel 6 Request Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7REQSTATUS</name>
|
|
<description>Channel 7 Request Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8REQSTATUS</name>
|
|
<description>Channel 8 Request Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9REQSTATUS</name>
|
|
<description>Channel 9 Request Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10REQSTATUS</name>
|
|
<description>Channel 10 Request Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11REQSTATUS</name>
|
|
<description>Channel 11 Request Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHSREQSTATUS</name>
|
|
<description>Channel Single Request Status</description>
|
|
<addressOffset>0xE18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0SREQSTATUS</name>
|
|
<description>Channel 0 Single Request Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1SREQSTATUS</name>
|
|
<description>Channel 1 Single Request Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2SREQSTATUS</name>
|
|
<description>Channel 2 Single Request Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3SREQSTATUS</name>
|
|
<description>Channel 3 Single Request Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4SREQSTATUS</name>
|
|
<description>Channel 4 Single Request Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5SREQSTATUS</name>
|
|
<description>Channel 5 Single Request Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6SREQSTATUS</name>
|
|
<description>Channel 6 Single Request Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7SREQSTATUS</name>
|
|
<description>Channel 7 Single Request Status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8SREQSTATUS</name>
|
|
<description>Channel 8 Single Request Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9SREQSTATUS</name>
|
|
<description>Channel 9 Single Request Status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10SREQSTATUS</name>
|
|
<description>Channel 10 Single Request Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11SREQSTATUS</name>
|
|
<description>Channel 11 Single Request Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x80000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0DONE</name>
|
|
<description>DMA Channel 0 Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1DONE</name>
|
|
<description>DMA Channel 1 Complete Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2DONE</name>
|
|
<description>DMA Channel 2 Complete Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3DONE</name>
|
|
<description>DMA Channel 3 Complete Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4DONE</name>
|
|
<description>DMA Channel 4 Complete Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5DONE</name>
|
|
<description>DMA Channel 5 Complete Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6DONE</name>
|
|
<description>DMA Channel 6 Complete Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7DONE</name>
|
|
<description>DMA Channel 7 Complete Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8DONE</name>
|
|
<description>DMA Channel 8 Complete Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9DONE</name>
|
|
<description>DMA Channel 9 Complete Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10DONE</name>
|
|
<description>DMA Channel 10 Complete Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11DONE</name>
|
|
<description>DMA Channel 11 Complete Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>DMA Error Interrupt Flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x80000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0DONE</name>
|
|
<description>DMA Channel 0 Complete Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1DONE</name>
|
|
<description>DMA Channel 1 Complete Interrupt Flag Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2DONE</name>
|
|
<description>DMA Channel 2 Complete Interrupt Flag Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3DONE</name>
|
|
<description>DMA Channel 3 Complete Interrupt Flag Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4DONE</name>
|
|
<description>DMA Channel 4 Complete Interrupt Flag Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5DONE</name>
|
|
<description>DMA Channel 5 Complete Interrupt Flag Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6DONE</name>
|
|
<description>DMA Channel 6 Complete Interrupt Flag Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7DONE</name>
|
|
<description>DMA Channel 7 Complete Interrupt Flag Set</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8DONE</name>
|
|
<description>DMA Channel 8 Complete Interrupt Flag Set</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9DONE</name>
|
|
<description>DMA Channel 9 Complete Interrupt Flag Set</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10DONE</name>
|
|
<description>DMA Channel 10 Complete Interrupt Flag Set</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11DONE</name>
|
|
<description>DMA Channel 11 Complete Interrupt Flag Set</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>DMA Error Interrupt Flag Set</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x80000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0DONE</name>
|
|
<description>DMA Channel 0 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1DONE</name>
|
|
<description>DMA Channel 1 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2DONE</name>
|
|
<description>DMA Channel 2 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3DONE</name>
|
|
<description>DMA Channel 3 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4DONE</name>
|
|
<description>DMA Channel 4 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5DONE</name>
|
|
<description>DMA Channel 5 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6DONE</name>
|
|
<description>DMA Channel 6 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7DONE</name>
|
|
<description>DMA Channel 7 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8DONE</name>
|
|
<description>DMA Channel 8 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9DONE</name>
|
|
<description>DMA Channel 9 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10DONE</name>
|
|
<description>DMA Channel 10 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11DONE</name>
|
|
<description>DMA Channel 11 Complete Interrupt Flag Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>DMA Error Interrupt Flag Clear</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable register</description>
|
|
<addressOffset>0x100C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x80000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0DONE</name>
|
|
<description>DMA Channel 0 Complete Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1DONE</name>
|
|
<description>DMA Channel 1 Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2DONE</name>
|
|
<description>DMA Channel 2 Complete Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3DONE</name>
|
|
<description>DMA Channel 3 Complete Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4DONE</name>
|
|
<description>DMA Channel 4 Complete Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5DONE</name>
|
|
<description>DMA Channel 5 Complete Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6DONE</name>
|
|
<description>DMA Channel 6 Complete Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7DONE</name>
|
|
<description>DMA Channel 7 Complete Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8DONE</name>
|
|
<description>DMA Channel 8 Complete Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9DONE</name>
|
|
<description>DMA Channel 9 Complete Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10DONE</name>
|
|
<description>DMA Channel 10 Complete Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11DONE</name>
|
|
<description>DMA Channel 11 Complete Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>DMA Error Interrupt Flag Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>DMA Control Register</description>
|
|
<addressOffset>0x1010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DESCRECT</name>
|
|
<description>Descriptor Specifies Rectangle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRDU</name>
|
|
<description>Prevent Rect Descriptor Update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDS</name>
|
|
<description>DMA Retain Descriptor State</description>
|
|
<addressOffset>0x1014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDSCH0</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDSCH1</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDSCH2</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDSCH3</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDSCH4</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDSCH5</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDSCH6</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDSCH7</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDSCH8</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDSCH9</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDSCH10</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDSCH11</name>
|
|
<description>Retain Descriptor State</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOOP0</name>
|
|
<description>Channel 0 Loop Register</description>
|
|
<addressOffset>0x1020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000103FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WIDTH</name>
|
|
<description>Loop Width</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>DMA Channel 0 Loop Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOOP1</name>
|
|
<description>Channel 1 Loop Register</description>
|
|
<addressOffset>0x1024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000103FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WIDTH</name>
|
|
<description>DMA Channel 1 Loop Width</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>DMA Channel 1 Loop Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RECT0</name>
|
|
<description>Channel 0 Rectangle Register</description>
|
|
<addressOffset>0x1060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HEIGHT</name>
|
|
<description>DMA Channel 0 Rectangle Height</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SRCSTRIDE</name>
|
|
<description>DMA Channel 0 Source Stride</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DSTSTRIDE</name>
|
|
<description>DMA Channel 0 Destination Stride</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x1100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x1104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x1108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x110C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH4_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x1110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH5_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x1114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH6_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x1118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH7_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x111C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH8_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x1120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH9_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x1124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH10_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x1128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH11_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x112C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C0</name>
|
|
<description>I2C 0</description>
|
|
<value>0x00000014</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2C1</name>
|
|
<description>I2C 1</description>
|
|
<value>0x00000015</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x00000018</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x00000019</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSC</name>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000032</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AES</name>
|
|
<description>AES</description>
|
|
<baseAddress>0x400E0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>AES</name>
|
|
<value>36</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000077</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DECRYPT</name>
|
|
<description>Decryption/Encryption Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AES256</name>
|
|
<description>AES-256 Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>KEYBUFEN</name>
|
|
<description>Key Buffer Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATASTART</name>
|
|
<description>AES_DATA Write Start</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XORSTART</name>
|
|
<description>AES_XORDATA Write Start</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYTEORDER</name>
|
|
<description>Configure byte order in data and key registers</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Encryption/Decryption Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Encryption/Decryption Stop</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUNNING</name>
|
|
<description>AES Running</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Encryption/Decryption Done Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Encryption/Decryption Done Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Encryption/Decryption Done Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Encryption/Decryption Done Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>DATA Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data Access</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XORDATA</name>
|
|
<description>XORDATA Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>XORDATA</name>
|
|
<description>XOR Data Access</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYLA</name>
|
|
<description>KEY Low Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>KEYLA</name>
|
|
<description>Key Low Access A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYLB</name>
|
|
<description>KEY Low Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>KEYLB</name>
|
|
<description>Key Low Access B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYLC</name>
|
|
<description>KEY Low Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>KEYLC</name>
|
|
<description>Key Low Access C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYLD</name>
|
|
<description>KEY Low Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>KEYLD</name>
|
|
<description>Key Low Access D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYHA</name>
|
|
<description>KEY High Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>KEYHA</name>
|
|
<description>Key High Access A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYHB</name>
|
|
<description>KEY High Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>KEYHB</name>
|
|
<description>Key High Access B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYHC</name>
|
|
<description>KEY High Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>KEYHC</name>
|
|
<description>Key High Access C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYHD</name>
|
|
<description>KEY High Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>KEYHD</name>
|
|
<description>Key High Access D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB</name>
|
|
<description>USB</description>
|
|
<baseAddress>0x400C4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x3C000</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>System Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x03330003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VBUSENAP</name>
|
|
<description>VBUSEN Active Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMPUAP</name>
|
|
<description>DMPU Active Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VREGDIS</name>
|
|
<description>Voltage Regulator Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VREGOSEN</name>
|
|
<description>VREGO Sense Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIASPROGEM01</name>
|
|
<description>Regulator Bias Programming Value in EM0/1</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIASPROGEM23</name>
|
|
<description>Regulator Bias Programming Value in EM2/3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>System Status Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VREGOS</name>
|
|
<description>VREGO Sense Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VREGOSH</name>
|
|
<description>VREGO Sense High Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VREGOSL</name>
|
|
<description>VREGO Sense Low Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VREGOSH</name>
|
|
<description>Set VREGO Sense High Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VREGOSL</name>
|
|
<description>Set VREGO Sense Low Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VREGOSH</name>
|
|
<description>Clear VREGO Sense High Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VREGOSL</name>
|
|
<description>Clear VREGO Sense Low Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VREGOSH</name>
|
|
<description>VREGO Sense High Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VREGOSL</name>
|
|
<description>VREGO Sense Low Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PHYPEN</name>
|
|
<description>USB PHY Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VBUSENPEN</name>
|
|
<description>VBUSEN Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMPUPEN</name>
|
|
<description>DMPU Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GOTGCTL</name>
|
|
<description>OTG Control and Status Register</description>
|
|
<addressOffset>0x3C000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010000</resetValue>
|
|
<resetMask>0x001F0FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SESREQSCS</name>
|
|
<description>Session Request Success device only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SESREQ</name>
|
|
<description>Session Request device only</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VBVALIDOVEN</name>
|
|
<description>VBUS-Valid Override Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VBVALIDOVVAL</name>
|
|
<description>VBUS Valid Override Value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BVALIDOVEN</name>
|
|
<description>BValid Override Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BVALIDOVVAL</name>
|
|
<description>Bvalid Override Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AVALIDOVEN</name>
|
|
<description>AValid Override Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AVALIDOVVAL</name>
|
|
<description>Avalid Override Value</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSTNEGSCS</name>
|
|
<description>Host Negotiation Success device only</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HNPREQ</name>
|
|
<description>HNP Request device only</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSTSETHNPEN</name>
|
|
<description>Host Set HNP Enable host only</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVHNPEN</name>
|
|
<description>Device HNP Enabled device only</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CONIDSTS</name>
|
|
<description>Connector ID Status host and device</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DBNCTIME</name>
|
|
<description>Long/Short Debounce Time host only</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ASESVLD</name>
|
|
<description>A-Session Valid host only</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSESVLD</name>
|
|
<description>B-Session Valid device only</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OTGVER</name>
|
|
<description>OTG Version</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GOTGINT</name>
|
|
<description>OTG Interrupt Register</description>
|
|
<addressOffset>0x3C004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000E0304</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SESENDDET</name>
|
|
<description>Session End Detected host and device</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SESREQSUCSTSCHNG</name>
|
|
<description>Session Request Success Status Change host and device</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSTNEGSUCSTSCHNG</name>
|
|
<description>Host Negotiation Success Status Change host and device</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSTNEGDET</name>
|
|
<description>Host Negotiation Detected host and device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADEVTOUTCHG</name>
|
|
<description>A-Device Timeout Change host and device</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBNCEDONE</name>
|
|
<description>Debounce Done host only</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GAHBCFG</name>
|
|
<description>AHB Configuration Register</description>
|
|
<addressOffset>0x3C008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x006001BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GLBLINTRMSK</name>
|
|
<description>Global Interrupt Mask host and device</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HBSTLEN</name>
|
|
<description>Burst Length/Type host and device</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>Single transfer.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INCR</name>
|
|
<description>Incrementing burst of unspecified length.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INCR4</name>
|
|
<description>4-beat incrementing burst.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INCR8</name>
|
|
<description>8-beat incrementing burst.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INCR16</name>
|
|
<description>16-beat incrementing burst.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable host and device</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NPTXFEMPLVL</name>
|
|
<description>Non-Periodic TxFIFO Empty Level host and device</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXFEMPLVL</name>
|
|
<description>Periodic TxFIFO Empty Level host only</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REMMEMSUPP</name>
|
|
<description>Remote Memory Support</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NOTIALLDMAWRIT</name>
|
|
<description>Notify All DMA Writes</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GUSBCFG</name>
|
|
<description>USB Configuration Register</description>
|
|
<addressOffset>0x3C00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00001440</resetValue>
|
|
<resetMask>0xF0403F27</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOUTCAL</name>
|
|
<description>Timeout Calibration host and device</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSINTF</name>
|
|
<description>Full-Speed Serial Interface Select host and device</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SRPCAP</name>
|
|
<description>SRP-Capable host and device</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HNPCAP</name>
|
|
<description>HNP-Capable host and device</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBTRDTIM</name>
|
|
<description>USB Turnaround Time device only</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TERMSELDLPULSE</name>
|
|
<description>TermSel DLine Pulsing Selection device only</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXENDDELAY</name>
|
|
<description>Tx End Delay device only</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FORCEHSTMODE</name>
|
|
<description>Force Host Mode host and device</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FORCEDEVMODE</name>
|
|
<description>Force Device Mode host and device</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CORRUPTTXPKT</name>
|
|
<description>Corrupt Tx packet host and device</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRSTCTL</name>
|
|
<description>Reset Register</description>
|
|
<addressOffset>0x3C010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xC00007F5</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSFTRST</name>
|
|
<description>Core Soft Reset host and device</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMCNTRRST</name>
|
|
<description>Host Frame Counter Reset host only</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFFLSH</name>
|
|
<description>RxFIFO Flush host and device</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFFLSH</name>
|
|
<description>TxFIFO Flush host and device</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO Number host and device</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>F0</name>
|
|
<description>Host mode: Non-periodic TxFIFO flush. Device: Tx FIFO 0 flush</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F1</name>
|
|
<description>Host mode: Periodic TxFIFO flush. Device: TXFIFO 1 flush.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F2</name>
|
|
<description>Device mode: TXFIFO 2 flush.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F3</name>
|
|
<description>Device mode: TXFIFO 3 flush.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F4</name>
|
|
<description>Device mode: TXFIFO 4 flush.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F5</name>
|
|
<description>Device mode: TXFIFO 5 flush.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F6</name>
|
|
<description>Device mode: TXFIFO 6 flush.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Flush all the transmit FIFOs in device or host mode.</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAREQ</name>
|
|
<description>DMA Request Signal host and device</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBIDLE</name>
|
|
<description>AHB Master Idle host and device</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GINTSTS</name>
|
|
<description>Interrupt Register</description>
|
|
<addressOffset>0x3C014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x14000020</resetValue>
|
|
<resetMask>0xF7FCFCFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CURMOD</name>
|
|
<description>Current Mode of Operation host and device</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MODEMIS</name>
|
|
<description>Mode Mismatch Interrupt host and device</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTGINT</name>
|
|
<description>OTG Interrupt host and device</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start of Frame host and device</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFLVL</name>
|
|
<description>RxFIFO Non-Empty host and device</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NPTXFEMP</name>
|
|
<description>Non-Periodic TxFIFO Empty host only</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GINNAKEFF</name>
|
|
<description>Global IN Non-periodic NAK Effective device only</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GOUTNAKEFF</name>
|
|
<description>Global OUT NAK Effective device only</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERLYSUSP</name>
|
|
<description>Early Suspend device only</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBSUSP</name>
|
|
<description>USB Suspend device only</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBRST</name>
|
|
<description>USB Reset device only</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUMDONE</name>
|
|
<description>Enumeration Done device only</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISOOUTDROP</name>
|
|
<description>Isochronous OUT Packet Dropped Interrupt device only</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EOPF</name>
|
|
<description>End of Periodic Frame Interrupt</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPINT</name>
|
|
<description>IN Endpoints Interrupt device only</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OEPINT</name>
|
|
<description>OUT Endpoints Interrupt device only</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INCOMPISOIN</name>
|
|
<description>Incomplete Isochronous IN Transfer device only</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INCOMPLP</name>
|
|
<description>Incomplete Periodic Transfer host and device</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FETSUSP</name>
|
|
<description>Data Fetch Suspended device only</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESETDET</name>
|
|
<description>Reset detected Interrupt device only</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTINT</name>
|
|
<description>Host Port Interrupt host only</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HCHINT</name>
|
|
<description>Host Channels Interrupt host only</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXFEMP</name>
|
|
<description>Periodic TxFIFO Empty host only</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CONIDSTSCHNG</name>
|
|
<description>Connector ID Status Change host and device</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCONNINT</name>
|
|
<description>Disconnect Detected Interrupt host only</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SESSREQINT</name>
|
|
<description>Session Request/New Session Detected Interrupt host and device</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WKUPINT</name>
|
|
<description>Resume/Remote Wakeup Detected Interrupt host and device</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GINTMSK</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x3C018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xF7FCFCFE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODEMISMSK</name>
|
|
<description>Mode Mismatch Interrupt Mask host and device</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTGINTMSK</name>
|
|
<description>OTG Interrupt Mask host and device</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFMSK</name>
|
|
<description>Start of Frame Mask host and device</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFLVLMSK</name>
|
|
<description>Receive FIFO Non-Empty Mask host and device</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NPTXFEMPMSK</name>
|
|
<description>Non-Periodic TxFIFO Empty Mask host only</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GINNAKEFFMSK</name>
|
|
<description>Global Non-periodic IN NAK Effective Mask device only</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GOUTNAKEFFMSK</name>
|
|
<description>Global OUT NAK Effective Mask device only</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERLYSUSPMSK</name>
|
|
<description>Early Suspend Mask device only</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBSUSPMSK</name>
|
|
<description>USB Suspend Mask device only</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBRSTMSK</name>
|
|
<description>USB Reset Mask device only</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUMDONEMSK</name>
|
|
<description>Enumeration Done Mask device only</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISOOUTDROPMSK</name>
|
|
<description>Isochronous OUT Packet Dropped Interrupt Mask device only</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EOPFMSK</name>
|
|
<description>End of Periodic Frame Interrupt Mask device only</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPINTMSK</name>
|
|
<description>IN Endpoints Interrupt Mask device only</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OEPINTMSK</name>
|
|
<description>OUT Endpoints Interrupt Mask device only</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INCOMPISOINMSK</name>
|
|
<description>Incomplete Isochronous IN Transfer Mask device only</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INCOMPLPMSK</name>
|
|
<description>Incomplete Periodic Transfer Mask host and device</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FETSUSPMSK</name>
|
|
<description>Data Fetch Suspended Mask device only</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESETDETMSK</name>
|
|
<description>Reset detected Interrupt Mask device only</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTINTMSK</name>
|
|
<description>Host Port Interrupt Mask host only</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HCHINTMSK</name>
|
|
<description>Host Channels Interrupt Mask host only</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXFEMPMSK</name>
|
|
<description>Periodic TxFIFO Empty Mask host only</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CONIDSTSCHNGMSK</name>
|
|
<description>Connector ID Status Change Mask host and device</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCONNINTMSK</name>
|
|
<description>Disconnect Detected Interrupt Mask host and device</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SESSREQINTMSK</name>
|
|
<description>Session Request/New Session Detected Interrupt Mask host and device</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WKUPINTMSK</name>
|
|
<description>Resume/Remote Wakeup Detected Interrupt Mask host and device</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRXSTSR</name>
|
|
<description>Receive Status Debug Read Register</description>
|
|
<addressOffset>0x3C01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x01FFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHEPNUM</name>
|
|
<description>Channel Number host only / Endpoint Number device only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BCNT</name>
|
|
<description>Byte Count (host or device)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID (host or device)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKTSTS</name>
|
|
<description>Packet Status (host or device)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GOUTNAK</name>
|
|
<description>Device mode: Global OUT NAK (triggers an interrupt).</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKTRCV</name>
|
|
<description>Host mode: IN data packet received. Device mode: OUT data packet received.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XFERCOMPL</name>
|
|
<description>Host mode: IN transfer completed (triggers an interrupt). Device mode: OUT transfer completed (triggers an interrupt).</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETUPCOMPL</name>
|
|
<description>Device mode: SETUP transaction completed (triggers an interrupt).</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TGLERR</name>
|
|
<description>Host mode: Data toggle error (triggers an interrupt).</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETUPRCV</name>
|
|
<description>Device mode: SETUP data packet received.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHLT</name>
|
|
<description>Host mode: Channel halted (triggers an interrupt).</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FN</name>
|
|
<description>Frame Number device only</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRXSTSP</name>
|
|
<description>Receive Status Read and Pop Register</description>
|
|
<addressOffset>0x3C020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x01FFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHEPNUM</name>
|
|
<description>Channel Number host only / Endpoint Number device only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BCNT</name>
|
|
<description>Byte Count (host or device)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID (host or device)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKTSTS</name>
|
|
<description>Packet Status (host or device)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GOUTNAK</name>
|
|
<description>Device mode: Global OUT NAK (triggers an interrupt).</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKTRCV</name>
|
|
<description>Host mode: IN data packet received. Device mode: OUT data packet received.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XFERCOMPL</name>
|
|
<description>Host mode: IN transfer completed (triggers an interrupt). Device mode: OUT transfer completed (triggers an interrupt).</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETUPCOMPL</name>
|
|
<description>Device mode: SETUP transaction completed (triggers an interrupt).</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TGLERR</name>
|
|
<description>Host mode: Data toggle error (triggers an interrupt).</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETUPRCV</name>
|
|
<description>Device mode: SETUP data packet received.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHLT</name>
|
|
<description>Host mode: Channel halted (triggers an interrupt).</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FN</name>
|
|
<description>Frame Number device only</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRXFSIZ</name>
|
|
<description>Receive FIFO Size Register</description>
|
|
<addressOffset>0x3C024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<resetMask>0x000003FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFDEP</name>
|
|
<description>RxFIFO Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GNPTXFSIZ</name>
|
|
<description>Non-periodic Transmit FIFO Size Register</description>
|
|
<addressOffset>0x3C028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000200</resetValue>
|
|
<resetMask>0xFFFF03FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NPTXFSTADDR</name>
|
|
<description>Non-periodic Transmit RAM Start Address host only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NPTXFINEPTXF0DEP</name>
|
|
<description>Non-periodic TxFIFO Depth host only / IN Endpoint TxFIFO 0 Depth device only</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GNPTXSTS</name>
|
|
<description>Non-periodic Transmit FIFO/Queue Status Register</description>
|
|
<addressOffset>0x3C02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00080200</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NPTXFSPCAVAIL</name>
|
|
<description>Non-periodic TxFIFO Space Available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NPTXQSPCAVAIL</name>
|
|
<description>Non-periodic Transmit Request Queue Space Available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NPTXQTOP</name>
|
|
<description>Top of the Non-periodic Transmit Request Queue</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GDFIFOCFG</name>
|
|
<description>Global DFIFO Configuration Register</description>
|
|
<addressOffset>0x3C05C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01F20200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GDFIFOCFG</name>
|
|
<description>DFIFO Config</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPINFOBASEADDR</name>
|
|
<description>Endpoint Info Base Address</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPTXFSIZ</name>
|
|
<description>Host Periodic Transmit FIFO Size Register</description>
|
|
<addressOffset>0x3C100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000400</resetValue>
|
|
<resetMask>0x03FF07FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTXFSTADDR</name>
|
|
<description>Host Periodic TxFIFO Start Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXFSIZE</name>
|
|
<description>Host Periodic TxFIFO Depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPTXF1</name>
|
|
<description>Device IN Endpoint Transmit FIFO 1 Size Register</description>
|
|
<addressOffset>0x3C104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000400</resetValue>
|
|
<resetMask>0x03FF07FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INEPNTXFSTADDR</name>
|
|
<description>IN Endpoint FIFO 1 Transmit RAM Start Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNTXFDEP</name>
|
|
<description>IN Endpoint TxFIFO Depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPTXF2</name>
|
|
<description>Device IN Endpoint Transmit FIFO 2 Size Register</description>
|
|
<addressOffset>0x3C108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000600</resetValue>
|
|
<resetMask>0x03FF07FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INEPNTXFSTADDR</name>
|
|
<description>IN Endpoint FIFO 2 Transmit RAM Start Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNTXFDEP</name>
|
|
<description>IN Endpoint TxFIFO Depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPTXF3</name>
|
|
<description>Device IN Endpoint Transmit FIFO 3 Size Register</description>
|
|
<addressOffset>0x3C10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000800</resetValue>
|
|
<resetMask>0x03FF0FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INEPNTXFSTADDR</name>
|
|
<description>IN Endpoint FIFO 3 Transmit RAM Start Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNTXFDEP</name>
|
|
<description>IN Endpoint TxFIFO Depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPTXF4</name>
|
|
<description>Device IN Endpoint Transmit FIFO 4 Size Register</description>
|
|
<addressOffset>0x3C110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000A00</resetValue>
|
|
<resetMask>0x03FF0FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INEPNTXFSTADDR</name>
|
|
<description>IN Endpoint FIFO 4 Transmit RAM Start Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNTXFDEP</name>
|
|
<description>IN Endpoint TxFIFO Depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPTXF5</name>
|
|
<description>Device IN Endpoint Transmit FIFO 5 Size Register</description>
|
|
<addressOffset>0x3C114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000C00</resetValue>
|
|
<resetMask>0x03FF0FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INEPNTXFSTADDR</name>
|
|
<description>IN Endpoint FIFO 5 Transmit RAM Start Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNTXFDEP</name>
|
|
<description>IN Endpoint TxFIFO Depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPTXF6</name>
|
|
<description>Device IN Endpoint Transmit FIFO 6 Size Register</description>
|
|
<addressOffset>0x3C118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000E00</resetValue>
|
|
<resetMask>0x03FF0FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INEPNTXFSTADDR</name>
|
|
<description>IN Endpoint FIFO 6 Transmit RAM Start Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNTXFDEP</name>
|
|
<description>IN Endpoint TxFIFO Depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCFG</name>
|
|
<description>Host Configuration Register</description>
|
|
<addressOffset>0x3C400</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00200000</resetValue>
|
|
<resetMask>0x8000FF87</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FSLSPCLKSEL</name>
|
|
<description>FS/LS PHY Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Internal PHY clock is running at 48 MHz (undivided).</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Internal PHY clock is running at 6 MHz (48 MHz divided by 8).</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSLSSUPP</name>
|
|
<description>FS- and LS-Only Support</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENA32KHZS</name>
|
|
<description>Enable 32 KHz Suspend mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESVALID</name>
|
|
<description>Resume Validation Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODECHTIMEN</name>
|
|
<description>Mode Change Time</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFIR</name>
|
|
<description>Host Frame Interval Register</description>
|
|
<addressOffset>0x3C404</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000017D7</resetValue>
|
|
<resetMask>0x0001FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRINT</name>
|
|
<description>Frame Interval</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HFIRRLDCTRL</name>
|
|
<description>Reload Control</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFNUM</name>
|
|
<description>Host Frame Number/Frame Time Remaining Register</description>
|
|
<addressOffset>0x3C408</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00003FFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRNUM</name>
|
|
<description>Frame Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRREM</name>
|
|
<description>Frame Time Remaining</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPTXSTS</name>
|
|
<description>Host Periodic Transmit FIFO/Queue Status Register</description>
|
|
<addressOffset>0x3C410</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00080200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTXFSPCAVAIL</name>
|
|
<description>Periodic Transmit Data FIFO Space Available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXQSPCAVAIL</name>
|
|
<description>Periodic Transmit Request Queue Space Available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXQTOP</name>
|
|
<description>Top of the Periodic Transmit Request Queue</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HAINT</name>
|
|
<description>Host All Channels Interrupt Register</description>
|
|
<addressOffset>0x3C414</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00003FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HAINT</name>
|
|
<description>Channel Interrupt for channel 0 - 13.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HAINTMSK</name>
|
|
<description>Host All Channels Interrupt Mask Register</description>
|
|
<addressOffset>0x3C418</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00003FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HAINTMSK</name>
|
|
<description>Channel Interrupt Mask for channel 0 - 13</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPRT</name>
|
|
<description>Host Port Control and Status Register</description>
|
|
<addressOffset>0x3C440</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0007FDFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRTCONNSTS</name>
|
|
<description>Port Connect Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTCONNDET</name>
|
|
<description>Port Connect Detected</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTENA</name>
|
|
<description>Port Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTENCHNG</name>
|
|
<description>Port Enable/Disable Change</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTOVRCURRACT</name>
|
|
<description>Port Overcurrent Active</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTOVRCURRCHNG</name>
|
|
<description>Port Overcurrent Change</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTRES</name>
|
|
<description>Port Resume</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTSUSP</name>
|
|
<description>Port Suspend</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTRST</name>
|
|
<description>Port Reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTLNSTS</name>
|
|
<description>Port Line Status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTPWR</name>
|
|
<description>Port Power</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRTTSTCTL</name>
|
|
<description>Port Test Control</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Test mode disabled.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>J</name>
|
|
<description>Test_J mode.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>K</name>
|
|
<description>Test_K mode.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE0NAK</name>
|
|
<description>Test_SE0_NAK mode.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PACKET</name>
|
|
<description>Test_Packet mode.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE</name>
|
|
<description>Test_Force_Enable.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRTSPD</name>
|
|
<description>Port Speed</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HS</name>
|
|
<description>High speed.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FS</name>
|
|
<description>Full speed.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LS</name>
|
|
<description>Low speed.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC0_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C500</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC0_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C508</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC0_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C50C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC0_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C510</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC0_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C514</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC1_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C520</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC1_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C528</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC1_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C52C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC1_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C530</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC1_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C534</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC2_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C540</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC2_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C548</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC2_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C54C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC2_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C550</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC2_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C554</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC3_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C560</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC3_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C568</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC3_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C56C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC3_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C570</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC3_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C574</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC4_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C580</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC4_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C588</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC4_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C58C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC4_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C590</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC4_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C594</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC5_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C5A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC5_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C5A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC5_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C5AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC5_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C5B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC5_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C5B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC6_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C5C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC6_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C5C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC6_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C5CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC6_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C5D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC6_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C5D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC7_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C5E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC7_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C5E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC7_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C5EC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC7_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C5F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC7_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C5F4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC8_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C600</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC8_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C608</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC8_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C60C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC8_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C610</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC8_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C614</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC9_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C620</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC9_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C628</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC9_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C62C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC9_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C630</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC9_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C634</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC10_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C640</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC10_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C648</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC10_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C64C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC10_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C650</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC10_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C654</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC11_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C660</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC11_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C668</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC11_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C66C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC11_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C670</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC11_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C674</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC12_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C680</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC12_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C688</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC12_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C68C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC12_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C690</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC12_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C694</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC13_CHAR</name>
|
|
<description>Host Channel x Characteristics Register</description>
|
|
<addressOffset>0x3C6A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFEFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint Number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint Direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSPDDEV</name>
|
|
<description>Low-Speed Device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHDIS</name>
|
|
<description>Channel Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHENA</name>
|
|
<description>Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC13_INT</name>
|
|
<description>Host Channel x Interrupt Register</description>
|
|
<addressOffset>0x3C6A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTD</name>
|
|
<description>Channel Halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Response Received Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK Response Received Interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERR</name>
|
|
<description>Transaction Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUN</name>
|
|
<description>Frame Overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERR</name>
|
|
<description>Data Toggle Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC13_INTMSK</name>
|
|
<description>Host Channel x Interrupt Mask Register</description>
|
|
<addressOffset>0x3C6AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007BF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHHLTDMSK</name>
|
|
<description>Channel Halted Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALLMSK</name>
|
|
<description>STALL Response Received Interrupt Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK Response Received Interrupt Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACKMSK</name>
|
|
<description>ACK Response Received/Transmitted Interrupt Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XACTERRMSK</name>
|
|
<description>Transaction Error Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLERRMSK</name>
|
|
<description>Babble Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRMOVRUNMSK</name>
|
|
<description>Frame Overrun Mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATATGLERRMSK</name>
|
|
<description>Data Toggle Error Mask</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC13_TSIZ</name>
|
|
<description>Host Channel x Transfer Size Register</description>
|
|
<addressOffset>0x3C6B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Packet ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA (non-control) / SETUP (control) PID.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HC13_DMAADDR</name>
|
|
<description>Host Channel x DMA Address Register</description>
|
|
<addressOffset>0x3C6B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCFG</name>
|
|
<description>Device Configuration Register</description>
|
|
<addressOffset>0x3C800</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x08200000</resetValue>
|
|
<resetMask>0xFC001FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVSPD</name>
|
|
<description>Device Speed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LS</name>
|
|
<description>Low speed (PHY clock is 6 MHz). If you select 6 MHz LS mode, you must do a soft reset.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FS</name>
|
|
<description>Full speed (PHY clock is 48 MHz).</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NZSTSOUTHSHK</name>
|
|
<description>Non-Zero-Length Status OUT Handshake</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENA32KHZSUSP</name>
|
|
<description>Enable 32 KHz Suspend mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVADDR</name>
|
|
<description>Device Address</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERFRINT</name>
|
|
<description>Periodic Frame Interval</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>80PCNT</name>
|
|
<description>80% of the frame interval.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>85PCNT</name>
|
|
<description>85% of the frame interval.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>90PCNT</name>
|
|
<description>90% of the frame interval.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>95PCNT</name>
|
|
<description>95% of the frame interval.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESVALID</name>
|
|
<description>Resume Validation Period</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCTL</name>
|
|
<description>Device Control Register</description>
|
|
<addressOffset>0x3C804</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00018FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RMTWKUPSIG</name>
|
|
<description>Remote Wakeup Signaling</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFTDISCON</name>
|
|
<description>Soft Disconnect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GNPINNAKSTS</name>
|
|
<description>Global Non-periodic IN NAK Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GOUTNAKSTS</name>
|
|
<description>Global OUT NAK Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TSTCTL</name>
|
|
<description>Test Control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Test mode disabled.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>J</name>
|
|
<description>Test_J mode.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>K</name>
|
|
<description>Test_K mode.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE0NAK</name>
|
|
<description>Test_SE0_NAK mode.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PACKET</name>
|
|
<description>Test_Packet mode.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE</name>
|
|
<description>Test_Force_Enable.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SGNPINNAK</name>
|
|
<description>Set Global Non-periodic IN NAK</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CGNPINNAK</name>
|
|
<description>Clear Global Non-periodic IN NAK</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SGOUTNAK</name>
|
|
<description>Set Global OUT NAK</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CGOUTNAK</name>
|
|
<description>Clear Global OUT NAK</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWRONPRGDONE</name>
|
|
<description>Power-On Programming Done</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IGNRFRMNUM</name>
|
|
<description>Ignore Frame number For Isochronous End points</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKONBBLE</name>
|
|
<description>NAK on Babble Error</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSTS</name>
|
|
<description>Device Status Register</description>
|
|
<addressOffset>0x3C808</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x003FFF0F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SUSPSTS</name>
|
|
<description>Suspend Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUMSPD</name>
|
|
<description>Enumerated Speed</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LS</name>
|
|
<description>Low speed (PHY clock is running at 6 MHz).</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FS</name>
|
|
<description>Full speed (PHY clock is running at 48 MHz).</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERRTICERR</name>
|
|
<description>Erratic Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFFN</name>
|
|
<description>Frame Number of the Received SOF</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPMSK</name>
|
|
<description>Device IN Endpoint Common Interrupt Mask Register</description>
|
|
<addressOffset>0x3C810</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000215F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLDMSK</name>
|
|
<description>Endpoint Disabled Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUTMSK</name>
|
|
<description>Timeout Condition Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTKNTXFEMPMSK</name>
|
|
<description>IN Token Received When TxFIFO Empty Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNAKEFFMSK</name>
|
|
<description>IN Endpoint NAK Effective Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOUNDRNMSK</name>
|
|
<description>Fifo Underrun Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK interrupt Mask</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEPMSK</name>
|
|
<description>Device OUT Endpoint Common Interrupt Mask Register</description>
|
|
<addressOffset>0x3C814</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000315F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPLMSK</name>
|
|
<description>Transfer Completed Interrupt Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLDMSK</name>
|
|
<description>Endpoint Disabled Interrupt Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERRMSK</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETUPMSK</name>
|
|
<description>SETUP Phase Done Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTTKNEPDISMSK</name>
|
|
<description>OUT Token Received when Endpoint Disabled Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BACK2BACKSETUP</name>
|
|
<description>Back-to-Back SETUP Packets Received Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPKTERRMSK</name>
|
|
<description>OUT Packet Error Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERRMSK</name>
|
|
<description>Babble Error interrupt Mask</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKMSK</name>
|
|
<description>NAK interrupt Mask</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAINT</name>
|
|
<description>Device All Endpoints Interrupt Register</description>
|
|
<addressOffset>0x3C818</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x007F007F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INEPINT0</name>
|
|
<description>IN Endpoint 0 Interrupt Bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPINT1</name>
|
|
<description>IN Endpoint 1 Interrupt Bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPINT2</name>
|
|
<description>IN Endpoint 2 Interrupt Bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPINT3</name>
|
|
<description>IN Endpoint 3 Interrupt Bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPINT4</name>
|
|
<description>IN Endpoint 4 Interrupt Bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPINT5</name>
|
|
<description>IN Endpoint 5 Interrupt Bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPINT6</name>
|
|
<description>IN Endpoint 6 Interrupt Bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPINT0</name>
|
|
<description>OUT Endpoint 0 Interrupt Bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPINT1</name>
|
|
<description>OUT Endpoint 1 Interrupt Bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPINT2</name>
|
|
<description>OUT Endpoint 2 Interrupt Bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPINT3</name>
|
|
<description>OUT Endpoint 3 Interrupt Bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPINT4</name>
|
|
<description>OUT Endpoint 4 Interrupt Bit</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPINT5</name>
|
|
<description>OUT Endpoint 5 Interrupt Bit</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPINT6</name>
|
|
<description>OUT Endpoint 6 Interrupt Bit</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAINTMSK</name>
|
|
<description>Device All Endpoints Interrupt Mask Register</description>
|
|
<addressOffset>0x3C81C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x007F007F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INEPMSK0</name>
|
|
<description>IN Endpoint 0 Interrupt mask Bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPMSK1</name>
|
|
<description>IN Endpoint 1 Interrupt mask Bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPMSK2</name>
|
|
<description>IN Endpoint 2 Interrupt mask Bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPMSK3</name>
|
|
<description>IN Endpoint 3 Interrupt mask Bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPMSK4</name>
|
|
<description>IN Endpoint 4 Interrupt mask Bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPMSK5</name>
|
|
<description>IN Endpoint 5 Interrupt mask Bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPMSK6</name>
|
|
<description>IN Endpoint 6 Interrupt mask Bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPMSK0</name>
|
|
<description>OUT Endpoint 0 Interrupt mask Bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPMSK1</name>
|
|
<description>OUT Endpoint 1 Interrupt mask Bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPMSK2</name>
|
|
<description>OUT Endpoint 2 Interrupt mask Bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPMSK3</name>
|
|
<description>OUT Endpoint 3 Interrupt mask Bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPMSK4</name>
|
|
<description>OUT Endpoint 4 Interrupt mask Bit</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPMSK5</name>
|
|
<description>OUT Endpoint 5 Interrupt mask Bit</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTEPMSK6</name>
|
|
<description>OUT Endpoint 6 Interrupt mask Bit</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DVBUSDIS</name>
|
|
<description>Device VBUS Discharge Time Register</description>
|
|
<addressOffset>0x3C828</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000017D7</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DVBUSDIS</name>
|
|
<description>Device VBUS Discharge Time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DVBUSPULSE</name>
|
|
<description>Device VBUS Pulsing Time Register</description>
|
|
<addressOffset>0x3C82C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000005B8</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DVBUSPULSE</name>
|
|
<description>Device VBUS Pulsing Time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPEMPMSK</name>
|
|
<description>Device IN Endpoint FIFO Empty Interrupt Mask Register</description>
|
|
<addressOffset>0x3C834</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIEPEMPMSK</name>
|
|
<description>IN EP Tx FIFO Empty Interrupt Mask Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0CTL</name>
|
|
<description>Device IN Endpoint 0 Control Register</description>
|
|
<addressOffset>0x3C900</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00008000</resetValue>
|
|
<resetMask>0xCFEE8003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64B</name>
|
|
<description>64 bytes.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32B</name>
|
|
<description>32 bytes.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16B</name>
|
|
<description>16 bytes.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8B</name>
|
|
<description>8 bytes.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO Number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0INT</name>
|
|
<description>Device IN Endpoint 0 Interrupt Register</description>
|
|
<addressOffset>0x3C908</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0x000038DF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Timeout Condition</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTKNTXFEMP</name>
|
|
<description>IN Token Received When TxFIFO is Empty</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNAKEFF</name>
|
|
<description>IN Endpoint NAK Effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFEMP</name>
|
|
<description>Transmit FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0TSIZ</name>
|
|
<description>Device IN Endpoint 0 Transfer Size Register</description>
|
|
<addressOffset>0x3C910</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0018007F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0DMAADDR</name>
|
|
<description>Device IN Endpoint 0 DMA Address Register</description>
|
|
<addressOffset>0x3C914</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIEP0DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0TXFSTS</name>
|
|
<description>Device IN Endpoint 0 Transmit FIFO Status Register</description>
|
|
<addressOffset>0x3C918</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPCAVAIL</name>
|
|
<description>TxFIFO Space Available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0_CTL</name>
|
|
<description>Device IN Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3C920</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFEF87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even or Odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO Number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0_INT</name>
|
|
<description>Device IN Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3C928</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0x000038DF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Timeout Condition</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTKNTXFEMP</name>
|
|
<description>IN Token Received When TxFIFO is Empty</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNAKEFF</name>
|
|
<description>IN Endpoint NAK Effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFEMP</name>
|
|
<description>Transmit FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0_TSIZ</name>
|
|
<description>Device IN Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3C930</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0_DMAADDR</name>
|
|
<description>Device IN Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3C934</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0_TXFSTS</name>
|
|
<description>Device IN Endpoint x+1 Transmit FIFO Status Register</description>
|
|
<addressOffset>0x3C938</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPCAVAIL</name>
|
|
<description>TxFIFO Space Available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1_CTL</name>
|
|
<description>Device IN Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3C940</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFEF87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even or Odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO Number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1_INT</name>
|
|
<description>Device IN Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3C948</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0x000038DF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Timeout Condition</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTKNTXFEMP</name>
|
|
<description>IN Token Received When TxFIFO is Empty</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNAKEFF</name>
|
|
<description>IN Endpoint NAK Effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFEMP</name>
|
|
<description>Transmit FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1_TSIZ</name>
|
|
<description>Device IN Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3C950</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1_DMAADDR</name>
|
|
<description>Device IN Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3C954</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1_TXFSTS</name>
|
|
<description>Device IN Endpoint x+1 Transmit FIFO Status Register</description>
|
|
<addressOffset>0x3C958</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPCAVAIL</name>
|
|
<description>TxFIFO Space Available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2_CTL</name>
|
|
<description>Device IN Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3C960</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFEF87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even or Odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO Number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2_INT</name>
|
|
<description>Device IN Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3C968</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0x000038DF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Timeout Condition</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTKNTXFEMP</name>
|
|
<description>IN Token Received When TxFIFO is Empty</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNAKEFF</name>
|
|
<description>IN Endpoint NAK Effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFEMP</name>
|
|
<description>Transmit FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2_TSIZ</name>
|
|
<description>Device IN Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3C970</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2_DMAADDR</name>
|
|
<description>Device IN Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3C974</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2_TXFSTS</name>
|
|
<description>Device IN Endpoint x+1 Transmit FIFO Status Register</description>
|
|
<addressOffset>0x3C978</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPCAVAIL</name>
|
|
<description>TxFIFO Space Available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3_CTL</name>
|
|
<description>Device IN Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3C980</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFEF87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even or Odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO Number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3_INT</name>
|
|
<description>Device IN Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3C988</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0x000038DF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Timeout Condition</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTKNTXFEMP</name>
|
|
<description>IN Token Received When TxFIFO is Empty</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNAKEFF</name>
|
|
<description>IN Endpoint NAK Effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFEMP</name>
|
|
<description>Transmit FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3_TSIZ</name>
|
|
<description>Device IN Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3C990</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3_DMAADDR</name>
|
|
<description>Device IN Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3C994</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3_TXFSTS</name>
|
|
<description>Device IN Endpoint x+1 Transmit FIFO Status Register</description>
|
|
<addressOffset>0x3C998</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPCAVAIL</name>
|
|
<description>TxFIFO Space Available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP4_CTL</name>
|
|
<description>Device IN Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3C9A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFEF87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even or Odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO Number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP4_INT</name>
|
|
<description>Device IN Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3C9A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0x000038DF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Timeout Condition</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTKNTXFEMP</name>
|
|
<description>IN Token Received When TxFIFO is Empty</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNAKEFF</name>
|
|
<description>IN Endpoint NAK Effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFEMP</name>
|
|
<description>Transmit FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP4_TSIZ</name>
|
|
<description>Device IN Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3C9B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP4_DMAADDR</name>
|
|
<description>Device IN Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3C9B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP4_TXFSTS</name>
|
|
<description>Device IN Endpoint x+1 Transmit FIFO Status Register</description>
|
|
<addressOffset>0x3C9B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPCAVAIL</name>
|
|
<description>TxFIFO Space Available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP5_CTL</name>
|
|
<description>Device IN Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3C9C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFEF87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even or Odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO Number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP5_INT</name>
|
|
<description>Device IN Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3C9C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0x000038DF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Timeout Condition</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTKNTXFEMP</name>
|
|
<description>IN Token Received When TxFIFO is Empty</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEPNAKEFF</name>
|
|
<description>IN Endpoint NAK Effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFEMP</name>
|
|
<description>Transmit FIFO Empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP5_TSIZ</name>
|
|
<description>Device IN Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3C9D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MC</name>
|
|
<description>Multi Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP5_DMAADDR</name>
|
|
<description>Device IN Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3C9D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP5_TXFSTS</name>
|
|
<description>Device IN Endpoint x+1 Transmit FIFO Status Register</description>
|
|
<addressOffset>0x3C9D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPCAVAIL</name>
|
|
<description>TxFIFO Space Available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0CTL</name>
|
|
<description>Device OUT Endpoint 0 Control Register</description>
|
|
<addressOffset>0x3CB00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00008000</resetValue>
|
|
<resetMask>0xCC3E8003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64B</name>
|
|
<description>64 bytes.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32B</name>
|
|
<description>32 bytes.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16B</name>
|
|
<description>16 bytes.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8B</name>
|
|
<description>8 bytes.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNP</name>
|
|
<description>Snoop Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0INT</name>
|
|
<description>Device OUT Endpoint 0 Interrupt Register</description>
|
|
<addressOffset>0x3CB08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000385F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Setup Phase Done</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTTKNEPDIS</name>
|
|
<description>OUT Token Received When Endpoint Disabled</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BACK2BACKSETUP</name>
|
|
<description>Back-to-Back SETUP Packets Received</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0TSIZ</name>
|
|
<description>Device OUT Endpoint 0 Transfer Size Register</description>
|
|
<addressOffset>0x3CB10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x6008007F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SUPCNT</name>
|
|
<description>SETUP Packet Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0DMAADDR</name>
|
|
<description>Device OUT Endpoint 0 DMA Address Register</description>
|
|
<addressOffset>0x3CB14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOEP0DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0_CTL</name>
|
|
<description>Device OUT Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3CB20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFC3F87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even-odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNP</name>
|
|
<description>Snoop Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0_INT</name>
|
|
<description>Device OUT Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3CB28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000385F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Setup Phase Done</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTTKNEPDIS</name>
|
|
<description>OUT Token Received When Endpoint Disabled</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BACK2BACKSETUP</name>
|
|
<description>Back-to-Back SETUP Packets Received</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0_TSIZ</name>
|
|
<description>Device OUT Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3CB30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDPIDSUPCNT</name>
|
|
<description>Receive Data PID / SETUP Packet Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID / 1 Packet.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID / 2 Packets.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA PID / 3 Packets.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0_DMAADDR</name>
|
|
<description>Device OUT Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3CB34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1_CTL</name>
|
|
<description>Device OUT Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3CB40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFC3F87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even-odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNP</name>
|
|
<description>Snoop Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1_INT</name>
|
|
<description>Device OUT Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3CB48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000385F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Setup Phase Done</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTTKNEPDIS</name>
|
|
<description>OUT Token Received When Endpoint Disabled</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BACK2BACKSETUP</name>
|
|
<description>Back-to-Back SETUP Packets Received</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1_TSIZ</name>
|
|
<description>Device OUT Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3CB50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDPIDSUPCNT</name>
|
|
<description>Receive Data PID / SETUP Packet Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID / 1 Packet.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID / 2 Packets.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA PID / 3 Packets.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1_DMAADDR</name>
|
|
<description>Device OUT Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3CB54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP2_CTL</name>
|
|
<description>Device OUT Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3CB60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFC3F87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even-odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNP</name>
|
|
<description>Snoop Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP2_INT</name>
|
|
<description>Device OUT Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3CB68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000385F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Setup Phase Done</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTTKNEPDIS</name>
|
|
<description>OUT Token Received When Endpoint Disabled</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BACK2BACKSETUP</name>
|
|
<description>Back-to-Back SETUP Packets Received</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP2_TSIZ</name>
|
|
<description>Device OUT Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3CB70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDPIDSUPCNT</name>
|
|
<description>Receive Data PID / SETUP Packet Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID / 1 Packet.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID / 2 Packets.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA PID / 3 Packets.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP2_DMAADDR</name>
|
|
<description>Device OUT Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3CB74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP3_CTL</name>
|
|
<description>Device OUT Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3CB80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFC3F87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even-odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNP</name>
|
|
<description>Snoop Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP3_INT</name>
|
|
<description>Device OUT Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3CB88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000385F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Setup Phase Done</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTTKNEPDIS</name>
|
|
<description>OUT Token Received When Endpoint Disabled</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BACK2BACKSETUP</name>
|
|
<description>Back-to-Back SETUP Packets Received</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP3_TSIZ</name>
|
|
<description>Device OUT Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3CB90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDPIDSUPCNT</name>
|
|
<description>Receive Data PID / SETUP Packet Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID / 1 Packet.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID / 2 Packets.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA PID / 3 Packets.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP3_DMAADDR</name>
|
|
<description>Device OUT Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3CB94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP4_CTL</name>
|
|
<description>Device OUT Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3CBA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFC3F87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even-odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNP</name>
|
|
<description>Snoop Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP4_INT</name>
|
|
<description>Device OUT Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3CBA8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000385F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Setup Phase Done</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTTKNEPDIS</name>
|
|
<description>OUT Token Received When Endpoint Disabled</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BACK2BACKSETUP</name>
|
|
<description>Back-to-Back SETUP Packets Received</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP4_TSIZ</name>
|
|
<description>Device OUT Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3CBB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDPIDSUPCNT</name>
|
|
<description>Receive Data PID / SETUP Packet Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID / 1 Packet.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID / 2 Packets.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA PID / 3 Packets.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP4_DMAADDR</name>
|
|
<description>Device OUT Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3CBB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP5_CTL</name>
|
|
<description>Device OUT Endpoint x+1 Control Register</description>
|
|
<addressOffset>0x3CBC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFC3F87FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPS</name>
|
|
<description>Maximum Packet Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBACTEP</name>
|
|
<description>USB Active Endpoint</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIDEOF</name>
|
|
<description>Endpoint Data PID / Even-odd Frame</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKSTS</name>
|
|
<description>NAK Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control Endpoint.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISO</name>
|
|
<description>Isochronous Endpoint.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk Endpoint.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT</name>
|
|
<description>Interrupt Endpoint.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SNP</name>
|
|
<description>Snoop Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL Handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD0PIDEF</name>
|
|
<description>Set DATA0 PID / Even Frame</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SETD1PIDOF</name>
|
|
<description>Set DATA1 PID / Odd Frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPENA</name>
|
|
<description>Endpoint Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP5_INT</name>
|
|
<description>Device OUT Endpoint x+1 Interrupt Register</description>
|
|
<addressOffset>0x3CBC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000385F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERCOMPL</name>
|
|
<description>Transfer Completed Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDISBLD</name>
|
|
<description>Endpoint Disabled Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBERR</name>
|
|
<description>AHB Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>Setup Phase Done</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTTKNEPDIS</name>
|
|
<description>OUT Token Received When Endpoint Disabled</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BACK2BACKSETUP</name>
|
|
<description>Back-to-Back SETUP Packets Received</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTDRPSTS</name>
|
|
<description>Packet Drop Status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BBLEERR</name>
|
|
<description>Babble Error</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKINTRPT</name>
|
|
<description>NAK Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP5_TSIZ</name>
|
|
<description>Device OUT Endpoint x+1 Transfer Size Register</description>
|
|
<addressOffset>0x3CBD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XFERSIZE</name>
|
|
<description>Transfer Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PKTCNT</name>
|
|
<description>Packet Count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDPIDSUPCNT</name>
|
|
<description>Receive Data PID / SETUP Packet Count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATA0</name>
|
|
<description>DATA0 PID.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA2</name>
|
|
<description>DATA2 PID / 1 Packet.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA1</name>
|
|
<description>DATA1 PID / 2 Packets.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDATA</name>
|
|
<description>MDATA PID / 3 Packets.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP5_DMAADDR</name>
|
|
<description>Device OUT Endpoint x+1 DMA Address Register</description>
|
|
<addressOffset>0x3CBD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCGCCTL</name>
|
|
<description>Power and Clock Gating Control Register</description>
|
|
<addressOffset>0x3CE00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000014F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOPPCLK</name>
|
|
<description>Stop PHY clock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GATEHCLK</name>
|
|
<description>Gate HCLK</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWRCLMP</name>
|
|
<description>Power Clamp</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTPDWNMODULE</name>
|
|
<description>Reset Power-Down Modules</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PHYSLEEP</name>
|
|
<description>PHY In Sleep</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RESETAFTERSUSP</name>
|
|
<description>Reset after suspend</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MSC</name>
|
|
<description>MSC</description>
|
|
<baseAddress>0x400C0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>MSC</name>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Memory System Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSFAULT</name>
|
|
<description>Bus Fault Response Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>READCTRL</name>
|
|
<description>Read Control Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x000301FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Read Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WS0</name>
|
|
<description>Zero wait-states inserted in fetch or read transfers.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WS1</name>
|
|
<description>One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WS0SCBTP</name>
|
|
<description>Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch (SCBTP) function enabled. SCBTP saves energy by delaying the Cortex' conditional branch target prefetches until the conditional branch instruction is in the execute stage. When the instruction reaches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction fetch is saved for each branch not taken, with a negligible performance penalty.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WS1SCBTP</name>
|
|
<description>One wait-state access with SCBTP enabled.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WS2</name>
|
|
<description>Two wait-states inserted for each fetch or read transfer. This mode is required for a core frequency above 32 MHz.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WS2SCBTP</name>
|
|
<description>Two wait-state access with SCBTP enabled.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFCDIS</name>
|
|
<description>Internal Flash Cache Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AIDIS</name>
|
|
<description>Automatic Invalidate Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICCDIS</name>
|
|
<description>Interrupt Context Cache Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EBICDIS</name>
|
|
<description>External Bus Interface Cache Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RAMCEN</name>
|
|
<description>RAM Cache Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PREFETCH</name>
|
|
<description>Prefetch Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSSTRATEGY</name>
|
|
<description>Strategy for bus matrix</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CPU</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA</name>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAEM1</name>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRITECTRL</name>
|
|
<description>Write Control Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>Enable Write/Erase Controller </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRQERASEABORT</name>
|
|
<description>Abort Page Erase on Interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDOUBLE</name>
|
|
<description>Write two words at a time</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LPWRITE</name>
|
|
<description>Low-Power Erase</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LPERASE</name>
|
|
<description>Low-Power Erase</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RWWEN</name>
|
|
<description>Read-While-Write Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRITECMD</name>
|
|
<description>Write Command Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000133F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LADDRIM</name>
|
|
<description>Load MSC_ADDRB into ADDR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERASEPAGE</name>
|
|
<description>Erase Page</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WRITEEND</name>
|
|
<description>End Write Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WRITEONCE</name>
|
|
<description>Word Write-Once Trigger</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WRITETRIG</name>
|
|
<description>Word Write Sequence Trigger</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERASEABORT</name>
|
|
<description>Abort erase sequence</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERASEMAIN0</name>
|
|
<description>Mass erase region 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERASEMAIN1</name>
|
|
<description>Mass erase region 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARWDATA</name>
|
|
<description>Clear WDATA state</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDRB</name>
|
|
<description>Page Erase/Write Address Buffer</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRB</name>
|
|
<description>Page Erase or Write Address Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDATA</name>
|
|
<description>Write Data Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDATA</name>
|
|
<description>Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0x0000007F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Erase/Write Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKED</name>
|
|
<description>Access Locked</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INVADDR</name>
|
|
<description>Invalid Write Address or Erase Page</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WDATAREADY</name>
|
|
<description>WDATA Write Ready</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WORDTIMEOUT</name>
|
|
<description>Flash Write Word Timeout</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERASEABORTED</name>
|
|
<description>The Current Flash Erase Operation Aborted</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCRUNNING</name>
|
|
<description>Performance Counters Running</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERASE</name>
|
|
<description>Erase Done Interrupt Read Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WRITE</name>
|
|
<description>Write Done Interrupt Read Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHOF</name>
|
|
<description>Cache Hits Overflow Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOF</name>
|
|
<description>Cache Misses Overflow Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERASE</name>
|
|
<description>Erase Done Interrupt Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WRITE</name>
|
|
<description>Write Done Interrupt Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHOF</name>
|
|
<description>Cache Hits Overflow Interrupt Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOF</name>
|
|
<description>Cache Misses Overflow Interrupt Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERASE</name>
|
|
<description>Erase Done Interrupt Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WRITE</name>
|
|
<description>Write Done Interrupt Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHOF</name>
|
|
<description>Cache Hits Overflow Interrupt Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOF</name>
|
|
<description>Cache Misses Overflow Interrupt Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERASE</name>
|
|
<description>Erase Done Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRITE</name>
|
|
<description>Write Done Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHOF</name>
|
|
<description>Cache Hits Overflow Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOF</name>
|
|
<description>Cache Misses Overflow Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<description>Configuration Lock Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKKEY</name>
|
|
<description>Configuration Lock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INVCACHE</name>
|
|
<description>Invalidate Instruction Cache</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTPC</name>
|
|
<description>Start Performance Counters</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOPPC</name>
|
|
<description>Stop Performance Counters</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CACHEHITS</name>
|
|
<description>Cache Hits Performance Counter</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CACHEHITS</name>
|
|
<description>Cache hits since last performance counter start command.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CACHEMISSES</name>
|
|
<description>Cache Misses Performance Counter</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CACHEMISSES</name>
|
|
<description>Cache misses since last performance counter start command.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMEBASE</name>
|
|
<description>Flash Write and Erase Timebase</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0x0001003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BASE</name>
|
|
<description>Timebase used by MSC to time flash writes and erases</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERIOD</name>
|
|
<description>Sets the timebase period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASSLOCK</name>
|
|
<description>Mass Erase Lock Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKKEY</name>
|
|
<description>Mass Erase Lock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<description>Mass erase unlocked.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<description>Mass erase locked.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EMU</name>
|
|
<description>EMU</description>
|
|
<baseAddress>0x400C6000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EMU</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EMVREG</name>
|
|
<description>Energy Mode Voltage Regulator Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EM2BLOCK</name>
|
|
<description>Energy Mode 2 Block</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EM4CTRL</name>
|
|
<description>Energy Mode 4 Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEMCTRL</name>
|
|
<description>Memory Control Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>RAM block power-down</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BLK3</name>
|
|
<description>Power down RAM block 3 (address range 0x20018000-0x2001FFFF).</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BLK23</name>
|
|
<description>Power down RAM blocks 2-3 (address range 0x20010000-0x2001FFFF).</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BLK123</name>
|
|
<description>Power down RAM blocks 1-3 (address range 0x20008000-0x2001FFFF).</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<description>Configuration Lock Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKKEY</name>
|
|
<description>Configuration Lock Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AUXCTRL</name>
|
|
<description>Auxiliary Control Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000101</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HRCCLR</name>
|
|
<description>Hard Reset Cause Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REDLFXOBOOST</name>
|
|
<description>Reduce LFXO Start-up Boost Current</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EM4CONF</name>
|
|
<description>Energy mode 4 configuration register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0001001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VREGEN</name>
|
|
<description>EM4 voltage regulator enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BURTCWU</name>
|
|
<description>Backup RTC EM4 wakeup enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC</name>
|
|
<description>Select EM4 duty oscillator</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ULFRCO</name>
|
|
<description>ULFRCO is available.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCO</name>
|
|
<description>LFRCO is available. Can only be set if LFRCO is running before EM4/backup entry.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXO</name>
|
|
<description>LFXO is available. Can only be set if LFXO is available before EM4/backup entry.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUBODRSTDIS</name>
|
|
<description>Disable reset from Backup BOD in EM4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKCONF</name>
|
|
<description>EM4 configuration lock enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUCTRL</name>
|
|
<description>Backup Power configuration register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000006F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enable backup mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STATEN</name>
|
|
<description>Enable backup mode status export</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BODCAL</name>
|
|
<description>Enable BOD calibration mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUMODEBODEN</name>
|
|
<description>Enable brown out detection on BU_VIN when in backup mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROBE</name>
|
|
<description>Voltage probe select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable voltage probe.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDDDREG</name>
|
|
<description>Connect probe to VDD_DREG.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUIN</name>
|
|
<description>Connect probe to BU_IN.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUOUT</name>
|
|
<description>Connect probe to BU_OUT.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWRCONF</name>
|
|
<description>Power connection configuration register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VOUTWEAK</name>
|
|
<description>BU_VOUT weak enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VOUTMED</name>
|
|
<description>BU_VOUT medium enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VOUTSTRONG</name>
|
|
<description>BU_VOUT strong enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWRRES</name>
|
|
<description>Power domain resistor select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RES0</name>
|
|
<description>Main power and backup power connected with RES0 series resistance.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES1</name>
|
|
<description>Main power and backup power connected with RES1 series resistance.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES2</name>
|
|
<description>Main power and backup power connected with RES2 series resistance.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES3</name>
|
|
<description>Main power and backup power connected with RES3 series resistance.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUINACT</name>
|
|
<description>Backup mode inactive configuration register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000000B</resetValue>
|
|
<resetMask>0x0000007F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUENTHRES</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUENRANGE</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWRCON</name>
|
|
<description>Power connection configuration when not in Backup mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No connection.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUMAIN</name>
|
|
<description>Main power and backup power are connected through a diode, allowing current to flow from backup power source to main power source, but not the other way.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAINBU</name>
|
|
<description>Main power and backup power are connected through a diode, allowing current to flow from main power source to backup power source, but not the other way.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NODIODE</name>
|
|
<description>Main power and backup power are connected without diode.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUACT</name>
|
|
<description>Backup mode active configuration register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000000B</resetValue>
|
|
<resetMask>0x0000007F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUEXTHRES</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUEXRANGE</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWRCON</name>
|
|
<description>Power connection configuration when in Backup mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No connection.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUMAIN</name>
|
|
<description>Main power and backup power are connected through a diode, allowing current to flow from backup power source to main power source, but not the other way.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAINBU</name>
|
|
<description>Main power and backup power are connected through a diode, allowing current to flow from main power source to backup power source, but not the other way.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NODIODE</name>
|
|
<description>Main power and backup power are connected without diode.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BURDY</name>
|
|
<description>Backup mode ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUVINPEN</name>
|
|
<description>BU_VIN Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BURDY</name>
|
|
<description>Backup functionality ready Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BURDY</name>
|
|
<description>Set Backup functionality ready Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BURDY</name>
|
|
<description>Clear Backup functionality ready Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BURDY</name>
|
|
<description>Backup functionality ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUBODBUVINCAL</name>
|
|
<description>BU_VIN Backup BOD calibration</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000000B</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THRES</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RANGE</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUBODUNREGCAL</name>
|
|
<description>Unregulated power Backup BOD calibration</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000000B</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THRES</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RANGE</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RMU</name>
|
|
<description>RMU</description>
|
|
<baseAddress>0x400CA000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKUPRDIS</name>
|
|
<description>Lockup Reset Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BURSTEN</name>
|
|
<description>Backup domain reset enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCAUSE</name>
|
|
<description>Reset Cause Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PORST</name>
|
|
<description>Power On Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BODUNREGRST</name>
|
|
<description>Brown Out Detector Unregulated Domain Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BODREGRST</name>
|
|
<description>Brown Out Detector Regulated Domain Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXTRST</name>
|
|
<description>External Pin Reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WDOGRST</name>
|
|
<description>Watchdog Reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKUPRST</name>
|
|
<description>LOCKUP Reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSREQRST</name>
|
|
<description>System Request Reset</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EM4RST</name>
|
|
<description>EM4 Reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EM4WURST</name>
|
|
<description>EM4 Wake-up Reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BODAVDD0</name>
|
|
<description>AVDD0 Bod Reset</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BODAVDD1</name>
|
|
<description>AVDD1 Bod Reset</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUBODVDDDREG</name>
|
|
<description>Backup Brown Out Detector, VDD_DREG</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUBODBUVIN</name>
|
|
<description>Backup Brown Out Detector, BU_VIN</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUBODUNREG</name>
|
|
<description>Backup Brown Out Detector Unregulated Domain</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUBODREG</name>
|
|
<description>Backup Brown Out Detector Regulated Domain</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUMODERST</name>
|
|
<description>Backup mode reset</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCCLR</name>
|
|
<description>Reset Cause Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CMU</name>
|
|
<description>CMU</description>
|
|
<baseAddress>0x400C8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMU</name>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>CMU Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000C062C</resetValue>
|
|
<resetMask>0x57FFFEEF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFXOMODE</name>
|
|
<description>HFXO Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XTAL</name>
|
|
<description>4-48 MHz crystal oscillator.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUFEXTCLK</name>
|
|
<description>An AC coupled buffer is coupled in series with HFXTAL_N, suitable for external sine wave (4-48 MHz). The sine wave should have a minimum of 200 mV peak to peak.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGEXTCLK</name>
|
|
<description>Digital external clock on HFXTAL_N pin. Oscillator is effectively bypassed.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXOBOOST</name>
|
|
<description>HFXO Start-up Boost Current</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>50PCENT</name>
|
|
<description>50 %.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>70PCENT</name>
|
|
<description>70 %.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>80PCENT</name>
|
|
<description>80 %.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100PCENT</name>
|
|
<description>100 % (default).</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXOBUFCUR</name>
|
|
<description>HFXO Boost Buffer Current</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BOOSTUPTO32MHZ</name>
|
|
<description>Boost Buffer Current level when HFXO is below or equal to 32 MHz.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOOSTABOVE32MHZ</name>
|
|
<description>Boost Buffer Current Level when HFXO is above 32 MHz.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFXOGLITCHDETEN</name>
|
|
<description>HFXO Glitch Detector Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HFXOTIMEOUT</name>
|
|
<description>HFXO Timeout</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>8CYCLES</name>
|
|
<description>Timeout period of 8 cycles.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256CYCLES</name>
|
|
<description>Timeout period of 256 cycles.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1KCYCLES</name>
|
|
<description>Timeout period of 1024 cycles.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16KCYCLES</name>
|
|
<description>Timeout period of 16384 cycles.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LFXOMODE</name>
|
|
<description>LFXO Mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XTAL</name>
|
|
<description>32.768 kHz crystal oscillator.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUFEXTCLK</name>
|
|
<description>An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable for external sinus wave (32.768 kHz).</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGEXTCLK</name>
|
|
<description>Digital external clock on LFXTAL_N pin. Oscillator is effectively bypassed.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LFXOBOOST</name>
|
|
<description>LFXO Start-up Boost Current</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HFCLKDIV</name>
|
|
<description>HFCLK Division</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXOBUFCUR</name>
|
|
<description>LFXO Boost Buffer Current</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXOTIMEOUT</name>
|
|
<description>LFXO Timeout</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>8CYCLES</name>
|
|
<description>Timeout period of 8 cycles.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1KCYCLES</name>
|
|
<description>Timeout period of 1024 cycles.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16KCYCLES</name>
|
|
<description>Timeout period of 16384 cycles.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32KCYCLES</name>
|
|
<description>Timeout period of 32768 cycles.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKOUTSEL0</name>
|
|
<description>Clock Output Select 0</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFRCO</name>
|
|
<description>HFRCO (directly from oscillator).</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXO</name>
|
|
<description>HFXO (directly from oscillator).</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK2</name>
|
|
<description>HFCLK/2.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK4</name>
|
|
<description>HFCLK/4.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK8</name>
|
|
<description>HFCLK/8.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK16</name>
|
|
<description>HFCLK/16.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULFRCO</name>
|
|
<description>ULFRCO (directly from oscillator).</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUXHFRCO</name>
|
|
<description>AUXHFRCO (directly from oscillator).</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKOUTSEL1</name>
|
|
<description>Clock Output Select 1</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LFRCO</name>
|
|
<description>LFRCO (directly from oscillator).</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXO</name>
|
|
<description>LFXO (directly from oscillator).</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK</name>
|
|
<description>HFCLK (undivided).</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXOQ</name>
|
|
<description>LFXO (qualified).</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXOQ</name>
|
|
<description>HFXO (qualified).</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCOQ</name>
|
|
<description>LFRCO (qualified).</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRCOQ</name>
|
|
<description>HFRCO (qualified).</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUXHFRCOQ</name>
|
|
<description>AUXHFRCO (qualified).</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGCLK</name>
|
|
<description>Debug Clock</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HFLE</name>
|
|
<description>High-Frequency LE Interface</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFCORECLKDIV</name>
|
|
<description>High Frequency Core Clock Division Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000010F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFCORECLKDIV</name>
|
|
<description>HFCORECLK Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFCLK</name>
|
|
<description>HFCORECLK = HFCLK.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK2</name>
|
|
<description>HFCORECLK = HFCLK/2.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK4</name>
|
|
<description>HFCORECLK = HFCLK/4.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK8</name>
|
|
<description>HFCORECLK = HFCLK/8.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK16</name>
|
|
<description>HFCORECLK = HFCLK/16.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK32</name>
|
|
<description>HFCORECLK = HFCLK/32.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK64</name>
|
|
<description>HFCORECLK = HFCLK/64.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK128</name>
|
|
<description>HFCORECLK = HFCLK/128.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK256</name>
|
|
<description>HFCORECLK = HFCLK/256.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK512</name>
|
|
<description>HFCORECLK = HFCLK/512.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFCORECLKLEDIV</name>
|
|
<description>Additional Division Factor For HFCORECLKLE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFPERCLKDIV</name>
|
|
<description>High Frequency Peripheral Clock Division Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<resetMask>0x0000010F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFPERCLKDIV</name>
|
|
<description>HFPERCLK Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFCLK</name>
|
|
<description>HFPERCLK = HFCLK.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK2</name>
|
|
<description>HFPERCLK = HFCLK/2.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK4</name>
|
|
<description>HFPERCLK = HFCLK/4.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK8</name>
|
|
<description>HFPERCLK = HFCLK/8.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK16</name>
|
|
<description>HFPERCLK = HFCLK/16.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK32</name>
|
|
<description>HFPERCLK = HFCLK/32.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK64</name>
|
|
<description>HFPERCLK = HFCLK/64.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK128</name>
|
|
<description>HFPERCLK = HFCLK/128.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK256</name>
|
|
<description>HFPERCLK = HFCLK/256.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCLK512</name>
|
|
<description>HFPERCLK = HFCLK/512.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HFPERCLKEN</name>
|
|
<description>HFPERCLK Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFRCOCTRL</name>
|
|
<description>HFRCO Control Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000380</resetValue>
|
|
<resetMask>0x0001F7FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TUNING</name>
|
|
<description>HFRCO Tuning Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BAND</name>
|
|
<description>HFRCO Band Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1MHZ</name>
|
|
<description>1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7MHZ</name>
|
|
<description>7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11MHZ</name>
|
|
<description>11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>14MHZ</name>
|
|
<description>14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>21MHZ</name>
|
|
<description>21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>28MHZ</name>
|
|
<description>28 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUDELAY</name>
|
|
<description>HFRCO Start-up Delay</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LFRCOCTRL</name>
|
|
<description>LFRCO Control Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000040</resetValue>
|
|
<resetMask>0x0000007F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TUNING</name>
|
|
<description>LFRCO Tuning Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AUXHFRCOCTRL</name>
|
|
<description>AUXHFRCO Control Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TUNING</name>
|
|
<description>AUXHFRCO Tuning Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BAND</name>
|
|
<description>AUXHFRCO Band Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>14MHZ</name>
|
|
<description>14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11MHZ</name>
|
|
<description>11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7MHZ</name>
|
|
<description>7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1MHZ</name>
|
|
<description>1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>28MHZ</name>
|
|
<description>28 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>21MHZ</name>
|
|
<description>21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALCTRL</name>
|
|
<description>Calibration Control Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000007F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UPSEL</name>
|
|
<description>Calibration Up-counter Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFXO</name>
|
|
<description>Select HFXO as up-counter.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXO</name>
|
|
<description>Select LFXO as up-counter.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRCO</name>
|
|
<description>Select HFRCO as up-counter.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCO</name>
|
|
<description>Select LFRCO as up-counter.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUXHFRCO</name>
|
|
<description>Select AUXHFRCO as up-counter.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOWNSEL</name>
|
|
<description>Calibration Down-counter Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFCLK</name>
|
|
<description>Select HFCLK for down-counter.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXO</name>
|
|
<description>Select HFXO for down-counter.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXO</name>
|
|
<description>Select LFXO for down-counter.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFRCO</name>
|
|
<description>Select HFRCO for down-counter.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCO</name>
|
|
<description>Select LFRCO for down-counter.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUXHFRCO</name>
|
|
<description>Select AUXHFRCO for down-counter.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous Calibration</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALCNT</name>
|
|
<description>Calibration Counter Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CALCNT</name>
|
|
<description>Calibration Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSCENCMD</name>
|
|
<description>Oscillator Enable/Disable Command Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000003FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFRCOEN</name>
|
|
<description>HFRCO Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HFRCODIS</name>
|
|
<description>HFRCO Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HFXOEN</name>
|
|
<description>HFXO Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HFXODIS</name>
|
|
<description>HFXO Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXHFRCOEN</name>
|
|
<description>AUXHFRCO Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXHFRCODIS</name>
|
|
<description>AUXHFRCO Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFRCOEN</name>
|
|
<description>LFRCO Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFRCODIS</name>
|
|
<description>LFRCO Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXOEN</name>
|
|
<description>LFXO Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXODIS</name>
|
|
<description>LFXO Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFCLKSEL</name>
|
|
<description>HFCLK Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFRCO</name>
|
|
<description>Select HFRCO as HFCLK.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFXO</name>
|
|
<description>Select HFXO as HFCLK.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCO</name>
|
|
<description>Select LFRCO as HFCLK.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXO</name>
|
|
<description>Select LFXO as HFCLK.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALSTART</name>
|
|
<description>Calibration Start</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALSTOP</name>
|
|
<description>Calibration Stop</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBCCLKSEL</name>
|
|
<description>USB Core Clock Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HFCLKNODIV</name>
|
|
<description>Select HFCLK (undivided) as HFCORECLKUSBC.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXO</name>
|
|
<description>Select LFXO as HFCORECLKUSBC.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCO</name>
|
|
<description>Select LFRCO as HFCORECLKUSBC.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LFCLKSEL</name>
|
|
<description>Low Frequency Clock Select Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
<resetMask>0x0011000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LFA</name>
|
|
<description>Clock Select for LFA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>LFACLK is disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCO</name>
|
|
<description>LFRCO selected as LFACLK</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXO</name>
|
|
<description>LFXO selected as LFACLK</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCORECLKLEDIV2</name>
|
|
<description>HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LFB</name>
|
|
<description>Clock Select for LFB</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>LFBCLK is disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCO</name>
|
|
<description>LFRCO selected as LFBCLK</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXO</name>
|
|
<description>LFXO selected as LFBCLK</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HFCORECLKLEDIV2</name>
|
|
<description>HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LFAE</name>
|
|
<description>Clock Select for LFA Extended</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LFBE</name>
|
|
<description>Clock Select for LFB Extended</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000403</resetValue>
|
|
<resetMask>0x0003FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFRCOENS</name>
|
|
<description>HFRCO Enable Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HFRCORDY</name>
|
|
<description>HFRCO Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HFXOENS</name>
|
|
<description>HFXO Enable Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HFXORDY</name>
|
|
<description>HFXO Ready</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXHFRCOENS</name>
|
|
<description>AUXHFRCO Enable Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXHFRCORDY</name>
|
|
<description>AUXHFRCO Ready</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFRCOENS</name>
|
|
<description>LFRCO Enable Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFRCORDY</name>
|
|
<description>LFRCO Ready</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXOENS</name>
|
|
<description>LFXO Enable Status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXORDY</name>
|
|
<description>LFXO Ready</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HFRCOSEL</name>
|
|
<description>HFRCO Selected</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HFXOSEL</name>
|
|
<description>HFXO Selected</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFRCOSEL</name>
|
|
<description>LFRCO Selected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXOSEL</name>
|
|
<description>LFXO Selected</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALBSY</name>
|
|
<description>Calibration Busy</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBCHFCLKSEL</name>
|
|
<description>USBC HFCLK Selected</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBCLFXOSEL</name>
|
|
<description>USBC LFXO Selected</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBCLFRCOSEL</name>
|
|
<description>USBC LFRCO Selected</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFRCORDY</name>
|
|
<description>HFRCO Ready Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HFXORDY</name>
|
|
<description>HFXO Ready Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFRCORDY</name>
|
|
<description>LFRCO Ready Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXORDY</name>
|
|
<description>LFXO Ready Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXHFRCORDY</name>
|
|
<description>AUXHFRCO Ready Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALRDY</name>
|
|
<description>Calibration Ready Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALOF</name>
|
|
<description>Calibration Overflow Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBCHFCLKSEL</name>
|
|
<description>USBC HFCLK Selected Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFRCORDY</name>
|
|
<description>HFRCO Ready Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HFXORDY</name>
|
|
<description>HFXO Ready Interrupt Flag Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFRCORDY</name>
|
|
<description>LFRCO Ready Interrupt Flag Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXORDY</name>
|
|
<description>LFXO Ready Interrupt Flag Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXHFRCORDY</name>
|
|
<description>AUXHFRCO Ready Interrupt Flag Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALRDY</name>
|
|
<description>Calibration Ready Interrupt Flag Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALOF</name>
|
|
<description>Calibration Overflow Interrupt Flag Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBCHFCLKSEL</name>
|
|
<description>USBC HFCLK Selected Interrupt Flag Set</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFRCORDY</name>
|
|
<description>HFRCO Ready Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HFXORDY</name>
|
|
<description>HFXO Ready Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFRCORDY</name>
|
|
<description>LFRCO Ready Interrupt Flag Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXORDY</name>
|
|
<description>LFXO Ready Interrupt Flag Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXHFRCORDY</name>
|
|
<description>AUXHFRCO Ready Interrupt Flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALRDY</name>
|
|
<description>Calibration Ready Interrupt Flag Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALOF</name>
|
|
<description>Calibration Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBCHFCLKSEL</name>
|
|
<description>USBC HFCLK Selected Interrupt Flag Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HFRCORDY</name>
|
|
<description>HFRCO Ready Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HFXORDY</name>
|
|
<description>HFXO Ready Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LFRCORDY</name>
|
|
<description>LFRCO Ready Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXORDY</name>
|
|
<description>LFXO Ready Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXHFRCORDY</name>
|
|
<description>AUXHFRCO Ready Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALRDY</name>
|
|
<description>Calibration Ready Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALOF</name>
|
|
<description>Calibration Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBCHFCLKSEL</name>
|
|
<description>USBC HFCLK Selected Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFCORECLKEN0</name>
|
|
<description>High Frequency Core Clock Enable Register 0</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>Direct Memory Access Controller Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AES</name>
|
|
<description>Advanced Encryption Standard Accelerator Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBC</name>
|
|
<description>Universal Serial Bus Interface Core Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface Clock Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LE</name>
|
|
<description>Low Energy Peripheral Interface Clock Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFPERCLKEN0</name>
|
|
<description>High Frequency Peripheral Clock Enable Register 0</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0003FFE7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0 Clock Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1 Clock Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2 Clock Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3 Clock Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0 Clock Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1 Clock Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C0</name>
|
|
<description>I2C 0 Clock Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C1</name>
|
|
<description>I2C 1 Clock Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GPIO</name>
|
|
<description>General purpose Input/Output Clock Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator Clock Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRS</name>
|
|
<description>Peripheral Reflex System Clock Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0 Clock Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0 Clock Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000055</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LFACLKEN0</name>
|
|
<description>Low Frequency A Clock Enable 0 Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFAPRESC0</name>
|
|
<description>Low Frequency A Prescaler 0 Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFBCLKEN0</name>
|
|
<description>Low Frequency B Clock Enable 0 Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFBPRESC0</name>
|
|
<description>Low Frequency B Prescaler 0 Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREEZE</name>
|
|
<description>Freeze Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGFREEZE</name>
|
|
<description>Register Update Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LFACLKEN0</name>
|
|
<description>Low Frequency A Clock Enable Register 0 (Async Reg)</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0 Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LFBCLKEN0</name>
|
|
<description>Low Frequency B Clock Enable Register 0 (Async Reg)</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0 Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1 Clock Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LFAPRESC0</name>
|
|
<description>Low Frequency A Prescaler Register 0 (Async Reg)</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FF3</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LESENSE</name>
|
|
<description>Low Energy Sensor Interface Prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>LFACLKLESENSE = LFACLK</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>LFACLKLESENSE = LFACLK/2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>LFACLKLESENSE = LFACLK/4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>LFACLKLESENSE = LFACLK/8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter Prescaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>LFACLKRTC = LFACLK</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>LFACLKRTC = LFACLK/2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>LFACLKRTC = LFACLK/4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>LFACLKRTC = LFACLK/8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>LFACLKRTC = LFACLK/16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>LFACLKRTC = LFACLK/32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>LFACLKRTC = LFACLK/64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>LFACLKRTC = LFACLK/128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>LFACLKRTC = LFACLK/256</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>LFACLKRTC = LFACLK/512</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>LFACLKRTC = LFACLK/1024</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2048</name>
|
|
<description>LFACLKRTC = LFACLK/2048</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4096</name>
|
|
<description>LFACLKRTC = LFACLK/4096</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8192</name>
|
|
<description>LFACLKRTC = LFACLK/8192</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16384</name>
|
|
<description>LFACLKRTC = LFACLK/16384</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32768</name>
|
|
<description>LFACLKRTC = LFACLK/32768</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0 Prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>LFACLKLETIMER0 = LFACLK</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/256</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/512</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/1024</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2048</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/2048</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4096</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/4096</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8192</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/8192</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16384</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/16384</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32768</name>
|
|
<description>LFACLKLETIMER0 = LFACLK/32768</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LFBPRESC0</name>
|
|
<description>Low Frequency B Prescaler Register 0 (Async Reg)</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000033</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LEUART0</name>
|
|
<description>Low Energy UART 0 Prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>LFBCLKLEUART0 = LFBCLK</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>LFBCLKLEUART0 = LFBCLK/2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>LFBCLKLEUART0 = LFBCLK/4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>LFBCLKLEUART0 = LFBCLK/8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LEUART1</name>
|
|
<description>Low Energy UART 1 Prescaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>LFBCLKLEUART1 = LFBCLK</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>LFBCLKLEUART1 = LFBCLK/2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>LFBCLKLEUART1 = LFBCLK/4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>LFBCLKLEUART1 = LFBCLK/8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCNTCTRL</name>
|
|
<description>PCNT Control Register</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCNT0CLKEN</name>
|
|
<description>PCNT0 Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCNT0CLKSEL</name>
|
|
<description>PCNT0 Clock Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCNT1CLKEN</name>
|
|
<description>PCNT1 Clock Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCNT1CLKSEL</name>
|
|
<description>PCNT1 Clock Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCNT2CLKEN</name>
|
|
<description>PCNT2 Clock Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCNT2CLKSEL</name>
|
|
<description>PCNT2 Clock Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKOUT0PEN</name>
|
|
<description>CLKOUT0 Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKOUT1PEN</name>
|
|
<description>CLKOUT1 Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<description>Configuration Lock Register</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKKEY</name>
|
|
<description>Configuration Lock Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LESENSE</name>
|
|
<description>LESENSE</description>
|
|
<baseAddress>0x4008C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LESENSE</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00772EFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCANMODE</name>
|
|
<description>Configure scan mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PERIODIC</name>
|
|
<description>A new scan is started each time the period counter overflows</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOT</name>
|
|
<description>A single scan is performed when START in CMD is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRS</name>
|
|
<description>Pulse on PRS channel</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Scan start PRS select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCANCONF</name>
|
|
<description>Select scan configuration</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIRMAP</name>
|
|
<description>The channel configuration register registers used are directly mapped to the channel number.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVMAP</name>
|
|
<description>The channel configuration register registers used are CHX+8_CONF for channels 0-7 and CHX-8_CONF for channels 8-15.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>The channel configuration register registers used toggles between CHX_CONF and CHX+8_CONF when channel x triggers</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DECDEF</name>
|
|
<description>The decoder state defines the CONF registers to be used.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP0INV</name>
|
|
<description>Invert analog comparator 0 output</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACMP1INV</name>
|
|
<description>Invert analog comparator 1 output</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEXMAP</name>
|
|
<description>Alternative excitation map</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DUALSAMPLE</name>
|
|
<description>Enable dual sample mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFOW</name>
|
|
<description>Result buffer overwrite</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSCANRES</name>
|
|
<description>Enable storing of SCANRES</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFIDL</name>
|
|
<description>Result buffer interrupt and DMA trigger level</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAWU</name>
|
|
<description>DMA wake-up from EM2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>No DMA wake-up from EM2</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUFDATAV</name>
|
|
<description>DMA wake-up from EM2 when data is valid in the result buffer</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUFLEVEL</name>
|
|
<description>DMA wake-up from EM2 when the result buffer is full/half-full depending on BUFIDL configuration</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGRUN</name>
|
|
<description>Debug Mode Run Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMCTRL</name>
|
|
<description>Timing Control Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00CFF773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUXPRESC</name>
|
|
<description>Prescaling factor for high frequency timer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>High frequency timer is clocked with AUXHFRCO/1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>High frequency timer is clocked with AUXHFRCO/2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>High frequency timer is clocked with AUXHFRCO/4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>High frequency timer is clocked with AUXHFRCO/8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LFPRESC</name>
|
|
<description>Prescaling factor for low frequency timer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>Low frequency timer is clocked with LFACLKLESENSE/1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Low frequency timer is clocked with LFACLKLESENSE/2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Low frequency timer is clocked with LFACLKLESENSE/4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Low frequency timer is clocked with LFACLKLESENSE/8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Low frequency timer is clocked with LFACLKLESENSE/16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Low frequency timer is clocked with LFACLKLESENSE/32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Low frequency timer is clocked with LFACLKLESENSE/64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>Low frequency timer is clocked with LFACLKLESENSE/128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCPRESC</name>
|
|
<description>Period counter prescaling</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>The period counter clock frequency is LFACLKLESENSE/1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>The period counter clock frequency is LFACLKLESENSE/2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>The period counter clock frequency is LFACLKLESENSE/4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>The period counter clock frequency is LFACLKLESENSE/8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>The period counter clock frequency is LFACLKLESENSE/16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>The period counter clock frequency is LFACLKLESENSE/32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>The period counter clock frequency is LFACLKLESENSE/64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>The period counter clock frequency is LFACLKLESENSE/128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCTOP</name>
|
|
<description>Period counter top value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTDLY</name>
|
|
<description>Start delay configuration</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERCTRL</name>
|
|
<description>Peripheral Control Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0CF47FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DACCH0DATA</name>
|
|
<description>DAC CH0 data selection.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACCH1DATA</name>
|
|
<description>DAC CH1 data selection.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACCH0CONV</name>
|
|
<description>DAC channel 0 conversion mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>LESENSE does not control DAC CH0.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>DAC channel 0 is driven in continuous mode.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPLEHOLD</name>
|
|
<description>DAC channel 0 is driven in sample hold mode.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPLEOFF</name>
|
|
<description>DAC channel 0 is driven in sample off mode.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACCH1CONV</name>
|
|
<description>DAC channel 1 conversion mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>LESENSE does not control DAC CH1.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>DAC channel 1 is driven in continuous mode.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPLEHOLD</name>
|
|
<description>DAC channel 1 is driven in sample hold mode.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPLEOFF</name>
|
|
<description>DAC channel 1 is driven in sample off mode.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACCH0OUT</name>
|
|
<description>DAC channel 0 output mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>DAC CH0 output to pin and ACMP/ADC disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN</name>
|
|
<description>DAC CH0 output to pin enabled, output to ADC and ACMP disabled</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCACMP</name>
|
|
<description>DAC CH0 output to pin disabled, output to ADC and ACMP enabled</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINADCACMP</name>
|
|
<description>DAC CH0 output to pin, ADC, and ACMP enabled.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACCH1OUT</name>
|
|
<description>DAC channel 1 output mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>DAC CH1 output to pin and ACMP/ADC disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN</name>
|
|
<description>DAC CH1 output to pin enabled, output to ADC and ACMP disabled</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCACMP</name>
|
|
<description>DAC CH1 output to pin disabled, output to ADC and ACMP enabled</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINADCACMP</name>
|
|
<description>DAC CH1 output to pin, ADC, and ACMP enabled.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACPRESC</name>
|
|
<description>DAC prescaler configuration.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACREF</name>
|
|
<description>DAC bandgap reference used</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACMP0MODE</name>
|
|
<description>ACMP0 mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>LESENSE does not control ACMP0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MUX</name>
|
|
<description>LESENSE controls the input mux (POSSEL) of ACMP0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MUXTHRES</name>
|
|
<description>LESENSE controls the input mux (POSSEL) and the threshold value (VDDLEVEL) of ACMP0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMP1MODE</name>
|
|
<description>ACMP1 mode</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>LESENSE does not control ACMP1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MUX</name>
|
|
<description>LESENSE controls the input mux (POSSEL) of ACMP1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MUXTHRES</name>
|
|
<description>LESENSE controls the input mux and the threshold value (VDDLEVEL) of ACMP1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WARMUPMODE</name>
|
|
<description>ACMP and DAC duty cycle mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>The analog comparators and DAC are shut down when LESENSE is idle</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KEEPACMPWARM</name>
|
|
<description>The analog comparators are kept powered up when LESENSE is idle</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KEEPDACWARM</name>
|
|
<description>The DAC is kept powered up when LESENSE is idle</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KEEPACMPDACWARM</name>
|
|
<description>The analog comparators and DAC are kept powered up when LESENSE is idle</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DECCTRL</name>
|
|
<description>Decoder control Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x03FFFDFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DISABLE</name>
|
|
<description>Disable the decoder</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRCHK</name>
|
|
<description>Enable check of current state</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTMAP</name>
|
|
<description>Enable decoder to channel interrupt mapping</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYSTPRS0</name>
|
|
<description>Enable decoder hysteresis on PRS0 output</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYSTPRS1</name>
|
|
<description>Enable decoder hysteresis on PRS1 output</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYSTPRS2</name>
|
|
<description>Enable decoder hysteresis on PRS2 output</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYSTIRQ</name>
|
|
<description>Enable decoder hysteresis on interrupt requests</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSCNT</name>
|
|
<description>Enable count mode on decoder PRS channels 0 and 1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INPUT</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL0</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL1</name>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL2</name>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL3</name>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BIASCTRL</name>
|
|
<description>Bias Control Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BIASMODE</name>
|
|
<description>Select bias mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DUTYCYCLE</name>
|
|
<description>Bias module duty cycled between low power and high accuracy mode</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGHACC</name>
|
|
<description>Bias module always in high accuracy mode</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DONTTOUCH</name>
|
|
<description>Bias module not affected by LESENSE</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start scanning of sensors.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop scanning of sensors</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Start decoder</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARBUF</name>
|
|
<description>Clear result buffer</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHEN</name>
|
|
<description>Channel enable Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>Enable scan channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCANRES</name>
|
|
<description>Scan result register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCANRES</name>
|
|
<description>Scan results</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUFDATAV</name>
|
|
<description>Result data valid</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFHALFFULL</name>
|
|
<description>Result buffer half full</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFFULL</name>
|
|
<description>Result buffer full</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RUNNING</name>
|
|
<description>LESENSE is active</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANACTIVE</name>
|
|
<description>LESENSE is currently interfacing sensors.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DACACTIVE</name>
|
|
<description>LESENSE DAC interface is active</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTR</name>
|
|
<description>Result buffer pointers</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000001EF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RD</name>
|
|
<description>Result buffer read pointer.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WR</name>
|
|
<description>Result buffer write pointer.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUFDATA</name>
|
|
<description>Result buffer data register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>BUFDATA</name>
|
|
<description>Result data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CURCH</name>
|
|
<description>Current channel index</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CURCH</name>
|
|
<description>Shows the index of the current channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DECSTATE</name>
|
|
<description>Current decoder state</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DECSTATE</name>
|
|
<description>Shows the current decoder state</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SENSORSTATE</name>
|
|
<description>Decoder input register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SENSORSTATE</name>
|
|
<description>Shows the status of sensors chosen as input to the decoder</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDLECONF</name>
|
|
<description>GPIO Idle phase configuration</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 idle phase configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH0 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH0 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH0 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACCH0</name>
|
|
<description>CH0 output is connected to DAC CH0 output in idle phase</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 idle phase configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH1 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH1 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH1 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACCH0</name>
|
|
<description>CH1 output is connected to DAC CH0 output in idle phase</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<description>Channel 2 idle phase configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH2 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH2 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH2 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACCH0</name>
|
|
<description>CH2 output is connected to DAC CH0 output in idle phase</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<description>Channel 3 idle phase configuration</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH3 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH3 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH3 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACCH0</name>
|
|
<description>CH3 output is connected to DAC CH0 output in idle phase</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<description>Channel 4 idle phase configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH4 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH4 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH4 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<description>Channel 5 idle phase configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH5 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH5 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH5 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<description>Channel 6 idle phase configuration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH6 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH6 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH6 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<description>Channel 7 idle phase configuration</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH7 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH7 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH7 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<description>Channel 8 idle phase configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH8 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH8 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH8 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<description>Channel 9 idle phase configuration</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH9 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH9 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH9 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<description>Channel 10 idle phase configuration</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH10 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH10 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH10 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<description>Channel 11 idle phase configuration</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH11 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH11 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH11 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<description>Channel 12 idle phase configuration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH12 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH12 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH12 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACCH1</name>
|
|
<description>CH12 output is connected to DAC CH1 output in idle phase</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<description>Channel 13 idle phase configuration</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH13 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH13 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH13 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACCH1</name>
|
|
<description>CH13 output is connected to DAC CH1 output in idle phase</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<description>Channel 14 idle phase configuration</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH14 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH14 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH14 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACCH1</name>
|
|
<description>CH14 output is connected to DAC CH1 output in idle phase</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<description>Channel 15 idle phase configuration</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>CH15 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>CH15 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>CH15 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACCH1</name>
|
|
<description>CH15 output is connected to DAC CH1 output in idle phase</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALTEXCONF</name>
|
|
<description>Alternative excite pin configuration</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00FFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IDLECONF0</name>
|
|
<description>ALTEX0 idle phase configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>ALTEX0 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>ALTEX0 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>ALTEX0 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLECONF1</name>
|
|
<description>ALTEX1 idle phase configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>ALTEX1 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>ALTEX1 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>ALTEX1 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLECONF2</name>
|
|
<description>ALTEX2 idle phase configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>ALTEX2 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>ALTEX2 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>ALTEX2 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLECONF3</name>
|
|
<description>ALTEX3 idle phase configuration</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>ALTEX3 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>ALTEX3 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>ALTEX3 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLECONF4</name>
|
|
<description>ALTEX4 idle phase configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>ALTEX4 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>ALTEX4 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>ALTEX4 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLECONF5</name>
|
|
<description>ALTEX5 idle phase configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>ALTEX5 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>ALTEX5 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>ALTEX5 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLECONF6</name>
|
|
<description>ALTEX6 idle phase configuration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>ALTEX6 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>ALTEX6 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>ALTEX6 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLECONF7</name>
|
|
<description>ALTEX7 idle phase configuration</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>ALTEX7 output is disabled in idle phase</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>ALTEX7 output is high in idle phase</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>ALTEX7 output is low in idle phase</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AEX0</name>
|
|
<description>ALTEX0 always excite enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AEX1</name>
|
|
<description>ALTEX1 always excite enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AEX2</name>
|
|
<description>ALTEX2 always excite enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AEX3</name>
|
|
<description>ALTEX3 always excite enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AEX4</name>
|
|
<description>ALTEX4 always excite enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AEX5</name>
|
|
<description>ALTEX5 always excite enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AEX6</name>
|
|
<description>ALTEX6 always excite enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AEX7</name>
|
|
<description>ALTEX7 always excite enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x007FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANCOMPLETE</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DEC</name>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DECERR</name>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFDATAV</name>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFLEVEL</name>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFOF</name>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNTOF</name>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x007FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANCOMPLETE</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DEC</name>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DECERR</name>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFDATAV</name>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFLEVEL</name>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFOF</name>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNTOF</name>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x007FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANCOMPLETE</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DEC</name>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DECERR</name>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFDATAV</name>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFLEVEL</name>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFOF</name>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNTOF</name>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x007FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2</name>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3</name>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4</name>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5</name>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6</name>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7</name>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8</name>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9</name>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10</name>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11</name>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH12</name>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH13</name>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH14</name>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH15</name>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANCOMPLETE</name>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEC</name>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECERR</name>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFDATAV</name>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFLEVEL</name>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFOF</name>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNTOF</name>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07E3FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>LESENSE_CTRL Register Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMCTRL</name>
|
|
<description>LESENSE_TIMCTRL Register Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERCTRL</name>
|
|
<description>LESENSE_PERCTRL Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DECCTRL</name>
|
|
<description>LESENSE_DECCTRL Register Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BIASCTRL</name>
|
|
<description>LESENSE_BIASCTRL Register Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>LESENSE_CMD Register Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>LESENSE_CHEN Register Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRES</name>
|
|
<description>LESENSE_SCANRES Register Busy</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATUS</name>
|
|
<description>LESENSE_STATUS Register Busy</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PTR</name>
|
|
<description>LESENSE_PTR Register Busy</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFDATA</name>
|
|
<description>LESENSE_BUFDATA Register Busy</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CURCH</name>
|
|
<description>LESENSE_CURCH Register Busy</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DECSTATE</name>
|
|
<description>LESENSE_DECSTATE Register Busy</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SENSORSTATE</name>
|
|
<description>LESENSE_SENSORSTATE Register Busy</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IDLECONF</name>
|
|
<description>LESENSE_IDLECONF Register Busy</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEXCONF</name>
|
|
<description>LESENSE_ALTEXCONF Register Busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ROUTE</name>
|
|
<description>LESENSE_ROUTE Register Busy</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>LESENSE_POWERDOWN Register Busy</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCONFA</name>
|
|
<description>LESENSE_STx_TCONFA Register Busy</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCONFB</name>
|
|
<description>LESENSE_STx_TCONFB Register Busy</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>LESENSE_BUFx_DATA Register Busy</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMING</name>
|
|
<description>LESENSE_CHx_TIMING Register Busy</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INTERACT</name>
|
|
<description>LESENSE_CHx_INTERACT Register Busy</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EVAL</name>
|
|
<description>LESENSE_CHx_EVAL Register Busy</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00FFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0PEN</name>
|
|
<description>CH0 Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1PEN</name>
|
|
<description>CH0 Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2PEN</name>
|
|
<description>CH2 Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3PEN</name>
|
|
<description>CH3 Pin Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4PEN</name>
|
|
<description>CH4 Pin Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5PEN</name>
|
|
<description>CH5 Pin Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6PEN</name>
|
|
<description>CH6 Pin Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7PEN</name>
|
|
<description>CH7 Pin Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8PEN</name>
|
|
<description>CH8 Pin Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9PEN</name>
|
|
<description>CH9 Pin Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10PEN</name>
|
|
<description>CH10 Pin Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11PEN</name>
|
|
<description>CH11 Pin Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH12PEN</name>
|
|
<description>CH12 Pin Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH13PEN</name>
|
|
<description>CH13 Pin Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH14PEN</name>
|
|
<description>CH14 Pin Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH15PEN</name>
|
|
<description>CH15 Pin Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX0PEN</name>
|
|
<description>ALTEX0 Pin Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX1PEN</name>
|
|
<description>ALTEX1 Pin Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX2PEN</name>
|
|
<description>ALTEX2 Pin Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX3PEN</name>
|
|
<description>ALTEX3 Pin Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX4PEN</name>
|
|
<description>ALTEX4 Pin Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX5PEN</name>
|
|
<description>ALTEX5 Pin Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX6PEN</name>
|
|
<description>ALTEX6 Pin Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX7PEN</name>
|
|
<description>ALTEX7 Pin Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POWERDOWN</name>
|
|
<description>LESENSE RAM power-down register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAM</name>
|
|
<description>LESENSE RAM power-down</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST0_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST0_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST1_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST1_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST2_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST2_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST3_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST3_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x21C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST4_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x220</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST4_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x224</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST5_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x228</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST5_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x22C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST6_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x230</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST6_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x234</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST7_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x238</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST7_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x23C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST8_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST8_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x244</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST9_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x248</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST9_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x24C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST10_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x250</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST10_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x254</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST11_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x258</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST11_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x25C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST12_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x260</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST12_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x264</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST13_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x268</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST13_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x26C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST14_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x270</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST14_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x274</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST15_TCONFA</name>
|
|
<description>State transition configuration A</description>
|
|
<addressOffset>0x278</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00057FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Enable state descriptor chaining</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST15_TCONFB</name>
|
|
<description>State transition configuration B</description>
|
|
<addressOffset>0x27C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00017FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Sensor compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Sensor mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTSTATE</name>
|
|
<description>Next state index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSACT</name>
|
|
<description>Configure transition action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Set interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF0_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF1_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x284</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF2_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x288</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF3_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x28C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF4_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x290</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF5_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x294</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF6_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x298</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF7_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x29C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF8_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x2A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF9_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x2A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF10_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x2A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF11_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x2AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF12_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x2B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF13_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x2B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF14_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x2B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUF15_DATA</name>
|
|
<description>Scan results</description>
|
|
<addressOffset>0x2BC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan result buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2F4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x2F8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH4_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH4_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH4_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH5_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH5_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH5_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x318</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH6_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x320</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH6_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x324</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH6_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x328</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH7_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x330</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH7_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x334</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH7_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x338</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH8_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x340</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH8_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x344</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH8_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x348</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH9_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x350</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH9_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x354</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH9_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x358</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH10_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x360</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH10_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x364</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH10_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x368</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH11_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x370</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH11_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x374</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH11_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x378</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH12_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x380</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH12_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x384</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH12_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x388</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH13_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x390</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH13_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x394</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH13_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x398</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH14_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x3A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH14_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x3A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH14_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x3A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH15_TIMING</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x3B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIME</name>
|
|
<description>Set excitation time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLEDLY</name>
|
|
<description>Set sample delay</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEASUREDLY</name>
|
|
<description>Set measure delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH15_INTERACT</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x3B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPTHRES</name>
|
|
<description>Set ACMP threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Select sample mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETIF</name>
|
|
<description>Enable interrupt generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No interrupt is generated</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL</name>
|
|
<description>Set interrupt flag if the sensor triggers.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>Set interrupt flag on positive edge on the sensor state</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>Set interrupt flag on negative edge on the sensor state</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXMODE</name>
|
|
<description>Set GPIO mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>Push Pull, GPIO is driven high</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Push Pull, GPIO is driven low</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACOUT</name>
|
|
<description>DAC output</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXCLK</name>
|
|
<description>Select clock used for excitation timing</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECLK</name>
|
|
<description>Select clock used for timing of sample delay</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALTEX</name>
|
|
<description>Use alternative excite pin</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH15_EVAL</name>
|
|
<description>Scan configuration</description>
|
|
<addressOffset>0x3B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000FFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPTHRES</name>
|
|
<description>Decision threshold for counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Select mode for counter comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECODE</name>
|
|
<description>Send result to decoder</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STRSAMPLE</name>
|
|
<description>Select if counter result should be stored</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANRESINV</name>
|
|
<description>Enable inversion of result</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>RTC</description>
|
|
<baseAddress>0x40080000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>RTC Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGRUN</name>
|
|
<description>Debug Mode Run Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0TOP</name>
|
|
<description>Compare Channel 0 is Top Value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter Value Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00FFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP0</name>
|
|
<description>Compare Value Register 0</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00FFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Compare Value 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP1</name>
|
|
<description>Compare Value Register 1</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00FFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Compare Value 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Compare Match 0 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Compare Match 1 Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Set Overflow Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Set Compare match 0 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Set Compare match 1 Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Clear Overflow Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Clear Compare match 0 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Clear Compare match 1 Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Compare Match 0 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Compare Match 1 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREEZE</name>
|
|
<description>Freeze Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGFREEZE</name>
|
|
<description>Register Update Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>CTRL Register Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>COMP0 Register Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>COMP1 Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LETIMER0</name>
|
|
<description>LETIMER0</description>
|
|
<baseAddress>0x40082000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LETIMER0</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REPMODE</name>
|
|
<description>Repeat Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FREE</name>
|
|
<description>When started, the LETIMER counts down until it is stopped by software.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOT</name>
|
|
<description>The counter counts REP0 times. When REP0 reaches zero, the counter stops.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUFFERED</name>
|
|
<description>The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero. Else the counter stops</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE</name>
|
|
<description>Both REP0 and REP1 are decremented when the LETIMER wraps around. The LETIMER counts until both REP0 and REP1 are zero</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UFOA0</name>
|
|
<description>Underflow Output Action 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>LETn_O0 is held at its idle value as defined by OPOL0.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>LETn_O0 is toggled on CNT underflow.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE</name>
|
|
<description>LETn_O0 is held active for one LFACLKLETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL0.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>LETn_O0 is set idle on CNT underflow, and active on compare match with COMP1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UFOA1</name>
|
|
<description>Underflow Output Action 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>LETn_O1 is held at its idle value as defined by OPOL1.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>LETn_O1 is toggled on CNT underflow.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULSE</name>
|
|
<description>LETn_O1 is held active for one LFACLKLETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL1.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>LETn_O1 is set idle on CNT underflow, and active on compare match with COMP1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPOL0</name>
|
|
<description>Output 0 Polarity</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPOL1</name>
|
|
<description>Output 1 Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFTOP</name>
|
|
<description>Buffered Top</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0TOP</name>
|
|
<description>Compare Value 0 Is Top Value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTCC0TEN</name>
|
|
<description>RTC Compare 0 Trigger Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTCC1TEN</name>
|
|
<description>RTC Compare 1 Trigger Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGRUN</name>
|
|
<description>Debug Mode Run Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start LETIMER</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop LETIMER</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEAR</name>
|
|
<description>Clear LETIMER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTO0</name>
|
|
<description>Clear Toggle Output 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTO1</name>
|
|
<description>Clear Toggle Output 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUNNING</name>
|
|
<description>LETIMER Running</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter Value Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP0</name>
|
|
<description>Compare Value Register 0</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Compare Value 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP1</name>
|
|
<description>Compare Value Register 1</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Compare Value 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REP0</name>
|
|
<description>Repeat Counter Register 0</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REP0</name>
|
|
<description>Repeat Counter 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REP1</name>
|
|
<description>Repeat Counter Register 1</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REP1</name>
|
|
<description>Repeat Counter 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Compare Match 0 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Compare Match 1 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REP0</name>
|
|
<description>Repeat Counter 0 Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REP1</name>
|
|
<description>Repeat Counter 1 Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Set Compare Match 0 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Set Compare Match 1 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Set Underflow Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REP0</name>
|
|
<description>Set Repeat Counter 0 Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REP1</name>
|
|
<description>Set Repeat Counter 1 Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Clear Compare Match 0 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Clear Compare Match 1 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Clear Underflow Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REP0</name>
|
|
<description>Clear Repeat Counter 0 Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REP1</name>
|
|
<description>Clear Repeat Counter 1 Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Compare Match 0 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Compare Match 1 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REP0</name>
|
|
<description>Repeat Counter 0 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REP1</name>
|
|
<description>Repeat Counter 1 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREEZE</name>
|
|
<description>Freeze Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGFREEZE</name>
|
|
<description>Register Update Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>CTRL Register Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>CMD Register Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>COMP0 Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>COMP1 Register Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REP0</name>
|
|
<description>REP0 Register Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REP1</name>
|
|
<description>REP1 Register Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000703</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUT0PEN</name>
|
|
<description>Output 0 Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUT1PEN</name>
|
|
<description>Output 1 Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USART0</name>
|
|
<description>USART0</description>
|
|
<baseAddress>0x4000C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART0_RX</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USART0_TX</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7DFFFF7F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>USART Synchronous Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPBK</name>
|
|
<description>Loopback Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CCEN</name>
|
|
<description>Collision Check Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPM</name>
|
|
<description>Multi-Processor Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAB</name>
|
|
<description>Multi-Processor Address-Bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVS</name>
|
|
<description>Oversampling</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>X16</name>
|
|
<description>Regular UART mode with 16X oversampling in asynchronous mode</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X8</name>
|
|
<description>Double speed with 8X oversampling in asynchronous mode</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X6</name>
|
|
<description>6X oversampling in asynchronous mode</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X4</name>
|
|
<description>Quadruple speed with 4X oversampling in asynchronous mode</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKPHA</name>
|
|
<description>Clock Edge For Setup/Sample</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most Significant Bit First</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSMA</name>
|
|
<description>Action On Slave-Select In Master Mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBIL</name>
|
|
<description>TX Buffer Interrupt Level</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receiver Input Invert</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmitter output Invert</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSINV</name>
|
|
<description>Chip Select Invert</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCS</name>
|
|
<description>Automatic Chip Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTRI</name>
|
|
<description>Automatic TX Tristate</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCMODE</name>
|
|
<description>SmartCard Mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCRETRANS</name>
|
|
<description>SmartCard Retransmit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SKIPPERRF</name>
|
|
<description>Skip Parity Error Frames</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIT8DV</name>
|
|
<description>Bit 8 Default Value</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRSDMA</name>
|
|
<description>Halt DMA On Error</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRSRX</name>
|
|
<description>Disable RX On Error</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRSTX</name>
|
|
<description>Disable TX On Error</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDELAY</name>
|
|
<description>TX Delay Transmission</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Frames are transmitted immediately</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>Transmission of new frames are delayed by a single baud period</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE</name>
|
|
<description>Transmission of new frames are delayed by two baud periods</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIPLE</name>
|
|
<description>Transmission of new frames are delayed by three baud periods</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYTESWAP</name>
|
|
<description>Byteswap In Double Accesses</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTX</name>
|
|
<description>Always Transmit When RX Not Full</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MVDIS</name>
|
|
<description>Majority Vote Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRAME</name>
|
|
<description>USART Frame Format Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00001005</resetValue>
|
|
<resetMask>0x0000330F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATABITS</name>
|
|
<description>Data-Bit Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>Each frame contains 4 data bits</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FIVE</name>
|
|
<description>Each frame contains 5 data bits</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIX</name>
|
|
<description>Each frame contains 6 data bits</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEVEN</name>
|
|
<description>Each frame contains 7 data bits</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EIGHT</name>
|
|
<description>Each frame contains 8 data bits</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NINE</name>
|
|
<description>Each frame contains 9 data bits</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEN</name>
|
|
<description>Each frame contains 10 data bits</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELEVEN</name>
|
|
<description>Each frame contains 11 data bits</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWELVE</name>
|
|
<description>Each frame contains 12 data bits</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THIRTEEN</name>
|
|
<description>Each frame contains 13 data bits</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOURTEEN</name>
|
|
<description>Each frame contains 14 data bits</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FIFTEEN</name>
|
|
<description>Each frame contains 15 data bits</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIXTEEN</name>
|
|
<description>Each frame contains 16 data bits</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PARITY</name>
|
|
<description>Parity-Bit Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Parity bits are not used</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even parity are used. Parity bits are automatically generated and checked by hardware.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd parity is used. Parity bits are automatically generated and checked by hardware.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPBITS</name>
|
|
<description>Stop-Bit Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>The transmitter generates a half stop bit. Stop-bits are not verified by receiver</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>One stop bit is generated and verified</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONEANDAHALF</name>
|
|
<description>The transmitter generates one and a half stop bit. The receiver verifies the first stop bit</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>The transmitter generates two stop bits. The receiver checks the first stop-bit only</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIGCTRL</name>
|
|
<description>USART Trigger Control register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000077</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSEL</name>
|
|
<description>Trigger PRS Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receive Trigger Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmit Trigger Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTXTEN</name>
|
|
<description>AUTOTX Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmitter Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASTEREN</name>
|
|
<description>Master Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASTERDIS</name>
|
|
<description>Master Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCKEN</name>
|
|
<description>Receiver Block Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCKDIS</name>
|
|
<description>Receiver Block Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIEN</name>
|
|
<description>Transmitter Tristate Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIDIS</name>
|
|
<description>Transmitter Tristate Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARTX</name>
|
|
<description>Clear TX</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARRX</name>
|
|
<description>Clear RX</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>USART Status Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000040</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXENS</name>
|
|
<description>Receiver Enable Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXENS</name>
|
|
<description>Transmitter Enable Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASTER</name>
|
|
<description>SPI Master Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCK</name>
|
|
<description>Block Incoming Data</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRI</name>
|
|
<description>Transmitter Tristated</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX FIFO Full</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBDRIGHT</name>
|
|
<description>TX Buffer Expects Double Right Data</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBSRIGHT</name>
|
|
<description>TX Buffer Expects Single Right Data</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAVRIGHT</name>
|
|
<description>RX Data Right</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULLRIGHT</name>
|
|
<description>RX Full of Right Data</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Control Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x001FFFC0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Fractional Clock Divider</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAX</name>
|
|
<description>RX Buffer Data Extended Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000C1FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Data Parity Error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Data Framing Error</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATA</name>
|
|
<description>RX Buffer Data Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDOUBLEX</name>
|
|
<description>RX Buffer Double Data Extended Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xC1FFC1FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA0</name>
|
|
<description>RX Data 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR0</name>
|
|
<description>Data Parity Error 0</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR0</name>
|
|
<description>Data Framing Error 0</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATA1</name>
|
|
<description>RX Data 1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR1</name>
|
|
<description>Data Parity Error 1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR1</name>
|
|
<description>Data Framing Error 1</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDOUBLE</name>
|
|
<description>RX FIFO Double Data Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA0</name>
|
|
<description>RX Data 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATA1</name>
|
|
<description>RX Data 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAXP</name>
|
|
<description>RX Buffer Data Extended Peek Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000C1FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATAP</name>
|
|
<description>RX Data Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRP</name>
|
|
<description>Data Parity Error Peek</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRP</name>
|
|
<description>Data Framing Error Peek</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDOUBLEXP</name>
|
|
<description>RX Buffer Double Data Extended Peek Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xC1FFC1FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATAP0</name>
|
|
<description>RX Data 0 Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRP0</name>
|
|
<description>Data Parity Error 0 Peek</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRP0</name>
|
|
<description>Data Framing Error 0 Peek</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAP1</name>
|
|
<description>RX Data 1 Peek</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRP1</name>
|
|
<description>Data Parity Error 1 Peek</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRP1</name>
|
|
<description>Data Framing Error 1 Peek</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATAX</name>
|
|
<description>TX Buffer Data Extended Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000F9FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATAX</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UBRXAT</name>
|
|
<description>Unblock RX After Transmission</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIAT</name>
|
|
<description>Set TXTRI After Transmission</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBREAK</name>
|
|
<description>Transmit Data As Break</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDISAT</name>
|
|
<description>Clear TXEN After Transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXENAT</name>
|
|
<description>Enable RX After Transmission</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATA</name>
|
|
<description>TX Buffer Data Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDOUBLEX</name>
|
|
<description>TX Buffer Double Data Extended Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xF9FFF9FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA0</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UBRXAT0</name>
|
|
<description>Unblock RX After Transmission</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIAT0</name>
|
|
<description>Set TXTRI After Transmission</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBREAK0</name>
|
|
<description>Transmit Data As Break</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDISAT0</name>
|
|
<description>Clear TXEN After Transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXENAT0</name>
|
|
<description>Enable RX After Transmission</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDATA1</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UBRXAT1</name>
|
|
<description>Unblock RX After Transmission</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIAT1</name>
|
|
<description>Set TXTRI After Transmission</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBREAK1</name>
|
|
<description>Transmit Data As Break</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDISAT1</name>
|
|
<description>Clear TXEN After Transmission</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXENAT1</name>
|
|
<description>Enable RX After Transmission</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDOUBLE</name>
|
|
<description>TX Buffer Double Data Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA0</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDATA1</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX Buffer Full Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>RX Overflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>RX Underflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>TX Overflow Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>TX Underflow Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Framing Error Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Slave-Select In Master Mode Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Collision Check Fail Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FF9</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Set TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>Set RX Buffer Full Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>Set RX Overflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Set RX Underflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Set TX Overflow Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>Set TX Underflow Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Set Parity Error Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Set Framing Error Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Set Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Set Slave-Select in Master mode Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Set Collision Check Fail Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FF9</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Clear TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>Clear RX Buffer Full Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>Clear RX Overflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Clear RX Underflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Clear TX Overflow Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>Clear TX Underflow Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Clear Parity Error Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Clear Framing Error Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Clear Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Clear Slave-Select In Master Mode Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Clear Collision Check Fail Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX Buffer Full Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>RX Overflow Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>RX Underflow Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>TX Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>TX Underflow Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Multi-Processor Address Frame Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Slave-Select In Master Mode Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Collision Check Fail Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRCTRL</name>
|
|
<description>IrDA Control Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Enable IrDA Module</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRPW</name>
|
|
<description>IrDA TX Pulse Width</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THREE</name>
|
|
<description>IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRFILT</name>
|
|
<description>IrDA RX Filter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRPRSSEL</name>
|
|
<description>IrDA PRS Channel Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRPRSEN</name>
|
|
<description>IrDA PRS Channel Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000070F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPEN</name>
|
|
<description>RX Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPEN</name>
|
|
<description>TX Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSPEN</name>
|
|
<description>CS Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKPEN</name>
|
|
<description>CLK Pin Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC4</name>
|
|
<description>Location 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC5</name>
|
|
<description>Location 5</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUT</name>
|
|
<description>USART Input Register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPRSSEL</name>
|
|
<description>RX PRS Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXPRS</name>
|
|
<description>PRS RX Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SCTRL</name>
|
|
<description>I2S Control Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000071F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enable I2S Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MONO</name>
|
|
<description>Stero or Mono</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>JUSTIFY</name>
|
|
<description>Justification of I2S Data</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMASPLIT</name>
|
|
<description>Separate DMA Request For Left/Right Data</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DELAY</name>
|
|
<description>Delay on I2S data</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FORMAT</name>
|
|
<description>I2S Word Format</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>W32D32</name>
|
|
<description>32-bit word, 32-bit data</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D24M</name>
|
|
<description>32-bit word, 32-bit data with 8 lsb masked</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D24</name>
|
|
<description>32-bit word, 24-bit data</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D16</name>
|
|
<description>32-bit word, 16-bit data</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D8</name>
|
|
<description>32-bit word, 8-bit data</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W16D16</name>
|
|
<description>16-bit word, 16-bit data</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W16D8</name>
|
|
<description>16-bit word, 8-bit data</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W8D8</name>
|
|
<description>8-bit word, 8-bit data</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USART1</name>
|
|
<description>USART1</description>
|
|
<baseAddress>0x4000C400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART1_RX</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USART1_TX</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7DFFFF7F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>USART Synchronous Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPBK</name>
|
|
<description>Loopback Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CCEN</name>
|
|
<description>Collision Check Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPM</name>
|
|
<description>Multi-Processor Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAB</name>
|
|
<description>Multi-Processor Address-Bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVS</name>
|
|
<description>Oversampling</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>X16</name>
|
|
<description>Regular UART mode with 16X oversampling in asynchronous mode</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X8</name>
|
|
<description>Double speed with 8X oversampling in asynchronous mode</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X6</name>
|
|
<description>6X oversampling in asynchronous mode</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X4</name>
|
|
<description>Quadruple speed with 4X oversampling in asynchronous mode</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKPHA</name>
|
|
<description>Clock Edge For Setup/Sample</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most Significant Bit First</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSMA</name>
|
|
<description>Action On Slave-Select In Master Mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBIL</name>
|
|
<description>TX Buffer Interrupt Level</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receiver Input Invert</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmitter output Invert</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSINV</name>
|
|
<description>Chip Select Invert</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCS</name>
|
|
<description>Automatic Chip Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTRI</name>
|
|
<description>Automatic TX Tristate</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCMODE</name>
|
|
<description>SmartCard Mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCRETRANS</name>
|
|
<description>SmartCard Retransmit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SKIPPERRF</name>
|
|
<description>Skip Parity Error Frames</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIT8DV</name>
|
|
<description>Bit 8 Default Value</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRSDMA</name>
|
|
<description>Halt DMA On Error</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRSRX</name>
|
|
<description>Disable RX On Error</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRSTX</name>
|
|
<description>Disable TX On Error</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDELAY</name>
|
|
<description>TX Delay Transmission</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Frames are transmitted immediately</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>Transmission of new frames are delayed by a single baud period</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE</name>
|
|
<description>Transmission of new frames are delayed by two baud periods</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIPLE</name>
|
|
<description>Transmission of new frames are delayed by three baud periods</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYTESWAP</name>
|
|
<description>Byteswap In Double Accesses</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTX</name>
|
|
<description>Always Transmit When RX Not Full</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MVDIS</name>
|
|
<description>Majority Vote Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRAME</name>
|
|
<description>USART Frame Format Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00001005</resetValue>
|
|
<resetMask>0x0000330F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATABITS</name>
|
|
<description>Data-Bit Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>Each frame contains 4 data bits</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FIVE</name>
|
|
<description>Each frame contains 5 data bits</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIX</name>
|
|
<description>Each frame contains 6 data bits</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEVEN</name>
|
|
<description>Each frame contains 7 data bits</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EIGHT</name>
|
|
<description>Each frame contains 8 data bits</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NINE</name>
|
|
<description>Each frame contains 9 data bits</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEN</name>
|
|
<description>Each frame contains 10 data bits</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELEVEN</name>
|
|
<description>Each frame contains 11 data bits</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWELVE</name>
|
|
<description>Each frame contains 12 data bits</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THIRTEEN</name>
|
|
<description>Each frame contains 13 data bits</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOURTEEN</name>
|
|
<description>Each frame contains 14 data bits</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FIFTEEN</name>
|
|
<description>Each frame contains 15 data bits</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIXTEEN</name>
|
|
<description>Each frame contains 16 data bits</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PARITY</name>
|
|
<description>Parity-Bit Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Parity bits are not used</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even parity are used. Parity bits are automatically generated and checked by hardware.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd parity is used. Parity bits are automatically generated and checked by hardware.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPBITS</name>
|
|
<description>Stop-Bit Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>The transmitter generates a half stop bit. Stop-bits are not verified by receiver</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>One stop bit is generated and verified</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONEANDAHALF</name>
|
|
<description>The transmitter generates one and a half stop bit. The receiver verifies the first stop bit</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>The transmitter generates two stop bits. The receiver checks the first stop-bit only</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIGCTRL</name>
|
|
<description>USART Trigger Control register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000077</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSEL</name>
|
|
<description>Trigger PRS Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receive Trigger Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmit Trigger Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTXTEN</name>
|
|
<description>AUTOTX Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmitter Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASTEREN</name>
|
|
<description>Master Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASTERDIS</name>
|
|
<description>Master Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCKEN</name>
|
|
<description>Receiver Block Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCKDIS</name>
|
|
<description>Receiver Block Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIEN</name>
|
|
<description>Transmitter Tristate Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIDIS</name>
|
|
<description>Transmitter Tristate Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARTX</name>
|
|
<description>Clear TX</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARRX</name>
|
|
<description>Clear RX</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>USART Status Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000040</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXENS</name>
|
|
<description>Receiver Enable Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXENS</name>
|
|
<description>Transmitter Enable Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASTER</name>
|
|
<description>SPI Master Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCK</name>
|
|
<description>Block Incoming Data</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRI</name>
|
|
<description>Transmitter Tristated</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX FIFO Full</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBDRIGHT</name>
|
|
<description>TX Buffer Expects Double Right Data</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBSRIGHT</name>
|
|
<description>TX Buffer Expects Single Right Data</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAVRIGHT</name>
|
|
<description>RX Data Right</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULLRIGHT</name>
|
|
<description>RX Full of Right Data</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Control Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x001FFFC0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Fractional Clock Divider</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAX</name>
|
|
<description>RX Buffer Data Extended Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000C1FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Data Parity Error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Data Framing Error</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATA</name>
|
|
<description>RX Buffer Data Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDOUBLEX</name>
|
|
<description>RX Buffer Double Data Extended Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xC1FFC1FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA0</name>
|
|
<description>RX Data 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR0</name>
|
|
<description>Data Parity Error 0</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR0</name>
|
|
<description>Data Framing Error 0</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATA1</name>
|
|
<description>RX Data 1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR1</name>
|
|
<description>Data Parity Error 1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR1</name>
|
|
<description>Data Framing Error 1</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDOUBLE</name>
|
|
<description>RX FIFO Double Data Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA0</name>
|
|
<description>RX Data 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATA1</name>
|
|
<description>RX Data 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAXP</name>
|
|
<description>RX Buffer Data Extended Peek Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000C1FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATAP</name>
|
|
<description>RX Data Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRP</name>
|
|
<description>Data Parity Error Peek</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRP</name>
|
|
<description>Data Framing Error Peek</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDOUBLEXP</name>
|
|
<description>RX Buffer Double Data Extended Peek Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xC1FFC1FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATAP0</name>
|
|
<description>RX Data 0 Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRP0</name>
|
|
<description>Data Parity Error 0 Peek</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRP0</name>
|
|
<description>Data Framing Error 0 Peek</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAP1</name>
|
|
<description>RX Data 1 Peek</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRP1</name>
|
|
<description>Data Parity Error 1 Peek</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRP1</name>
|
|
<description>Data Framing Error 1 Peek</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATAX</name>
|
|
<description>TX Buffer Data Extended Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000F9FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATAX</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UBRXAT</name>
|
|
<description>Unblock RX After Transmission</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIAT</name>
|
|
<description>Set TXTRI After Transmission</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBREAK</name>
|
|
<description>Transmit Data As Break</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDISAT</name>
|
|
<description>Clear TXEN After Transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXENAT</name>
|
|
<description>Enable RX After Transmission</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATA</name>
|
|
<description>TX Buffer Data Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDOUBLEX</name>
|
|
<description>TX Buffer Double Data Extended Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xF9FFF9FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA0</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UBRXAT0</name>
|
|
<description>Unblock RX After Transmission</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIAT0</name>
|
|
<description>Set TXTRI After Transmission</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBREAK0</name>
|
|
<description>Transmit Data As Break</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDISAT0</name>
|
|
<description>Clear TXEN After Transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXENAT0</name>
|
|
<description>Enable RX After Transmission</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDATA1</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UBRXAT1</name>
|
|
<description>Unblock RX After Transmission</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIAT1</name>
|
|
<description>Set TXTRI After Transmission</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBREAK1</name>
|
|
<description>Transmit Data As Break</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDISAT1</name>
|
|
<description>Clear TXEN After Transmission</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXENAT1</name>
|
|
<description>Enable RX After Transmission</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDOUBLE</name>
|
|
<description>TX Buffer Double Data Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA0</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDATA1</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX Buffer Full Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>RX Overflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>RX Underflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>TX Overflow Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>TX Underflow Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Framing Error Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Slave-Select In Master Mode Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Collision Check Fail Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FF9</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Set TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>Set RX Buffer Full Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>Set RX Overflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Set RX Underflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Set TX Overflow Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>Set TX Underflow Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Set Parity Error Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Set Framing Error Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Set Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Set Slave-Select in Master mode Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Set Collision Check Fail Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FF9</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Clear TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>Clear RX Buffer Full Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>Clear RX Overflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Clear RX Underflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Clear TX Overflow Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>Clear TX Underflow Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Clear Parity Error Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Clear Framing Error Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Clear Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Clear Slave-Select In Master Mode Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Clear Collision Check Fail Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX Buffer Full Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>RX Overflow Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>RX Underflow Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>TX Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>TX Underflow Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Multi-Processor Address Frame Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Slave-Select In Master Mode Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Collision Check Fail Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRCTRL</name>
|
|
<description>IrDA Control Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Enable IrDA Module</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRPW</name>
|
|
<description>IrDA TX Pulse Width</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THREE</name>
|
|
<description>IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRFILT</name>
|
|
<description>IrDA RX Filter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRPRSSEL</name>
|
|
<description>IrDA PRS Channel Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRPRSEN</name>
|
|
<description>IrDA PRS Channel Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000070F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPEN</name>
|
|
<description>RX Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPEN</name>
|
|
<description>TX Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSPEN</name>
|
|
<description>CS Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKPEN</name>
|
|
<description>CLK Pin Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC4</name>
|
|
<description>Location 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC5</name>
|
|
<description>Location 5</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUT</name>
|
|
<description>USART Input Register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPRSSEL</name>
|
|
<description>RX PRS Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXPRS</name>
|
|
<description>PRS RX Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SCTRL</name>
|
|
<description>I2S Control Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000071F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enable I2S Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MONO</name>
|
|
<description>Stero or Mono</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>JUSTIFY</name>
|
|
<description>Justification of I2S Data</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMASPLIT</name>
|
|
<description>Separate DMA Request For Left/Right Data</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DELAY</name>
|
|
<description>Delay on I2S data</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FORMAT</name>
|
|
<description>I2S Word Format</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>W32D32</name>
|
|
<description>32-bit word, 32-bit data</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D24M</name>
|
|
<description>32-bit word, 32-bit data with 8 lsb masked</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D24</name>
|
|
<description>32-bit word, 24-bit data</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D16</name>
|
|
<description>32-bit word, 16-bit data</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D8</name>
|
|
<description>32-bit word, 8-bit data</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W16D16</name>
|
|
<description>16-bit word, 16-bit data</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W16D8</name>
|
|
<description>16-bit word, 8-bit data</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W8D8</name>
|
|
<description>8-bit word, 8-bit data</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USART2</name>
|
|
<description>USART2</description>
|
|
<baseAddress>0x4000C800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART2_RX</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USART2_TX</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7DFFFF7F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>USART Synchronous Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPBK</name>
|
|
<description>Loopback Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CCEN</name>
|
|
<description>Collision Check Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPM</name>
|
|
<description>Multi-Processor Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAB</name>
|
|
<description>Multi-Processor Address-Bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVS</name>
|
|
<description>Oversampling</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>X16</name>
|
|
<description>Regular UART mode with 16X oversampling in asynchronous mode</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X8</name>
|
|
<description>Double speed with 8X oversampling in asynchronous mode</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X6</name>
|
|
<description>6X oversampling in asynchronous mode</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X4</name>
|
|
<description>Quadruple speed with 4X oversampling in asynchronous mode</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKPHA</name>
|
|
<description>Clock Edge For Setup/Sample</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most Significant Bit First</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSMA</name>
|
|
<description>Action On Slave-Select In Master Mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBIL</name>
|
|
<description>TX Buffer Interrupt Level</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receiver Input Invert</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmitter output Invert</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSINV</name>
|
|
<description>Chip Select Invert</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOCS</name>
|
|
<description>Automatic Chip Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTRI</name>
|
|
<description>Automatic TX Tristate</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCMODE</name>
|
|
<description>SmartCard Mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCRETRANS</name>
|
|
<description>SmartCard Retransmit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SKIPPERRF</name>
|
|
<description>Skip Parity Error Frames</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIT8DV</name>
|
|
<description>Bit 8 Default Value</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRSDMA</name>
|
|
<description>Halt DMA On Error</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRSRX</name>
|
|
<description>Disable RX On Error</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRSTX</name>
|
|
<description>Disable TX On Error</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDELAY</name>
|
|
<description>TX Delay Transmission</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Frames are transmitted immediately</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>Transmission of new frames are delayed by a single baud period</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE</name>
|
|
<description>Transmission of new frames are delayed by two baud periods</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIPLE</name>
|
|
<description>Transmission of new frames are delayed by three baud periods</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYTESWAP</name>
|
|
<description>Byteswap In Double Accesses</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTX</name>
|
|
<description>Always Transmit When RX Not Full</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MVDIS</name>
|
|
<description>Majority Vote Disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRAME</name>
|
|
<description>USART Frame Format Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00001005</resetValue>
|
|
<resetMask>0x0000330F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATABITS</name>
|
|
<description>Data-Bit Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>Each frame contains 4 data bits</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FIVE</name>
|
|
<description>Each frame contains 5 data bits</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIX</name>
|
|
<description>Each frame contains 6 data bits</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEVEN</name>
|
|
<description>Each frame contains 7 data bits</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EIGHT</name>
|
|
<description>Each frame contains 8 data bits</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NINE</name>
|
|
<description>Each frame contains 9 data bits</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEN</name>
|
|
<description>Each frame contains 10 data bits</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELEVEN</name>
|
|
<description>Each frame contains 11 data bits</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWELVE</name>
|
|
<description>Each frame contains 12 data bits</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THIRTEEN</name>
|
|
<description>Each frame contains 13 data bits</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOURTEEN</name>
|
|
<description>Each frame contains 14 data bits</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FIFTEEN</name>
|
|
<description>Each frame contains 15 data bits</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIXTEEN</name>
|
|
<description>Each frame contains 16 data bits</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PARITY</name>
|
|
<description>Parity-Bit Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Parity bits are not used</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even parity are used. Parity bits are automatically generated and checked by hardware.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd parity is used. Parity bits are automatically generated and checked by hardware.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPBITS</name>
|
|
<description>Stop-Bit Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>The transmitter generates a half stop bit. Stop-bits are not verified by receiver</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>One stop bit is generated and verified</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONEANDAHALF</name>
|
|
<description>The transmitter generates one and a half stop bit. The receiver verifies the first stop bit</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>The transmitter generates two stop bits. The receiver checks the first stop-bit only</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIGCTRL</name>
|
|
<description>USART Trigger Control register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000077</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSEL</name>
|
|
<description>Trigger PRS Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXTEN</name>
|
|
<description>Receive Trigger Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTEN</name>
|
|
<description>Transmit Trigger Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTXTEN</name>
|
|
<description>AUTOTX Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmitter Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASTEREN</name>
|
|
<description>Master Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASTERDIS</name>
|
|
<description>Master Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCKEN</name>
|
|
<description>Receiver Block Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCKDIS</name>
|
|
<description>Receiver Block Disable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIEN</name>
|
|
<description>Transmitter Tristate Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIDIS</name>
|
|
<description>Transmitter Tristate Disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARTX</name>
|
|
<description>Clear TX</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARRX</name>
|
|
<description>Clear RX</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>USART Status Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000040</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXENS</name>
|
|
<description>Receiver Enable Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXENS</name>
|
|
<description>Transmitter Enable Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASTER</name>
|
|
<description>SPI Master Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCK</name>
|
|
<description>Block Incoming Data</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRI</name>
|
|
<description>Transmitter Tristated</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX FIFO Full</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBDRIGHT</name>
|
|
<description>TX Buffer Expects Double Right Data</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBSRIGHT</name>
|
|
<description>TX Buffer Expects Single Right Data</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAVRIGHT</name>
|
|
<description>RX Data Right</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULLRIGHT</name>
|
|
<description>RX Full of Right Data</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Control Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x001FFFC0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Fractional Clock Divider</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAX</name>
|
|
<description>RX Buffer Data Extended Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000C1FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Data Parity Error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Data Framing Error</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATA</name>
|
|
<description>RX Buffer Data Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDOUBLEX</name>
|
|
<description>RX Buffer Double Data Extended Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xC1FFC1FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA0</name>
|
|
<description>RX Data 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR0</name>
|
|
<description>Data Parity Error 0</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR0</name>
|
|
<description>Data Framing Error 0</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATA1</name>
|
|
<description>RX Data 1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR1</name>
|
|
<description>Data Parity Error 1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR1</name>
|
|
<description>Data Framing Error 1</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDOUBLE</name>
|
|
<description>RX FIFO Double Data Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA0</name>
|
|
<description>RX Data 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATA1</name>
|
|
<description>RX Data 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAXP</name>
|
|
<description>RX Buffer Data Extended Peek Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000C1FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATAP</name>
|
|
<description>RX Data Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRP</name>
|
|
<description>Data Parity Error Peek</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRP</name>
|
|
<description>Data Framing Error Peek</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDOUBLEXP</name>
|
|
<description>RX Buffer Double Data Extended Peek Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xC1FFC1FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATAP0</name>
|
|
<description>RX Data 0 Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRP0</name>
|
|
<description>Data Parity Error 0 Peek</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRP0</name>
|
|
<description>Data Framing Error 0 Peek</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAP1</name>
|
|
<description>RX Data 1 Peek</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRP1</name>
|
|
<description>Data Parity Error 1 Peek</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRP1</name>
|
|
<description>Data Framing Error 1 Peek</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATAX</name>
|
|
<description>TX Buffer Data Extended Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000F9FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATAX</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UBRXAT</name>
|
|
<description>Unblock RX After Transmission</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIAT</name>
|
|
<description>Set TXTRI After Transmission</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBREAK</name>
|
|
<description>Transmit Data As Break</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDISAT</name>
|
|
<description>Clear TXEN After Transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXENAT</name>
|
|
<description>Enable RX After Transmission</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATA</name>
|
|
<description>TX Buffer Data Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDOUBLEX</name>
|
|
<description>TX Buffer Double Data Extended Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xF9FFF9FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA0</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UBRXAT0</name>
|
|
<description>Unblock RX After Transmission</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIAT0</name>
|
|
<description>Set TXTRI After Transmission</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBREAK0</name>
|
|
<description>Transmit Data As Break</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDISAT0</name>
|
|
<description>Clear TXEN After Transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXENAT0</name>
|
|
<description>Enable RX After Transmission</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDATA1</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UBRXAT1</name>
|
|
<description>Unblock RX After Transmission</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXTRIAT1</name>
|
|
<description>Set TXTRI After Transmission</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBREAK1</name>
|
|
<description>Transmit Data As Break</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDISAT1</name>
|
|
<description>Clear TXEN After Transmission</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXENAT1</name>
|
|
<description>Enable RX After Transmission</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDOUBLE</name>
|
|
<description>TX Buffer Double Data Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA0</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDATA1</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX Buffer Full Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>RX Overflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>RX Underflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>TX Overflow Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>TX Underflow Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Framing Error Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Slave-Select In Master Mode Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Collision Check Fail Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FF9</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Set TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>Set RX Buffer Full Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>Set RX Overflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Set RX Underflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Set TX Overflow Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>Set TX Underflow Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Set Parity Error Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Set Framing Error Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Set Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Set Slave-Select in Master mode Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Set Collision Check Fail Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FF9</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Clear TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>Clear RX Buffer Full Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>Clear RX Overflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Clear RX Underflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Clear TX Overflow Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>Clear TX Underflow Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Clear Parity Error Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Clear Framing Error Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Clear Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Clear Slave-Select In Master Mode Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Clear Collision Check Fail Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00001FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFULL</name>
|
|
<description>RX Buffer Full Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>RX Overflow Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>RX Underflow Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>TX Overflow Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXUF</name>
|
|
<description>TX Underflow Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Multi-Processor Address Frame Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Slave-Select In Master Mode Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CCF</name>
|
|
<description>Collision Check Fail Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRCTRL</name>
|
|
<description>IrDA Control Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Enable IrDA Module</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRPW</name>
|
|
<description>IrDA TX Pulse Width</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THREE</name>
|
|
<description>IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FOUR</name>
|
|
<description>IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRFILT</name>
|
|
<description>IrDA RX Filter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRPRSSEL</name>
|
|
<description>IrDA PRS Channel Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRPRSEN</name>
|
|
<description>IrDA PRS Channel Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000070F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPEN</name>
|
|
<description>RX Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPEN</name>
|
|
<description>TX Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSPEN</name>
|
|
<description>CS Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKPEN</name>
|
|
<description>CLK Pin Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC4</name>
|
|
<description>Location 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC5</name>
|
|
<description>Location 5</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUT</name>
|
|
<description>USART Input Register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPRSSEL</name>
|
|
<description>RX PRS Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXPRS</name>
|
|
<description>PRS RX Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SCTRL</name>
|
|
<description>I2S Control Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000071F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enable I2S Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MONO</name>
|
|
<description>Stero or Mono</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>JUSTIFY</name>
|
|
<description>Justification of I2S Data</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMASPLIT</name>
|
|
<description>Separate DMA Request For Left/Right Data</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DELAY</name>
|
|
<description>Delay on I2S data</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FORMAT</name>
|
|
<description>I2S Word Format</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>W32D32</name>
|
|
<description>32-bit word, 32-bit data</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D24M</name>
|
|
<description>32-bit word, 32-bit data with 8 lsb masked</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D24</name>
|
|
<description>32-bit word, 24-bit data</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D16</name>
|
|
<description>32-bit word, 16-bit data</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W32D8</name>
|
|
<description>32-bit word, 8-bit data</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W16D16</name>
|
|
<description>16-bit word, 16-bit data</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W16D8</name>
|
|
<description>16-bit word, 8-bit data</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>W8D8</name>
|
|
<description>8-bit word, 8-bit data</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER0</name>
|
|
<description>TIMER0</description>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER0</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x3F032FFB</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Timer Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>Up-count mode</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOWN</name>
|
|
<description>Down-count mode</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDOWN</name>
|
|
<description>Up/down-count mode</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QDEC</name>
|
|
<description>Quadrature decoder mode</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Timer Start/Stop/Reload Synchronization</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSMEN</name>
|
|
<description>One-shot Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>QDM</name>
|
|
<description>Quadrature Decoder Mode Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGRUN</name>
|
|
<description>Debug Mode Run Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMACLRACT</name>
|
|
<description>DMA Request Clear on Active</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RISEA</name>
|
|
<description>Timer Rising Input Edge Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start counter without reload</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop counter without reload</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOADSTART</name>
|
|
<description>Reload and start counter</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FALLA</name>
|
|
<description>Timer Falling Input Edge Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start counter without reload</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop counter without reload</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOADSTART</name>
|
|
<description>Reload and start counter</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>X2CNT</name>
|
|
<description>2x Count Mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Clock Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRESCHFPERCLK</name>
|
|
<description>Prescaled HFPERCLK</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Compare/Capture Channel 1 Input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMEROUF</name>
|
|
<description>Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Prescaler Setting</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>The HFPERCLK is undivided</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>The HFPERCLK is divided by 2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>The HFPERCLK is divided by 4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>The HFPERCLK is divided by 8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>The HFPERCLK is divided by 16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>The HFPERCLK is divided by 32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>The HFPERCLK is divided by 64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>The HFPERCLK is divided by 128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>The HFPERCLK is divided by 256</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>The HFPERCLK is divided by 512</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>The HFPERCLK is divided by 1024</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATI</name>
|
|
<description>Always Track Inputs</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSSCOIST</name>
|
|
<description>Reload-Start Sets Compare Output initial State</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start Timer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Timer</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07070707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUNNING</name>
|
|
<description>Running</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOPBV</name>
|
|
<description>TOPB Valid</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV0</name>
|
|
<description>CC0 CCVB Valid</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV1</name>
|
|
<description>CC1 CCVB Valid</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV2</name>
|
|
<description>CC2 CCVB Valid</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV0</name>
|
|
<description>CC0 Input Capture Valid</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV1</name>
|
|
<description>CC1 Input Capture Valid</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV2</name>
|
|
<description>CC2 Input Capture Valid</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL0</name>
|
|
<description>CC0 Polarity</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL1</name>
|
|
<description>CC1 Polarity</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL2</name>
|
|
<description>CC2 Polarity</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOP</name>
|
|
<description>Counter Top Value Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOP</name>
|
|
<description>Counter Top Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOPB</name>
|
|
<description>Counter Top Value Buffer Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOPB</name>
|
|
<description>Counter Top Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter Value Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00070707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC0PEN</name>
|
|
<description>CC Channel 0 Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1PEN</name>
|
|
<description>CC Channel 1 Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2PEN</name>
|
|
<description>CC Channel 2 Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI0PEN</name>
|
|
<description>CC Channel 0 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI1PEN</name>
|
|
<description>CC Channel 1 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI2PEN</name>
|
|
<description>CC Channel 2 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC4</name>
|
|
<description>Location 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC5</name>
|
|
<description>Location 5</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTCTRL</name>
|
|
<description>DTI Control Register</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x010000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTEN</name>
|
|
<description>DTI Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDAS</name>
|
|
<description>DTI Automatic Start-up Functionality</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTIPOL</name>
|
|
<description>DTI Inactive Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTCINV</name>
|
|
<description>DTI Complementary Output Invert.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSSEL</name>
|
|
<description>DTI PRS Source Channel Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSEN</name>
|
|
<description>DTI PRS Source Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTTIME</name>
|
|
<description>DTI Time Control Register</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F3F0F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRESC</name>
|
|
<description>DTI Prescaler Setting</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>The HFPERCLK is undivided</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>The HFPERCLK is divided by 2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>The HFPERCLK is divided by 4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>The HFPERCLK is divided by 8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>The HFPERCLK is divided by 16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>The HFPERCLK is divided by 32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>The HFPERCLK is divided by 64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>The HFPERCLK is divided by 128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>The HFPERCLK is divided by 256</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>The HFPERCLK is divided by 512</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>The HFPERCLK is divided by 1024</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTRISET</name>
|
|
<description>DTI Rise-time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTFALLT</name>
|
|
<description>DTI Fall-time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFC</name>
|
|
<description>DTI Fault Configuration Register</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F030707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0FSEL</name>
|
|
<description>DTI PRS Fault Source 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as fault source 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as fault source 0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as fault source 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as fault source 0</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as fault source 0</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as fault source 0</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as fault source 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as fault source 0</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FSEL</name>
|
|
<description>DTI PRS Fault Source 1 Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as fault source 1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as fault source 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as fault source 1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as fault source 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as fault source 1</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as fault source 1</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as fault source 1</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as fault source 1</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTFA</name>
|
|
<description>DTI Fault Action</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on fault</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Set outputs inactive</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear outputs</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRISTATE</name>
|
|
<description>Tristate outputs</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS0FEN</name>
|
|
<description>DTI PRS 0 Fault Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FEN</name>
|
|
<description>DTI PRS 1 Fault Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGFEN</name>
|
|
<description>DTI Debugger Fault Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLOCKUPFEN</name>
|
|
<description>DTI Lockup Fault Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTOGEN</name>
|
|
<description>DTI Output Generation Enable Register</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTOGCC0EN</name>
|
|
<description>DTI CC0 Output Generation Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCC1EN</name>
|
|
<description>DTI CC1 Output Generation Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCC2EN</name>
|
|
<description>DTI CC2 Output Generation Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI0EN</name>
|
|
<description>DTI CDTI0 Output Generation Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI1EN</name>
|
|
<description>DTI CDTI1 Output Generation Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI2EN</name>
|
|
<description>DTI CDTI2 Output Generation Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFAULT</name>
|
|
<description>DTI Fault Register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0F</name>
|
|
<description>DTI PRS 0 Fault</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1F</name>
|
|
<description>DTI PRS 1 Fault</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGF</name>
|
|
<description>DTI Debugger Fault</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLOCKUPF</name>
|
|
<description>DTI Lockup Fault</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFAULTC</name>
|
|
<description>DTI Fault Clear Register</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0FC</name>
|
|
<description>DTI PRS0 Fault Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FC</name>
|
|
<description>DTI PRS1 Fault Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGFC</name>
|
|
<description>DTI Debugger Fault Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TLOCKUPFC</name>
|
|
<description>DTI Lockup Fault Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTLOCK</name>
|
|
<description>DTI Configuration Lock Register</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKKEY</name>
|
|
<description>DTI Lock Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER1</name>
|
|
<description>TIMER1</description>
|
|
<baseAddress>0x40010400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER1</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x3F032FFB</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Timer Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>Up-count mode</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOWN</name>
|
|
<description>Down-count mode</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDOWN</name>
|
|
<description>Up/down-count mode</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QDEC</name>
|
|
<description>Quadrature decoder mode</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Timer Start/Stop/Reload Synchronization</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSMEN</name>
|
|
<description>One-shot Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>QDM</name>
|
|
<description>Quadrature Decoder Mode Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGRUN</name>
|
|
<description>Debug Mode Run Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMACLRACT</name>
|
|
<description>DMA Request Clear on Active</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RISEA</name>
|
|
<description>Timer Rising Input Edge Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start counter without reload</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop counter without reload</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOADSTART</name>
|
|
<description>Reload and start counter</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FALLA</name>
|
|
<description>Timer Falling Input Edge Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start counter without reload</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop counter without reload</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOADSTART</name>
|
|
<description>Reload and start counter</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>X2CNT</name>
|
|
<description>2x Count Mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Clock Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRESCHFPERCLK</name>
|
|
<description>Prescaled HFPERCLK</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Compare/Capture Channel 1 Input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMEROUF</name>
|
|
<description>Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Prescaler Setting</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>The HFPERCLK is undivided</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>The HFPERCLK is divided by 2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>The HFPERCLK is divided by 4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>The HFPERCLK is divided by 8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>The HFPERCLK is divided by 16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>The HFPERCLK is divided by 32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>The HFPERCLK is divided by 64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>The HFPERCLK is divided by 128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>The HFPERCLK is divided by 256</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>The HFPERCLK is divided by 512</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>The HFPERCLK is divided by 1024</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATI</name>
|
|
<description>Always Track Inputs</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSSCOIST</name>
|
|
<description>Reload-Start Sets Compare Output initial State</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start Timer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Timer</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07070707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUNNING</name>
|
|
<description>Running</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOPBV</name>
|
|
<description>TOPB Valid</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV0</name>
|
|
<description>CC0 CCVB Valid</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV1</name>
|
|
<description>CC1 CCVB Valid</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV2</name>
|
|
<description>CC2 CCVB Valid</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV0</name>
|
|
<description>CC0 Input Capture Valid</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV1</name>
|
|
<description>CC1 Input Capture Valid</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV2</name>
|
|
<description>CC2 Input Capture Valid</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL0</name>
|
|
<description>CC0 Polarity</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL1</name>
|
|
<description>CC1 Polarity</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL2</name>
|
|
<description>CC2 Polarity</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOP</name>
|
|
<description>Counter Top Value Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOP</name>
|
|
<description>Counter Top Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOPB</name>
|
|
<description>Counter Top Value Buffer Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOPB</name>
|
|
<description>Counter Top Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter Value Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00070707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC0PEN</name>
|
|
<description>CC Channel 0 Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1PEN</name>
|
|
<description>CC Channel 1 Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2PEN</name>
|
|
<description>CC Channel 2 Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI0PEN</name>
|
|
<description>CC Channel 0 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI1PEN</name>
|
|
<description>CC Channel 1 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI2PEN</name>
|
|
<description>CC Channel 2 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC4</name>
|
|
<description>Location 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC5</name>
|
|
<description>Location 5</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTCTRL</name>
|
|
<description>DTI Control Register</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x010000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTEN</name>
|
|
<description>DTI Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDAS</name>
|
|
<description>DTI Automatic Start-up Functionality</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTIPOL</name>
|
|
<description>DTI Inactive Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTCINV</name>
|
|
<description>DTI Complementary Output Invert.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSSEL</name>
|
|
<description>DTI PRS Source Channel Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSEN</name>
|
|
<description>DTI PRS Source Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTTIME</name>
|
|
<description>DTI Time Control Register</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F3F0F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRESC</name>
|
|
<description>DTI Prescaler Setting</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>The HFPERCLK is undivided</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>The HFPERCLK is divided by 2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>The HFPERCLK is divided by 4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>The HFPERCLK is divided by 8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>The HFPERCLK is divided by 16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>The HFPERCLK is divided by 32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>The HFPERCLK is divided by 64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>The HFPERCLK is divided by 128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>The HFPERCLK is divided by 256</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>The HFPERCLK is divided by 512</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>The HFPERCLK is divided by 1024</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTRISET</name>
|
|
<description>DTI Rise-time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTFALLT</name>
|
|
<description>DTI Fall-time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFC</name>
|
|
<description>DTI Fault Configuration Register</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F030707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0FSEL</name>
|
|
<description>DTI PRS Fault Source 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as fault source 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as fault source 0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as fault source 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as fault source 0</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as fault source 0</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as fault source 0</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as fault source 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as fault source 0</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FSEL</name>
|
|
<description>DTI PRS Fault Source 1 Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as fault source 1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as fault source 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as fault source 1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as fault source 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as fault source 1</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as fault source 1</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as fault source 1</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as fault source 1</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTFA</name>
|
|
<description>DTI Fault Action</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on fault</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Set outputs inactive</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear outputs</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRISTATE</name>
|
|
<description>Tristate outputs</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS0FEN</name>
|
|
<description>DTI PRS 0 Fault Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FEN</name>
|
|
<description>DTI PRS 1 Fault Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGFEN</name>
|
|
<description>DTI Debugger Fault Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLOCKUPFEN</name>
|
|
<description>DTI Lockup Fault Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTOGEN</name>
|
|
<description>DTI Output Generation Enable Register</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTOGCC0EN</name>
|
|
<description>DTI CC0 Output Generation Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCC1EN</name>
|
|
<description>DTI CC1 Output Generation Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCC2EN</name>
|
|
<description>DTI CC2 Output Generation Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI0EN</name>
|
|
<description>DTI CDTI0 Output Generation Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI1EN</name>
|
|
<description>DTI CDTI1 Output Generation Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI2EN</name>
|
|
<description>DTI CDTI2 Output Generation Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFAULT</name>
|
|
<description>DTI Fault Register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0F</name>
|
|
<description>DTI PRS 0 Fault</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1F</name>
|
|
<description>DTI PRS 1 Fault</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGF</name>
|
|
<description>DTI Debugger Fault</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLOCKUPF</name>
|
|
<description>DTI Lockup Fault</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFAULTC</name>
|
|
<description>DTI Fault Clear Register</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0FC</name>
|
|
<description>DTI PRS0 Fault Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FC</name>
|
|
<description>DTI PRS1 Fault Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGFC</name>
|
|
<description>DTI Debugger Fault Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TLOCKUPFC</name>
|
|
<description>DTI Lockup Fault Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTLOCK</name>
|
|
<description>DTI Configuration Lock Register</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKKEY</name>
|
|
<description>DTI Lock Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER2</name>
|
|
<description>TIMER2</description>
|
|
<baseAddress>0x40010800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER2</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x3F032FFB</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Timer Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>Up-count mode</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOWN</name>
|
|
<description>Down-count mode</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDOWN</name>
|
|
<description>Up/down-count mode</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QDEC</name>
|
|
<description>Quadrature decoder mode</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Timer Start/Stop/Reload Synchronization</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSMEN</name>
|
|
<description>One-shot Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>QDM</name>
|
|
<description>Quadrature Decoder Mode Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGRUN</name>
|
|
<description>Debug Mode Run Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMACLRACT</name>
|
|
<description>DMA Request Clear on Active</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RISEA</name>
|
|
<description>Timer Rising Input Edge Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start counter without reload</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop counter without reload</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOADSTART</name>
|
|
<description>Reload and start counter</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FALLA</name>
|
|
<description>Timer Falling Input Edge Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start counter without reload</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop counter without reload</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOADSTART</name>
|
|
<description>Reload and start counter</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>X2CNT</name>
|
|
<description>2x Count Mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Clock Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRESCHFPERCLK</name>
|
|
<description>Prescaled HFPERCLK</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Compare/Capture Channel 1 Input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMEROUF</name>
|
|
<description>Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Prescaler Setting</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>The HFPERCLK is undivided</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>The HFPERCLK is divided by 2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>The HFPERCLK is divided by 4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>The HFPERCLK is divided by 8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>The HFPERCLK is divided by 16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>The HFPERCLK is divided by 32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>The HFPERCLK is divided by 64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>The HFPERCLK is divided by 128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>The HFPERCLK is divided by 256</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>The HFPERCLK is divided by 512</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>The HFPERCLK is divided by 1024</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATI</name>
|
|
<description>Always Track Inputs</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSSCOIST</name>
|
|
<description>Reload-Start Sets Compare Output initial State</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start Timer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Timer</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07070707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUNNING</name>
|
|
<description>Running</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOPBV</name>
|
|
<description>TOPB Valid</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV0</name>
|
|
<description>CC0 CCVB Valid</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV1</name>
|
|
<description>CC1 CCVB Valid</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV2</name>
|
|
<description>CC2 CCVB Valid</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV0</name>
|
|
<description>CC0 Input Capture Valid</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV1</name>
|
|
<description>CC1 Input Capture Valid</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV2</name>
|
|
<description>CC2 Input Capture Valid</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL0</name>
|
|
<description>CC0 Polarity</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL1</name>
|
|
<description>CC1 Polarity</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL2</name>
|
|
<description>CC2 Polarity</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOP</name>
|
|
<description>Counter Top Value Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOP</name>
|
|
<description>Counter Top Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOPB</name>
|
|
<description>Counter Top Value Buffer Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOPB</name>
|
|
<description>Counter Top Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter Value Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00070707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC0PEN</name>
|
|
<description>CC Channel 0 Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1PEN</name>
|
|
<description>CC Channel 1 Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2PEN</name>
|
|
<description>CC Channel 2 Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI0PEN</name>
|
|
<description>CC Channel 0 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI1PEN</name>
|
|
<description>CC Channel 1 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI2PEN</name>
|
|
<description>CC Channel 2 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC4</name>
|
|
<description>Location 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC5</name>
|
|
<description>Location 5</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTCTRL</name>
|
|
<description>DTI Control Register</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x010000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTEN</name>
|
|
<description>DTI Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDAS</name>
|
|
<description>DTI Automatic Start-up Functionality</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTIPOL</name>
|
|
<description>DTI Inactive Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTCINV</name>
|
|
<description>DTI Complementary Output Invert.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSSEL</name>
|
|
<description>DTI PRS Source Channel Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSEN</name>
|
|
<description>DTI PRS Source Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTTIME</name>
|
|
<description>DTI Time Control Register</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F3F0F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRESC</name>
|
|
<description>DTI Prescaler Setting</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>The HFPERCLK is undivided</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>The HFPERCLK is divided by 2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>The HFPERCLK is divided by 4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>The HFPERCLK is divided by 8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>The HFPERCLK is divided by 16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>The HFPERCLK is divided by 32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>The HFPERCLK is divided by 64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>The HFPERCLK is divided by 128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>The HFPERCLK is divided by 256</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>The HFPERCLK is divided by 512</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>The HFPERCLK is divided by 1024</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTRISET</name>
|
|
<description>DTI Rise-time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTFALLT</name>
|
|
<description>DTI Fall-time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFC</name>
|
|
<description>DTI Fault Configuration Register</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F030707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0FSEL</name>
|
|
<description>DTI PRS Fault Source 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as fault source 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as fault source 0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as fault source 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as fault source 0</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as fault source 0</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as fault source 0</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as fault source 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as fault source 0</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FSEL</name>
|
|
<description>DTI PRS Fault Source 1 Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as fault source 1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as fault source 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as fault source 1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as fault source 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as fault source 1</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as fault source 1</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as fault source 1</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as fault source 1</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTFA</name>
|
|
<description>DTI Fault Action</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on fault</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Set outputs inactive</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear outputs</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRISTATE</name>
|
|
<description>Tristate outputs</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS0FEN</name>
|
|
<description>DTI PRS 0 Fault Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FEN</name>
|
|
<description>DTI PRS 1 Fault Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGFEN</name>
|
|
<description>DTI Debugger Fault Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLOCKUPFEN</name>
|
|
<description>DTI Lockup Fault Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTOGEN</name>
|
|
<description>DTI Output Generation Enable Register</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTOGCC0EN</name>
|
|
<description>DTI CC0 Output Generation Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCC1EN</name>
|
|
<description>DTI CC1 Output Generation Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCC2EN</name>
|
|
<description>DTI CC2 Output Generation Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI0EN</name>
|
|
<description>DTI CDTI0 Output Generation Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI1EN</name>
|
|
<description>DTI CDTI1 Output Generation Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI2EN</name>
|
|
<description>DTI CDTI2 Output Generation Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFAULT</name>
|
|
<description>DTI Fault Register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0F</name>
|
|
<description>DTI PRS 0 Fault</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1F</name>
|
|
<description>DTI PRS 1 Fault</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGF</name>
|
|
<description>DTI Debugger Fault</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLOCKUPF</name>
|
|
<description>DTI Lockup Fault</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFAULTC</name>
|
|
<description>DTI Fault Clear Register</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0FC</name>
|
|
<description>DTI PRS0 Fault Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FC</name>
|
|
<description>DTI PRS1 Fault Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGFC</name>
|
|
<description>DTI Debugger Fault Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TLOCKUPFC</name>
|
|
<description>DTI Lockup Fault Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTLOCK</name>
|
|
<description>DTI Configuration Lock Register</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKKEY</name>
|
|
<description>DTI Lock Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER3</name>
|
|
<description>TIMER3</description>
|
|
<baseAddress>0x40010C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER3</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x3F032FFB</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Timer Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>Up-count mode</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOWN</name>
|
|
<description>Down-count mode</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDOWN</name>
|
|
<description>Up/down-count mode</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QDEC</name>
|
|
<description>Quadrature decoder mode</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Timer Start/Stop/Reload Synchronization</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSMEN</name>
|
|
<description>One-shot Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>QDM</name>
|
|
<description>Quadrature Decoder Mode Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGRUN</name>
|
|
<description>Debug Mode Run Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMACLRACT</name>
|
|
<description>DMA Request Clear on Active</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RISEA</name>
|
|
<description>Timer Rising Input Edge Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start counter without reload</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop counter without reload</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOADSTART</name>
|
|
<description>Reload and start counter</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FALLA</name>
|
|
<description>Timer Falling Input Edge Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start counter without reload</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop counter without reload</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOADSTART</name>
|
|
<description>Reload and start counter</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>X2CNT</name>
|
|
<description>2x Count Mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Clock Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRESCHFPERCLK</name>
|
|
<description>Prescaled HFPERCLK</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CC1</name>
|
|
<description>Compare/Capture Channel 1 Input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMEROUF</name>
|
|
<description>Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Prescaler Setting</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>The HFPERCLK is undivided</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>The HFPERCLK is divided by 2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>The HFPERCLK is divided by 4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>The HFPERCLK is divided by 8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>The HFPERCLK is divided by 16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>The HFPERCLK is divided by 32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>The HFPERCLK is divided by 64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>The HFPERCLK is divided by 128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>The HFPERCLK is divided by 256</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>The HFPERCLK is divided by 512</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>The HFPERCLK is divided by 1024</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATI</name>
|
|
<description>Always Track Inputs</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSSCOIST</name>
|
|
<description>Reload-Start Sets Compare Output initial State</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start Timer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Timer</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07070707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUNNING</name>
|
|
<description>Running</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOPBV</name>
|
|
<description>TOPB Valid</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV0</name>
|
|
<description>CC0 CCVB Valid</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV1</name>
|
|
<description>CC1 CCVB Valid</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCVBV2</name>
|
|
<description>CC2 CCVB Valid</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV0</name>
|
|
<description>CC0 Input Capture Valid</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV1</name>
|
|
<description>CC1 Input Capture Valid</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICV2</name>
|
|
<description>CC2 Input Capture Valid</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL0</name>
|
|
<description>CC0 Polarity</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL1</name>
|
|
<description>CC1 Polarity</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CCPOL2</name>
|
|
<description>CC2 Polarity</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag Set</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000773</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC0</name>
|
|
<description>CC Channel 0 Interrupt Flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1</name>
|
|
<description>CC Channel 1 Interrupt Flag Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2</name>
|
|
<description>CC Channel 2 Interrupt Flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF0</name>
|
|
<description>CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF1</name>
|
|
<description>CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ICBOF2</name>
|
|
<description>CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOP</name>
|
|
<description>Counter Top Value Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOP</name>
|
|
<description>Counter Top Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOPB</name>
|
|
<description>Counter Top Value Buffer Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOPB</name>
|
|
<description>Counter Top Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter Value Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00070707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC0PEN</name>
|
|
<description>CC Channel 0 Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1PEN</name>
|
|
<description>CC Channel 1 Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2PEN</name>
|
|
<description>CC Channel 2 Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI0PEN</name>
|
|
<description>CC Channel 0 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI1PEN</name>
|
|
<description>CC Channel 1 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CDTI2PEN</name>
|
|
<description>CC Channel 2 Complementary Dead-Time Insertion Pin Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC4</name>
|
|
<description>Location 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC5</name>
|
|
<description>Location 5</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC0_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC1_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CTRL</name>
|
|
<description>CC Channel Control Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F3F3F17</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>CC Channel Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Compare/Capture channel turned off</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTCAPTURE</name>
|
|
<description>Input capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUTCOMPARE</name>
|
|
<description>Output compare</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM</name>
|
|
<description>Pulse-Width Modulation</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTINV</name>
|
|
<description>Output Invert</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COIST</name>
|
|
<description>Compare Output Initial State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMOA</name>
|
|
<description>Compare Match Output Action</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on compare match</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on compare match</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on compare match</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on compare match</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COFOA</name>
|
|
<description>Counter Overflow Output Action</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter overflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter overflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter overflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter overflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUFOA</name>
|
|
<description>Counter Underflow Output Action</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on counter underflow</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle output on counter underflow</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear output on counter underflow</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set output on counter underflow</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Compare/Capture Channel PRS Input Channel Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSEL</name>
|
|
<description>Input Selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Digital Filter</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEDGE</name>
|
|
<description>Input Capture Edge Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising edges detected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling edges detected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Both edges detected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No edge detection, signal is left as it is</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICEVCTRL</name>
|
|
<description>Input Capture Event Control</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EVERYEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every capture</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVERYSECONDEDGE</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on every second capture</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCV</name>
|
|
<description>CC Channel Value Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCV</name>
|
|
<description>CC Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCVP</name>
|
|
<description>CC Channel Value Peek Register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVP</name>
|
|
<description>CC Channel Value Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CC2_CCVB</name>
|
|
<description>CC Channel Buffer Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCVB</name>
|
|
<description>CC Channel Value Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTCTRL</name>
|
|
<description>DTI Control Register</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x010000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTEN</name>
|
|
<description>DTI Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDAS</name>
|
|
<description>DTI Automatic Start-up Functionality</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTIPOL</name>
|
|
<description>DTI Inactive Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTCINV</name>
|
|
<description>DTI Complementary Output Invert.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSSEL</name>
|
|
<description>DTI PRS Source Channel Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as input</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as input</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as input</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as input</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected as input</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected as input</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected as input</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected as input</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSEN</name>
|
|
<description>DTI PRS Source Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTTIME</name>
|
|
<description>DTI Time Control Register</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x003F3F0F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRESC</name>
|
|
<description>DTI Prescaler Setting</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>The HFPERCLK is undivided</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>The HFPERCLK is divided by 2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>The HFPERCLK is divided by 4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>The HFPERCLK is divided by 8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>The HFPERCLK is divided by 16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>The HFPERCLK is divided by 32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>The HFPERCLK is divided by 64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>The HFPERCLK is divided by 128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV256</name>
|
|
<description>The HFPERCLK is divided by 256</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV512</name>
|
|
<description>The HFPERCLK is divided by 512</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV1024</name>
|
|
<description>The HFPERCLK is divided by 1024</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTRISET</name>
|
|
<description>DTI Rise-time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTFALLT</name>
|
|
<description>DTI Fall-time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFC</name>
|
|
<description>DTI Fault Configuration Register</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0F030707</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0FSEL</name>
|
|
<description>DTI PRS Fault Source 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as fault source 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as fault source 0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as fault source 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as fault source 0</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as fault source 0</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as fault source 0</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as fault source 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as fault source 0</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FSEL</name>
|
|
<description>DTI PRS Fault Source 1 Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected as fault source 1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected as fault source 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected as fault source 1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected as fault source 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected as fault source 1</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected as fault source 1</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected as fault source 1</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected as fault source 1</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTFA</name>
|
|
<description>DTI Fault Action</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No action on fault</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Set outputs inactive</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear outputs</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRISTATE</name>
|
|
<description>Tristate outputs</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS0FEN</name>
|
|
<description>DTI PRS 0 Fault Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FEN</name>
|
|
<description>DTI PRS 1 Fault Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGFEN</name>
|
|
<description>DTI Debugger Fault Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLOCKUPFEN</name>
|
|
<description>DTI Lockup Fault Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTOGEN</name>
|
|
<description>DTI Output Generation Enable Register</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTOGCC0EN</name>
|
|
<description>DTI CC0 Output Generation Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCC1EN</name>
|
|
<description>DTI CC1 Output Generation Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCC2EN</name>
|
|
<description>DTI CC2 Output Generation Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI0EN</name>
|
|
<description>DTI CDTI0 Output Generation Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI1EN</name>
|
|
<description>DTI CDTI1 Output Generation Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTOGCDTI2EN</name>
|
|
<description>DTI CDTI2 Output Generation Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFAULT</name>
|
|
<description>DTI Fault Register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0F</name>
|
|
<description>DTI PRS 0 Fault</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1F</name>
|
|
<description>DTI PRS 1 Fault</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGF</name>
|
|
<description>DTI Debugger Fault</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTLOCKUPF</name>
|
|
<description>DTI Lockup Fault</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFAULTC</name>
|
|
<description>DTI Fault Clear Register</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTPRS0FC</name>
|
|
<description>DTI PRS0 Fault Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPRS1FC</name>
|
|
<description>DTI PRS1 Fault Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DTDBGFC</name>
|
|
<description>DTI Debugger Fault Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TLOCKUPFC</name>
|
|
<description>DTI Lockup Fault Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTLOCK</name>
|
|
<description>DTI Configuration Lock Register</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKKEY</name>
|
|
<description>DTI Lock Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ACMP0</name>
|
|
<description>ACMP0</description>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ACMP0</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x47000000</resetValue>
|
|
<resetMask>0xCF03077F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Analog Comparator Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MUXEN</name>
|
|
<description>Input Mux Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INACTVAL</name>
|
|
<description>Inactive Value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GPIOINV</name>
|
|
<description>Comparator GPIO Output Invert</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYSTSEL</name>
|
|
<description>Hysteresis Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYST0</name>
|
|
<description>No hysteresis.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST1</name>
|
|
<description>~15 mV hysteresis.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST2</name>
|
|
<description>~22 mV hysteresis.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST3</name>
|
|
<description>~29 mV hysteresis.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST4</name>
|
|
<description>~36 mV hysteresis.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST5</name>
|
|
<description>~43 mV hysteresis.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST6</name>
|
|
<description>~50 mV hysteresis.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST7</name>
|
|
<description>~57 mV hysteresis.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WARMTIME</name>
|
|
<description>Warm-up Time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>4CYCLES</name>
|
|
<description>4 HFPERCLK cycles.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8CYCLES</name>
|
|
<description>8 HFPERCLK cycles.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16CYCLES</name>
|
|
<description>16 HFPERCLK cycles.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32CYCLES</name>
|
|
<description>32 HFPERCLK cycles.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64CYCLES</name>
|
|
<description>64 HFPERCLK cycles.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128CYCLES</name>
|
|
<description>128 HFPERCLK cycles.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256CYCLES</name>
|
|
<description>256 HFPERCLK cycles.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512CYCLES</name>
|
|
<description>512 HFPERCLK cycles.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRISE</name>
|
|
<description>Rising Edge Interrupt Sense</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IFALL</name>
|
|
<description>Falling Edge Interrupt Sense</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIASPROG</name>
|
|
<description>Bias Configuration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HALFBIAS</name>
|
|
<description>Half Bias Current</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FULLBIAS</name>
|
|
<description>Full Bias Current</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUTSEL</name>
|
|
<description>Input Selection Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010080</resetValue>
|
|
<resetMask>0x31013FF7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POSSEL</name>
|
|
<description>Positive Input Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>Channel 0 as positive input.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>Channel 1 as positive input.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>Channel 2 as positive input.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>Channel 3 as positive input.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH4</name>
|
|
<description>Channel 4 as positive input.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH5</name>
|
|
<description>Channel 5 as positive input.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH6</name>
|
|
<description>Channel 6 as positive input.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH7</name>
|
|
<description>Channel 7 as positive input.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEGSEL</name>
|
|
<description>Negative Input Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>Channel 0 as negative input.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>Channel 1 as negative input.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>Channel 2 as negative input.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>Channel 3 as negative input.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH4</name>
|
|
<description>Channel 4 as negative input.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH5</name>
|
|
<description>Channel 5 as negative input.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH6</name>
|
|
<description>Channel 6 as negative input.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH7</name>
|
|
<description>Channel 7 as negative input.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1V25</name>
|
|
<description>1.25 V as negative input.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V5</name>
|
|
<description>2.5 V as negative input.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDD</name>
|
|
<description>Scaled VDD as negative input.</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPSENSE</name>
|
|
<description>Capacitive sense mode.</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0CH0</name>
|
|
<description>DAC0 channel 0.</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0CH1</name>
|
|
<description>DAC0 channel 1.</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VDDLEVEL</name>
|
|
<description>VDD Reference Level</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LPREF</name>
|
|
<description>Low Power Reference Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSRESEN</name>
|
|
<description>Capacitive Sense Mode Internal Resistor Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSRESSEL</name>
|
|
<description>Capacitive Sense Mode Internal Resistor Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RES0</name>
|
|
<description>Internal capacitive sense resistor value 0.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES1</name>
|
|
<description>Internal capacitive sense resistor value 1.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES2</name>
|
|
<description>Internal capacitive sense resistor value 2.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES3</name>
|
|
<description>Internal capacitive sense resistor value 3.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPACT</name>
|
|
<description>Analog Comparator Active</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACMPOUT</name>
|
|
<description>Analog Comparator Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Trigger Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Triggered Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Triggered Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Flag Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Triggered Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000701</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPPEN</name>
|
|
<description>ACMP Output Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ACMP1</name>
|
|
<description>ACMP1</description>
|
|
<baseAddress>0x40001400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ACMP0</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x47000000</resetValue>
|
|
<resetMask>0xCF03077F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Analog Comparator Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MUXEN</name>
|
|
<description>Input Mux Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INACTVAL</name>
|
|
<description>Inactive Value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GPIOINV</name>
|
|
<description>Comparator GPIO Output Invert</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYSTSEL</name>
|
|
<description>Hysteresis Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYST0</name>
|
|
<description>No hysteresis.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST1</name>
|
|
<description>~15 mV hysteresis.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST2</name>
|
|
<description>~22 mV hysteresis.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST3</name>
|
|
<description>~29 mV hysteresis.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST4</name>
|
|
<description>~36 mV hysteresis.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST5</name>
|
|
<description>~43 mV hysteresis.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST6</name>
|
|
<description>~50 mV hysteresis.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYST7</name>
|
|
<description>~57 mV hysteresis.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WARMTIME</name>
|
|
<description>Warm-up Time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>4CYCLES</name>
|
|
<description>4 HFPERCLK cycles.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8CYCLES</name>
|
|
<description>8 HFPERCLK cycles.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16CYCLES</name>
|
|
<description>16 HFPERCLK cycles.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32CYCLES</name>
|
|
<description>32 HFPERCLK cycles.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64CYCLES</name>
|
|
<description>64 HFPERCLK cycles.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128CYCLES</name>
|
|
<description>128 HFPERCLK cycles.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256CYCLES</name>
|
|
<description>256 HFPERCLK cycles.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512CYCLES</name>
|
|
<description>512 HFPERCLK cycles.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRISE</name>
|
|
<description>Rising Edge Interrupt Sense</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IFALL</name>
|
|
<description>Falling Edge Interrupt Sense</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIASPROG</name>
|
|
<description>Bias Configuration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HALFBIAS</name>
|
|
<description>Half Bias Current</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FULLBIAS</name>
|
|
<description>Full Bias Current</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUTSEL</name>
|
|
<description>Input Selection Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010080</resetValue>
|
|
<resetMask>0x31013FF7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POSSEL</name>
|
|
<description>Positive Input Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>Channel 0 as positive input.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>Channel 1 as positive input.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>Channel 2 as positive input.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>Channel 3 as positive input.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH4</name>
|
|
<description>Channel 4 as positive input.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH5</name>
|
|
<description>Channel 5 as positive input.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH6</name>
|
|
<description>Channel 6 as positive input.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH7</name>
|
|
<description>Channel 7 as positive input.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEGSEL</name>
|
|
<description>Negative Input Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>Channel 0 as negative input.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>Channel 1 as negative input.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>Channel 2 as negative input.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>Channel 3 as negative input.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH4</name>
|
|
<description>Channel 4 as negative input.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH5</name>
|
|
<description>Channel 5 as negative input.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH6</name>
|
|
<description>Channel 6 as negative input.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH7</name>
|
|
<description>Channel 7 as negative input.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1V25</name>
|
|
<description>1.25 V as negative input.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V5</name>
|
|
<description>2.5 V as negative input.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDD</name>
|
|
<description>Scaled VDD as negative input.</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPSENSE</name>
|
|
<description>Capacitive sense mode.</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0CH0</name>
|
|
<description>DAC0 channel 0.</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0CH1</name>
|
|
<description>DAC0 channel 1.</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VDDLEVEL</name>
|
|
<description>VDD Reference Level</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LPREF</name>
|
|
<description>Low Power Reference Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSRESEN</name>
|
|
<description>Capacitive Sense Mode Internal Resistor Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSRESSEL</name>
|
|
<description>Capacitive Sense Mode Internal Resistor Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RES0</name>
|
|
<description>Internal capacitive sense resistor value 0.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES1</name>
|
|
<description>Internal capacitive sense resistor value 1.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES2</name>
|
|
<description>Internal capacitive sense resistor value 2.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES3</name>
|
|
<description>Internal capacitive sense resistor value 3.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPACT</name>
|
|
<description>Analog Comparator Active</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACMPOUT</name>
|
|
<description>Analog Comparator Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Trigger Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Triggered Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Triggered Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Flag Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Triggered Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000701</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACMPPEN</name>
|
|
<description>ACMP Output Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C0</name>
|
|
<description>I2C0</description>
|
|
<baseAddress>0x4000A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C0</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0007B37F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>I2C Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SLAVE</name>
|
|
<description>Addressable as Slave</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOACK</name>
|
|
<description>Automatic Acknowledge</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSE</name>
|
|
<description>Automatic STOP when Empty</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSN</name>
|
|
<description>Automatic STOP on NACK</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBDIS</name>
|
|
<description>Arbitration Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GCAMEN</name>
|
|
<description>General Call Address Match Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLHR</name>
|
|
<description>Clock Low High Ratio</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>The ratio between low period and high period counters (Nlow:Nhigh) is 4:4</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYMMETRIC</name>
|
|
<description>The ratio between low period and high period counters (Nlow:Nhigh) is 6:3</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>The ratio between low period and high period counters (Nlow:Nhigh) is 11:6</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BITO</name>
|
|
<description>Bus Idle Timeout</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Timeout disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>40PCC</name>
|
|
<description>Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>80PCC</name>
|
|
<description>Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>160PCC</name>
|
|
<description>Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GIBITO</name>
|
|
<description>Go Idle on Bus Idle Timeout </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLTO</name>
|
|
<description>Clock Low Timeout</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Timeout disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>40PCC</name>
|
|
<description>Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>80PCC</name>
|
|
<description>Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>160PCC</name>
|
|
<description>Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>320PPC</name>
|
|
<description>Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024PPC</name>
|
|
<description>Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Send start condition</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Send stop condition</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Send ACK</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Send NACK</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continue transmission</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ABORT</name>
|
|
<description>Abort transmission</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARTX</name>
|
|
<description>Clear TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARPC</name>
|
|
<description>Clear Pending Commands</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATE</name>
|
|
<description>State Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Bus Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASTER</name>
|
|
<description>Master</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRANSMITTER</name>
|
|
<description>Transmitter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACKED</name>
|
|
<description>Nack Received</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSHOLD</name>
|
|
<description>Bus Held</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATE</name>
|
|
<description>Transmission State</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>No transmission is being performed.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT</name>
|
|
<description>Waiting for idle. Will send a start condition as soon as the bus is idle.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start transmitted or received</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADDR</name>
|
|
<description>Address transmitted or received</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADDRACK</name>
|
|
<description>Address ack/nack transmitted or received</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA</name>
|
|
<description>Data transmitted or received</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATAACK</name>
|
|
<description>Data ack/nack transmitted or received</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0x000001FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSTART</name>
|
|
<description>Pending START</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PSTOP</name>
|
|
<description>Pending STOP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PACK</name>
|
|
<description>Pending ACK</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PNACK</name>
|
|
<description>Pending NACK</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCONT</name>
|
|
<description>Pending continue</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PABORT</name>
|
|
<description>Pending abort</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Division Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000001FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Clock Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SADDR</name>
|
|
<description>Slave Address Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Slave address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SADDRMASK</name>
|
|
<description>Slave Address Mask Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Slave Address Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATA</name>
|
|
<description>Receive Buffer Data Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAP</name>
|
|
<description>Receive Buffer Data Peek Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATAP</name>
|
|
<description>RX Data Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Buffer Data Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0x0001FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>START condition Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTART</name>
|
|
<description>Repeated START condition Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transfer Completed Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>Transmit Buffer Level Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>Receive Data Valid Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTOP</name>
|
|
<description>Master STOP Condition Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>Arbitration Lost Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Bus Error Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSHOLD</name>
|
|
<description>Bus Held Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmit Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receive Buffer Underflow Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BITO</name>
|
|
<description>Bus Idle Timeout Interrupt Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLTO</name>
|
|
<description>Clock Low Timeout Interrupt Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSTOP</name>
|
|
<description>Slave STOP condition Interrupt Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0001FFCF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Set START Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTART</name>
|
|
<description>Set Repeated START Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Set Address Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Set Transfer Completed Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Set Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Set Not Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTOP</name>
|
|
<description>Set MSTOP Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>Set Arbitration Lost Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Set Bus Error Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSHOLD</name>
|
|
<description>Set Bus Held Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Set Transmit Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Set Receive Buffer Underflow Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BITO</name>
|
|
<description>Set Bus Idle Timeout Interrupt Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLTO</name>
|
|
<description>Set Clock Low Interrupt Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSTOP</name>
|
|
<description>Set SSTOP Interrupt Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0001FFCF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Clear START Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTART</name>
|
|
<description>Clear Repeated START Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Clear Address Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Clear Transfer Completed Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Clear Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Clear Not Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTOP</name>
|
|
<description>Clear MSTOP Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>Clear Arbitration Lost Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Clear Bus Error Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSHOLD</name>
|
|
<description>Clear Bus Held Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Clear Transmit Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Clear Receive Buffer Underflow Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BITO</name>
|
|
<description>Clear Bus Idle Timeout Interrupt Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLTO</name>
|
|
<description>Clear Clock Low Interrupt Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSTOP</name>
|
|
<description>Clear SSTOP Interrupt Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0001FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>START Condition Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTART</name>
|
|
<description>Repeated START condition Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transfer Completed Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>Transmit Buffer level Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>Receive Data Valid Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Acknowledge Received Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledge Received Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTOP</name>
|
|
<description>MSTOP Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>Arbitration Lost Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Bus Error Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSHOLD</name>
|
|
<description>Bus Held Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmit Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receive Buffer Underflow Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BITO</name>
|
|
<description>Bus Idle Timeout Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLTO</name>
|
|
<description>Clock Low Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSTOP</name>
|
|
<description>SSTOP Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000703</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SDAPEN</name>
|
|
<description>SDA Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLPEN</name>
|
|
<description>SCL Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC4</name>
|
|
<description>Location 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC5</name>
|
|
<description>Location 5</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC6</name>
|
|
<description>Location 6</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C1</name>
|
|
<description>I2C1</description>
|
|
<baseAddress>0x4000A400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C1</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0007B37F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>I2C Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SLAVE</name>
|
|
<description>Addressable as Slave</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOACK</name>
|
|
<description>Automatic Acknowledge</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSE</name>
|
|
<description>Automatic STOP when Empty</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSN</name>
|
|
<description>Automatic STOP on NACK</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBDIS</name>
|
|
<description>Arbitration Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GCAMEN</name>
|
|
<description>General Call Address Match Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLHR</name>
|
|
<description>Clock Low High Ratio</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>The ratio between low period and high period counters (Nlow:Nhigh) is 4:4</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASYMMETRIC</name>
|
|
<description>The ratio between low period and high period counters (Nlow:Nhigh) is 6:3</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>The ratio between low period and high period counters (Nlow:Nhigh) is 11:6</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BITO</name>
|
|
<description>Bus Idle Timeout</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Timeout disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>40PCC</name>
|
|
<description>Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>80PCC</name>
|
|
<description>Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>160PCC</name>
|
|
<description>Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GIBITO</name>
|
|
<description>Go Idle on Bus Idle Timeout </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLTO</name>
|
|
<description>Clock Low Timeout</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Timeout disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>40PCC</name>
|
|
<description>Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>80PCC</name>
|
|
<description>Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>160PCC</name>
|
|
<description>Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>320PPC</name>
|
|
<description>Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1024PPC</name>
|
|
<description>Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Send start condition</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Send stop condition</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Send ACK</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Send NACK</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continue transmission</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ABORT</name>
|
|
<description>Abort transmission</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARTX</name>
|
|
<description>Clear TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARPC</name>
|
|
<description>Clear Pending Commands</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATE</name>
|
|
<description>State Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Bus Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MASTER</name>
|
|
<description>Master</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRANSMITTER</name>
|
|
<description>Transmitter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACKED</name>
|
|
<description>Nack Received</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSHOLD</name>
|
|
<description>Bus Held</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATE</name>
|
|
<description>Transmission State</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>No transmission is being performed.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT</name>
|
|
<description>Waiting for idle. Will send a start condition as soon as the bus is idle.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start transmitted or received</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADDR</name>
|
|
<description>Address transmitted or received</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADDRACK</name>
|
|
<description>Address ack/nack transmitted or received</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA</name>
|
|
<description>Data transmitted or received</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATAACK</name>
|
|
<description>Data ack/nack transmitted or received</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<resetMask>0x000001FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSTART</name>
|
|
<description>Pending START</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PSTOP</name>
|
|
<description>Pending STOP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PACK</name>
|
|
<description>Pending ACK</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PNACK</name>
|
|
<description>Pending NACK</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCONT</name>
|
|
<description>Pending continue</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PABORT</name>
|
|
<description>Pending abort</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Division Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000001FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Clock Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SADDR</name>
|
|
<description>Slave Address Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Slave address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SADDRMASK</name>
|
|
<description>Slave Address Mask Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FE</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Slave Address Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATA</name>
|
|
<description>Receive Buffer Data Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAP</name>
|
|
<description>Receive Buffer Data Peek Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATAP</name>
|
|
<description>RX Data Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Buffer Data Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0x0001FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>START condition Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTART</name>
|
|
<description>Repeated START condition Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transfer Completed Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>Transmit Buffer Level Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>Receive Data Valid Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTOP</name>
|
|
<description>Master STOP Condition Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>Arbitration Lost Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Bus Error Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSHOLD</name>
|
|
<description>Bus Held Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmit Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receive Buffer Underflow Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BITO</name>
|
|
<description>Bus Idle Timeout Interrupt Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLTO</name>
|
|
<description>Clock Low Timeout Interrupt Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSTOP</name>
|
|
<description>Slave STOP condition Interrupt Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0001FFCF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Set START Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTART</name>
|
|
<description>Set Repeated START Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Set Address Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Set Transfer Completed Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Set Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Set Not Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTOP</name>
|
|
<description>Set MSTOP Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>Set Arbitration Lost Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Set Bus Error Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSHOLD</name>
|
|
<description>Set Bus Held Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Set Transmit Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Set Receive Buffer Underflow Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BITO</name>
|
|
<description>Set Bus Idle Timeout Interrupt Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLTO</name>
|
|
<description>Set Clock Low Interrupt Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSTOP</name>
|
|
<description>Set SSTOP Interrupt Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0001FFCF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Clear START Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTART</name>
|
|
<description>Clear Repeated START Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Clear Address Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Clear Transfer Completed Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Clear Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Clear Not Acknowledge Received Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTOP</name>
|
|
<description>Clear MSTOP Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>Clear Arbitration Lost Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Clear Bus Error Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSHOLD</name>
|
|
<description>Clear Bus Held Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Clear Transmit Buffer Overflow Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Clear Receive Buffer Underflow Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BITO</name>
|
|
<description>Clear Bus Idle Timeout Interrupt Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLTO</name>
|
|
<description>Clear Clock Low Interrupt Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSTOP</name>
|
|
<description>Clear SSTOP Interrupt Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0001FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>START Condition Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTART</name>
|
|
<description>Repeated START condition Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Transfer Completed Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>Transmit Buffer level Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>Receive Data Valid Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Acknowledge Received Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Not Acknowledge Received Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTOP</name>
|
|
<description>MSTOP Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBLOST</name>
|
|
<description>Arbitration Lost Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSERR</name>
|
|
<description>Bus Error Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSHOLD</name>
|
|
<description>Bus Held Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmit Buffer Overflow Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receive Buffer Underflow Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BITO</name>
|
|
<description>Bus Idle Timeout Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLTO</name>
|
|
<description>Clock Low Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSTOP</name>
|
|
<description>SSTOP Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000703</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SDAPEN</name>
|
|
<description>SDA Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCLPEN</name>
|
|
<description>SCL Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC4</name>
|
|
<description>Location 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC5</name>
|
|
<description>Location 5</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC6</name>
|
|
<description>Location 6</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIO</name>
|
|
<description>GPIO</description>
|
|
<baseAddress>0x40006000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPIO_EVEN</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>GPIO_ODD</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PA_CTRL</name>
|
|
<description>Port Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DRIVEMODE</name>
|
|
<description>Drive Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>6 mA drive current</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOWEST</name>
|
|
<description>0.1 mA drive current</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>20 mA drive current</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>1 mA drive current</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PA_MODEL</name>
|
|
<description>Port Pin Mode Low Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE0</name>
|
|
<description>Pin 0 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>Pin 1 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>Pin 2 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE3</name>
|
|
<description>Pin 3 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE4</name>
|
|
<description>Pin 4 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE5</name>
|
|
<description>Pin 5 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE6</name>
|
|
<description>Pin 6 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE7</name>
|
|
<description>Pin 7 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PA_MODEH</name>
|
|
<description>Port Pin Mode High Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE8</name>
|
|
<description>Pin 8 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE9</name>
|
|
<description>Pin 9 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE10</name>
|
|
<description>Pin 10 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE11</name>
|
|
<description>Pin 11 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE12</name>
|
|
<description>Pin 12 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE13</name>
|
|
<description>Pin 13 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE14</name>
|
|
<description>Pin 14 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE15</name>
|
|
<description>Pin 15 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PA_DOUT</name>
|
|
<description>Port Data Out Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUT</name>
|
|
<description>Data Out</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PA_DOUTSET</name>
|
|
<description>Port Data Out Set Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTSET</name>
|
|
<description>Data Out Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PA_DOUTCLR</name>
|
|
<description>Port Data Out Clear Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTCLR</name>
|
|
<description>Data Out Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PA_DOUTTGL</name>
|
|
<description>Port Data Out Toggle Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTTGL</name>
|
|
<description>Data Out Toggle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PA_DIN</name>
|
|
<description>Port Data In Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIN</name>
|
|
<description>Data In</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PA_PINLOCKN</name>
|
|
<description>Port Unlocked Pins Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINLOCKN</name>
|
|
<description>Unlocked Pins</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PB_CTRL</name>
|
|
<description>Port Control Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DRIVEMODE</name>
|
|
<description>Drive Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>6 mA drive current</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOWEST</name>
|
|
<description>0.1 mA drive current</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>20 mA drive current</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>1 mA drive current</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PB_MODEL</name>
|
|
<description>Port Pin Mode Low Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE0</name>
|
|
<description>Pin 0 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>Pin 1 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>Pin 2 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE3</name>
|
|
<description>Pin 3 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE4</name>
|
|
<description>Pin 4 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE5</name>
|
|
<description>Pin 5 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE6</name>
|
|
<description>Pin 6 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE7</name>
|
|
<description>Pin 7 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PB_MODEH</name>
|
|
<description>Port Pin Mode High Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE8</name>
|
|
<description>Pin 8 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE9</name>
|
|
<description>Pin 9 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE10</name>
|
|
<description>Pin 10 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE11</name>
|
|
<description>Pin 11 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE12</name>
|
|
<description>Pin 12 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE13</name>
|
|
<description>Pin 13 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE14</name>
|
|
<description>Pin 14 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE15</name>
|
|
<description>Pin 15 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PB_DOUT</name>
|
|
<description>Port Data Out Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUT</name>
|
|
<description>Data Out</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PB_DOUTSET</name>
|
|
<description>Port Data Out Set Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTSET</name>
|
|
<description>Data Out Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PB_DOUTCLR</name>
|
|
<description>Port Data Out Clear Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTCLR</name>
|
|
<description>Data Out Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PB_DOUTTGL</name>
|
|
<description>Port Data Out Toggle Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTTGL</name>
|
|
<description>Data Out Toggle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PB_DIN</name>
|
|
<description>Port Data In Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIN</name>
|
|
<description>Data In</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PB_PINLOCKN</name>
|
|
<description>Port Unlocked Pins Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINLOCKN</name>
|
|
<description>Unlocked Pins</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC_CTRL</name>
|
|
<description>Port Control Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DRIVEMODE</name>
|
|
<description>Drive Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>6 mA drive current</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOWEST</name>
|
|
<description>0.1 mA drive current</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>20 mA drive current</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>1 mA drive current</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC_MODEL</name>
|
|
<description>Port Pin Mode Low Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE0</name>
|
|
<description>Pin 0 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>Pin 1 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>Pin 2 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE3</name>
|
|
<description>Pin 3 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE4</name>
|
|
<description>Pin 4 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE5</name>
|
|
<description>Pin 5 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE6</name>
|
|
<description>Pin 6 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE7</name>
|
|
<description>Pin 7 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC_MODEH</name>
|
|
<description>Port Pin Mode High Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE8</name>
|
|
<description>Pin 8 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE9</name>
|
|
<description>Pin 9 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE10</name>
|
|
<description>Pin 10 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE11</name>
|
|
<description>Pin 11 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE12</name>
|
|
<description>Pin 12 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE13</name>
|
|
<description>Pin 13 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE14</name>
|
|
<description>Pin 14 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE15</name>
|
|
<description>Pin 15 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC_DOUT</name>
|
|
<description>Port Data Out Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUT</name>
|
|
<description>Data Out</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC_DOUTSET</name>
|
|
<description>Port Data Out Set Register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTSET</name>
|
|
<description>Data Out Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC_DOUTCLR</name>
|
|
<description>Port Data Out Clear Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTCLR</name>
|
|
<description>Data Out Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC_DOUTTGL</name>
|
|
<description>Port Data Out Toggle Register</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTTGL</name>
|
|
<description>Data Out Toggle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC_DIN</name>
|
|
<description>Port Data In Register</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIN</name>
|
|
<description>Data In</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC_PINLOCKN</name>
|
|
<description>Port Unlocked Pins Register</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINLOCKN</name>
|
|
<description>Unlocked Pins</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PD_CTRL</name>
|
|
<description>Port Control Register</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DRIVEMODE</name>
|
|
<description>Drive Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>6 mA drive current</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOWEST</name>
|
|
<description>0.1 mA drive current</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>20 mA drive current</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>1 mA drive current</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PD_MODEL</name>
|
|
<description>Port Pin Mode Low Register</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE0</name>
|
|
<description>Pin 0 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>Pin 1 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>Pin 2 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE3</name>
|
|
<description>Pin 3 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE4</name>
|
|
<description>Pin 4 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE5</name>
|
|
<description>Pin 5 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE6</name>
|
|
<description>Pin 6 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE7</name>
|
|
<description>Pin 7 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PD_MODEH</name>
|
|
<description>Port Pin Mode High Register</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE8</name>
|
|
<description>Pin 8 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE9</name>
|
|
<description>Pin 9 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE10</name>
|
|
<description>Pin 10 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE11</name>
|
|
<description>Pin 11 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE12</name>
|
|
<description>Pin 12 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE13</name>
|
|
<description>Pin 13 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE14</name>
|
|
<description>Pin 14 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE15</name>
|
|
<description>Pin 15 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PD_DOUT</name>
|
|
<description>Port Data Out Register</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUT</name>
|
|
<description>Data Out</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PD_DOUTSET</name>
|
|
<description>Port Data Out Set Register</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTSET</name>
|
|
<description>Data Out Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PD_DOUTCLR</name>
|
|
<description>Port Data Out Clear Register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTCLR</name>
|
|
<description>Data Out Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PD_DOUTTGL</name>
|
|
<description>Port Data Out Toggle Register</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTTGL</name>
|
|
<description>Data Out Toggle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PD_DIN</name>
|
|
<description>Port Data In Register</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIN</name>
|
|
<description>Data In</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PD_PINLOCKN</name>
|
|
<description>Port Unlocked Pins Register</description>
|
|
<addressOffset>0x08C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINLOCKN</name>
|
|
<description>Unlocked Pins</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE_CTRL</name>
|
|
<description>Port Control Register</description>
|
|
<addressOffset>0x090</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DRIVEMODE</name>
|
|
<description>Drive Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>6 mA drive current</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOWEST</name>
|
|
<description>0.1 mA drive current</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>20 mA drive current</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>1 mA drive current</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE_MODEL</name>
|
|
<description>Port Pin Mode Low Register</description>
|
|
<addressOffset>0x094</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE0</name>
|
|
<description>Pin 0 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>Pin 1 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>Pin 2 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE3</name>
|
|
<description>Pin 3 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE4</name>
|
|
<description>Pin 4 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE5</name>
|
|
<description>Pin 5 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE6</name>
|
|
<description>Pin 6 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE7</name>
|
|
<description>Pin 7 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE_MODEH</name>
|
|
<description>Port Pin Mode High Register</description>
|
|
<addressOffset>0x098</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE8</name>
|
|
<description>Pin 8 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE9</name>
|
|
<description>Pin 9 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE10</name>
|
|
<description>Pin 10 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE11</name>
|
|
<description>Pin 11 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE12</name>
|
|
<description>Pin 12 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE13</name>
|
|
<description>Pin 13 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE14</name>
|
|
<description>Pin 14 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE15</name>
|
|
<description>Pin 15 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE_DOUT</name>
|
|
<description>Port Data Out Register</description>
|
|
<addressOffset>0x09C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUT</name>
|
|
<description>Data Out</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE_DOUTSET</name>
|
|
<description>Port Data Out Set Register</description>
|
|
<addressOffset>0x0A0</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTSET</name>
|
|
<description>Data Out Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE_DOUTCLR</name>
|
|
<description>Port Data Out Clear Register</description>
|
|
<addressOffset>0x0A4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTCLR</name>
|
|
<description>Data Out Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE_DOUTTGL</name>
|
|
<description>Port Data Out Toggle Register</description>
|
|
<addressOffset>0x0A8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTTGL</name>
|
|
<description>Data Out Toggle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE_DIN</name>
|
|
<description>Port Data In Register</description>
|
|
<addressOffset>0x0AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIN</name>
|
|
<description>Data In</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PE_PINLOCKN</name>
|
|
<description>Port Unlocked Pins Register</description>
|
|
<addressOffset>0x0B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINLOCKN</name>
|
|
<description>Unlocked Pins</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PF_CTRL</name>
|
|
<description>Port Control Register</description>
|
|
<addressOffset>0x0B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DRIVEMODE</name>
|
|
<description>Drive Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STANDARD</name>
|
|
<description>6 mA drive current</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOWEST</name>
|
|
<description>0.1 mA drive current</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>20 mA drive current</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>1 mA drive current</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PF_MODEL</name>
|
|
<description>Port Pin Mode Low Register</description>
|
|
<addressOffset>0x0B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE0</name>
|
|
<description>Pin 0 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>Pin 1 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>Pin 2 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE3</name>
|
|
<description>Pin 3 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE4</name>
|
|
<description>Pin 4 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE5</name>
|
|
<description>Pin 5 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE6</name>
|
|
<description>Pin 6 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE7</name>
|
|
<description>Pin 7 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PF_MODEH</name>
|
|
<description>Port Pin Mode High Register</description>
|
|
<addressOffset>0x0BC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE8</name>
|
|
<description>Pin 8 Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE9</name>
|
|
<description>Pin 9 Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE10</name>
|
|
<description>Pin 10 Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE11</name>
|
|
<description>Pin 11 Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE12</name>
|
|
<description>Pin 12 Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE13</name>
|
|
<description>Pin 13 Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE14</name>
|
|
<description>Pin 14 Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE15</name>
|
|
<description>Pin 15 Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input disabled. Pullup if DOUT is set.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input enabled. Filter if DOUT is set</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULL</name>
|
|
<description>Input enabled. DOUT determines pull direction</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUTPULLFILTER</name>
|
|
<description>Input enabled with filter. DOUT determines pull direction</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULL</name>
|
|
<description>Push-pull output</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUSHPULLDRIVE</name>
|
|
<description>Push-pull output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDOR</name>
|
|
<description>Wired-or output</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDORPULLDOWN</name>
|
|
<description>Wired-or output with pull-down</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDAND</name>
|
|
<description>Open-drain output</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDFILTER</name>
|
|
<description>Open-drain output with filter</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUP</name>
|
|
<description>Open-drain output with pullup</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDPULLUPFILTER</name>
|
|
<description>Open-drain output with filter and pullup</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVE</name>
|
|
<description>Open-drain output with drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEFILTER</name>
|
|
<description>Open-drain output with filter and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUP</name>
|
|
<description>Open-drain output with pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIREDANDDRIVEPULLUPFILTER</name>
|
|
<description>Open-drain output with filter, pullup and drive-strength set by DRIVEMODE</description>
|
|
<value>0x0000000F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PF_DOUT</name>
|
|
<description>Port Data Out Register</description>
|
|
<addressOffset>0x0C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUT</name>
|
|
<description>Data Out</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PF_DOUTSET</name>
|
|
<description>Port Data Out Set Register</description>
|
|
<addressOffset>0x0C4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTSET</name>
|
|
<description>Data Out Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PF_DOUTCLR</name>
|
|
<description>Port Data Out Clear Register</description>
|
|
<addressOffset>0x0C8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTCLR</name>
|
|
<description>Data Out Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PF_DOUTTGL</name>
|
|
<description>Port Data Out Toggle Register</description>
|
|
<addressOffset>0x0CC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOUTTGL</name>
|
|
<description>Data Out Toggle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PF_DIN</name>
|
|
<description>Port Data In Register</description>
|
|
<addressOffset>0x0D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIN</name>
|
|
<description>Data In</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PF_PINLOCKN</name>
|
|
<description>Port Unlocked Pins Register</description>
|
|
<addressOffset>0x0D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINLOCKN</name>
|
|
<description>Unlocked Pins</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTIPSELL</name>
|
|
<description>External Interrupt Port Select Low Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x77777777</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIPSEL0</name>
|
|
<description>External Interrupt 0 Port Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 0 selected for external interrupt 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 0 selected for external interrupt 0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 0 selected for external interrupt 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 0 selected for external interrupt 0</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 0 selected for external interrupt 0</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 0 selected for external interrupt 0</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL1</name>
|
|
<description>External Interrupt 1 Port Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 1 selected for external interrupt 1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 1 selected for external interrupt 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 1 selected for external interrupt 1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 1 selected for external interrupt 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 1 selected for external interrupt 1</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 1 selected for external interrupt 1</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL2</name>
|
|
<description>External Interrupt 2 Port Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 2 selected for external interrupt 2</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 2 selected for external interrupt 2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 2 selected for external interrupt 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 2 selected for external interrupt 2</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 2 selected for external interrupt 2</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 2 selected for external interrupt 2</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL3</name>
|
|
<description>External Interrupt 3 Port Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 3 selected for external interrupt 3</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 3 selected for external interrupt 3</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 3 selected for external interrupt 3</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 3 selected for external interrupt 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 3 selected for external interrupt 3</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 3 selected for external interrupt 3</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL4</name>
|
|
<description>External Interrupt 4 Port Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 4 selected for external interrupt 4</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 4 selected for external interrupt 4</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 4 selected for external interrupt 4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 4 selected for external interrupt 4</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 4 selected for external interrupt 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 4 selected for external interrupt 4</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL5</name>
|
|
<description>External Interrupt 5 Port Select</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 5 selected for external interrupt 5</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 5 selected for external interrupt 5</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 5 selected for external interrupt 5</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 5 selected for external interrupt 5</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 5 selected for external interrupt 5</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 5 selected for external interrupt 5</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL6</name>
|
|
<description>External Interrupt 6 Port Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 6 selected for external interrupt 6</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 6 selected for external interrupt 6</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 6 selected for external interrupt 6</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 6 selected for external interrupt 6</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 6 selected for external interrupt 6</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 6 selected for external interrupt 6</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL7</name>
|
|
<description>External Interrupt 7 Port Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 7 selected for external interrupt 7</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 7 selected for external interrupt 7</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 7 selected for external interrupt 7</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 7 selected for external interrupt 7</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 7 selected for external interrupt 7</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 7 selected for external interrupt 7</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTIPSELH</name>
|
|
<description>External Interrupt Port Select High Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x77777777</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIPSEL8</name>
|
|
<description>External Interrupt 8 Port Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 8 selected for external interrupt 8</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 8 selected for external interrupt 8</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 8 selected for external interrupt 8</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 8 selected for external interrupt 8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 8 selected for external interrupt 8</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 8 selected for external interrupt 8</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL9</name>
|
|
<description>External Interrupt 9 Port Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 9 selected for external interrupt 9</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 9 selected for external interrupt 9</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 9 selected for external interrupt 9</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 9 selected for external interrupt 9</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 9 selected for external interrupt 9</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 9 selected for external interrupt 9</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL10</name>
|
|
<description>External Interrupt 10 Port Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 10 selected for external interrupt 10</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 10 selected for external interrupt 10</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 10 selected for external interrupt 10</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 10 selected for external interrupt 10</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 10 selected for external interrupt 10</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 10 selected for external interrupt 10</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL11</name>
|
|
<description>External Interrupt 11 Port Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 11 selected for external interrupt 11</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 11 selected for external interrupt 11</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 11 selected for external interrupt 11</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 11 selected for external interrupt 11</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 11 selected for external interrupt 11</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 11 selected for external interrupt 11</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL12</name>
|
|
<description>External Interrupt 12 Port Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 12 selected for external interrupt 12</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 12 selected for external interrupt 12</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 12 selected for external interrupt 12</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 12 selected for external interrupt 12</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 12 selected for external interrupt 12</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 12 selected for external interrupt 12</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL13</name>
|
|
<description>External Interrupt 13 Port Select</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 13 selected for external interrupt 13</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 13 selected for external interrupt 13</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 13 selected for external interrupt 13</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 13 selected for external interrupt 13</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 13 selected for external interrupt 13</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 13 selected for external interrupt 13</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL14</name>
|
|
<description>External Interrupt 14 Port Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 14 selected for external interrupt 14</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 14 selected for external interrupt 14</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 14 selected for external interrupt 14</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 14 selected for external interrupt 14</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 14 selected for external interrupt 14</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 14 selected for external interrupt 14</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTIPSEL15</name>
|
|
<description>External Interrupt 15 Port Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PORTA</name>
|
|
<description>Port A pin 15 selected for external interrupt 15</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTB</name>
|
|
<description>Port B pin 15 selected for external interrupt 15</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTC</name>
|
|
<description>Port C pin 15 selected for external interrupt 15</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTD</name>
|
|
<description>Port D pin 15 selected for external interrupt 15</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTE</name>
|
|
<description>Port E pin 15 selected for external interrupt 15</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORTF</name>
|
|
<description>Port F pin 15 selected for external interrupt 15</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTIRISE</name>
|
|
<description>External Interrupt Rising Edge Trigger Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIRISE</name>
|
|
<description>External Interrupt n Rising Edge Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTIFALL</name>
|
|
<description>External Interrupt Falling Edge Trigger Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIFALL</name>
|
|
<description>External Interrupt n Falling Edge Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXT</name>
|
|
<description>External Interrupt n Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXT</name>
|
|
<description>External Interrupt Flag n</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXT</name>
|
|
<description>External Interrupt Flag n Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXT</name>
|
|
<description>External Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x0301F307</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWCLKPEN</name>
|
|
<description>Serial Wire Clock Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWDIOPEN</name>
|
|
<description>Serial Wire Data Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWOPEN</name>
|
|
<description>Serial Wire Viewer Output Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWLOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCLKPEN</name>
|
|
<description>ETM Trace Clock Pin Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TD0PEN</name>
|
|
<description>ETM Trace Data Pin Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TD1PEN</name>
|
|
<description>ETM Trace Data Pin Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TD2PEN</name>
|
|
<description>ETM Trace Data Pin Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TD3PEN</name>
|
|
<description>ETM Trace Data Pin Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETMLOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INSENSE</name>
|
|
<description>Input Sense Register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT</name>
|
|
<description>Interrupt Sense Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRS</name>
|
|
<description>PRS Sense Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<description>Configuration Lock Register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKKEY</name>
|
|
<description>Configuration Lock Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>GPIO Control Register</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM4RET</name>
|
|
<description>Enable EM4 retention</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>GPIO Command Register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM4WUCLR</name>
|
|
<description>EM4 Wake-up clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EM4WUEN</name>
|
|
<description>EM4 Wake-up Enable Register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM4WUEN</name>
|
|
<description>EM4 Wake-up enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>A0</name>
|
|
<description>Enable em4 wakeup on pin A0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>A6</name>
|
|
<description>Enable em4 wakeup on pin A6</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>C9</name>
|
|
<description>Enable em4 wakeup on pin C9</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F1</name>
|
|
<description>Enable em4 wakeup on pin F1</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F2</name>
|
|
<description>Enable em4 wakeup on pin F2</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>E13</name>
|
|
<description>Enable em4 wakeup on pin E13</description>
|
|
<value>0x00000020</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EM4WUPOL</name>
|
|
<description>EM4 Wake-up Polarity Register</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM4WUPOL</name>
|
|
<description>EM4 Wake-up Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>A0</name>
|
|
<description>Determines polarity on pin A0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>A6</name>
|
|
<description>Determines polarity on pin A6</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>C9</name>
|
|
<description>Determines polarity on pin C9</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F1</name>
|
|
<description>Determines polarity on pin F1</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F2</name>
|
|
<description>Determines polarity on pin F2</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>E13</name>
|
|
<description>Determines polarity on pin E13</description>
|
|
<value>0x00000020</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EM4WUCAUSE</name>
|
|
<description>EM4 Wake-up Cause Register</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM4WUCAUSE</name>
|
|
<description>EM4 wake-up cause</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>A0</name>
|
|
<description>This bit indicates an em4 wake-up request occurred on pin A0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>A6</name>
|
|
<description>This bit indicates an em4 wake-up request occurred on pin A6</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>C9</name>
|
|
<description>This bit indicates an em4 wake-up request occurred on pin C9</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F1</name>
|
|
<description>This bit indicates an em4 wake-up request occurred on pin F1</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>F2</name>
|
|
<description>This bit indicates an em4 wake-up request occurred on pin F2</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>E13</name>
|
|
<description>This bit indicates an em4 wake-up request occurred on pin E13</description>
|
|
<value>0x00000020</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>VCMP</name>
|
|
<description>VCMP</description>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>VCMP</name>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x47000000</resetValue>
|
|
<resetMask>0x4F030715</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Voltage Supply Comparator Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INACTVAL</name>
|
|
<description>Inactive Value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYSTEN</name>
|
|
<description>Hysteresis Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMTIME</name>
|
|
<description>Warm-Up Time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>4CYCLES</name>
|
|
<description>4 HFPERCLK cycles</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8CYCLES</name>
|
|
<description>8 HFPERCLK cycles</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16CYCLES</name>
|
|
<description>16 HFPERCLK cycles</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32CYCLES</name>
|
|
<description>32 HFPERCLK cycles</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64CYCLES</name>
|
|
<description>64 HFPERCLK cycles</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128CYCLES</name>
|
|
<description>128 HFPERCLK cycles</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256CYCLES</name>
|
|
<description>256 HFPERCLK cycles</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512CYCLES</name>
|
|
<description>512 HFPERCLK cycles</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRISE</name>
|
|
<description>Rising Edge Interrupt Sense</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IFALL</name>
|
|
<description>Falling Edge Interrupt Sense</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIASPROG</name>
|
|
<description>VCMP Bias Programming Value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HALFBIAS</name>
|
|
<description>Half Bias Current</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUTSEL</name>
|
|
<description>Input Selection Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000013F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIGLEVEL</name>
|
|
<description>Trigger Level</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LPREF</name>
|
|
<description>Low Power Reference</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VCMPACT</name>
|
|
<description>Voltage Supply Comparator Active</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VCMPOUT</name>
|
|
<description>Voltage Supply Comparator Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Trigger Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Triggered Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Triggered Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Flag Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Triggered Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WARMUP</name>
|
|
<description>Warm-up Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PRS</name>
|
|
<description>PRS</description>
|
|
<baseAddress>0x400CC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SWPULSE</name>
|
|
<description>Software Pulse Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0PULSE</name>
|
|
<description>Channel 0 Pulse Generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1PULSE</name>
|
|
<description>Channel 1 Pulse Generation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2PULSE</name>
|
|
<description>Channel 2 Pulse Generation</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3PULSE</name>
|
|
<description>Channel 3 Pulse Generation</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4PULSE</name>
|
|
<description>Channel 4 Pulse Generation</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5PULSE</name>
|
|
<description>Channel 5 Pulse Generation</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6PULSE</name>
|
|
<description>Channel 6 Pulse Generation</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7PULSE</name>
|
|
<description>Channel 7 Pulse Generation</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8PULSE</name>
|
|
<description>Channel 8 Pulse Generation</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9PULSE</name>
|
|
<description>Channel 9 Pulse Generation</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10PULSE</name>
|
|
<description>Channel 10 Pulse Generation</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11PULSE</name>
|
|
<description>Channel 11 Pulse Generation</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWLEVEL</name>
|
|
<description>Software Level Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0LEVEL</name>
|
|
<description>Channel 0 Software Level</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1LEVEL</name>
|
|
<description>Channel 1 Software Level</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2LEVEL</name>
|
|
<description>Channel 2 Software Level</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3LEVEL</name>
|
|
<description>Channel 3 Software Level</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4LEVEL</name>
|
|
<description>Channel 4 Software Level</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5LEVEL</name>
|
|
<description>Channel 5 Software Level</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6LEVEL</name>
|
|
<description>Channel 6 Software Level</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7LEVEL</name>
|
|
<description>Channel 7 Software Level</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH8LEVEL</name>
|
|
<description>Channel 8 Software Level</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH9LEVEL</name>
|
|
<description>Channel 9 Software Level</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH10LEVEL</name>
|
|
<description>Channel 10 Software Level</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH11LEVEL</name>
|
|
<description>Channel 11 Software Level</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000070F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0PEN</name>
|
|
<description>CH0 Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1PEN</name>
|
|
<description>CH1 Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2PEN</name>
|
|
<description>CH2 Pin Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3PEN</name>
|
|
<description>CH3 Pin Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH4_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH5_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH6_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH7_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH8_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH9_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH10_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH11_CTRL</name>
|
|
<description>Channel Control Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x133F0007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGSEL</name>
|
|
<description>Signal Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOURCESEL</name>
|
|
<description>Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No source selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCMP</name>
|
|
<description>Voltage Comparator</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACMP1</name>
|
|
<description>Analog Comparator 1</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC0</name>
|
|
<description>Digital to Analog Converter 0</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>Analog to Digital Converter 0</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 0</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART1</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 1</description>
|
|
<value>0x00000011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2</name>
|
|
<description>Universal Synchronous/Asynchronous Receiver/Transmitter 2</description>
|
|
<value>0x00000012</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER0</name>
|
|
<description>Timer 0</description>
|
|
<value>0x0000001C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER1</name>
|
|
<description>Timer 1</description>
|
|
<value>0x0000001D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER2</name>
|
|
<description>Timer 2</description>
|
|
<value>0x0000001E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3</name>
|
|
<description>Timer 3</description>
|
|
<value>0x0000001F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB</name>
|
|
<description>Universal Serial Bus Interface</description>
|
|
<value>0x00000024</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC</name>
|
|
<description>Real-Time Counter</description>
|
|
<value>0x00000028</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOL</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000030</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIOH</name>
|
|
<description>General purpose Input/Output</description>
|
|
<value>0x00000031</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LETIMER0</name>
|
|
<description>Low Energy Timer 0</description>
|
|
<value>0x00000034</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURTC</name>
|
|
<description>Backup RTC</description>
|
|
<value>0x00000037</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEL</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x00000039</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSEH</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LESENSED</name>
|
|
<description>Low Energy Sensor Interface</description>
|
|
<value>0x0000003B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDSEL</name>
|
|
<description>Edge Detect Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Signal is left as it is</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSEDGE</name>
|
|
<description>A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGEDGE</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGES</name>
|
|
<description>A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASYNC</name>
|
|
<description>Asynchronous reflex</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LEUART0</name>
|
|
<description>LEUART0</description>
|
|
<baseAddress>0x40084000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LEUART0</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUTOTRI</name>
|
|
<description>Automatic Transmitter Tristate</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATABITS</name>
|
|
<description>Data-Bit Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PARITY</name>
|
|
<description>Parity-Bit Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Parity bits are not used</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even parity are used. Parity bits are automatically generated and checked by hardware.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd parity is used. Parity bits are automatically generated and checked by hardware.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPBITS</name>
|
|
<description>Stop-Bit Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert Input And Output</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRSDMA</name>
|
|
<description>Clear RX DMA On Error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPBK</name>
|
|
<description>Loopback Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFUBRX</name>
|
|
<description>Start-Frame UnBlock RX</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPM</name>
|
|
<description>Multi-Processor Mode</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAB</name>
|
|
<description>Multi-Processor Address-Bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIT8DV</name>
|
|
<description>Bit 8 Default Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDMAWU</name>
|
|
<description>RX DMA Wakeup</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAWU</name>
|
|
<description>TX DMA Wakeup</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDELAY</name>
|
|
<description>TX Delay Transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Frames are transmitted immediately</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>Transmission of new frames are delayed by a single baud period</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE</name>
|
|
<description>Transmission of new frames are delayed by two baud periods</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIPLE</name>
|
|
<description>Transmission of new frames are delayed by three baud periods</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmitter Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCKEN</name>
|
|
<description>Receiver Block Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCKDIS</name>
|
|
<description>Receiver Block Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARTX</name>
|
|
<description>Clear TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARRX</name>
|
|
<description>Clear RX</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXENS</name>
|
|
<description>Receiver Enable Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXENS</name>
|
|
<description>Transmitter Enable Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCK</name>
|
|
<description>Block Incoming Data</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Control Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00007FF8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Fractional Clock Divider</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STARTFRAME</name>
|
|
<description>Start Frame Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000001FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STARTFRAME</name>
|
|
<description>Start Frame</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIGFRAME</name>
|
|
<description>Signal Frame Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000001FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGFRAME</name>
|
|
<description>Signal Frame</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAX</name>
|
|
<description>Receive Buffer Data Extended Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000C1FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Receive Data Parity Error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Receive Data Framing Error</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATA</name>
|
|
<description>Receive Buffer Data Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAXP</name>
|
|
<description>Receive Buffer Data Extended Peek Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000C1FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATAP</name>
|
|
<description>RX Data Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRP</name>
|
|
<description>Receive Data Parity Error Peek</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRP</name>
|
|
<description>Receive Data Framing Error Peek</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATAX</name>
|
|
<description>Transmit Buffer Data Extended Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000E1FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBREAK</name>
|
|
<description>Transmit Data As Break</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDISAT</name>
|
|
<description>Disable TX After Transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXENAT</name>
|
|
<description>Enable RX After Transmission</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Buffer Data Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>RX Overflow Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>RX Underflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>TX Overflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Framing Error Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>Start Frame Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SIGF</name>
|
|
<description>Signal Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007F9</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Set TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>Set RX Overflow Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Set RX Underflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Set TX Overflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Set Parity Error Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Set Framing Error Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Set Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>Set Start Frame Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SIGF</name>
|
|
<description>Set Signal Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007F9</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Clear TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>Clear RX Overflow Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Clear RX Underflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Clear TX Overflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Clear Parity Error Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Clear Framing Error Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Clear Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>Clear Start-Frame Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SIGF</name>
|
|
<description>Clear Signal-Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>RX Overflow Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>RX Underflow Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>TX Overflow Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Multi-Processor Address Frame Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>Start Frame Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SIGF</name>
|
|
<description>Signal Frame Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PULSECTRL</name>
|
|
<description>Pulse Control Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PULSEW</name>
|
|
<description>Pulse Width</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PULSEEN</name>
|
|
<description>Pulse Generator/Extender Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PULSEFILT</name>
|
|
<description>Pulse Filter</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREEZE</name>
|
|
<description>Freeze Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGFREEZE</name>
|
|
<description>Register Update Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>CTRL Register Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>CMD Register Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>CLKDIV Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTFRAME</name>
|
|
<description>STARTFRAME Register Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SIGFRAME</name>
|
|
<description>SIGFRAME Register Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDATAX</name>
|
|
<description>TXDATAX Register Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TXDATA Register Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PULSECTRL</name>
|
|
<description>PULSECTRL Register Busy</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000703</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPEN</name>
|
|
<description>RX Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPEN</name>
|
|
<description>TX Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC4</name>
|
|
<description>Location 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUT</name>
|
|
<description>LEUART Input Register</description>
|
|
<addressOffset>0x0AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPRSSEL</name>
|
|
<description>RX PRS Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXPRS</name>
|
|
<description>PRS RX Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LEUART1</name>
|
|
<description>LEUART1</description>
|
|
<baseAddress>0x40084400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LEUART1</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUTOTRI</name>
|
|
<description>Automatic Transmitter Tristate</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATABITS</name>
|
|
<description>Data-Bit Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PARITY</name>
|
|
<description>Parity-Bit Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Parity bits are not used</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN</name>
|
|
<description>Even parity are used. Parity bits are automatically generated and checked by hardware.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODD</name>
|
|
<description>Odd parity is used. Parity bits are automatically generated and checked by hardware.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPBITS</name>
|
|
<description>Stop-Bit Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert Input And Output</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRSDMA</name>
|
|
<description>Clear RX DMA On Error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPBK</name>
|
|
<description>Loopback Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFUBRX</name>
|
|
<description>Start-Frame UnBlock RX</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPM</name>
|
|
<description>Multi-Processor Mode</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAB</name>
|
|
<description>Multi-Processor Address-Bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIT8DV</name>
|
|
<description>Bit 8 Default Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDMAWU</name>
|
|
<description>RX DMA Wakeup</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAWU</name>
|
|
<description>TX DMA Wakeup</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDELAY</name>
|
|
<description>TX Delay Transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Frames are transmitted immediately</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SINGLE</name>
|
|
<description>Transmission of new frames are delayed by a single baud period</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUBLE</name>
|
|
<description>Transmission of new frames are delayed by two baud periods</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIPLE</name>
|
|
<description>Transmission of new frames are delayed by three baud periods</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXEN</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDIS</name>
|
|
<description>Transmitter Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCKEN</name>
|
|
<description>Receiver Block Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCKDIS</name>
|
|
<description>Receiver Block Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARTX</name>
|
|
<description>Clear TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLEARRX</name>
|
|
<description>Clear RX</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXENS</name>
|
|
<description>Receiver Enable Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXENS</name>
|
|
<description>Transmitter Enable Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXBLOCK</name>
|
|
<description>Block Incoming Data</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Control Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00007FF8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Fractional Clock Divider</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STARTFRAME</name>
|
|
<description>Start Frame Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000001FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STARTFRAME</name>
|
|
<description>Start Frame</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIGFRAME</name>
|
|
<description>Signal Frame Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000001FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIGFRAME</name>
|
|
<description>Signal Frame</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAX</name>
|
|
<description>Receive Buffer Data Extended Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000C1FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Receive Data Parity Error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Receive Data Framing Error</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATA</name>
|
|
<description>Receive Buffer Data Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDATAXP</name>
|
|
<description>Receive Buffer Data Extended Peek Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000C1FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATAP</name>
|
|
<description>RX Data Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERRP</name>
|
|
<description>Receive Data Parity Error Peek</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERRP</name>
|
|
<description>Receive Data Framing Error Peek</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATAX</name>
|
|
<description>Transmit Buffer Data Extended Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000E1FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBREAK</name>
|
|
<description>Transmit Data As Break</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDISAT</name>
|
|
<description>Disable TX After Transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXENAT</name>
|
|
<description>Enable RX After Transmission</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDATA</name>
|
|
<description>Transmit Buffer Data Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>RX Overflow Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>RX Underflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>TX Overflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Framing Error Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>Start Frame Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SIGF</name>
|
|
<description>Signal Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007F9</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Set TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>Set RX Overflow Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Set RX Underflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Set TX Overflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Set Parity Error Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Set Framing Error Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Set Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>Set Start Frame Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SIGF</name>
|
|
<description>Set Signal Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007F9</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>Clear TX Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>Clear RX Overflow Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Clear RX Underflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Clear TX Overflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Clear Parity Error Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Clear Framing Error Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Clear Multi-Processor Address Frame Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>Clear Start-Frame Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SIGF</name>
|
|
<description>Clear Signal-Frame Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXC</name>
|
|
<description>TX Complete Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXBL</name>
|
|
<description>TX Buffer Level Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDATAV</name>
|
|
<description>RX Data Valid Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXOF</name>
|
|
<description>RX Overflow Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>RX Underflow Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>TX Overflow Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPAF</name>
|
|
<description>Multi-Processor Address Frame Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTF</name>
|
|
<description>Start Frame Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SIGF</name>
|
|
<description>Signal Frame Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PULSECTRL</name>
|
|
<description>Pulse Control Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PULSEW</name>
|
|
<description>Pulse Width</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PULSEEN</name>
|
|
<description>Pulse Generator/Extender Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PULSEFILT</name>
|
|
<description>Pulse Filter</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREEZE</name>
|
|
<description>Freeze Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGFREEZE</name>
|
|
<description>Register Update Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>CTRL Register Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>CMD Register Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>CLKDIV Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STARTFRAME</name>
|
|
<description>STARTFRAME Register Busy</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SIGFRAME</name>
|
|
<description>SIGFRAME Register Busy</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDATAX</name>
|
|
<description>TXDATAX Register Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TXDATA Register Busy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PULSECTRL</name>
|
|
<description>PULSECTRL Register Busy</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000703</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPEN</name>
|
|
<description>RX Pin Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPEN</name>
|
|
<description>TX Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC4</name>
|
|
<description>Location 4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUT</name>
|
|
<description>LEUART Input Register</description>
|
|
<addressOffset>0x0AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000001F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPRSSEL</name>
|
|
<description>RX PRS Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXPRS</name>
|
|
<description>PRS RX Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PCNT0</name>
|
|
<description>PCNT0</description>
|
|
<baseAddress>0x40086000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PCNT0</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000CF3F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The module is disabled.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVSSINGLE</name>
|
|
<description>Single input LFACLK oversampling mode (available in EM0-EM2).</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTCLKSINGLE</name>
|
|
<description>Externally clocked single input counter mode (available in EM0-EM3).</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTCLKQUAD</name>
|
|
<description>Externally clocked quadrature decoder mode (available in EM0-EM3).</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTDIR</name>
|
|
<description>Non-Quadrature Mode Counter Direction Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Enable Digital Pulse Width Filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTEN</name>
|
|
<description>Enable PCNT Clock Domain Reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>Enable Hysteresis</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>S1CDIR</name>
|
|
<description>Count direction determined by S1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNTEV</name>
|
|
<description>Controls when the counter counts</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Counts up on up-count and down on down-count events.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>Only counts up on up-count events.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOWN</name>
|
|
<description>Only counts down on down-count events.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Never counts.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUXCNTEV</name>
|
|
<description>Controls when the auxiliary counter counts</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Never counts.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>Counts up on up-count events.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOWN</name>
|
|
<description>Counts up on down-count events.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Counts up on both up-count and down-count events.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCNTIM</name>
|
|
<description>Load CNT Immediately</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LTOPBIM</name>
|
|
<description>Load TOPB Immediately</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Current Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter Value Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOP</name>
|
|
<description>Top Value Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000FF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOP</name>
|
|
<description>Counter Top Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOPB</name>
|
|
<description>Top Value Buffer Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000FF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOPB</name>
|
|
<description>Counter Top Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Read Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Read Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Overflow Interrupt Read Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow interrupt set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Auxiliary Overflow Interrupt Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Auxiliary Overflow Interrupt Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Auxiliary Overflow Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000700</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREEZE</name>
|
|
<description>Freeze Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGFREEZE</name>
|
|
<description>Register Update Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>CTRL Register Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>CMD Register Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOPB</name>
|
|
<description>TOPB Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AUXCNT</name>
|
|
<description>Auxiliary Counter Value Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUXCNT</name>
|
|
<description>Auxiliary Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUT</name>
|
|
<description>PCNT Input Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007DF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>S0PRSSEL</name>
|
|
<description>S0IN PRS Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected.</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected.</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S0PRSEN</name>
|
|
<description>S0IN PRS Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>S1PRSSEL</name>
|
|
<description>S1IN PRS Channel Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected.</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected.</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S1PRSEN</name>
|
|
<description>S1IN PRS Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PCNT1</name>
|
|
<description>PCNT1</description>
|
|
<baseAddress>0x40086400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PCNT1</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000CF3F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The module is disabled.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVSSINGLE</name>
|
|
<description>Single input LFACLK oversampling mode (available in EM0-EM2).</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTCLKSINGLE</name>
|
|
<description>Externally clocked single input counter mode (available in EM0-EM3).</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTCLKQUAD</name>
|
|
<description>Externally clocked quadrature decoder mode (available in EM0-EM3).</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTDIR</name>
|
|
<description>Non-Quadrature Mode Counter Direction Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Enable Digital Pulse Width Filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTEN</name>
|
|
<description>Enable PCNT Clock Domain Reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>Enable Hysteresis</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>S1CDIR</name>
|
|
<description>Count direction determined by S1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNTEV</name>
|
|
<description>Controls when the counter counts</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Counts up on up-count and down on down-count events.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>Only counts up on up-count events.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOWN</name>
|
|
<description>Only counts down on down-count events.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Never counts.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUXCNTEV</name>
|
|
<description>Controls when the auxiliary counter counts</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Never counts.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>Counts up on up-count events.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOWN</name>
|
|
<description>Counts up on down-count events.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Counts up on both up-count and down-count events.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCNTIM</name>
|
|
<description>Load CNT Immediately</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LTOPBIM</name>
|
|
<description>Load TOPB Immediately</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Current Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter Value Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOP</name>
|
|
<description>Top Value Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000FF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOP</name>
|
|
<description>Counter Top Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOPB</name>
|
|
<description>Top Value Buffer Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000FF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOPB</name>
|
|
<description>Counter Top Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Read Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Read Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Overflow Interrupt Read Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow interrupt set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Auxiliary Overflow Interrupt Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Auxiliary Overflow Interrupt Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Auxiliary Overflow Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000700</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREEZE</name>
|
|
<description>Freeze Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGFREEZE</name>
|
|
<description>Register Update Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>CTRL Register Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>CMD Register Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOPB</name>
|
|
<description>TOPB Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AUXCNT</name>
|
|
<description>Auxiliary Counter Value Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUXCNT</name>
|
|
<description>Auxiliary Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUT</name>
|
|
<description>PCNT Input Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007DF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>S0PRSSEL</name>
|
|
<description>S0IN PRS Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected.</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected.</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S0PRSEN</name>
|
|
<description>S0IN PRS Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>S1PRSSEL</name>
|
|
<description>S1IN PRS Channel Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected.</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected.</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S1PRSEN</name>
|
|
<description>S1IN PRS Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PCNT2</name>
|
|
<description>PCNT2</description>
|
|
<baseAddress>0x40086800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PCNT2</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000CF3F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Mode Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The module is disabled.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVSSINGLE</name>
|
|
<description>Single input LFACLK oversampling mode (available in EM0-EM2).</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTCLKSINGLE</name>
|
|
<description>Externally clocked single input counter mode (available in EM0-EM3).</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTCLKQUAD</name>
|
|
<description>Externally clocked quadrature decoder mode (available in EM0-EM3).</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTDIR</name>
|
|
<description>Non-Quadrature Mode Counter Direction Control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Edge Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Enable Digital Pulse Width Filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTEN</name>
|
|
<description>Enable PCNT Clock Domain Reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>Enable Hysteresis</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>S1CDIR</name>
|
|
<description>Count direction determined by S1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNTEV</name>
|
|
<description>Controls when the counter counts</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Counts up on up-count and down on down-count events.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>Only counts up on up-count events.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOWN</name>
|
|
<description>Only counts down on down-count events.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Never counts.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUXCNTEV</name>
|
|
<description>Controls when the auxiliary counter counts</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>Never counts.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UP</name>
|
|
<description>Counts up on up-count events.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOWN</name>
|
|
<description>Counts up on down-count events.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH</name>
|
|
<description>Counts up on both up-count and down-count events.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCNTIM</name>
|
|
<description>Load CNT Immediately</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LTOPBIM</name>
|
|
<description>Load TOPB Immediately</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Current Counter Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter Value Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOP</name>
|
|
<description>Top Value Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000FF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOP</name>
|
|
<description>Counter Top Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOPB</name>
|
|
<description>Top Value Buffer Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000FF</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOPB</name>
|
|
<description>Counter Top Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Read Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Read Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Overflow Interrupt Read Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow interrupt set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Set</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Auxiliary Overflow Interrupt Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Auxiliary Overflow Interrupt Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UF</name>
|
|
<description>Underflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIRCNG</name>
|
|
<description>Direction Change Detect Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUXOF</name>
|
|
<description>Auxiliary Overflow Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROUTE</name>
|
|
<description>I/O Routing Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000700</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCATION</name>
|
|
<description>I/O Location</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC0</name>
|
|
<description>Location 0</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC1</name>
|
|
<description>Location 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC2</name>
|
|
<description>Location 2</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC3</name>
|
|
<description>Location 3</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREEZE</name>
|
|
<description>Freeze Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGFREEZE</name>
|
|
<description>Register Update Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>CTRL Register Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>CMD Register Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOPB</name>
|
|
<description>TOPB Register Busy</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AUXCNT</name>
|
|
<description>Auxiliary Counter Value Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUXCNT</name>
|
|
<description>Auxiliary Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUT</name>
|
|
<description>PCNT Input Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000007DF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>S0PRSSEL</name>
|
|
<description>S0IN PRS Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected.</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected.</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S0PRSEN</name>
|
|
<description>S0IN PRS Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>S1PRSSEL</name>
|
|
<description>S1IN PRS Channel Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS Channel 0 selected.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS Channel 1 selected.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS Channel 2 selected.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS Channel 3 selected.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS Channel 4 selected.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS Channel 5 selected.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS Channel 6 selected.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS Channel 7 selected.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS Channel 8 selected.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS Channel 9 selected.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS Channel 10 selected.</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS Channel 11 selected.</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S1PRSEN</name>
|
|
<description>S1IN PRS Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC0</name>
|
|
<description>ADC0</description>
|
|
<baseAddress>0x40002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC0</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x001F0000</resetValue>
|
|
<resetMask>0x0F1F7F3B</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WARMUPMODE</name>
|
|
<description>Warm-up Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>ADC is shut down after each conversion</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FASTBG</name>
|
|
<description>Bandgap references do not need warm up, but have reduced accuracy.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KEEPSCANREFWARM</name>
|
|
<description>Reference selected for scan mode is kept warm.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KEEPADCWARM</name>
|
|
<description>ADC is kept warmed up and scan reference is kept warm</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAILGATE</name>
|
|
<description>Conversion Tailgating</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LPFMODE</name>
|
|
<description>Low Pass Filter Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BYPASS</name>
|
|
<description>No filter or decoupling capacitor</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DECAP</name>
|
|
<description>On chip decoupling capacitor selected</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RCFILT</name>
|
|
<description>On chip RC filter selected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Prescaler Setting</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NODIVISION</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMEBASE</name>
|
|
<description>Time Base</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVSRSEL</name>
|
|
<description>Oversample Rate Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>X2</name>
|
|
<description>2 samples for each conversion result</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X4</name>
|
|
<description>4 samples for each conversion result</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X8</name>
|
|
<description>8 samples for each conversion result</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X16</name>
|
|
<description>16 samples for each conversion result</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X32</name>
|
|
<description>32 samples for each conversion result</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X64</name>
|
|
<description>64 samples for each conversion result</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X128</name>
|
|
<description>128 samples for each conversion result</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X256</name>
|
|
<description>256 samples for each conversion result</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X512</name>
|
|
<description>512 samples for each conversion result</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X1024</name>
|
|
<description>1024 samples for each conversion result</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X2048</name>
|
|
<description>2048 samples for each conversion result</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>X4096</name>
|
|
<description>4096 samples for each conversion result</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SINGLESTART</name>
|
|
<description>Single Conversion Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SINGLESTOP</name>
|
|
<description>Single Conversion Stop</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANSTART</name>
|
|
<description>Scan Sequence Start</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANSTOP</name>
|
|
<description>Scan Sequence Stop</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x07031303</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SINGLEACT</name>
|
|
<description>Single Conversion Active</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANACT</name>
|
|
<description>Scan Conversion Active</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SINGLEREFWARM</name>
|
|
<description>Single Reference Warmed Up</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANREFWARM</name>
|
|
<description>Scan Reference Warmed Up</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WARM</name>
|
|
<description>ADC Warmed Up</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SINGLEDV</name>
|
|
<description>Single Sample Data Valid</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANDV</name>
|
|
<description>Scan Data Valid</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANDATASRC</name>
|
|
<description>Scan Data Source</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>Single ended mode: SCANDATA result originates from ADCn_CH0. Differential mode: SCANDATA result originates from ADCn_CH0-ADCn_CH1</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>Single ended mode: SCANDATA result originates from ADCn_CH1. Differential mode: SCANDATA result originates from ADCn_CH2_ADCn_CH3</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>Single ended mode: SCANDATA result originates from ADCn_CH2. Differential mode: SCANDATA result originates from ADCn_CH4-ADCn_CH5</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>Single ended mode: SCANDATA result originates from ADCn_CH3. Differential mode: SCANDATA result originates from ADCn_CH6-ADCn_CH7</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH4</name>
|
|
<description>SCANDATA result originates from ADCn_CH4</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH5</name>
|
|
<description>SCANDATA result originates from ADCn_CH5</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH6</name>
|
|
<description>SCANDATA result originates from ADCn_CH6</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH7</name>
|
|
<description>SCANDATA result originates from ADCn_CH7</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SINGLECTRL</name>
|
|
<description>Single Sample Control Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xF1F70F37</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Single Sample Repetitive Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF</name>
|
|
<description>Single Sample Differential Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADJ</name>
|
|
<description>Single Sample Result Adjustment</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RES</name>
|
|
<description>Single Sample Resolution Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>12BIT</name>
|
|
<description>12-bit resolution</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8BIT</name>
|
|
<description>8-bit resolution</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6BIT</name>
|
|
<description>6-bit resolution</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVS</name>
|
|
<description>Oversampling enabled. Oversampling rate is set in OVSRSEL</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INPUTSEL</name>
|
|
<description>Single Sample Input Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REF</name>
|
|
<description>Single Sample Reference Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1V25</name>
|
|
<description>Internal 1.25 V reference</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V5</name>
|
|
<description>Internal 2.5 V reference</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDD</name>
|
|
<description>Buffered VDD</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5VDIFF</name>
|
|
<description>Internal differential 5 V reference</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTSINGLE</name>
|
|
<description>Single ended external reference from ADCn_CH6</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2XEXTDIFF</name>
|
|
<description>Differential external reference, 2x(ADCn_CH6 - ADCn_CH7)</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2XVDD</name>
|
|
<description>Unbuffered 2xVDD</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AT</name>
|
|
<description>Single Sample Acquisition Time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1CYCLE</name>
|
|
<description>1 ADC_CLK cycle acquisition time for single sample</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2CYCLES</name>
|
|
<description>2 ADC_CLK cycles acquisition time for single sample</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4CYCLES</name>
|
|
<description>4 ADC_CLK cycles acquisition time for single sample</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8CYCLES</name>
|
|
<description>8 ADC_CLK cycles acquisition time for single sample</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16CYCLES</name>
|
|
<description>16 ADC_CLK cycles acquisition time for single sample</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32CYCLES</name>
|
|
<description>32 ADC_CLK cycles acquisition time for single sample</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64CYCLES</name>
|
|
<description>64 ADC_CLK cycles acquisition time for single sample</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128CYCLES</name>
|
|
<description>128 ADC_CLK cycles acquisition time for single sample</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256CYCLES</name>
|
|
<description>256 ADC_CLK cycles acquisition time for single sample</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSEN</name>
|
|
<description>Single Sample PRS Trigger Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Single Sample PRS Trigger Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS ch 0 triggers single sample</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS ch 1 triggers single sample</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS ch 2 triggers single sample</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS ch 3 triggers single sample</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS ch 4 triggers single sample</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS ch 5 triggers single sample</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS ch 6 triggers single sample</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS ch 7 triggers single sample</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS ch 8 triggers single sample</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS ch 9 triggers single sample</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS ch 10 triggers single sample</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS ch 11 triggers single sample</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCANCTRL</name>
|
|
<description>Scan Control Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xF1F7FF37</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Scan Sequence Repetitive Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFF</name>
|
|
<description>Scan Sequence Differential Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADJ</name>
|
|
<description>Scan Sequence Result Adjustment</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RES</name>
|
|
<description>Scan Sequence Resolution Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>12BIT</name>
|
|
<description>12-bit resolution</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8BIT</name>
|
|
<description>8-bit resolution</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6BIT</name>
|
|
<description>6-bit resolution</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVS</name>
|
|
<description>Oversampling enabled. Oversampling rate is set in OVSRSEL</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INPUTMASK</name>
|
|
<description>Scan Sequence Input Mask</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REF</name>
|
|
<description>Scan Sequence Reference Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1V25</name>
|
|
<description>Internal 1.25 V reference</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V5</name>
|
|
<description>Internal 2.5 V reference</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDD</name>
|
|
<description>VDD</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5VDIFF</name>
|
|
<description>Internal differential 5 V reference</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTSINGLE</name>
|
|
<description>Single ended external reference from ADCn_CH6</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2XEXTDIFF</name>
|
|
<description>Differential external reference, 2x(ADCn_CH6 - ADCn_CH7)</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2XVDD</name>
|
|
<description>Unbuffered 2xVDD</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AT</name>
|
|
<description>Scan Sample Acquisition Time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1CYCLE</name>
|
|
<description>1 ADC_CLK cycle acquisition time for scan samples</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2CYCLES</name>
|
|
<description>2 ADC_CLK cycles acquisition time for scan samples</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4CYCLES</name>
|
|
<description>4 ADC_CLK cycles acquisition time for scan samples</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8CYCLES</name>
|
|
<description>8 ADC_CLK cycles acquisition time for scan samples</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16CYCLES</name>
|
|
<description>16 ADC_CLK cycles acquisition time for scan samples</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32CYCLES</name>
|
|
<description>32 ADC_CLK cycles acquisition time for scan samples</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64CYCLES</name>
|
|
<description>64 ADC_CLK cycles acquisition time for scan samples</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128CYCLES</name>
|
|
<description>128 ADC_CLK cycles acquisition time for scan samples</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256CYCLES</name>
|
|
<description>256 ADC_CLK cycles acquisition time for scan samples</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSEN</name>
|
|
<description>Scan Sequence PRS Trigger Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Scan Sequence PRS Trigger Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS ch 0 triggers scan sequence</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS ch 1 triggers scan sequence</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS ch 2 triggers scan sequence</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS ch 3 triggers scan sequence</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS ch 4 triggers scan sequence</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS ch 5 triggers scan sequence</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS ch 6 triggers scan sequence</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS ch 7 triggers scan sequence</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS ch 8 triggers scan sequence</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS ch 9 triggers scan sequence</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS ch 10 triggers scan sequence</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS ch 11 triggers scan sequence</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000303</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SINGLE</name>
|
|
<description>Single Conversion Complete Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCAN</name>
|
|
<description>Scan Conversion Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SINGLEOF</name>
|
|
<description>Single Result Overflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANOF</name>
|
|
<description>Scan Result Overflow Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000303</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SINGLE</name>
|
|
<description>Single Conversion Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCAN</name>
|
|
<description>Scan Conversion Complete Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SINGLEOF</name>
|
|
<description>Single Result Overflow Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANOF</name>
|
|
<description>Scan Result Overflow Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000303</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SINGLE</name>
|
|
<description>Single Conversion Complete Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCAN</name>
|
|
<description>Scan Conversion Complete Interrupt Flag Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SINGLEOF</name>
|
|
<description>Single Result Overflow Interrupt Flag Set</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANOF</name>
|
|
<description>Scan Result Overflow Interrupt Flag Set</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000303</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SINGLE</name>
|
|
<description>Single Conversion Complete Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCAN</name>
|
|
<description>Scan Conversion Complete Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SINGLEOF</name>
|
|
<description>Single Result Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANOF</name>
|
|
<description>Scan Result Overflow Interrupt Flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SINGLEDATA</name>
|
|
<description>Single Conversion Result Data</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Single Conversion Result Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCANDATA</name>
|
|
<description>Scan Conversion Result Data</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modifyExternal</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Scan Conversion Result Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SINGLEDATAP</name>
|
|
<description>Single Conversion Result Data Peek Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAP</name>
|
|
<description>Single Conversion Result Data Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCANDATAP</name>
|
|
<description>Scan Sequence Result Data Peek Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAP</name>
|
|
<description>Scan Conversion Result Data Peek</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAL</name>
|
|
<description>Calibration Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3F003F00</resetValue>
|
|
<resetMask>0x7F7F7F7F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SINGLEOFFSET</name>
|
|
<description>Single Mode Offset Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SINGLEGAIN</name>
|
|
<description>Single Mode Gain Calibration Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANOFFSET</name>
|
|
<description>Scan Mode Offset Calibration Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCANGAIN</name>
|
|
<description>Scan Mode Gain Calibration Value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BIASPROG</name>
|
|
<description>Bias Programming Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000747</resetValue>
|
|
<resetMask>0x00000F4F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BIASPROG</name>
|
|
<description>Bias Programming Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HALFBIAS</name>
|
|
<description>Half Bias Current</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMPBIAS</name>
|
|
<description>Comparator Bias Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC0</name>
|
|
<description>DAC0</description>
|
|
<baseAddress>0x40004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DAC0</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0x003703FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIFF</name>
|
|
<description>Differential Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SINEMODE</name>
|
|
<description>Sine Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CONVMODE</name>
|
|
<description>Conversion Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUS</name>
|
|
<description>DAC is set in continuous mode</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPLEHOLD</name>
|
|
<description>DAC is set in sample/hold mode</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPLEOFF</name>
|
|
<description>DAC is set in sample/shut off mode</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTMODE</name>
|
|
<description>Output Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>DAC output to pin and ADC disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIN</name>
|
|
<description>DAC output to pin enabled. DAC output to ADC and ACMP disabled</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC</name>
|
|
<description>DAC output to pin disabled. DAC output to ADC and ACMP enabled</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINADC</name>
|
|
<description>DAC output to pin, ADC, and ACMP enabled</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTENPRS</name>
|
|
<description>PRS Controlled Output Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0PRESCRST</name>
|
|
<description>Channel 0 Start Reset Prescaler</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Reference Selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>1V25</name>
|
|
<description>Internal 1.25 V bandgap reference</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2V5</name>
|
|
<description>Internal 2.5 V bandgap reference</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VDD</name>
|
|
<description>VDD reference</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Prescaler Setting</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NODIVISION</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFRSEL</name>
|
|
<description>Refresh Interval Select</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>8CYCLES</name>
|
|
<description>All channels with enabled refresh are refreshed every 8 prescaled cycles</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16CYCLES</name>
|
|
<description>All channels with enabled refresh are refreshed every 16 prescaled cycles</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32CYCLES</name>
|
|
<description>All channels with enabled refresh are refreshed every 32 prescaled cycles</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64CYCLES</name>
|
|
<description>All channels with enabled refresh are refreshed every 64 prescaled cycles</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0DV</name>
|
|
<description>Channel 0 Data Valid</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1DV</name>
|
|
<description>Channel 1 Data Valid</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0CTRL</name>
|
|
<description>Channel 0 Control Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000F7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Channel 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFREN</name>
|
|
<description>Channel 0 Automatic Refresh Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSEN</name>
|
|
<description>Channel 0 PRS Trigger Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Channel 0 PRS Trigger Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS ch 0 triggers channel 0 conversion.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS ch 1 triggers channel 0 conversion.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS ch 2 triggers channel 0 conversion.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS ch 3 triggers channel 0 conversion.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS ch 4 triggers channel 0 conversion.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS ch 5 triggers channel 0 conversion.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS ch 6 triggers channel 0 conversion.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS ch 7 triggers channel 0 conversion.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS ch 8 triggers channel 0 conversion.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS ch 9 triggers channel 0 conversion.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS ch 10 triggers channel 0 conversion.</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS ch 11 triggers channel 0 conversion.</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1CTRL</name>
|
|
<description>Channel 1 Control Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000F7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Channel 1 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFREN</name>
|
|
<description>Channel 1 Automatic Refresh Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSEN</name>
|
|
<description>Channel 1 PRS Trigger Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRSSEL</name>
|
|
<description>Channel 1 PRS Trigger Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSCH0</name>
|
|
<description>PRS ch 0 triggers channel 1 conversion.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH1</name>
|
|
<description>PRS ch 1 triggers channel 1 conversion.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH2</name>
|
|
<description>PRS ch 2 triggers channel 1 conversion.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH3</name>
|
|
<description>PRS ch 3 triggers channel 1 conversion.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH4</name>
|
|
<description>PRS ch 4 triggers channel 1 conversion.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH5</name>
|
|
<description>PRS ch 5 triggers channel 1 conversion.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH6</name>
|
|
<description>PRS ch 6 triggers channel 1 conversion.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH7</name>
|
|
<description>PRS ch 7 triggers channel 1 conversion.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH8</name>
|
|
<description>PRS ch 8 triggers channel 1 conversion.</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH9</name>
|
|
<description>PRS ch 9 triggers channel 1 conversion.</description>
|
|
<value>0x00000009</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH10</name>
|
|
<description>PRS ch 10 triggers channel 1 conversion.</description>
|
|
<value>0x0000000A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSCH11</name>
|
|
<description>PRS ch 11 triggers channel 1 conversion.</description>
|
|
<value>0x0000000B</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000033</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Conversion Complete Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Conversion Complete Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0UF</name>
|
|
<description>Channel 0 Conversion Data Underflow Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1UF</name>
|
|
<description>Channel 1 Conversion Data Underflow Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000033</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Conversion Complete Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Conversion Complete Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0UF</name>
|
|
<description>Channel 0 Data Underflow Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1UF</name>
|
|
<description>Channel 1 Data Underflow Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000033</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Conversion Complete Interrupt Flag Set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Conversion Complete Interrupt Flag Set</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0UF</name>
|
|
<description>Channel 0 Data Underflow Interrupt Flag Set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1UF</name>
|
|
<description>Channel 1 Data Underflow Interrupt Flag Set</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000033</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0</name>
|
|
<description>Channel 0 Conversion Complete Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1</name>
|
|
<description>Channel 1 Conversion Complete Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH0UF</name>
|
|
<description>Channel 0 Data Underflow Interrupt Flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1UF</name>
|
|
<description>Channel 1 Data Underflow Interrupt Flag Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0DATA</name>
|
|
<description>Channel 0 Data Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Channel 0 Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1DATA</name>
|
|
<description>Channel 1 Data Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Channel 1 Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMBDATA</name>
|
|
<description>Combined Data Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0FFF0FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0DATA</name>
|
|
<description>Channel 0 Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1DATA</name>
|
|
<description>Channel 1 Data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAL</name>
|
|
<description>Calibration Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00400000</resetValue>
|
|
<resetMask>0x007F3F3F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OFFSET</name>
|
|
<description>Channel 0 Offset Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1OFFSET</name>
|
|
<description>Channel 1 Offset Calibration Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GAIN</name>
|
|
<description>Gain Calibration Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BIASPROG</name>
|
|
<description>Bias Programming Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00004747</resetValue>
|
|
<resetMask>0x00004F4F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BIASPROG</name>
|
|
<description>Bias Programming Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HALFBIAS</name>
|
|
<description>Half Bias Current</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA2BIASPROG</name>
|
|
<description>Bias Programming Value for OPA2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA2HALFBIAS</name>
|
|
<description>Half Bias Current</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPACTRL</name>
|
|
<description>Operational Amplifier Control Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x01C3F1C7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPA0EN</name>
|
|
<description>OPA0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA1EN</name>
|
|
<description>OPA1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA2EN</name>
|
|
<description>OPA2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA0HCMDIS</name>
|
|
<description>High Common Mode Disable.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA1HCMDIS</name>
|
|
<description>High Common Mode Disable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA2HCMDIS</name>
|
|
<description>High Common Mode Disable.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA0LPFDIS</name>
|
|
<description>Disables Low Pass Filter.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLPFDIS</name>
|
|
<description>Disables the LPF between positive pad and positive input.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NLPFDIS</name>
|
|
<description>Disables the LPF between negative pad and negative input.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPA1LPFDIS</name>
|
|
<description>Disables Low Pass Filter.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLPFDIS</name>
|
|
<description>Disables the LPF between positive pad and positive input.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NLPFDIS</name>
|
|
<description>Disables the LPF between negative pad and negative input.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPA2LPFDIS</name>
|
|
<description>Disables Low Pass Filter.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLPFDIS</name>
|
|
<description>Disables the LPF between positive pad and positive input.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NLPFDIS</name>
|
|
<description>Disables the LPF between negative pad and negative input.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPA0SHORT</name>
|
|
<description>Short the non-inverting and inverting input.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA1SHORT</name>
|
|
<description>Short the non-inverting and inverting input.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA2SHORT</name>
|
|
<description>Short the non-inverting and inverting input.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPAOFFSET</name>
|
|
<description>Operational Amplifier Offset Register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000020</resetValue>
|
|
<resetMask>0x0000003F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPA2OFFSET</name>
|
|
<description>OPA2 Offset Configuration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPA0MUX</name>
|
|
<description>Operational Amplifier Mux Configuration Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00400000</resetValue>
|
|
<resetMask>0x74C7F737</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POSSEL</name>
|
|
<description>OPA0 non-inverting Input Mux</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Input disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC</name>
|
|
<description>DAC as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSPAD</name>
|
|
<description>POS PAD as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPA0INP</name>
|
|
<description>OPA0 as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPATAP</name>
|
|
<description>OPA0 Resistor ladder as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEGSEL</name>
|
|
<description>OPA0 inverting Input Mux</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Input disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UG</name>
|
|
<description>Unity Gain feedback path</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPATAP</name>
|
|
<description>OPA0 Resistor ladder as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGPAD</name>
|
|
<description>Input from NEG PAD</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESINMUX</name>
|
|
<description>OPA0 Resistor Ladder Input Mux</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Set for Unity Gain</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPA0INP</name>
|
|
<description>Set for OPA0 input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGPAD</name>
|
|
<description>NEG pad connected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSPAD</name>
|
|
<description>POS pad connected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSS</name>
|
|
<description>VSS connected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PPEN</name>
|
|
<description>OPA0 Positive Pad Input Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NPEN</name>
|
|
<description>OPA0 Negative Pad Input Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPEN</name>
|
|
<description>OPA0 Output Enable Value</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT0</name>
|
|
<description>Alternate Output 0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT1</name>
|
|
<description>Alternate Output 1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT2</name>
|
|
<description>Alternate Output 2</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT3</name>
|
|
<description>Alternate Output 3</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT4</name>
|
|
<description>Alternate Output 4</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTMODE</name>
|
|
<description>Output Select</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>OPA0 output is disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAIN</name>
|
|
<description>Main OPA0 output to pin enabled </description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT</name>
|
|
<description>OPA0 alternative output enabled.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALL</name>
|
|
<description>Main OPA0 output drives both main and alternative outputs.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEXTOUT</name>
|
|
<description>OPA0 Next Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESSEL</name>
|
|
<description>OPA0 Resistor Ladder Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RES0</name>
|
|
<description>Gain of 1/3</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES1</name>
|
|
<description>Gain of 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES2</name>
|
|
<description>Gain of 1 2/3</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES3</name>
|
|
<description>Gain of 2</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES4</name>
|
|
<description>Gain of 3</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES5</name>
|
|
<description>Gain of 4 1/3</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES6</name>
|
|
<description>Gain of 7</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES7</name>
|
|
<description>Gain of 15</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPA1MUX</name>
|
|
<description>Operational Amplifier Mux Configuration Register</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x74C7F737</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POSSEL</name>
|
|
<description>OPA1 non-inverting Input Mux</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Input disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAC</name>
|
|
<description>DAC as input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSPAD</name>
|
|
<description>POS PAD as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPA0INP</name>
|
|
<description>OPA0 as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPATAP</name>
|
|
<description>OPA 1 Resistor ladder as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEGSEL</name>
|
|
<description>OPA1 inverting Input Mux</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Input disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UG</name>
|
|
<description>Unity Gain feedback path</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPATAP</name>
|
|
<description>OPA1 Resistor ladder as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGPAD</name>
|
|
<description>Input from NEG PAD</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESINMUX</name>
|
|
<description>OPA1 Resistor Ladder Input Mux</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Set for Unity Gain</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPA0INP</name>
|
|
<description>Set for OPA0 input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGPAD</name>
|
|
<description>NEG PAD connected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSPAD</name>
|
|
<description>POS PAD connected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSS</name>
|
|
<description>VSS connected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PPEN</name>
|
|
<description>OPA1 Positive Pad Input Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NPEN</name>
|
|
<description>OPA1 Negative Pad Input Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPEN</name>
|
|
<description>OPA1 Output Enable Value</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT0</name>
|
|
<description>Alternate Output 0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT1</name>
|
|
<description>Alternate Output 1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT2</name>
|
|
<description>Alternate Output 2</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT3</name>
|
|
<description>Alternate Output 3</description>
|
|
<value>0x00000008</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT4</name>
|
|
<description>Alternate Output 4</description>
|
|
<value>0x00000010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTMODE</name>
|
|
<description>Output Select</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>OPA0 output is disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAIN</name>
|
|
<description>Main OPA1 output to pin enabled </description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT</name>
|
|
<description>OPA1 alternative output enabled.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALL</name>
|
|
<description>Main OPA1 output drives both main and alternative outputs.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEXTOUT</name>
|
|
<description>OPA1 Next Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESSEL</name>
|
|
<description>OPA1 Resistor Ladder Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RES0</name>
|
|
<description>Gain of 1/3</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES1</name>
|
|
<description>Gain of 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES2</name>
|
|
<description>Gain of 1 2/3</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES3</name>
|
|
<description>Gain of 2</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES4</name>
|
|
<description>Gain of 3</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES5</name>
|
|
<description>Gain of 4 1/3</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES6</name>
|
|
<description>Gain of 7</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES7</name>
|
|
<description>Gain of 15</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPA2MUX</name>
|
|
<description>Operational Amplifier Mux Configuration Register</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x7440F737</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POSSEL</name>
|
|
<description>OPA2 non-inverting Input Mux</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Input disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSPAD</name>
|
|
<description>POS PAD as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPA1INP</name>
|
|
<description>OPA1 as input</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPATAP</name>
|
|
<description>OPA0 Resistor ladder as input</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEGSEL</name>
|
|
<description>OPA2 inverting Input Mux</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Input disabled</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UG</name>
|
|
<description>Unity Gain feedback path</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPATAP</name>
|
|
<description>OPA2 Resistor ladder as input</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGPAD</name>
|
|
<description>Input from NEG PAD</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESINMUX</name>
|
|
<description>OPA2 Resistor Ladder Input Mux</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Set for Unity Gain</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPA1INP</name>
|
|
<description>Set for OPA1 input</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEGPAD</name>
|
|
<description>NEG PAD connected</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSPAD</name>
|
|
<description>POS PAD connected</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSS</name>
|
|
<description>VSS connected</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PPEN</name>
|
|
<description>OPA2 Positive Pad Input Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NPEN</name>
|
|
<description>OPA2 Negative Pad Input Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPEN</name>
|
|
<description>OPA2 Output Location</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT0</name>
|
|
<description>Main Output 0</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT1</name>
|
|
<description>Main Output 1</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTMODE</name>
|
|
<description>Output Select</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NEXTOUT</name>
|
|
<description>OPA2 Next Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESSEL</name>
|
|
<description>OPA2 Resistor Ladder Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RES0</name>
|
|
<description>Gain of 1/3</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES1</name>
|
|
<description>Gain of 1</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES2</name>
|
|
<description>Gain of 1 2/3</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES3</name>
|
|
<description>Gain of 2</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES4</name>
|
|
<description>Gain of 3</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES5</name>
|
|
<description>Gain of 4 1/3</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES6</name>
|
|
<description>Gain of 7</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RES7</name>
|
|
<description>Gain of 15</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>BURTC</name>
|
|
<description>BURTC</description>
|
|
<baseAddress>0x40081000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>BURTC</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0x000077FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>BURTC Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The BURTC is disabled.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EM2EN</name>
|
|
<description>The BURTC is in normal operating mode, operating in EM0-EM2. Oscillators must be enabled in CMU for use.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EM3EN</name>
|
|
<description>The BURTC is enabled in EM0-EM3. Will prevent CMU from disabling used oscillators all the way down to EM3.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EM4EN</name>
|
|
<description>The BURTC is enabled in EM0-EM4. Will prevent CMU from disabling used oscillators all the way down to EM4.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGRUN</name>
|
|
<description>Debug Mode Run Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTEN</name>
|
|
<description>Enable BURTC reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0TOP</name>
|
|
<description>Compare clear enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LPCOMP</name>
|
|
<description>Low power mode compare configuration</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IGN0LSB</name>
|
|
<description>Do not ignore any bits for compare match evaluation.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGN1LSB</name>
|
|
<description>The LSB of the counter is ignored for compare match evaluation.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGN2LSB</name>
|
|
<description>The two LSBs of the counter are ignored for compare match evaluation.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGN3LSB</name>
|
|
<description>The three LSBs of the counter are ignored for compare match evaluation.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGN4LSB</name>
|
|
<description>The four LSBs of the counter are ignored for compare match evaluation.</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGN5LSB</name>
|
|
<description>The five LSBs of the counter are ignored for compare match evaluation.</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGN6LSB</name>
|
|
<description>The six LSBs of the counter are ignored for compare match evaluation.</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGN7LSB</name>
|
|
<description>The seven LSBs of the counter are ignored for compare match evaluation.</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Select BURTC prescaler factor</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>No prescaling.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>Prescaling factor of 2</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>Prescaling factor of 4</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV8</name>
|
|
<description>Prescaling factor of 8</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV16</name>
|
|
<description>Prescaling factor of 16</description>
|
|
<value>0x00000004</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV32</name>
|
|
<description>Prescaling factor of 32</description>
|
|
<value>0x00000005</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV64</name>
|
|
<description>Prescaling factor of 64</description>
|
|
<value>0x00000006</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV128</name>
|
|
<description>Prescaling factor of 128</description>
|
|
<value>0x00000007</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Select BURTC clock source</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>No clock source selected for BURTC.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCO</name>
|
|
<description>LFRCO selected as BURTC clock source.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXO</name>
|
|
<description>LFXO selected as BURTC clock source.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULFRCO</name>
|
|
<description>ULFRCO selected as BURTC clock source.</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUMODETSEN</name>
|
|
<description>Backup mode timestamp enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPMODE</name>
|
|
<description>Low power mode configuration</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPMODE</name>
|
|
<description>Low power mode configuration.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Low power mode is disabled.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Low power mode always enabled.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUEN</name>
|
|
<description>Low power mode enabled in backup mode.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter Value Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP0</name>
|
|
<description>Counter Compare Value</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Compare match value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMESTAMP</name>
|
|
<description>Backup mode timestamp</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMESTAMP</name>
|
|
<description>Backup mode timestamp.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LFXOFDET</name>
|
|
<description>LFXO </description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000001F3</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OSC</name>
|
|
<description>LFXO failure detection configuration.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>LFXO failure detection disabled.</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCO</name>
|
|
<description>LFRCO used for LFXO failure detection.</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULFRCO</name>
|
|
<description>ULFRCO used for LFXO failure detection.</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOP</name>
|
|
<description>LFXO failure counter top value.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPMODEACT</name>
|
|
<description>Low power mode active</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUMODETS</name>
|
|
<description>Timestamp for backup mode entry stored.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RAMWERR</name>
|
|
<description>RAM write error.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRSTATUS</name>
|
|
<description>Clear BURTC_STATUS register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POWERDOWN</name>
|
|
<description>Retention RAM power-down Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAM</name>
|
|
<description>Retention RAM power-down</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<description>Configuration Lock Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKKEY</name>
|
|
<description>Configuration Lock Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNLOCKED</name>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCKED</name>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IF</name>
|
|
<description>Interrupt Flag Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Compare match Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXOFAIL</name>
|
|
<description>LFXO failure Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFS</name>
|
|
<description>Interrupt Flag Set Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Set Overflow Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Set compare match Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXOFAIL</name>
|
|
<description>Set LFXO fail Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFC</name>
|
|
<description>Interrupt Flag Clear Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Clear Overflow Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Clear compare match Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXOFAIL</name>
|
|
<description>Clear LFXO failure Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000007</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Compare match Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LFXOFAIL</name>
|
|
<description>LFXO failure Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FREEZE</name>
|
|
<description>Freeze Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGFREEZE</name>
|
|
<description>Register Update Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPMODE</name>
|
|
<description>LPMODE Register Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>COMP0 Register Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET0_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET1_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET2_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET3_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET4_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET5_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET6_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET7_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET8_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET9_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET10_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET11_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET12_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET13_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET14_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET15_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET16_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET17_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET18_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET19_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET20_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET21_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET22_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET23_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET24_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET25_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET26_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET27_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET28_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET29_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET30_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET31_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x17C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET32_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET33_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET34_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET35_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET36_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET37_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET38_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET39_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET40_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET41_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET42_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET43_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET44_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET45_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET46_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET47_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET48_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET49_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET50_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET51_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET52_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET53_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET54_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET55_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1DC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET56_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET57_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET58_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET59_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1EC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET60_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET61_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1F4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET62_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1F8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET63_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x1FC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET64_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET65_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET66_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET67_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET68_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET69_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET70_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET71_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x21C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET72_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x220</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET73_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x224</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET74_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x228</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET75_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x22C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET76_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x230</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET77_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x234</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET78_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x238</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET79_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x23C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET80_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET81_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x244</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET82_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x248</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET83_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x24C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET84_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x250</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET85_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x254</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET86_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x258</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET87_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x25C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET88_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x260</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET89_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x264</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET90_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x268</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET91_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x26C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET92_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x270</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET93_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x274</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET94_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x278</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET95_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x27C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET96_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET97_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x284</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET98_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x288</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET99_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x28C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET100_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x290</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET101_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x294</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET102_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x298</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET103_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x29C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET104_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET105_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET106_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET107_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET108_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET109_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET110_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET111_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2BC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET112_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET113_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET114_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET115_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET116_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET117_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET118_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET119_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2DC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET120_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET121_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET122_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET123_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2EC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET124_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET125_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2F4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET126_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2F8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RET127_REG</name>
|
|
<description>Retention Register</description>
|
|
<addressOffset>0x2FC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>General Purpose Retention Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WDOG</name>
|
|
<description>WDOG</description>
|
|
<baseAddress>0x40088000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00000400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000F00</resetValue>
|
|
<resetMask>0x00003F7F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Watchdog Timer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGRUN</name>
|
|
<description>Debug Mode Run Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EM2RUN</name>
|
|
<description>Energy Mode 2 Run Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EM3RUN</name>
|
|
<description>Energy Mode 3 Run Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Configuration lock</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EM4BLOCK</name>
|
|
<description>Energy Mode 4 Block</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWOSCBLOCK</name>
|
|
<description>Software Oscillator Disable Block</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERSEL</name>
|
|
<description>Watchdog Timeout Period Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Watchdog Clock Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ULFRCO</name>
|
|
<description>ULFRCO</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFRCO</name>
|
|
<description>LFRCO</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LFXO</name>
|
|
<description>LFXO</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLEAR</name>
|
|
<description>Watchdog Timer Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCBUSY</name>
|
|
<description>Synchronization Busy Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>CTRL Register Busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>CMD Register Busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ETM</name>
|
|
<description>ETM</description>
|
|
<baseAddress>0xE0041000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00040000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ETMCR</name>
|
|
<description>Main Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000411</resetValue>
|
|
<resetMask>0x10632FF1</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POWERDWN</name>
|
|
<description>ETM Control in low power mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PORTSIZE</name>
|
|
<description>ETM Port Size</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>Stall Processor</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRANCHOUTPUT</name>
|
|
<description>Branch Output</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBGREQCTRL</name>
|
|
<description>Debug Request Control</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETMPROG</name>
|
|
<description>ETM Programming</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETMPORTSEL</name>
|
|
<description>ETM Port Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PORTMODE2</name>
|
|
<description>Port Mode[2]</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PORTMODE</name>
|
|
<description>Port Mode Control</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPORTSIZE</name>
|
|
<description>Port Size[3]</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSTAMPEN</name>
|
|
<description>Time Stamp Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMCCR</name>
|
|
<description>Configuration Code Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x8C802000</resetValue>
|
|
<resetMask>0x8FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRCMPPAIR</name>
|
|
<description>Number of Address Comparator Pairs</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATACMPNUM</name>
|
|
<description>Number of Data Value Comparators</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MMDECCNT</name>
|
|
<description>Number of Memeory Map Decoders</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COUNTNUM</name>
|
|
<description>Number of Counters</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SEQPRES</name>
|
|
<description>Sequencer Present</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXTINPNUM</name>
|
|
<description>Number of External Inputs</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZERO</name>
|
|
<description>Zero inputs presents</description>
|
|
<value>0x00000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE</name>
|
|
<description>One inputs presents</description>
|
|
<value>0x00000001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO</name>
|
|
<description>Two inputs presents</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTOUTNUM</name>
|
|
<description>Number of External Output</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FIFOFULLPRES</name>
|
|
<description>FIFIO FULL present</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IDCOMPNUM</name>
|
|
<description>Number of context ID Comparators</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRACESS</name>
|
|
<description>Trace Start/Stop Block Present</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MMACCESS</name>
|
|
<description>Coprocessor and Memeory Access</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETMID</name>
|
|
<description>ETM ID Register Present</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMTRIGGER</name>
|
|
<description>ETM Trigger Event Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0001FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESA</name>
|
|
<description>ETM Resource A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESB</name>
|
|
<description>ETM Resource B</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETMFCN</name>
|
|
<description>ETM Function</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMSR</name>
|
|
<description>ETM Status Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<resetMask>0x0000000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ETHOF</name>
|
|
<description>ETM Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETMPROGBIT</name>
|
|
<description>ETM Programming Bit Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRACESTAT</name>
|
|
<description>Trace Start/Stop Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIGBIT</name>
|
|
<description>Trigger Bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMSCR</name>
|
|
<description>ETM System Configuration Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00020D09</resetValue>
|
|
<resetMask>0x00027F0F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAXPORTSIZE</name>
|
|
<description>Maximum Port Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FIFOFULL</name>
|
|
<description>FIFO FULL Supported</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAXPORTSIZE3</name>
|
|
<description>Max Port Size[3]</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PORTSIZE</name>
|
|
<description>Port Size Supported</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PORTMODE</name>
|
|
<description>Port Mode Supported</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PROCNUM</name>
|
|
<description>Number of Supported Processros</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NOFETCHCOMP</name>
|
|
<description>No Fetch Comparison</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMTEEVR</name>
|
|
<description>ETM TraceEnable Event Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0001FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESA</name>
|
|
<description>ETM Resource A Trace Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESB</name>
|
|
<description>ETM Resource B Trace Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETMFCNEN</name>
|
|
<description>ETM Function Trace Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMTECR1</name>
|
|
<description>ETM Trace control Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x03FFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRCMP</name>
|
|
<description>Address Comparator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEMMAP</name>
|
|
<description>Memmap</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INCEXCTL</name>
|
|
<description>Trace Include/Exclude Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCE</name>
|
|
<description>Trace Control Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMFFLR</name>
|
|
<description>ETM Fifo Full Level Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BYTENUM</name>
|
|
<description>Bytes left in FIFO</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMCNTRLDVR1</name>
|
|
<description>Counter Reload Value</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Free running counter reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMSYNCFR</name>
|
|
<description>Synchronisation Frequency Register</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000400</resetValue>
|
|
<resetMask>0x00000FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FREQ</name>
|
|
<description>Synchronisation Frequency Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMIDR</name>
|
|
<description>ID Register</description>
|
|
<addressOffset>0x1E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4114F253</resetValue>
|
|
<resetMask>0xFF1DFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMPVER</name>
|
|
<description>Implementation Revision</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETMMINVER</name>
|
|
<description>Minor ETM Architecture Version</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETMMAJVER</name>
|
|
<description>Major ETM Architecture Version</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PROCFAM</name>
|
|
<description>Implementer Code</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LPCF</name>
|
|
<description>Load PC First</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>THUMBT</name>
|
|
<description>32-bit Thumb Instruction Tracing</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SECEXT</name>
|
|
<description>Security Extension Support</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BPE</name>
|
|
<description>Branch Packet Encoding</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IMPCODE</name>
|
|
<description>Implementer Code</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMCCER</name>
|
|
<description>Configuration Code Extension Register</description>
|
|
<addressOffset>0x1E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x18541800</resetValue>
|
|
<resetMask>0x387FFFFB</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTINPSEL</name>
|
|
<description>Extended External Input Selectors</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXTINPBUS</name>
|
|
<description>Extended External Input Bus</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>READREGS</name>
|
|
<description>Readable Registers</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DADDRCMP</name>
|
|
<description>Data Address comparisons</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INSTRES</name>
|
|
<description>Instrumentation Resources</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EICEWPNT</name>
|
|
<description>EmbeddedICE watchpoint inputs</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TEICEWPNT</name>
|
|
<description>Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EICEIMP</name>
|
|
<description>EmbeddedICE Behavior control Implemented</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMP</name>
|
|
<description>Timestamping Implemented</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RFCNT</name>
|
|
<description>Reduced Function Counter</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TENC</name>
|
|
<description>Timestamp Encoding</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TSIZE</name>
|
|
<description>Timestamp Size</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMTESSEICR</name>
|
|
<description>TraceEnable Start/Stop EmbeddedICE Control Register</description>
|
|
<addressOffset>0x1F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000F000F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STARTRSEL</name>
|
|
<description>Stop Resource Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOPRSEL</name>
|
|
<description>Stop Resource Selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMTSEVR</name>
|
|
<description>Timestamp Event Register</description>
|
|
<addressOffset>0x1F8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0001FFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESAEVT</name>
|
|
<description>ETM Resource A Event</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESBEVT</name>
|
|
<description>ETM Resource B Event</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETMFCNEVT</name>
|
|
<description>ETM Function Event</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMTRACEIDR</name>
|
|
<description>CoreSight Trace ID Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x0000007F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRACEID</name>
|
|
<description>Trace ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMIDR2</name>
|
|
<description>ETM ID Register 2</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFE</name>
|
|
<description>RFE Transfer Order</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWP</name>
|
|
<description>SWP Transfer Order</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMPDSR</name>
|
|
<description>Device Power-down Status Register</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ETMUP</name>
|
|
<description>ETM Powered Up</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMISCIN</name>
|
|
<description>Integration Test Miscellaneous Inputs Register</description>
|
|
<addressOffset>0xEE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000013</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTIN</name>
|
|
<description>EXTIN Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COREHALT</name>
|
|
<description>Core Halt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ITTRIGOUT</name>
|
|
<description>Integration Test Trigger Out Register</description>
|
|
<addressOffset>0xEE8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIGGEROUT</name>
|
|
<description>Trigger output value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMITATBCTR2</name>
|
|
<description>ETM Integration Test ATB Control 2 Register</description>
|
|
<addressOffset>0xEF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ATREADY</name>
|
|
<description>ATREADY Input Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMITATBCTR0</name>
|
|
<description>ETM Integration Test ATB Control 0 Register</description>
|
|
<addressOffset>0xEF8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ATVALID</name>
|
|
<description>ATVALID Output Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMITCTRL</name>
|
|
<description>ETM Integration Control Register</description>
|
|
<addressOffset>0xF00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ITEN</name>
|
|
<description>Integration Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMCLAIMSET</name>
|
|
<description>ETM Claim Tag Set Register</description>
|
|
<addressOffset>0xFA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000000F</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETTAG</name>
|
|
<description>Tag Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMCLAIMCLR</name>
|
|
<description>ETM Claim Tag Clear Register</description>
|
|
<addressOffset>0xFA4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRTAG</name>
|
|
<description>Tag Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMLAR</name>
|
|
<description>ETM Lock Access Register</description>
|
|
<addressOffset>0xFB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000001</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Key Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMLSR</name>
|
|
<description>Lock Status Register</description>
|
|
<addressOffset>0xFB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0x00000003</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKIMP</name>
|
|
<description>ETM Locking Implemented</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKED</name>
|
|
<description>ETM locked</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMAUTHSTATUS</name>
|
|
<description>ETM Authentication Status Register</description>
|
|
<addressOffset>0xFB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000C0</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NONSECINVDBG</name>
|
|
<description>Non-secure invasive Debug Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NONSECNONINVDBG</name>
|
|
<description>Non-secure non-invasive Debug Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Non-secure non-invasive debug disable</description>
|
|
<value>0x00000002</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Non-secure non-invasive debug enable</description>
|
|
<value>0x00000003</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SECINVDBG</name>
|
|
<description>Secure invasive Debug Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SECNONINVDBG</name>
|
|
<description>Secure non-invasive Debug Status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMDEVTYPE</name>
|
|
<description>CoreSight Device Type Register</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000013</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRACESRC</name>
|
|
<description>Trace Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PROCTRACE</name>
|
|
<description>Processor Trace</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMPIDR4</name>
|
|
<description>Peripheral ID4 Register</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000004</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CONTCODE</name>
|
|
<description>JEP106 Continuation Code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>4KB Count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMPIDR5</name>
|
|
<description>Peripheral ID5 Register</description>
|
|
<addressOffset>0xFD4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ETMPIDR6</name>
|
|
<description>Peripheral ID6 Register</description>
|
|
<addressOffset>0xFD8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ETMPIDR7</name>
|
|
<description>Peripheral ID7 Register</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ETMPIDR0</name>
|
|
<description>Peripheral ID0 Register</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000024</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PARTNUM</name>
|
|
<description>Part Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMPIDR1</name>
|
|
<description>Peripheral ID1 Register</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B9</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PARTNUM</name>
|
|
<description>Part Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IDCODE</name>
|
|
<description>JEP106 Identity Code</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMPIDR2</name>
|
|
<description>Peripheral ID2 Register</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000003B</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IDCODE</name>
|
|
<description>JEP106 Identity Code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALWAYS1</name>
|
|
<description>Always 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REV</name>
|
|
<description>Revision</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMPIDR3</name>
|
|
<description>Peripheral ID3 Register</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CUSTMOD</name>
|
|
<description>Customer Modified</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REVAND</name>
|
|
<description>RevAnd</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMCIDR0</name>
|
|
<description>Component ID0 Register</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000D</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMB</name>
|
|
<description>CoreSight Preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMCIDR1</name>
|
|
<description>Component ID1 Register</description>
|
|
<addressOffset>0xFF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000090</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMB</name>
|
|
<description>CoreSight Preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMCIDR2</name>
|
|
<description>Component ID2 Register</description>
|
|
<addressOffset>0xFF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMB</name>
|
|
<description>CoreSight Preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETMCIDR3</name>
|
|
<description>Component ID3 Register</description>
|
|
<addressOffset>0xFFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000B1</resetValue>
|
|
<resetMask>0x000000FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PREAMB</name>
|
|
<description>CoreSight Preamble</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
<!-- vendorExtions is _reqiuired_ to pass through Schema validation -->
|
|
<vendorExtensions>
|
|
<name>Copyright 2021 Silicon Laboratories, Inc.</name>
|
|
<flashBaseAddress>0x00000000</flashBaseAddress>
|
|
<flashSize>0x00080000</flashSize>
|
|
<flashAccessTypes>rx</flashAccessTypes>
|
|
<sramBaseAddress>0x20000000</sramBaseAddress>
|
|
<sramSize>0x00020000</sramSize>
|
|
<sramAccessTypes>rwx</sramAccessTypes>
|
|
</vendorExtensions>
|
|
</device>
|